Merge tag 'sunxi-fixes-for-4.0' of https://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / pci / pci.h
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1#ifndef DRIVERS_PCI_H
2#define DRIVERS_PCI_H
3
4#define PCI_CFG_SPACE_SIZE 256
5#define PCI_CFG_SPACE_EXP_SIZE 4096
6
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7extern const unsigned char pcie_link_speed[];
8
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9bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
10
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11/* Functions internal to the PCI core code */
12
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13int pci_create_sysfs_dev_files(struct pci_dev *pdev);
14void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b 15#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b 16static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f 17{ return; }
911e1c9b 18static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f 19{ return; }
911e1c9b 20#else
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21void pci_create_firmware_label_files(struct pci_dev *pdev);
22void pci_remove_firmware_label_files(struct pci_dev *pdev);
911e1c9b 23#endif
f39d5b72 24void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2 25#ifdef HAVE_PCI_MMAP
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26enum pci_mmap_api {
27 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
28 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
29};
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30int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
31 enum pci_mmap_api mmap_api);
9eff02e2 32#endif
711d5779 33int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef 34
961d9120 35/**
b33bfdef 36 * struct pci_platform_pm_ops - Firmware PM callbacks
961d9120 37 *
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38 * @is_manageable: returns 'true' if given device is power manageable by the
39 * platform firmware
961d9120 40 *
b33bfdef 41 * @set_state: invokes the platform firmware to set the device's power state
961d9120 42 *
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43 * @choose_state: returns PCI power state of given device preferred by the
44 * platform; to be used during system-wide transitions from a
45 * sleeping state to the working state and vice versa
961d9120 46 *
b33bfdef 47 * @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4 48 *
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49 * @run_wake: enables/disables the platform to generate run-time wake-up events
50 * for given device (the device's wake-up capability has to be
51 * enabled by @sleep_wake for this feature to work)
52 *
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53 * @need_resume: returns 'true' if the given device (which is currently
54 * suspended) needs to be resumed to be configured for system
55 * wakeup.
56 *
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57 * If given platform is generally capable of power managing PCI devices, all of
58 * these callbacks are mandatory.
59 */
60struct pci_platform_pm_ops {
61 bool (*is_manageable)(struct pci_dev *dev);
62 int (*set_state)(struct pci_dev *dev, pci_power_t state);
63 pci_power_t (*choose_state)(struct pci_dev *dev);
eb9d0fe4 64 int (*sleep_wake)(struct pci_dev *dev, bool enable);
b67ea761 65 int (*run_wake)(struct pci_dev *dev, bool enable);
bac2a909 66 bool (*need_resume)(struct pci_dev *dev);
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67};
68
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69int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
70void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
71void pci_power_up(struct pci_dev *dev);
72void pci_disable_enabled_device(struct pci_dev *dev);
73int pci_finish_runtime_suspend(struct pci_dev *dev);
74int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
bac2a909 75bool pci_dev_keep_suspended(struct pci_dev *dev);
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76void pci_config_pm_runtime_get(struct pci_dev *dev);
77void pci_config_pm_runtime_put(struct pci_dev *dev);
78void pci_pm_init(struct pci_dev *dev);
79void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e 80void pci_free_cap_save_buffers(struct pci_dev *dev);
aa8c6c93 81
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82static inline void pci_wakeup_event(struct pci_dev *dev)
83{
84 /* Wait 100 ms before the system can be put into a sleep state. */
85 pm_wakeup_event(&dev->dev, 100);
86}
87
326c1cda 88static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
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89{
90 return !!(pci_dev->subordinate);
91}
0f64474b 92
94e61088 93struct pci_vpd_ops {
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94 ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
95 ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
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96 void (*release)(struct pci_dev *dev);
97};
98
99struct pci_vpd {
99cb233d 100 unsigned int len;
287d19ce 101 const struct pci_vpd_ops *ops;
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102 struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
103};
104
f39d5b72 105int pci_vpd_pci22_init(struct pci_dev *dev);
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106static inline void pci_vpd_release(struct pci_dev *dev)
107{
108 if (dev->vpd)
109 dev->vpd->ops->release(dev);
110}
111
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112/* PCI /proc functions */
113#ifdef CONFIG_PROC_FS
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114int pci_proc_attach_device(struct pci_dev *dev);
115int pci_proc_detach_device(struct pci_dev *dev);
116int pci_proc_detach_bus(struct pci_bus *bus);
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117#else
118static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
119static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
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120static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
121#endif
122
123/* Functions for PCI Hotplug drivers to use */
a8e4b9c1 124int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4 125
f19aeb1f 126#ifdef HAVE_PCI_LEGACY
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127void pci_create_legacy_files(struct pci_bus *bus);
128void pci_remove_legacy_files(struct pci_bus *bus);
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129#else
130static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
131static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
132#endif
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133
134/* Lock for read/write access to pci device and bus lists */
d71374da 135extern struct rw_semaphore pci_bus_sem;
1da177e4 136
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137extern raw_spinlock_t pci_lock;
138
ffadcc2f 139extern unsigned int pci_pm_d3_delay;
88187dfa 140
4b47b0ee 141#ifdef CONFIG_PCI_MSI
309e57df 142void pci_no_msi(void);
f39d5b72 143void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee 144#else
309e57df 145static inline void pci_no_msi(void) { }
4aa9bc95 146static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee 147#endif
8fed4b65 148
b55438fd 149void pci_realloc_get_opt(char *);
f483d392 150
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151static inline int pci_no_d1d2(struct pci_dev *dev)
152{
153 unsigned int parent_dstates = 0;
4b47b0ee 154
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155 if (dev->bus->self)
156 parent_dstates = dev->bus->self->no_d1d2;
157 return (dev->no_d1d2 || parent_dstates);
158
159}
5136b2da 160extern const struct attribute_group *pci_dev_groups[];
56039e65 161extern const struct attribute_group *pcibus_groups[];
4e15c46b 162extern struct device_type pci_dev_type;
0f49ba55 163extern const struct attribute_group *pci_bus_groups[];
705b1aaa 164
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165
166/**
167 * pci_match_one_device - Tell if a PCI device structure has a matching
168 * PCI device id structure
169 * @id: single PCI device id structure to match
170 * @dev: the PCI device structure to match against
367b09fe 171 *
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172 * Returns the matching pci_device_id structure or %NULL if there is no match.
173 */
174static inline const struct pci_device_id *
175pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
176{
177 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
178 (id->device == PCI_ANY_ID || id->device == dev->device) &&
179 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
180 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
181 !((id->class ^ dev->class) & id->class_mask))
182 return id;
183 return NULL;
184}
185
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186/* PCI slot sysfs helper code */
187#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
188
189extern struct kset *pci_slots_kset;
190
191struct pci_slot_attribute {
192 struct attribute attr;
193 ssize_t (*show)(struct pci_slot *, char *);
194 ssize_t (*store)(struct pci_slot *, const char *, size_t);
195};
196#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
197
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198enum pci_bar_type {
199 pci_bar_unknown, /* Standard PCI BAR probe */
200 pci_bar_io, /* An io port BAR */
201 pci_bar_mem32, /* A 32-bit memory BAR */
202 pci_bar_mem64, /* A 64-bit memory BAR */
203};
204
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205bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
206 int crs_timeout);
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207int pci_setup_device(struct pci_dev *dev);
208int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
209 struct resource *res, unsigned int reg);
210int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type);
211void pci_configure_ari(struct pci_dev *dev);
10874f5a 212void __pci_bus_size_bridges(struct pci_bus *bus,
d66ecb72 213 struct list_head *realloc_head);
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214void __pci_bus_assign_resources(const struct pci_bus *bus,
215 struct list_head *realloc_head,
216 struct list_head *fail_head);
0f7e7aee 217bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
939de1d6 218
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219/**
220 * pci_ari_enabled - query ARI forwarding status
6a49d812 221 * @bus: the PCI bus
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222 *
223 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
224 */
6a49d812 225static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727 226{
6a49d812 227 return bus->self && bus->self->ari_enabled;
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228}
229
2069ecfb 230void pci_reassigndev_resource_alignment(struct pci_dev *dev);
f39d5b72 231void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682 232
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233/* Single Root I/O Virtualization */
234struct pci_sriov {
235 int pos; /* capability position */
236 int nres; /* number of resources */
237 u32 cap; /* SR-IOV Capabilities */
238 u16 ctrl; /* SR-IOV Control */
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239 u16 total_VFs; /* total VFs associated with the PF */
240 u16 initial_VFs; /* initial VFs associated with the PF */
241 u16 num_VFs; /* number of VFs available */
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242 u16 offset; /* first VF Routing ID offset */
243 u16 stride; /* following VF stride */
244 u32 pgsz; /* page size for BAR alignment */
245 u8 link; /* Function Dependency Link */
6b136724 246 u16 driver_max_VFs; /* max num VFs driver supports */
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247 struct pci_dev *dev; /* lowest numbered PF */
248 struct pci_dev *self; /* this PF */
249 struct mutex lock; /* lock for VF bus */
250};
251
1900ca13 252#ifdef CONFIG_PCI_ATS
f39d5b72 253void pci_restore_ats_state(struct pci_dev *dev);
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254#else
255static inline void pci_restore_ats_state(struct pci_dev *dev)
256{
257}
258#endif /* CONFIG_PCI_ATS */
259
d1b054da 260#ifdef CONFIG_PCI_IOV
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261int pci_iov_init(struct pci_dev *dev);
262void pci_iov_release(struct pci_dev *dev);
26ff46c6 263int pci_iov_resource_bar(struct pci_dev *dev, int resno);
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264resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
265void pci_restore_iov_state(struct pci_dev *dev);
266int pci_iov_bus_range(struct pci_bus *bus);
302b4215 267
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268#else
269static inline int pci_iov_init(struct pci_dev *dev)
270{
271 return -ENODEV;
272}
273static inline void pci_iov_release(struct pci_dev *dev)
274
275{
276}
26ff46c6 277static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno)
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278{
279 return 0;
280}
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281static inline void pci_restore_iov_state(struct pci_dev *dev)
282{
283}
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284static inline int pci_iov_bus_range(struct pci_bus *bus)
285{
286 return 0;
287}
302b4215 288
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289#endif /* CONFIG_PCI_IOV */
290
f39d5b72 291unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c 292
0e52247a 293static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
f39d5b72 294 struct resource *res)
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295{
296#ifdef CONFIG_PCI_IOV
297 int resno = res - dev->resource;
298
299 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
300 return pci_sriov_resource_alignment(dev, resno);
301#endif
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302 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
303 return pci_cardbus_resource_alignment(res);
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304 return resource_alignment(res);
305}
306
f39d5b72 307void pci_enable_acs(struct pci_dev *dev);
ae21ee65 308
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DC
309struct pci_dev_reset_methods {
310 u16 vendor;
311 u16 device;
312 int (*reset)(struct pci_dev *dev, int probe);
313};
314
93177a74 315#ifdef CONFIG_PCI_QUIRKS
f39d5b72 316int pci_dev_specific_reset(struct pci_dev *dev, int probe);
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317#else
318static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
319{
320 return -ENOTTY;
321}
322#endif
b9c3b266 323
557848c3 324#endif /* DRIVERS_PCI_H */
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