[deliverable/linux.git] / drivers / pci / pci.h

#ifndef DRIVERS_PCI_H
#define DRIVERS_PCI_H

#include <linux/workqueue.h>

#define PCI_CFG_SPACE_SIZE	256
#define PCI_CFG_SPACE_EXP_SIZE	4096

/* Functions internal to the PCI core code */

extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
{ return; }
static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
{ return; }
#else
extern void pci_create_firmware_label_files(struct pci_dev *pdev);
extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
#endif
extern void pci_cleanup_rom(struct pci_dev *dev);
#ifdef HAVE_PCI_MMAP
enum pci_mmap_api {
	PCI_MMAP_SYSFS,	/* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	PCI_MMAP_PROCFS	/* mmap on /proc/bus/pci/<BDF> */
};
extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
			 struct vm_area_struct *vmai,
			 enum pci_mmap_api mmap_api);
#endif
int pci_probe_reset_function(struct pci_dev *dev);

/**
 * struct pci_platform_pm_ops - Firmware PM callbacks
 *
 * @is_manageable: returns 'true' if given device is power manageable by the
 *                 platform firmware
 *
 * @set_state: invokes the platform firmware to set the device's power state
 *
 * @choose_state: returns PCI power state of given device preferred by the
 *                platform; to be used during system-wide transitions from a
 *                sleeping state to the working state and vice versa
 *
 * @can_wakeup: returns 'true' if given device is capable of waking up the
 *              system from a sleeping state
 *
 * @sleep_wake: enables/disables the system wake up capability of given device
 *
 * @run_wake: enables/disables the platform to generate run-time wake-up events
 *		for given device (the device's wake-up capability has to be
 *		enabled by @sleep_wake for this feature to work)
 *
 * If given platform is generally capable of power managing PCI devices, all of
 * these callbacks are mandatory.
 */
struct pci_platform_pm_ops {
	bool (*is_manageable)(struct pci_dev *dev);
	int (*set_state)(struct pci_dev *dev, pci_power_t state);
	pci_power_t (*choose_state)(struct pci_dev *dev);
	bool (*can_wakeup)(struct pci_dev *dev);
	int (*sleep_wake)(struct pci_dev *dev, bool enable);
	int (*run_wake)(struct pci_dev *dev, bool enable);
};

extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
extern void pci_power_up(struct pci_dev *dev);
extern void pci_disable_enabled_device(struct pci_dev *dev);
extern int pci_finish_runtime_suspend(struct pci_dev *dev);
extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
extern void pci_wakeup_bus(struct pci_bus *bus);
extern void pci_pm_init(struct pci_dev *dev);
extern void platform_pci_wakeup_init(struct pci_dev *dev);
extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
void pci_free_cap_save_buffers(struct pci_dev *dev);

static inline void pci_wakeup_event(struct pci_dev *dev)
{
	/* Wait 100 ms before the system can be put into a sleep state. */
	pm_wakeup_event(&dev->dev, 100);
}

static inline bool pci_is_bridge(struct pci_dev *pci_dev)
{
	return !!(pci_dev->subordinate);
}

struct pci_vpd_ops {
	ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
	ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
	void (*release)(struct pci_dev *dev);
};

struct pci_vpd {
	unsigned int len;
	const struct pci_vpd_ops *ops;
	struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
};

extern int pci_vpd_pci22_init(struct pci_dev *dev);
static inline void pci_vpd_release(struct pci_dev *dev)
{
	if (dev->vpd)
		dev->vpd->ops->release(dev);
}

/* PCI /proc functions */
#ifdef CONFIG_PROC_FS
extern int pci_proc_attach_device(struct pci_dev *dev);
extern int pci_proc_detach_device(struct pci_dev *dev);
extern int pci_proc_detach_bus(struct pci_bus *bus);
#else
static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
#endif

/* Functions for PCI Hotplug drivers to use */
int pci_hp_add_bridge(struct pci_dev *dev);

#ifdef HAVE_PCI_LEGACY
extern void pci_create_legacy_files(struct pci_bus *bus);
extern void pci_remove_legacy_files(struct pci_bus *bus);
#else
static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
#endif

/* Lock for read/write access to pci device and bus lists */
extern struct rw_semaphore pci_bus_sem;

extern raw_spinlock_t pci_lock;

extern unsigned int pci_pm_d3_delay;

#ifdef CONFIG_PCI_MSI
void pci_no_msi(void);
extern void pci_msi_init_pci_dev(struct pci_dev *dev);
#else
static inline void pci_no_msi(void) { }
static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
#endif

void pci_realloc_get_opt(char *);

static inline int pci_no_d1d2(struct pci_dev *dev)
{
	unsigned int parent_dstates = 0;

	if (dev->bus->self)
		parent_dstates = dev->bus->self->no_d1d2;
	return (dev->no_d1d2 || parent_dstates);

}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute pcibus_dev_attrs[];
#ifdef CONFIG_HOTPLUG
extern struct bus_attribute pci_bus_attrs[];
#else
#define pci_bus_attrs	NULL
#endif


/**
 * pci_match_one_device - Tell if a PCI device structure has a matching
 *                        PCI device id structure
 * @id: single PCI device id structure to match
 * @dev: the PCI device structure to match against
 *
 * Returns the matching pci_device_id structure or %NULL if there is no match.
 */
static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
{
	if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
	    (id->device == PCI_ANY_ID || id->device == dev->device) &&
	    (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
	    (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
	    !((id->class ^ dev->class) & id->class_mask))
		return id;
	return NULL;
}

/* PCI slot sysfs helper code */
#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)

extern struct kset *pci_slots_kset;

struct pci_slot_attribute {
	struct attribute attr;
	ssize_t (*show)(struct pci_slot *, char *);
	ssize_t (*store)(struct pci_slot *, const char *, size_t);
};
#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)

enum pci_bar_type {
	pci_bar_unknown,	/* Standard PCI BAR probe */
	pci_bar_io,		/* An io port BAR */
	pci_bar_mem32,		/* A 32-bit memory BAR */
	pci_bar_mem64,		/* A 64-bit memory BAR */
};

bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
				int crs_timeout);
extern int pci_setup_device(struct pci_dev *dev);
extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
				struct resource *res, unsigned int reg);
extern int pci_resource_bar(struct pci_dev *dev, int resno,
			    enum pci_bar_type *type);
extern int pci_bus_add_child(struct pci_bus *bus);
extern void pci_enable_ari(struct pci_dev *dev);
/**
 * pci_ari_enabled - query ARI forwarding status
 * @bus: the PCI bus
 *
 * Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
 */
static inline int pci_ari_enabled(struct pci_bus *bus)
{
	return bus->self && bus->self->ari_enabled;
}

void pci_reassigndev_resource_alignment(struct pci_dev *dev);
extern void pci_disable_bridge_window(struct pci_dev *dev);

/* Single Root I/O Virtualization */
struct pci_sriov {
	int pos;		/* capability position */
	int nres;		/* number of resources */
	u32 cap;		/* SR-IOV Capabilities */
	u16 ctrl;		/* SR-IOV Control */
	u16 total;		/* total VFs associated with the PF */
	u16 initial;		/* initial VFs associated with the PF */
	u16 nr_virtfn;		/* number of VFs available */
	u16 offset;		/* first VF Routing ID offset */
	u16 stride;		/* following VF stride */
	u32 pgsz;		/* page size for BAR alignment */
	u8 link;		/* Function Dependency Link */
	struct pci_dev *dev;	/* lowest numbered PF */
	struct pci_dev *self;	/* this PF */
	struct mutex lock;	/* lock for VF bus */
	struct work_struct mtask; /* VF Migration task */
	u8 __iomem *mstate;	/* VF Migration State Array */
};

#ifdef CONFIG_PCI_ATS
extern void pci_restore_ats_state(struct pci_dev *dev);
#else
static inline void pci_restore_ats_state(struct pci_dev *dev)
{
}
#endif /* CONFIG_PCI_ATS */

#ifdef CONFIG_PCI_IOV
extern int pci_iov_init(struct pci_dev *dev);
extern void pci_iov_release(struct pci_dev *dev);
extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				enum pci_bar_type *type);
extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
						    int resno);
extern void pci_restore_iov_state(struct pci_dev *dev);
extern int pci_iov_bus_range(struct pci_bus *bus);

#else
static inline int pci_iov_init(struct pci_dev *dev)
{
	return -ENODEV;
}
static inline void pci_iov_release(struct pci_dev *dev)

{
}
static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
				       enum pci_bar_type *type)
{
	return 0;
}
static inline void pci_restore_iov_state(struct pci_dev *dev)
{
}
static inline int pci_iov_bus_range(struct pci_bus *bus)
{
	return 0;
}

#endif /* CONFIG_PCI_IOV */

extern unsigned long pci_cardbus_resource_alignment(struct resource *);

static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
					 struct resource *res)
{
#ifdef CONFIG_PCI_IOV
	int resno = res - dev->resource;

	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
		return pci_sriov_resource_alignment(dev, resno);
#endif
	if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
		return pci_cardbus_resource_alignment(res);
	return resource_alignment(res);
}

extern void pci_enable_acs(struct pci_dev *dev);

struct pci_dev_reset_methods {
	u16 vendor;
	u16 device;
	int (*reset)(struct pci_dev *dev, int probe);
};

#ifdef CONFIG_PCI_QUIRKS
extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
#else
static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
{
	return -ENOTTY;
}
#endif

#endif /* DRIVERS_PCI_H */
Commit	Line	Data
557848c3 ZY	1	#ifndef DRIVERS_PCI_H
	2	#define DRIVERS_PCI_H
	3
74bb1bcc YZ	4	#include <linux/workqueue.h>
74bb1bcc YZ	5
557848c3 ZY	6	#define PCI_CFG_SPACE_SIZE 256
	7	#define PCI_CFG_SPACE_EXP_SIZE 4096
	8
1da177e4 LT	9	/* Functions internal to the PCI core code */
1da177e4 LT	10
7eff2e7a	11	extern int pci_uevent(struct device dev, struct kobj_uevent_env env);
1da177e4 LT	12	extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
1da177e4 LT	13	extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6058989b	14	#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
911e1c9b	15	static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
b879743f	16	{ return; }
911e1c9b	17	static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
b879743f	18	{ return; }
911e1c9b N	19	#else
	20	extern void pci_create_firmware_label_files(struct pci_dev *pdev);
	21	extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
	22	#endif
1da177e4	23	extern void pci_cleanup_rom(struct pci_dev *dev);
9eff02e2	24	#ifdef HAVE_PCI_MMAP
3b519e4e MW	25	enum pci_mmap_api {
	26	PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
	27	PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
	28	};
9eff02e2	29	extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
3b519e4e MW	30	struct vm_area_struct *vmai,
3b519e4e MW	31	enum pci_mmap_api mmap_api);
9eff02e2	32	#endif
711d5779	33	int pci_probe_reset_function(struct pci_dev *dev);
ce5ccdef	34
961d9120	35	/**
b33bfdef	36	* struct pci_platform_pm_ops - Firmware PM callbacks
961d9120	37	*
b33bfdef RD	38	* @is_manageable: returns 'true' if given device is power manageable by the
b33bfdef RD	39	* platform firmware
961d9120	40	*
b33bfdef	41	* @set_state: invokes the platform firmware to set the device's power state
961d9120	42	*
b33bfdef RD	43	* @choose_state: returns PCI power state of given device preferred by the
	44	* platform; to be used during system-wide transitions from a
	45	* sleeping state to the working state and vice versa
961d9120	46	*
b33bfdef RD	47	* @can_wakeup: returns 'true' if given device is capable of waking up the
b33bfdef RD	48	* system from a sleeping state
eb9d0fe4	49	*
b33bfdef	50	* @sleep_wake: enables/disables the system wake up capability of given device
eb9d0fe4	51	*
b67ea761 RW	52	* @run_wake: enables/disables the platform to generate run-time wake-up events
	53	* for given device (the device's wake-up capability has to be
	54	* enabled by @sleep_wake for this feature to work)
	55	*
961d9120 RW	56	* If given platform is generally capable of power managing PCI devices, all of
	57	* these callbacks are mandatory.
	58	*/
	59	struct pci_platform_pm_ops {
	60	bool (is_manageable)(struct pci_dev dev);
	61	int (set_state)(struct pci_dev dev, pci_power_t state);
	62	pci_power_t (choose_state)(struct pci_dev dev);
eb9d0fe4 RW	63	bool (can_wakeup)(struct pci_dev dev);
eb9d0fe4 RW	64	int (sleep_wake)(struct pci_dev dev, bool enable);
b67ea761	65	int (run_wake)(struct pci_dev dev, bool enable);
961d9120 RW	66	};
	67
	68	extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
73410429	69	extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
db288c9c	70	extern void pci_power_up(struct pci_dev *dev);
fa58d305	71	extern void pci_disable_enabled_device(struct pci_dev *dev);
6cbf8214	72	extern int pci_finish_runtime_suspend(struct pci_dev *dev);
b67ea761	73	extern int __pci_pme_wakeup(struct pci_dev dev, void ign);
448bd857	74	extern void pci_wakeup_bus(struct pci_bus *bus);
eb9d0fe4	75	extern void pci_pm_init(struct pci_dev *dev);
eb9c39d0	76	extern void platform_pci_wakeup_init(struct pci_dev *dev);
63f4898a	77	extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
f796841e	78	void pci_free_cap_save_buffers(struct pci_dev *dev);
aa8c6c93	79
b6e335ae RW	80	static inline void pci_wakeup_event(struct pci_dev *dev)
	81	{
	82	/* Wait 100 ms before the system can be put into a sleep state. */
	83	pm_wakeup_event(&dev->dev, 100);
	84	}
	85
aa8c6c93 RW	86	static inline bool pci_is_bridge(struct pci_dev *pci_dev)
	87	{
	88	return !!(pci_dev->subordinate);
	89	}
0f64474b	90
94e61088	91	struct pci_vpd_ops {
287d19ce SH	92	ssize_t (read)(struct pci_dev dev, loff_t pos, size_t count, void *buf);
287d19ce SH	93	ssize_t (write)(struct pci_dev dev, loff_t pos, size_t count, const void *buf);
94e61088 BH	94	void (release)(struct pci_dev dev);
	95	};
	96
	97	struct pci_vpd {
99cb233d	98	unsigned int len;
287d19ce	99	const struct pci_vpd_ops *ops;
94e61088 BH	100	struct bin_attribute attr; / descriptor for sysfs VPD entry */
	101	};
	102
	103	extern int pci_vpd_pci22_init(struct pci_dev *dev);
	104	static inline void pci_vpd_release(struct pci_dev *dev)
	105	{
	106	if (dev->vpd)
	107	dev->vpd->ops->release(dev);
	108	}
	109
1da177e4 LT	110	/* PCI /proc functions */
	111	#ifdef CONFIG_PROC_FS
	112	extern int pci_proc_attach_device(struct pci_dev *dev);
	113	extern int pci_proc_detach_device(struct pci_dev *dev);
1da177e4 LT	114	extern int pci_proc_detach_bus(struct pci_bus *bus);
	115	#else
	116	static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
	117	static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
1da177e4 LT	118	static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
	119	#endif
	120
	121	/* Functions for PCI Hotplug drivers to use */
a8e4b9c1	122	int pci_hp_add_bridge(struct pci_dev *dev);
1da177e4	123
f19aeb1f BH	124	#ifdef HAVE_PCI_LEGACY
f19aeb1f BH	125	extern void pci_create_legacy_files(struct pci_bus *bus);
1da177e4	126	extern void pci_remove_legacy_files(struct pci_bus *bus);
f19aeb1f BH	127	#else
	128	static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
	129	static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
	130	#endif
1da177e4 LT	131
1da177e4 LT	132	/* Lock for read/write access to pci device and bus lists */
d71374da	133	extern struct rw_semaphore pci_bus_sem;
1da177e4	134
a2e27787 JK	135	extern raw_spinlock_t pci_lock;
a2e27787 JK	136
ffadcc2f	137	extern unsigned int pci_pm_d3_delay;
88187dfa	138
4b47b0ee	139	#ifdef CONFIG_PCI_MSI
309e57df	140	void pci_no_msi(void);
4aa9bc95	141	extern void pci_msi_init_pci_dev(struct pci_dev *dev);
4b47b0ee	142	#else
309e57df	143	static inline void pci_no_msi(void) { }
4aa9bc95	144	static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
4b47b0ee	145	#endif
8fed4b65	146
b55438fd	147	void pci_realloc_get_opt(char *);
f483d392	148
ffadcc2f KCA	149	static inline int pci_no_d1d2(struct pci_dev *dev)
	150	{
	151	unsigned int parent_dstates = 0;
4b47b0ee	152
ffadcc2f KCA	153	if (dev->bus->self)
	154	parent_dstates = dev->bus->self->no_d1d2;
	155	return (dev->no_d1d2 \|\| parent_dstates);
	156
	157	}
1da177e4	158	extern struct device_attribute pci_dev_attrs[];
b9d320fc	159	extern struct device_attribute pcibus_dev_attrs[];
705b1aaa AC	160	#ifdef CONFIG_HOTPLUG
	161	extern struct bus_attribute pci_bus_attrs[];
	162	#else
	163	#define pci_bus_attrs NULL
	164	#endif
	165
1da177e4 LT	166
	167	/**
	168	* pci_match_one_device - Tell if a PCI device structure has a matching
	169	* PCI device id structure
	170	* @id: single PCI device id structure to match
	171	* @dev: the PCI device structure to match against
367b09fe	172	*
1da177e4 LT	173	* Returns the matching pci_device_id structure or %NULL if there is no match.
	174	*/
	175	static inline const struct pci_device_id *
	176	pci_match_one_device(const struct pci_device_id id, const struct pci_dev dev)
	177	{
	178	if ((id->vendor == PCI_ANY_ID \|\| id->vendor == dev->vendor) &&
	179	(id->device == PCI_ANY_ID \|\| id->device == dev->device) &&
	180	(id->subvendor == PCI_ANY_ID \|\| id->subvendor == dev->subsystem_vendor) &&
	181	(id->subdevice == PCI_ANY_ID \|\| id->subdevice == dev->subsystem_device) &&
	182	!((id->class ^ dev->class) & id->class_mask))
	183	return id;
	184	return NULL;
	185	}
	186
f46753c5 AC	187	/* PCI slot sysfs helper code */
	188	#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
	189
	190	extern struct kset *pci_slots_kset;
	191
	192	struct pci_slot_attribute {
	193	struct attribute attr;
	194	ssize_t (show)(struct pci_slot , char *);
	195	ssize_t (store)(struct pci_slot , const char *, size_t);
	196	};
	197	#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
	198
0b400c7e YZ	199	enum pci_bar_type {
	200	pci_bar_unknown, /* Standard PCI BAR probe */
	201	pci_bar_io, /* An io port BAR */
	202	pci_bar_mem32, /* A 32-bit memory BAR */
	203	pci_bar_mem64, /* A 64-bit memory BAR */
	204	};
	205
efdc87da YL	206	bool pci_bus_read_dev_vendor_id(struct pci_bus bus, int devfn, u32 pl,
efdc87da YL	207	int crs_timeout);
480b93b7	208	extern int pci_setup_device(struct pci_dev *dev);
0b400c7e YZ	209	extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
0b400c7e YZ	210	struct resource *res, unsigned int reg);
613e7ed6 YZ	211	extern int pci_resource_bar(struct pci_dev *dev, int resno,
613e7ed6 YZ	212	enum pci_bar_type *type);
876e501a	213	extern int pci_bus_add_child(struct pci_bus *bus);
58c3a727 YZ	214	extern void pci_enable_ari(struct pci_dev *dev);
	215	/**
	216	* pci_ari_enabled - query ARI forwarding status
6a49d812	217	* @bus: the PCI bus
58c3a727 YZ	218	*
	219	* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
	220	*/
6a49d812	221	static inline int pci_ari_enabled(struct pci_bus *bus)
58c3a727	222	{
6a49d812	223	return bus->self && bus->self->ari_enabled;
58c3a727 YZ	224	}
58c3a727 YZ	225
2069ecfb	226	void pci_reassigndev_resource_alignment(struct pci_dev *dev);
32a9a682	227	extern void pci_disable_bridge_window(struct pci_dev *dev);
32a9a682	228
d1b054da YZ	229	/* Single Root I/O Virtualization */
	230	struct pci_sriov {
	231	int pos; /* capability position */
	232	int nres; /* number of resources */
	233	u32 cap; /* SR-IOV Capabilities */
	234	u16 ctrl; /* SR-IOV Control */
	235	u16 total; /* total VFs associated with the PF */
dd7cc44d YZ	236	u16 initial; /* initial VFs associated with the PF */
dd7cc44d YZ	237	u16 nr_virtfn; /* number of VFs available */
d1b054da YZ	238	u16 offset; /* first VF Routing ID offset */
	239	u16 stride; /* following VF stride */
	240	u32 pgsz; /* page size for BAR alignment */
	241	u8 link; /* Function Dependency Link */
	242	struct pci_dev dev; / lowest numbered PF */
	243	struct pci_dev self; / this PF */
	244	struct mutex lock; /* lock for VF bus */
74bb1bcc YZ	245	struct work_struct mtask; /* VF Migration task */
74bb1bcc YZ	246	u8 __iomem mstate; / VF Migration State Array */
d1b054da YZ	247	};
d1b054da YZ	248
1900ca13 HX	249	#ifdef CONFIG_PCI_ATS
	250	extern void pci_restore_ats_state(struct pci_dev *dev);
	251	#else
	252	static inline void pci_restore_ats_state(struct pci_dev *dev)
	253	{
	254	}
	255	#endif /* CONFIG_PCI_ATS */
	256
d1b054da YZ	257	#ifdef CONFIG_PCI_IOV
	258	extern int pci_iov_init(struct pci_dev *dev);
	259	extern void pci_iov_release(struct pci_dev *dev);
	260	extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	261	enum pci_bar_type *type);
0e52247a CM	262	extern resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev,
0e52247a CM	263	int resno);
8c5cdb6a	264	extern void pci_restore_iov_state(struct pci_dev *dev);
a28724b0	265	extern int pci_iov_bus_range(struct pci_bus *bus);
302b4215	266
d1b054da YZ	267	#else
	268	static inline int pci_iov_init(struct pci_dev *dev)
	269	{
	270	return -ENODEV;
	271	}
	272	static inline void pci_iov_release(struct pci_dev *dev)
	273
	274	{
	275	}
	276	static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
	277	enum pci_bar_type *type)
	278	{
	279	return 0;
	280	}
8c5cdb6a YZ	281	static inline void pci_restore_iov_state(struct pci_dev *dev)
	282	{
	283	}
a28724b0 YZ	284	static inline int pci_iov_bus_range(struct pci_bus *bus)
	285	{
	286	return 0;
	287	}
302b4215	288
d1b054da YZ	289	#endif /* CONFIG_PCI_IOV */
d1b054da YZ	290
0a2daa1c RP	291	extern unsigned long pci_cardbus_resource_alignment(struct resource *);
0a2daa1c RP	292
0e52247a	293	static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
6faf17f6 CW	294	struct resource *res)
	295	{
	296	#ifdef CONFIG_PCI_IOV
	297	int resno = res - dev->resource;
	298
	299	if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
	300	return pci_sriov_resource_alignment(dev, resno);
	301	#endif
0a2daa1c RP	302	if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0a2daa1c RP	303	return pci_cardbus_resource_alignment(res);
6faf17f6 CW	304	return resource_alignment(res);
	305	}
	306
ae21ee65 AK	307	extern void pci_enable_acs(struct pci_dev *dev);
ae21ee65 AK	308
b9c3b266 DC	309	struct pci_dev_reset_methods {
	310	u16 vendor;
	311	u16 device;
	312	int (reset)(struct pci_dev dev, int probe);
	313	};
	314
93177a74	315	#ifdef CONFIG_PCI_QUIRKS
5b889bf2	316	extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
93177a74 RW	317	#else
	318	static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
	319	{
	320	return -ENOTTY;
	321	}
	322	#endif
b9c3b266	323
557848c3	324	#endif /* DRIVERS_PCI_H */