Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
45e829ea | 3 | * Enabling PCIe link L0s/L1 state and Clock Power Management |
7d715a6c SL |
4 | * |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
ac18018a KK |
29 | /* Note: those are not register definitions */ |
30 | #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */ | |
31 | #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */ | |
32 | #define ASPM_STATE_L1 (4) /* L1 state */ | |
33 | #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW) | |
34 | #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1) | |
35 | ||
b6c2e54d KK |
36 | struct aspm_latency { |
37 | u32 l0s; /* L0s latency (nsec) */ | |
38 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
39 | }; |
40 | ||
41 | struct pcie_link_state { | |
5cde89d8 | 42 | struct pci_dev *pdev; /* Upstream component of the Link */ |
5c92ffb1 | 43 | struct pcie_link_state *root; /* pointer to the root port link */ |
5cde89d8 KK |
44 | struct pcie_link_state *parent; /* pointer to the parent Link state */ |
45 | struct list_head sibling; /* node in link_list */ | |
46 | struct list_head children; /* list of child link states */ | |
47 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
48 | |
49 | /* ASPM state */ | |
ac18018a KK |
50 | u32 aspm_support:3; /* Supported ASPM state */ |
51 | u32 aspm_enabled:3; /* Enabled ASPM state */ | |
52 | u32 aspm_capable:3; /* Capable ASPM state with latency */ | |
53 | u32 aspm_default:3; /* Default ASPM state by BIOS */ | |
54 | u32 aspm_disable:3; /* Disabled ASPM state */ | |
80bfdbe3 | 55 | |
4d246e45 KK |
56 | /* Clock PM state */ |
57 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
58 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
59 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
60 | ||
ac18018a KK |
61 | /* Exit latencies */ |
62 | struct aspm_latency latency_up; /* Upstream direction exit latency */ | |
63 | struct aspm_latency latency_dw; /* Downstream direction exit latency */ | |
7d715a6c | 64 | /* |
b6c2e54d KK |
65 | * Endpoint acceptable latencies. A pcie downstream port only |
66 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 67 | */ |
b6c2e54d | 68 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
69 | }; |
70 | ||
3c076351 | 71 | static int aspm_disabled, aspm_force; |
8b8bae90 | 72 | static bool aspm_support_enabled = true; |
7d715a6c SL |
73 | static DEFINE_MUTEX(aspm_lock); |
74 | static LIST_HEAD(link_list); | |
75 | ||
76 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
77 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
78 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
ad71c962 MG |
79 | |
80 | #ifdef CONFIG_PCIEASPM_PERFORMANCE | |
81 | static int aspm_policy = POLICY_PERFORMANCE; | |
82 | #elif defined CONFIG_PCIEASPM_POWERSAVE | |
83 | static int aspm_policy = POLICY_POWERSAVE; | |
84 | #else | |
7d715a6c | 85 | static int aspm_policy; |
ad71c962 MG |
86 | #endif |
87 | ||
7d715a6c SL |
88 | static const char *policy_str[] = { |
89 | [POLICY_DEFAULT] = "default", | |
90 | [POLICY_PERFORMANCE] = "performance", | |
91 | [POLICY_POWERSAVE] = "powersave" | |
92 | }; | |
93 | ||
987a4c78 AP |
94 | #define LINK_RETRAIN_TIMEOUT HZ |
95 | ||
5aa63583 | 96 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 97 | { |
7d715a6c SL |
98 | switch (aspm_policy) { |
99 | case POLICY_PERFORMANCE: | |
100 | /* Disable ASPM and Clock PM */ | |
101 | return 0; | |
102 | case POLICY_POWERSAVE: | |
103 | /* Enable ASPM L0s/L1 */ | |
ac18018a | 104 | return ASPM_STATE_ALL; |
7d715a6c | 105 | case POLICY_DEFAULT: |
5aa63583 | 106 | return link->aspm_default; |
7d715a6c SL |
107 | } |
108 | return 0; | |
109 | } | |
110 | ||
5aa63583 | 111 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 112 | { |
7d715a6c SL |
113 | switch (aspm_policy) { |
114 | case POLICY_PERFORMANCE: | |
115 | /* Disable ASPM and Clock PM */ | |
116 | return 0; | |
117 | case POLICY_POWERSAVE: | |
118 | /* Disable Clock PM */ | |
119 | return 1; | |
120 | case POLICY_DEFAULT: | |
5aa63583 | 121 | return link->clkpm_default; |
7d715a6c SL |
122 | } |
123 | return 0; | |
124 | } | |
125 | ||
430842e2 | 126 | static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable) |
7d715a6c | 127 | { |
7d715a6c SL |
128 | int pos; |
129 | u16 reg16; | |
5aa63583 KK |
130 | struct pci_dev *child; |
131 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 132 | |
5aa63583 | 133 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 134 | pos = pci_pcie_cap(child); |
7d715a6c SL |
135 | if (!pos) |
136 | return; | |
5aa63583 | 137 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
138 | if (enable) |
139 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
140 | else | |
141 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
5aa63583 | 142 | pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 143 | } |
5aa63583 | 144 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
145 | } |
146 | ||
430842e2 KK |
147 | static void pcie_set_clkpm(struct pcie_link_state *link, int enable) |
148 | { | |
149 | /* Don't enable Clock PM if the link is not Clock PM capable */ | |
150 | if (!link->clkpm_capable && enable) | |
2f671e2d | 151 | enable = 0; |
430842e2 KK |
152 | /* Need nothing if the specified equals to current state */ |
153 | if (link->clkpm_enabled == enable) | |
154 | return; | |
155 | pcie_set_clkpm_nocheck(link, enable); | |
156 | } | |
157 | ||
8d349ace | 158 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 159 | { |
5aa63583 | 160 | int pos, capable = 1, enabled = 1; |
7d715a6c SL |
161 | u32 reg32; |
162 | u16 reg16; | |
5aa63583 KK |
163 | struct pci_dev *child; |
164 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
165 | |
166 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 | 167 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 168 | pos = pci_pcie_cap(child); |
7d715a6c SL |
169 | if (!pos) |
170 | return; | |
5aa63583 | 171 | pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
172 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
173 | capable = 0; | |
174 | enabled = 0; | |
175 | break; | |
176 | } | |
5aa63583 | 177 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
178 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
179 | enabled = 0; | |
180 | } | |
5aa63583 KK |
181 | link->clkpm_enabled = enabled; |
182 | link->clkpm_default = enabled; | |
8d349ace | 183 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
184 | } |
185 | ||
7d715a6c SL |
186 | /* |
187 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
188 | * could use common clock. If they are, configure them to use the | |
189 | * common clock. That will reduce the ASPM state exit latency. | |
190 | */ | |
5aa63583 | 191 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 192 | { |
5aa63583 KK |
193 | int ppos, cpos, same_clock = 1; |
194 | u16 reg16, parent_reg, child_reg[8]; | |
2a42d9db | 195 | unsigned long start_jiffies; |
5aa63583 KK |
196 | struct pci_dev *child, *parent = link->pdev; |
197 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 198 | /* |
5aa63583 | 199 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 200 | * Configuration, so just check one function |
5aa63583 KK |
201 | */ |
202 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
8b06477d | 203 | BUG_ON(!pci_is_pcie(child)); |
7d715a6c SL |
204 | |
205 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
db9538a7 | 206 | cpos = pci_pcie_cap(child); |
5aa63583 | 207 | pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
208 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
209 | same_clock = 0; | |
210 | ||
211 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
db9538a7 | 212 | ppos = pci_pcie_cap(parent); |
5aa63583 | 213 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
214 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
215 | same_clock = 0; | |
216 | ||
217 | /* Configure downstream component, all functions */ | |
5aa63583 | 218 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
db9538a7 | 219 | cpos = pci_pcie_cap(child); |
5aa63583 KK |
220 | pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); |
221 | child_reg[PCI_FUNC(child->devfn)] = reg16; | |
7d715a6c SL |
222 | if (same_clock) |
223 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
224 | else | |
225 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 226 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
227 | } |
228 | ||
229 | /* Configure upstream component */ | |
5aa63583 | 230 | pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); |
2a42d9db | 231 | parent_reg = reg16; |
7d715a6c SL |
232 | if (same_clock) |
233 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
234 | else | |
235 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 236 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 237 | |
5aa63583 | 238 | /* Retrain link */ |
7d715a6c | 239 | reg16 |= PCI_EXP_LNKCTL_RL; |
5aa63583 | 240 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 241 | |
5aa63583 | 242 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 243 | start_jiffies = jiffies; |
987a4c78 | 244 | for (;;) { |
5aa63583 | 245 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
246 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
247 | break; | |
987a4c78 AP |
248 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
249 | break; | |
250 | msleep(1); | |
7d715a6c | 251 | } |
5aa63583 KK |
252 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
253 | return; | |
254 | ||
255 | /* Training failed. Restore common clock configurations */ | |
256 | dev_printk(KERN_ERR, &parent->dev, | |
257 | "ASPM: Could not configure common clock\n"); | |
258 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
db9538a7 | 259 | cpos = pci_pcie_cap(child); |
5aa63583 KK |
260 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, |
261 | child_reg[PCI_FUNC(child->devfn)]); | |
2a42d9db | 262 | } |
5aa63583 | 263 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); |
7d715a6c SL |
264 | } |
265 | ||
5e0eaa7d KK |
266 | /* Convert L0s latency encoding to ns */ |
267 | static u32 calc_l0s_latency(u32 encoding) | |
7d715a6c | 268 | { |
5e0eaa7d KK |
269 | if (encoding == 0x7) |
270 | return (5 * 1000); /* > 4us */ | |
271 | return (64 << encoding); | |
272 | } | |
7d715a6c | 273 | |
5e0eaa7d KK |
274 | /* Convert L0s acceptable latency encoding to ns */ |
275 | static u32 calc_l0s_acceptable(u32 encoding) | |
276 | { | |
277 | if (encoding == 0x7) | |
278 | return -1U; | |
279 | return (64 << encoding); | |
7d715a6c SL |
280 | } |
281 | ||
5e0eaa7d KK |
282 | /* Convert L1 latency encoding to ns */ |
283 | static u32 calc_l1_latency(u32 encoding) | |
7d715a6c | 284 | { |
5e0eaa7d KK |
285 | if (encoding == 0x7) |
286 | return (65 * 1000); /* > 64us */ | |
287 | return (1000 << encoding); | |
288 | } | |
7d715a6c | 289 | |
5e0eaa7d KK |
290 | /* Convert L1 acceptable latency encoding to ns */ |
291 | static u32 calc_l1_acceptable(u32 encoding) | |
292 | { | |
293 | if (encoding == 0x7) | |
294 | return -1U; | |
295 | return (1000 << encoding); | |
7d715a6c SL |
296 | } |
297 | ||
ac18018a KK |
298 | struct aspm_register_info { |
299 | u32 support:2; | |
300 | u32 enabled:2; | |
301 | u32 latency_encoding_l0s; | |
302 | u32 latency_encoding_l1; | |
303 | }; | |
304 | ||
305 | static void pcie_get_aspm_reg(struct pci_dev *pdev, | |
306 | struct aspm_register_info *info) | |
7d715a6c SL |
307 | { |
308 | int pos; | |
309 | u16 reg16; | |
ac18018a | 310 | u32 reg32; |
7d715a6c | 311 | |
db9538a7 | 312 | pos = pci_pcie_cap(pdev); |
7d715a6c | 313 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); |
ac18018a | 314 | info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; |
ac18018a KK |
315 | info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; |
316 | info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
7d715a6c | 317 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); |
ac18018a | 318 | info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC; |
7d715a6c SL |
319 | } |
320 | ||
07d92760 KK |
321 | static void pcie_aspm_check_latency(struct pci_dev *endpoint) |
322 | { | |
ac18018a | 323 | u32 latency, l1_switch_latency = 0; |
07d92760 KK |
324 | struct aspm_latency *acceptable; |
325 | struct pcie_link_state *link; | |
326 | ||
327 | /* Device not in D0 doesn't need latency check */ | |
328 | if ((endpoint->current_state != PCI_D0) && | |
329 | (endpoint->current_state != PCI_UNKNOWN)) | |
330 | return; | |
331 | ||
332 | link = endpoint->bus->self->link_state; | |
333 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
334 | ||
335 | while (link) { | |
ac18018a KK |
336 | /* Check upstream direction L0s latency */ |
337 | if ((link->aspm_capable & ASPM_STATE_L0S_UP) && | |
338 | (link->latency_up.l0s > acceptable->l0s)) | |
339 | link->aspm_capable &= ~ASPM_STATE_L0S_UP; | |
340 | ||
341 | /* Check downstream direction L0s latency */ | |
342 | if ((link->aspm_capable & ASPM_STATE_L0S_DW) && | |
343 | (link->latency_dw.l0s > acceptable->l0s)) | |
344 | link->aspm_capable &= ~ASPM_STATE_L0S_DW; | |
07d92760 KK |
345 | /* |
346 | * Check L1 latency. | |
347 | * Every switch on the path to root complex need 1 | |
348 | * more microsecond for L1. Spec doesn't mention L0s. | |
349 | */ | |
ac18018a KK |
350 | latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1); |
351 | if ((link->aspm_capable & ASPM_STATE_L1) && | |
352 | (latency + l1_switch_latency > acceptable->l1)) | |
353 | link->aspm_capable &= ~ASPM_STATE_L1; | |
07d92760 KK |
354 | l1_switch_latency += 1000; |
355 | ||
356 | link = link->parent; | |
357 | } | |
358 | } | |
359 | ||
8d349ace | 360 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 361 | { |
5aa63583 KK |
362 | struct pci_dev *child, *parent = link->pdev; |
363 | struct pci_bus *linkbus = parent->subordinate; | |
ac18018a | 364 | struct aspm_register_info upreg, dwreg; |
7d715a6c | 365 | |
8d349ace | 366 | if (blacklist) { |
f1c0ca29 | 367 | /* Set enabled/disable so that we will disable ASPM later */ |
ac18018a KK |
368 | link->aspm_enabled = ASPM_STATE_ALL; |
369 | link->aspm_disable = ASPM_STATE_ALL; | |
8d349ace KK |
370 | return; |
371 | } | |
372 | ||
373 | /* Configure common clock before checking latencies */ | |
374 | pcie_aspm_configure_common_clock(link); | |
375 | ||
ac18018a KK |
376 | /* Get upstream/downstream components' register state */ |
377 | pcie_get_aspm_reg(parent, &upreg); | |
5aa63583 | 378 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
ac18018a KK |
379 | pcie_get_aspm_reg(child, &dwreg); |
380 | ||
381 | /* | |
382 | * Setup L0s state | |
383 | * | |
384 | * Note that we must not enable L0s in either direction on a | |
385 | * given link unless components on both sides of the link each | |
386 | * support L0s. | |
387 | */ | |
388 | if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S) | |
389 | link->aspm_support |= ASPM_STATE_L0S; | |
390 | if (dwreg.enabled & PCIE_LINK_STATE_L0S) | |
391 | link->aspm_enabled |= ASPM_STATE_L0S_UP; | |
392 | if (upreg.enabled & PCIE_LINK_STATE_L0S) | |
393 | link->aspm_enabled |= ASPM_STATE_L0S_DW; | |
394 | link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s); | |
395 | link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s); | |
396 | ||
397 | /* Setup L1 state */ | |
398 | if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1) | |
399 | link->aspm_support |= ASPM_STATE_L1; | |
400 | if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1) | |
401 | link->aspm_enabled |= ASPM_STATE_L1; | |
402 | link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1); | |
403 | link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1); | |
5aa63583 | 404 | |
b127bd55 KK |
405 | /* Save default state */ |
406 | link->aspm_default = link->aspm_enabled; | |
07d92760 KK |
407 | |
408 | /* Setup initial capable state. Will be updated later */ | |
409 | link->aspm_capable = link->aspm_support; | |
f1c0ca29 KK |
410 | /* |
411 | * If the downstream component has pci bridge function, don't | |
412 | * do ASPM for now. | |
413 | */ | |
414 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
415 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { | |
ac18018a | 416 | link->aspm_disable = ASPM_STATE_ALL; |
f1c0ca29 KK |
417 | break; |
418 | } | |
419 | } | |
b127bd55 | 420 | |
b7206cbf | 421 | /* Get and check endpoint acceptable latencies */ |
5aa63583 | 422 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c | 423 | int pos; |
5e0eaa7d | 424 | u32 reg32, encoding; |
b6c2e54d | 425 | struct aspm_latency *acceptable = |
5aa63583 | 426 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 427 | |
5aa63583 KK |
428 | if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && |
429 | child->pcie_type != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
430 | continue; |
431 | ||
db9538a7 | 432 | pos = pci_pcie_cap(child); |
5aa63583 | 433 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
07d92760 | 434 | /* Calculate endpoint L0s acceptable latency */ |
5e0eaa7d KK |
435 | encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
436 | acceptable->l0s = calc_l0s_acceptable(encoding); | |
07d92760 KK |
437 | /* Calculate endpoint L1 acceptable latency */ |
438 | encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
439 | acceptable->l1 = calc_l1_acceptable(encoding); | |
440 | ||
441 | pcie_aspm_check_latency(child); | |
7d715a6c SL |
442 | } |
443 | } | |
444 | ||
ac18018a | 445 | static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) |
7d715a6c SL |
446 | { |
447 | u16 reg16; | |
db9538a7 | 448 | int pos = pci_pcie_cap(pdev); |
7d715a6c SL |
449 | |
450 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
451 | reg16 &= ~0x3; | |
ac18018a | 452 | reg16 |= val; |
7d715a6c SL |
453 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); |
454 | } | |
455 | ||
b7206cbf | 456 | static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 457 | { |
ac18018a | 458 | u32 upstream = 0, dwstream = 0; |
5aa63583 KK |
459 | struct pci_dev *child, *parent = link->pdev; |
460 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 461 | |
f1c0ca29 | 462 | /* Nothing to do if the link is already in the requested state */ |
b7206cbf | 463 | state &= (link->aspm_capable & ~link->aspm_disable); |
f1c0ca29 KK |
464 | if (link->aspm_enabled == state) |
465 | return; | |
ac18018a KK |
466 | /* Convert ASPM state to upstream/downstream ASPM register state */ |
467 | if (state & ASPM_STATE_L0S_UP) | |
468 | dwstream |= PCIE_LINK_STATE_L0S; | |
469 | if (state & ASPM_STATE_L0S_DW) | |
470 | upstream |= PCIE_LINK_STATE_L0S; | |
471 | if (state & ASPM_STATE_L1) { | |
472 | upstream |= PCIE_LINK_STATE_L1; | |
473 | dwstream |= PCIE_LINK_STATE_L1; | |
474 | } | |
7d715a6c | 475 | /* |
5aa63583 KK |
476 | * Spec 2.0 suggests all functions should be configured the |
477 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
478 | * upstream component first and then downstream, and vice | |
479 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c | 480 | */ |
ac18018a KK |
481 | if (state & ASPM_STATE_L1) |
482 | pcie_config_aspm_dev(parent, upstream); | |
5aa63583 | 483 | list_for_each_entry(child, &linkbus->devices, bus_list) |
ac18018a KK |
484 | pcie_config_aspm_dev(child, dwstream); |
485 | if (!(state & ASPM_STATE_L1)) | |
486 | pcie_config_aspm_dev(parent, upstream); | |
7d715a6c | 487 | |
5aa63583 | 488 | link->aspm_enabled = state; |
7d715a6c SL |
489 | } |
490 | ||
b7206cbf | 491 | static void pcie_config_aspm_path(struct pcie_link_state *link) |
7d715a6c | 492 | { |
b7206cbf KK |
493 | while (link) { |
494 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
495 | link = link->parent; | |
46bbdfa4 | 496 | } |
7d715a6c SL |
497 | } |
498 | ||
5aa63583 | 499 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 500 | { |
5aa63583 KK |
501 | link->pdev->link_state = NULL; |
502 | kfree(link); | |
7d715a6c SL |
503 | } |
504 | ||
ddc9753f SL |
505 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
506 | { | |
3647584d KK |
507 | struct pci_dev *child; |
508 | int pos; | |
149e1637 | 509 | u32 reg32; |
2f671e2d | 510 | |
4949be16 MG |
511 | if (aspm_disabled) |
512 | return 0; | |
513 | ||
ddc9753f | 514 | /* |
45e829ea | 515 | * Some functions in a slot might not all be PCIe functions, |
3647584d | 516 | * very strange. Disable ASPM for the whole slot |
ddc9753f | 517 | */ |
3647584d | 518 | list_for_each_entry(child, &pdev->subordinate->devices, bus_list) { |
db9538a7 | 519 | pos = pci_pcie_cap(child); |
3647584d | 520 | if (!pos) |
ddc9753f | 521 | return -EINVAL; |
149e1637 SL |
522 | /* |
523 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
524 | * RBER bit to determine if a function is 1.1 version device | |
525 | */ | |
3647584d | 526 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); |
e1f4f59d | 527 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
3647584d | 528 | dev_printk(KERN_INFO, &child->dev, "disabling ASPM" |
f393d9b1 VL |
529 | " on pre-1.1 PCIe device. You can enable it" |
530 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
531 | return -EINVAL; |
532 | } | |
ddc9753f SL |
533 | } |
534 | return 0; | |
535 | } | |
536 | ||
b7206cbf | 537 | static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev) |
8d349ace KK |
538 | { |
539 | struct pcie_link_state *link; | |
8d349ace KK |
540 | |
541 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
542 | if (!link) | |
543 | return NULL; | |
544 | INIT_LIST_HEAD(&link->sibling); | |
545 | INIT_LIST_HEAD(&link->children); | |
546 | INIT_LIST_HEAD(&link->link); | |
547 | link->pdev = pdev; | |
8d349ace KK |
548 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { |
549 | struct pcie_link_state *parent; | |
550 | parent = pdev->bus->parent->self->link_state; | |
551 | if (!parent) { | |
552 | kfree(link); | |
553 | return NULL; | |
554 | } | |
555 | link->parent = parent; | |
556 | list_add(&link->link, &parent->children); | |
557 | } | |
5c92ffb1 KK |
558 | /* Setup a pointer to the root port link */ |
559 | if (!link->parent) | |
560 | link->root = link; | |
561 | else | |
562 | link->root = link->parent->root; | |
563 | ||
8d349ace | 564 | list_add(&link->sibling, &link_list); |
8d349ace | 565 | pdev->link_state = link; |
8d349ace KK |
566 | return link; |
567 | } | |
568 | ||
7d715a6c SL |
569 | /* |
570 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
571 | * It is called after the pcie and its children devices are scaned. | |
572 | * @pdev: the root port or switch downstream port | |
573 | */ | |
574 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
575 | { | |
8d349ace | 576 | struct pcie_link_state *link; |
b7206cbf | 577 | int blacklist = !!pcie_aspm_sanity_check(pdev); |
7d715a6c | 578 | |
2f671e2d | 579 | if (!pci_is_pcie(pdev) || pdev->link_state) |
7d715a6c SL |
580 | return; |
581 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 582 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) |
7d715a6c | 583 | return; |
8d349ace | 584 | |
8e822df7 SL |
585 | /* VIA has a strange chipset, root port is under a bridge */ |
586 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 587 | pdev->bus->self) |
8e822df7 | 588 | return; |
8d349ace | 589 | |
7d715a6c SL |
590 | down_read(&pci_bus_sem); |
591 | if (list_empty(&pdev->subordinate->devices)) | |
592 | goto out; | |
593 | ||
594 | mutex_lock(&aspm_lock); | |
b7206cbf | 595 | link = alloc_pcie_link_state(pdev); |
8d349ace KK |
596 | if (!link) |
597 | goto unlock; | |
598 | /* | |
b7206cbf KK |
599 | * Setup initial ASPM state. Note that we need to configure |
600 | * upstream links also because capable state of them can be | |
601 | * update through pcie_aspm_cap_init(). | |
8d349ace | 602 | */ |
b7206cbf | 603 | pcie_aspm_cap_init(link, blacklist); |
7d715a6c | 604 | |
8d349ace | 605 | /* Setup initial Clock PM state */ |
b7206cbf | 606 | pcie_clkpm_cap_init(link, blacklist); |
41cd766b MG |
607 | |
608 | /* | |
609 | * At this stage drivers haven't had an opportunity to change the | |
610 | * link policy setting. Enabling ASPM on broken hardware can cripple | |
611 | * it even before the driver has had a chance to disable ASPM, so | |
612 | * default to a safe level right now. If we're enabling ASPM beyond | |
613 | * the BIOS's expectation, we'll do so once pci_enable_device() is | |
614 | * called. | |
615 | */ | |
3c076351 | 616 | if (aspm_policy != POLICY_POWERSAVE) { |
41cd766b MG |
617 | pcie_config_aspm_path(link); |
618 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
619 | } | |
620 | ||
8d349ace | 621 | unlock: |
7d715a6c SL |
622 | mutex_unlock(&aspm_lock); |
623 | out: | |
624 | up_read(&pci_bus_sem); | |
625 | } | |
626 | ||
07d92760 KK |
627 | /* Recheck latencies and update aspm_capable for links under the root */ |
628 | static void pcie_update_aspm_capable(struct pcie_link_state *root) | |
629 | { | |
630 | struct pcie_link_state *link; | |
631 | BUG_ON(root->parent); | |
632 | list_for_each_entry(link, &link_list, sibling) { | |
633 | if (link->root != root) | |
634 | continue; | |
635 | link->aspm_capable = link->aspm_support; | |
636 | } | |
637 | list_for_each_entry(link, &link_list, sibling) { | |
638 | struct pci_dev *child; | |
639 | struct pci_bus *linkbus = link->pdev->subordinate; | |
640 | if (link->root != root) | |
641 | continue; | |
642 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
643 | if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT) && | |
644 | (child->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
645 | continue; | |
646 | pcie_aspm_check_latency(child); | |
647 | } | |
648 | } | |
649 | } | |
650 | ||
7d715a6c SL |
651 | /* @pdev: the endpoint device */ |
652 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
653 | { | |
654 | struct pci_dev *parent = pdev->bus->self; | |
b7206cbf | 655 | struct pcie_link_state *link, *root, *parent_link; |
7d715a6c | 656 | |
3c076351 | 657 | if (!pci_is_pcie(pdev) || !parent || !parent->link_state) |
7d715a6c | 658 | return; |
b7206cbf KK |
659 | if ((parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && |
660 | (parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c | 661 | return; |
fc87e919 | 662 | |
7d715a6c SL |
663 | down_read(&pci_bus_sem); |
664 | mutex_lock(&aspm_lock); | |
7d715a6c SL |
665 | /* |
666 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 667 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 668 | */ |
3419c75e | 669 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
670 | goto out; |
671 | ||
fc87e919 | 672 | link = parent->link_state; |
07d92760 | 673 | root = link->root; |
b7206cbf | 674 | parent_link = link->parent; |
fc87e919 | 675 | |
7d715a6c | 676 | /* All functions are removed, so just disable ASPM for the link */ |
b7206cbf | 677 | pcie_config_aspm_link(link, 0); |
fc87e919 KK |
678 | list_del(&link->sibling); |
679 | list_del(&link->link); | |
7d715a6c | 680 | /* Clock PM is for endpoint device */ |
fc87e919 | 681 | free_link_state(link); |
07d92760 KK |
682 | |
683 | /* Recheck latencies and configure upstream links */ | |
b26a34aa KK |
684 | if (parent_link) { |
685 | pcie_update_aspm_capable(root); | |
686 | pcie_config_aspm_path(parent_link); | |
687 | } | |
7d715a6c SL |
688 | out: |
689 | mutex_unlock(&aspm_lock); | |
690 | up_read(&pci_bus_sem); | |
691 | } | |
692 | ||
693 | /* @pdev: the root port or switch downstream port */ | |
694 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
695 | { | |
07d92760 | 696 | struct pcie_link_state *link = pdev->link_state; |
7d715a6c | 697 | |
8b06477d | 698 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) |
7d715a6c | 699 | return; |
07d92760 KK |
700 | if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && |
701 | (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
7d715a6c SL |
702 | return; |
703 | /* | |
07d92760 KK |
704 | * Devices changed PM state, we should recheck if latency |
705 | * meets all functions' requirement | |
7d715a6c | 706 | */ |
07d92760 KK |
707 | down_read(&pci_bus_sem); |
708 | mutex_lock(&aspm_lock); | |
709 | pcie_update_aspm_capable(link->root); | |
b7206cbf | 710 | pcie_config_aspm_path(link); |
07d92760 KK |
711 | mutex_unlock(&aspm_lock); |
712 | up_read(&pci_bus_sem); | |
7d715a6c SL |
713 | } |
714 | ||
1a680b7c NC |
715 | void pcie_aspm_powersave_config_link(struct pci_dev *pdev) |
716 | { | |
717 | struct pcie_link_state *link = pdev->link_state; | |
718 | ||
719 | if (aspm_disabled || !pci_is_pcie(pdev) || !link) | |
720 | return; | |
721 | ||
722 | if (aspm_policy != POLICY_POWERSAVE) | |
723 | return; | |
724 | ||
725 | if ((pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) && | |
726 | (pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) | |
727 | return; | |
728 | ||
729 | down_read(&pci_bus_sem); | |
730 | mutex_lock(&aspm_lock); | |
731 | pcie_config_aspm_path(link); | |
732 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
733 | mutex_unlock(&aspm_lock); | |
734 | up_read(&pci_bus_sem); | |
735 | } | |
736 | ||
7d715a6c SL |
737 | /* |
738 | * pci_disable_link_state - disable pci device's link state, so the link will | |
739 | * never enter specific states | |
740 | */ | |
3c076351 MG |
741 | static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem, |
742 | bool force) | |
7d715a6c SL |
743 | { |
744 | struct pci_dev *parent = pdev->bus->self; | |
f1c0ca29 | 745 | struct pcie_link_state *link; |
7d715a6c | 746 | |
3c076351 MG |
747 | if (aspm_disabled && !force) |
748 | return; | |
749 | ||
750 | if (!pci_is_pcie(pdev)) | |
7d715a6c | 751 | return; |
3c076351 | 752 | |
7d715a6c SL |
753 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || |
754 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
755 | parent = pdev; | |
756 | if (!parent || !parent->link_state) | |
757 | return; | |
758 | ||
9f728f53 YL |
759 | if (sem) |
760 | down_read(&pci_bus_sem); | |
7d715a6c | 761 | mutex_lock(&aspm_lock); |
f1c0ca29 | 762 | link = parent->link_state; |
ac18018a KK |
763 | if (state & PCIE_LINK_STATE_L0S) |
764 | link->aspm_disable |= ASPM_STATE_L0S; | |
765 | if (state & PCIE_LINK_STATE_L1) | |
766 | link->aspm_disable |= ASPM_STATE_L1; | |
b7206cbf KK |
767 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); |
768 | ||
430842e2 | 769 | if (state & PCIE_LINK_STATE_CLKPM) { |
f1c0ca29 KK |
770 | link->clkpm_capable = 0; |
771 | pcie_set_clkpm(link, 0); | |
430842e2 | 772 | } |
7d715a6c | 773 | mutex_unlock(&aspm_lock); |
9f728f53 YL |
774 | if (sem) |
775 | up_read(&pci_bus_sem); | |
776 | } | |
777 | ||
778 | void pci_disable_link_state_locked(struct pci_dev *pdev, int state) | |
779 | { | |
3c076351 | 780 | __pci_disable_link_state(pdev, state, false, false); |
9f728f53 YL |
781 | } |
782 | EXPORT_SYMBOL(pci_disable_link_state_locked); | |
783 | ||
784 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
785 | { | |
3c076351 | 786 | __pci_disable_link_state(pdev, state, true, false); |
7d715a6c SL |
787 | } |
788 | EXPORT_SYMBOL(pci_disable_link_state); | |
789 | ||
3c076351 MG |
790 | void pcie_clear_aspm(struct pci_bus *bus) |
791 | { | |
792 | struct pci_dev *child; | |
793 | ||
794 | /* | |
795 | * Clear any ASPM setup that the firmware has carried out on this bus | |
796 | */ | |
797 | list_for_each_entry(child, &bus->devices, bus_list) { | |
798 | __pci_disable_link_state(child, PCIE_LINK_STATE_L0S | | |
799 | PCIE_LINK_STATE_L1 | | |
800 | PCIE_LINK_STATE_CLKPM, | |
801 | false, true); | |
802 | } | |
803 | } | |
804 | ||
7d715a6c SL |
805 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) |
806 | { | |
807 | int i; | |
b7206cbf | 808 | struct pcie_link_state *link; |
7d715a6c | 809 | |
bbfa306a NC |
810 | if (aspm_disabled) |
811 | return -EPERM; | |
7d715a6c SL |
812 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) |
813 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
814 | break; | |
815 | if (i >= ARRAY_SIZE(policy_str)) | |
816 | return -EINVAL; | |
817 | if (i == aspm_policy) | |
818 | return 0; | |
819 | ||
820 | down_read(&pci_bus_sem); | |
821 | mutex_lock(&aspm_lock); | |
822 | aspm_policy = i; | |
b7206cbf KK |
823 | list_for_each_entry(link, &link_list, sibling) { |
824 | pcie_config_aspm_link(link, policy_to_aspm_state(link)); | |
825 | pcie_set_clkpm(link, policy_to_clkpm_state(link)); | |
7d715a6c SL |
826 | } |
827 | mutex_unlock(&aspm_lock); | |
828 | up_read(&pci_bus_sem); | |
829 | return 0; | |
830 | } | |
831 | ||
832 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
833 | { | |
834 | int i, cnt = 0; | |
835 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
836 | if (i == aspm_policy) | |
837 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
838 | else | |
839 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
840 | return cnt; | |
841 | } | |
842 | ||
843 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
844 | NULL, 0644); | |
845 | ||
846 | #ifdef CONFIG_PCIEASPM_DEBUG | |
847 | static ssize_t link_state_show(struct device *dev, | |
848 | struct device_attribute *attr, | |
849 | char *buf) | |
850 | { | |
851 | struct pci_dev *pci_device = to_pci_dev(dev); | |
852 | struct pcie_link_state *link_state = pci_device->link_state; | |
853 | ||
80bfdbe3 | 854 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
855 | } |
856 | ||
857 | static ssize_t link_state_store(struct device *dev, | |
858 | struct device_attribute *attr, | |
859 | const char *buf, | |
860 | size_t n) | |
861 | { | |
5aa63583 | 862 | struct pci_dev *pdev = to_pci_dev(dev); |
b7206cbf | 863 | struct pcie_link_state *link, *root = pdev->link_state->root; |
ac18018a | 864 | u32 val = buf[0] - '0', state = 0; |
7d715a6c | 865 | |
bbfa306a NC |
866 | if (aspm_disabled) |
867 | return -EPERM; | |
ac18018a | 868 | if (n < 1 || val > 3) |
7d715a6c | 869 | return -EINVAL; |
7d715a6c | 870 | |
ac18018a KK |
871 | /* Convert requested state to ASPM state */ |
872 | if (val & PCIE_LINK_STATE_L0S) | |
873 | state |= ASPM_STATE_L0S; | |
874 | if (val & PCIE_LINK_STATE_L1) | |
875 | state |= ASPM_STATE_L1; | |
876 | ||
b7206cbf KK |
877 | down_read(&pci_bus_sem); |
878 | mutex_lock(&aspm_lock); | |
879 | list_for_each_entry(link, &link_list, sibling) { | |
880 | if (link->root != root) | |
881 | continue; | |
882 | pcie_config_aspm_link(link, state); | |
883 | } | |
884 | mutex_unlock(&aspm_lock); | |
885 | up_read(&pci_bus_sem); | |
886 | return n; | |
7d715a6c SL |
887 | } |
888 | ||
889 | static ssize_t clk_ctl_show(struct device *dev, | |
890 | struct device_attribute *attr, | |
891 | char *buf) | |
892 | { | |
893 | struct pci_dev *pci_device = to_pci_dev(dev); | |
894 | struct pcie_link_state *link_state = pci_device->link_state; | |
895 | ||
4d246e45 | 896 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
897 | } |
898 | ||
899 | static ssize_t clk_ctl_store(struct device *dev, | |
900 | struct device_attribute *attr, | |
901 | const char *buf, | |
902 | size_t n) | |
903 | { | |
430842e2 | 904 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
905 | int state; |
906 | ||
907 | if (n < 1) | |
908 | return -EINVAL; | |
909 | state = buf[0]-'0'; | |
910 | ||
911 | down_read(&pci_bus_sem); | |
912 | mutex_lock(&aspm_lock); | |
430842e2 | 913 | pcie_set_clkpm_nocheck(pdev->link_state, !!state); |
7d715a6c SL |
914 | mutex_unlock(&aspm_lock); |
915 | up_read(&pci_bus_sem); | |
916 | ||
917 | return n; | |
918 | } | |
919 | ||
920 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
921 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
922 | ||
923 | static char power_group[] = "power"; | |
924 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
925 | { | |
926 | struct pcie_link_state *link_state = pdev->link_state; | |
927 | ||
8b06477d KK |
928 | if (!pci_is_pcie(pdev) || |
929 | (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
930 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
931 | return; |
932 | ||
80bfdbe3 | 933 | if (link_state->aspm_support) |
7d715a6c SL |
934 | sysfs_add_file_to_group(&pdev->dev.kobj, |
935 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 936 | if (link_state->clkpm_capable) |
7d715a6c SL |
937 | sysfs_add_file_to_group(&pdev->dev.kobj, |
938 | &dev_attr_clk_ctl.attr, power_group); | |
939 | } | |
940 | ||
941 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
942 | { | |
943 | struct pcie_link_state *link_state = pdev->link_state; | |
944 | ||
8b06477d KK |
945 | if (!pci_is_pcie(pdev) || |
946 | (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
947 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
7d715a6c SL |
948 | return; |
949 | ||
80bfdbe3 | 950 | if (link_state->aspm_support) |
7d715a6c SL |
951 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
952 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 953 | if (link_state->clkpm_capable) |
7d715a6c SL |
954 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
955 | &dev_attr_clk_ctl.attr, power_group); | |
956 | } | |
957 | #endif | |
958 | ||
959 | static int __init pcie_aspm_disable(char *str) | |
960 | { | |
d6d38574 | 961 | if (!strcmp(str, "off")) { |
3c076351 | 962 | aspm_policy = POLICY_DEFAULT; |
d6d38574 | 963 | aspm_disabled = 1; |
8b8bae90 | 964 | aspm_support_enabled = false; |
d6d38574 SL |
965 | printk(KERN_INFO "PCIe ASPM is disabled\n"); |
966 | } else if (!strcmp(str, "force")) { | |
967 | aspm_force = 1; | |
8072ba1b | 968 | printk(KERN_INFO "PCIe ASPM is forcibly enabled\n"); |
d6d38574 | 969 | } |
7d715a6c SL |
970 | return 1; |
971 | } | |
972 | ||
d6d38574 | 973 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 974 | |
5fde244d SL |
975 | void pcie_no_aspm(void) |
976 | { | |
3c076351 MG |
977 | /* |
978 | * Disabling ASPM is intended to prevent the kernel from modifying | |
979 | * existing hardware state, not to clear existing state. To that end: | |
980 | * (a) set policy to POLICY_DEFAULT in order to avoid changing state | |
981 | * (b) prevent userspace from changing policy | |
982 | */ | |
983 | if (!aspm_force) { | |
984 | aspm_policy = POLICY_DEFAULT; | |
d6d38574 | 985 | aspm_disabled = 1; |
3c076351 | 986 | } |
5fde244d SL |
987 | } |
988 | ||
3e1b1600 AP |
989 | /** |
990 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
991 | * | |
992 | * Returns true if ASPM has not been disabled by the command-line option | |
993 | * pcie_aspm=off. | |
994 | **/ | |
995 | int pcie_aspm_enabled(void) | |
7d715a6c | 996 | { |
3e1b1600 | 997 | return !aspm_disabled; |
7d715a6c | 998 | } |
3e1b1600 | 999 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 1000 | |
8b8bae90 RW |
1001 | bool pcie_aspm_support_enabled(void) |
1002 | { | |
1003 | return aspm_support_enabled; | |
1004 | } | |
1005 | EXPORT_SYMBOL(pcie_aspm_support_enabled); |