Commit | Line | Data |
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7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
3 | * Enabling PCIE link L0s/L1 state and Clock Power Management | |
4 | * | |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
7d715a6c SL |
20 | #include <linux/pci-aspm.h> |
21 | #include "../pci.h" | |
22 | ||
23 | #ifdef MODULE_PARAM_PREFIX | |
24 | #undef MODULE_PARAM_PREFIX | |
25 | #endif | |
26 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
27 | ||
28 | struct endpoint_state { | |
29 | unsigned int l0s_acceptable_latency; | |
30 | unsigned int l1_acceptable_latency; | |
31 | }; | |
32 | ||
33 | struct pcie_link_state { | |
34 | struct list_head sibiling; | |
35 | struct pci_dev *pdev; | |
46bbdfa4 SL |
36 | bool downstream_has_switch; |
37 | ||
38 | struct pcie_link_state *parent; | |
39 | struct list_head children; | |
40 | struct list_head link; | |
7d715a6c SL |
41 | |
42 | /* ASPM state */ | |
43 | unsigned int support_state; | |
44 | unsigned int enabled_state; | |
45 | unsigned int bios_aspm_state; | |
46 | /* upstream component */ | |
47 | unsigned int l0s_upper_latency; | |
48 | unsigned int l1_upper_latency; | |
49 | /* downstream component */ | |
50 | unsigned int l0s_down_latency; | |
51 | unsigned int l1_down_latency; | |
52 | /* Clock PM state*/ | |
53 | unsigned int clk_pm_capable; | |
54 | unsigned int clk_pm_enabled; | |
55 | unsigned int bios_clk_state; | |
56 | ||
57 | /* | |
58 | * A pcie downstream port only has one slot under it, so at most there | |
59 | * are 8 functions | |
60 | */ | |
61 | struct endpoint_state endpoints[8]; | |
62 | }; | |
63 | ||
d6d38574 | 64 | static int aspm_disabled, aspm_force; |
7d715a6c SL |
65 | static DEFINE_MUTEX(aspm_lock); |
66 | static LIST_HEAD(link_list); | |
67 | ||
68 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
69 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
70 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
71 | static int aspm_policy; | |
72 | static const char *policy_str[] = { | |
73 | [POLICY_DEFAULT] = "default", | |
74 | [POLICY_PERFORMANCE] = "performance", | |
75 | [POLICY_POWERSAVE] = "powersave" | |
76 | }; | |
77 | ||
78 | static int policy_to_aspm_state(struct pci_dev *pdev) | |
79 | { | |
80 | struct pcie_link_state *link_state = pdev->link_state; | |
81 | ||
82 | switch (aspm_policy) { | |
83 | case POLICY_PERFORMANCE: | |
84 | /* Disable ASPM and Clock PM */ | |
85 | return 0; | |
86 | case POLICY_POWERSAVE: | |
87 | /* Enable ASPM L0s/L1 */ | |
88 | return PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1; | |
89 | case POLICY_DEFAULT: | |
90 | return link_state->bios_aspm_state; | |
91 | } | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static int policy_to_clkpm_state(struct pci_dev *pdev) | |
96 | { | |
97 | struct pcie_link_state *link_state = pdev->link_state; | |
98 | ||
99 | switch (aspm_policy) { | |
100 | case POLICY_PERFORMANCE: | |
101 | /* Disable ASPM and Clock PM */ | |
102 | return 0; | |
103 | case POLICY_POWERSAVE: | |
104 | /* Disable Clock PM */ | |
105 | return 1; | |
106 | case POLICY_DEFAULT: | |
107 | return link_state->bios_clk_state; | |
108 | } | |
109 | return 0; | |
110 | } | |
111 | ||
112 | static void pcie_set_clock_pm(struct pci_dev *pdev, int enable) | |
113 | { | |
114 | struct pci_dev *child_dev; | |
115 | int pos; | |
116 | u16 reg16; | |
117 | struct pcie_link_state *link_state = pdev->link_state; | |
118 | ||
119 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
120 | pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
121 | if (!pos) | |
122 | return; | |
123 | pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16); | |
124 | if (enable) | |
125 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
126 | else | |
127 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
128 | pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16); | |
129 | } | |
130 | link_state->clk_pm_enabled = !!enable; | |
131 | } | |
132 | ||
46bbdfa4 | 133 | static void pcie_check_clock_pm(struct pci_dev *pdev, int blacklist) |
7d715a6c SL |
134 | { |
135 | int pos; | |
136 | u32 reg32; | |
137 | u16 reg16; | |
138 | int capable = 1, enabled = 1; | |
139 | struct pci_dev *child_dev; | |
140 | struct pcie_link_state *link_state = pdev->link_state; | |
141 | ||
142 | /* All functions should have the same cap and state, take the worst */ | |
143 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
144 | pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
145 | if (!pos) | |
146 | return; | |
147 | pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, ®32); | |
148 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { | |
149 | capable = 0; | |
150 | enabled = 0; | |
151 | break; | |
152 | } | |
153 | pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16); | |
154 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) | |
155 | enabled = 0; | |
156 | } | |
7d715a6c SL |
157 | link_state->clk_pm_enabled = enabled; |
158 | link_state->bios_clk_state = enabled; | |
46bbdfa4 SL |
159 | if (!blacklist) { |
160 | link_state->clk_pm_capable = capable; | |
161 | pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev)); | |
162 | } else { | |
163 | link_state->clk_pm_capable = 0; | |
164 | pcie_set_clock_pm(pdev, 0); | |
165 | } | |
166 | } | |
167 | ||
168 | static bool pcie_aspm_downstream_has_switch(struct pci_dev *pdev) | |
169 | { | |
170 | struct pci_dev *child_dev; | |
171 | ||
172 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
173 | if (child_dev->pcie_type == PCI_EXP_TYPE_UPSTREAM) | |
174 | return true; | |
175 | } | |
176 | return false; | |
7d715a6c SL |
177 | } |
178 | ||
179 | /* | |
180 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
181 | * could use common clock. If they are, configure them to use the | |
182 | * common clock. That will reduce the ASPM state exit latency. | |
183 | */ | |
184 | static void pcie_aspm_configure_common_clock(struct pci_dev *pdev) | |
185 | { | |
2a42d9db | 186 | int pos, child_pos, i = 0; |
7d715a6c SL |
187 | u16 reg16 = 0; |
188 | struct pci_dev *child_dev; | |
189 | int same_clock = 1; | |
2a42d9db TR |
190 | unsigned long start_jiffies; |
191 | u16 child_regs[8], parent_reg; | |
7d715a6c SL |
192 | /* |
193 | * all functions of a slot should have the same Slot Clock | |
194 | * Configuration, so just check one function | |
195 | * */ | |
196 | child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev, | |
197 | bus_list); | |
198 | BUG_ON(!child_dev->is_pcie); | |
199 | ||
200 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
201 | child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
202 | pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, ®16); | |
203 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) | |
204 | same_clock = 0; | |
205 | ||
206 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
207 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
208 | pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16); | |
209 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) | |
210 | same_clock = 0; | |
211 | ||
212 | /* Configure downstream component, all functions */ | |
213 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
214 | child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
215 | pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL, | |
216 | ®16); | |
2a42d9db | 217 | child_regs[i] = reg16; |
7d715a6c SL |
218 | if (same_clock) |
219 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
220 | else | |
221 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
222 | pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL, | |
223 | reg16); | |
2a42d9db | 224 | i++; |
7d715a6c SL |
225 | } |
226 | ||
227 | /* Configure upstream component */ | |
228 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
2a42d9db | 229 | parent_reg = reg16; |
7d715a6c SL |
230 | if (same_clock) |
231 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
232 | else | |
233 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
234 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); | |
235 | ||
236 | /* retrain link */ | |
237 | reg16 |= PCI_EXP_LNKCTL_RL; | |
238 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); | |
239 | ||
240 | /* Wait for link training end */ | |
2a42d9db TR |
241 | /* break out after waiting for 1 second */ |
242 | start_jiffies = jiffies; | |
243 | while ((jiffies - start_jiffies) < HZ) { | |
7d715a6c SL |
244 | pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16); |
245 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) | |
246 | break; | |
247 | cpu_relax(); | |
248 | } | |
2a42d9db TR |
249 | /* training failed -> recover */ |
250 | if ((jiffies - start_jiffies) >= HZ) { | |
251 | dev_printk (KERN_ERR, &pdev->dev, "ASPM: Could not configure" | |
252 | " common clock\n"); | |
253 | i = 0; | |
254 | list_for_each_entry(child_dev, &pdev->subordinate->devices, | |
255 | bus_list) { | |
256 | child_pos = pci_find_capability(child_dev, | |
257 | PCI_CAP_ID_EXP); | |
258 | pci_write_config_word(child_dev, | |
259 | child_pos + PCI_EXP_LNKCTL, | |
260 | child_regs[i]); | |
261 | i++; | |
262 | } | |
263 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, parent_reg); | |
264 | } | |
7d715a6c SL |
265 | } |
266 | ||
267 | /* | |
268 | * calc_L0S_latency: Convert L0s latency encoding to ns | |
269 | */ | |
270 | static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac) | |
271 | { | |
272 | unsigned int ns = 64; | |
273 | ||
274 | if (latency_encoding == 0x7) { | |
275 | if (ac) | |
276 | ns = -1U; | |
277 | else | |
278 | ns = 5*1000; /* > 4us */ | |
279 | } else | |
280 | ns *= (1 << latency_encoding); | |
281 | return ns; | |
282 | } | |
283 | ||
284 | /* | |
285 | * calc_L1_latency: Convert L1 latency encoding to ns | |
286 | */ | |
287 | static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac) | |
288 | { | |
289 | unsigned int ns = 1000; | |
290 | ||
291 | if (latency_encoding == 0x7) { | |
292 | if (ac) | |
293 | ns = -1U; | |
294 | else | |
295 | ns = 65*1000; /* > 64us */ | |
296 | } else | |
297 | ns *= (1 << latency_encoding); | |
298 | return ns; | |
299 | } | |
300 | ||
301 | static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state, | |
302 | unsigned int *l0s, unsigned int *l1, unsigned int *enabled) | |
303 | { | |
304 | int pos; | |
305 | u16 reg16; | |
306 | u32 reg32; | |
307 | unsigned int latency; | |
308 | ||
309 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
310 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); | |
311 | *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; | |
312 | if (*state != PCIE_LINK_STATE_L0S && | |
313 | *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S)) | |
314 | *state = 0; | |
315 | if (*state == 0) | |
316 | return; | |
317 | ||
318 | latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; | |
319 | *l0s = calc_L0S_latency(latency, 0); | |
320 | if (*state & PCIE_LINK_STATE_L1) { | |
321 | latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
322 | *l1 = calc_L1_latency(latency, 0); | |
323 | } | |
324 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
325 | *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1); | |
326 | } | |
327 | ||
328 | static void pcie_aspm_cap_init(struct pci_dev *pdev) | |
329 | { | |
330 | struct pci_dev *child_dev; | |
331 | u32 state, tmp; | |
332 | struct pcie_link_state *link_state = pdev->link_state; | |
333 | ||
334 | /* upstream component states */ | |
335 | pcie_aspm_get_cap_device(pdev, &link_state->support_state, | |
336 | &link_state->l0s_upper_latency, | |
337 | &link_state->l1_upper_latency, | |
338 | &link_state->enabled_state); | |
339 | /* downstream component states, all functions have the same setting */ | |
340 | child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev, | |
341 | bus_list); | |
342 | pcie_aspm_get_cap_device(child_dev, &state, | |
343 | &link_state->l0s_down_latency, | |
344 | &link_state->l1_down_latency, | |
345 | &tmp); | |
346 | link_state->support_state &= state; | |
347 | if (!link_state->support_state) | |
348 | return; | |
349 | link_state->enabled_state &= link_state->support_state; | |
350 | link_state->bios_aspm_state = link_state->enabled_state; | |
351 | ||
352 | /* ENDPOINT states*/ | |
353 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
354 | int pos; | |
355 | u32 reg32; | |
356 | unsigned int latency; | |
357 | struct endpoint_state *ep_state = | |
358 | &link_state->endpoints[PCI_FUNC(child_dev->devfn)]; | |
359 | ||
360 | if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT && | |
361 | child_dev->pcie_type != PCI_EXP_TYPE_LEG_END) | |
362 | continue; | |
363 | ||
364 | pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
365 | pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, ®32); | |
366 | latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; | |
367 | latency = calc_L0S_latency(latency, 1); | |
368 | ep_state->l0s_acceptable_latency = latency; | |
369 | if (link_state->support_state & PCIE_LINK_STATE_L1) { | |
370 | latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; | |
371 | latency = calc_L1_latency(latency, 1); | |
372 | ep_state->l1_acceptable_latency = latency; | |
373 | } | |
374 | } | |
375 | } | |
376 | ||
377 | static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev, | |
378 | unsigned int state) | |
379 | { | |
380 | struct pci_dev *parent_dev, *tmp_dev; | |
381 | unsigned int latency, l1_latency = 0; | |
382 | struct pcie_link_state *link_state; | |
383 | struct endpoint_state *ep_state; | |
384 | ||
385 | parent_dev = pdev->bus->self; | |
386 | link_state = parent_dev->link_state; | |
387 | state &= link_state->support_state; | |
388 | if (state == 0) | |
389 | return 0; | |
390 | ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)]; | |
391 | ||
392 | /* | |
393 | * Check latency for endpoint device. | |
394 | * TBD: The latency from the endpoint to root complex vary per | |
395 | * switch's upstream link state above the device. Here we just do a | |
396 | * simple check which assumes all links above the device can be in L1 | |
397 | * state, that is we just consider the worst case. If switch's upstream | |
398 | * link can't be put into L0S/L1, then our check is too strictly. | |
399 | */ | |
400 | tmp_dev = pdev; | |
401 | while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { | |
402 | parent_dev = tmp_dev->bus->self; | |
403 | link_state = parent_dev->link_state; | |
404 | if (state & PCIE_LINK_STATE_L0S) { | |
405 | latency = max_t(unsigned int, | |
406 | link_state->l0s_upper_latency, | |
407 | link_state->l0s_down_latency); | |
408 | if (latency > ep_state->l0s_acceptable_latency) | |
409 | state &= ~PCIE_LINK_STATE_L0S; | |
410 | } | |
411 | if (state & PCIE_LINK_STATE_L1) { | |
412 | latency = max_t(unsigned int, | |
413 | link_state->l1_upper_latency, | |
414 | link_state->l1_down_latency); | |
415 | if (latency + l1_latency > | |
416 | ep_state->l1_acceptable_latency) | |
417 | state &= ~PCIE_LINK_STATE_L1; | |
418 | } | |
419 | if (!parent_dev->bus->self) /* parent_dev is a root port */ | |
420 | break; | |
421 | else { | |
422 | /* | |
423 | * parent_dev is the downstream port of a switch, make | |
424 | * tmp_dev the upstream port of the switch | |
425 | */ | |
426 | tmp_dev = parent_dev->bus->self; | |
427 | /* | |
428 | * every switch on the path to root complex need 1 more | |
429 | * microsecond for L1. Spec doesn't mention L0S. | |
430 | */ | |
431 | if (state & PCIE_LINK_STATE_L1) | |
432 | l1_latency += 1000; | |
433 | } | |
434 | } | |
435 | return state; | |
436 | } | |
437 | ||
438 | static unsigned int pcie_aspm_check_state(struct pci_dev *pdev, | |
439 | unsigned int state) | |
440 | { | |
441 | struct pci_dev *child_dev; | |
442 | ||
46bbdfa4 | 443 | /* If no child, ignore the link */ |
7d715a6c | 444 | if (list_empty(&pdev->subordinate->devices)) |
46bbdfa4 | 445 | return state; |
7d715a6c SL |
446 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { |
447 | if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { | |
448 | /* | |
449 | * If downstream component of a link is pci bridge, we | |
450 | * disable ASPM for now for the link | |
451 | * */ | |
452 | state = 0; | |
453 | break; | |
454 | } | |
455 | if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT && | |
456 | child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
457 | continue; | |
458 | /* Device not in D0 doesn't need check latency */ | |
459 | if (child_dev->current_state == PCI_D1 || | |
460 | child_dev->current_state == PCI_D2 || | |
461 | child_dev->current_state == PCI_D3hot || | |
462 | child_dev->current_state == PCI_D3cold) | |
463 | continue; | |
464 | state = __pcie_aspm_check_state_one(child_dev, state); | |
465 | } | |
466 | return state; | |
467 | } | |
468 | ||
469 | static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state) | |
470 | { | |
471 | u16 reg16; | |
472 | int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
473 | ||
474 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
475 | reg16 &= ~0x3; | |
476 | reg16 |= state; | |
477 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); | |
478 | } | |
479 | ||
480 | static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state) | |
481 | { | |
482 | struct pci_dev *child_dev; | |
483 | int valid = 1; | |
484 | struct pcie_link_state *link_state = pdev->link_state; | |
485 | ||
46bbdfa4 SL |
486 | /* If no child, disable the link */ |
487 | if (list_empty(&pdev->subordinate->devices)) | |
488 | state = 0; | |
7d715a6c SL |
489 | /* |
490 | * if the downstream component has pci bridge function, don't do ASPM | |
491 | * now | |
492 | */ | |
493 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
494 | if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { | |
495 | valid = 0; | |
496 | break; | |
497 | } | |
498 | } | |
499 | if (!valid) | |
500 | return; | |
501 | ||
502 | /* | |
503 | * spec 2.0 suggests all functions should be configured the same | |
504 | * setting for ASPM. Enabling ASPM L1 should be done in upstream | |
505 | * component first and then downstream, and vice versa for disabling | |
506 | * ASPM L1. Spec doesn't mention L0S. | |
507 | */ | |
508 | if (state & PCIE_LINK_STATE_L1) | |
509 | __pcie_aspm_config_one_dev(pdev, state); | |
510 | ||
511 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) | |
512 | __pcie_aspm_config_one_dev(child_dev, state); | |
513 | ||
514 | if (!(state & PCIE_LINK_STATE_L1)) | |
515 | __pcie_aspm_config_one_dev(pdev, state); | |
516 | ||
517 | link_state->enabled_state = state; | |
518 | } | |
519 | ||
46bbdfa4 SL |
520 | static struct pcie_link_state *get_root_port_link(struct pcie_link_state *link) |
521 | { | |
522 | struct pcie_link_state *root_port_link = link; | |
523 | while (root_port_link->parent) | |
524 | root_port_link = root_port_link->parent; | |
525 | return root_port_link; | |
526 | } | |
527 | ||
528 | /* check the whole hierarchy, and configure each link in the hierarchy */ | |
7d715a6c SL |
529 | static void __pcie_aspm_configure_link_state(struct pci_dev *pdev, |
530 | unsigned int state) | |
531 | { | |
532 | struct pcie_link_state *link_state = pdev->link_state; | |
46bbdfa4 SL |
533 | struct pcie_link_state *root_port_link = get_root_port_link(link_state); |
534 | struct pcie_link_state *leaf; | |
7d715a6c | 535 | |
7d715a6c SL |
536 | state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1; |
537 | ||
46bbdfa4 SL |
538 | /* check all links who have specific root port link */ |
539 | list_for_each_entry(leaf, &link_list, sibiling) { | |
540 | if (!list_empty(&leaf->children) || | |
541 | get_root_port_link(leaf) != root_port_link) | |
542 | continue; | |
543 | state = pcie_aspm_check_state(leaf->pdev, state); | |
544 | } | |
545 | /* check root port link too in case it hasn't children */ | |
546 | state = pcie_aspm_check_state(root_port_link->pdev, state); | |
547 | ||
7d715a6c SL |
548 | if (link_state->enabled_state == state) |
549 | return; | |
46bbdfa4 SL |
550 | |
551 | /* | |
552 | * we must change the hierarchy. See comments in | |
553 | * __pcie_aspm_config_link for the order | |
554 | **/ | |
555 | if (state & PCIE_LINK_STATE_L1) { | |
556 | list_for_each_entry(leaf, &link_list, sibiling) { | |
557 | if (get_root_port_link(leaf) == root_port_link) | |
558 | __pcie_aspm_config_link(leaf->pdev, state); | |
559 | } | |
560 | } else { | |
561 | list_for_each_entry_reverse(leaf, &link_list, sibiling) { | |
562 | if (get_root_port_link(leaf) == root_port_link) | |
563 | __pcie_aspm_config_link(leaf->pdev, state); | |
564 | } | |
565 | } | |
7d715a6c SL |
566 | } |
567 | ||
568 | /* | |
569 | * pcie_aspm_configure_link_state: enable/disable PCI express link state | |
570 | * @pdev: the root port or switch downstream port | |
571 | */ | |
572 | static void pcie_aspm_configure_link_state(struct pci_dev *pdev, | |
573 | unsigned int state) | |
574 | { | |
575 | down_read(&pci_bus_sem); | |
576 | mutex_lock(&aspm_lock); | |
577 | __pcie_aspm_configure_link_state(pdev, state); | |
578 | mutex_unlock(&aspm_lock); | |
579 | up_read(&pci_bus_sem); | |
580 | } | |
581 | ||
582 | static void free_link_state(struct pci_dev *pdev) | |
583 | { | |
584 | kfree(pdev->link_state); | |
585 | pdev->link_state = NULL; | |
586 | } | |
587 | ||
ddc9753f SL |
588 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
589 | { | |
590 | struct pci_dev *child_dev; | |
591 | int child_pos; | |
149e1637 | 592 | u32 reg32; |
ddc9753f SL |
593 | |
594 | /* | |
595 | * Some functions in a slot might not all be PCIE functions, very | |
596 | * strange. Disable ASPM for the whole slot | |
597 | */ | |
598 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
599 | child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
600 | if (!child_pos) | |
601 | return -EINVAL; | |
149e1637 SL |
602 | |
603 | /* | |
604 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
605 | * RBER bit to determine if a function is 1.1 version device | |
606 | */ | |
607 | pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP, | |
608 | ®32); | |
e1f4f59d | 609 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
f393d9b1 VL |
610 | dev_printk(KERN_INFO, &child_dev->dev, "disabling ASPM" |
611 | " on pre-1.1 PCIe device. You can enable it" | |
612 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
613 | return -EINVAL; |
614 | } | |
ddc9753f SL |
615 | } |
616 | return 0; | |
617 | } | |
618 | ||
7d715a6c SL |
619 | /* |
620 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
621 | * It is called after the pcie and its children devices are scaned. | |
622 | * @pdev: the root port or switch downstream port | |
623 | */ | |
624 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
625 | { | |
626 | unsigned int state; | |
627 | struct pcie_link_state *link_state; | |
628 | int error = 0; | |
46bbdfa4 | 629 | int blacklist; |
7d715a6c SL |
630 | |
631 | if (aspm_disabled || !pdev->is_pcie || pdev->link_state) | |
632 | return; | |
633 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
634 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
635 | return; | |
636 | down_read(&pci_bus_sem); | |
637 | if (list_empty(&pdev->subordinate->devices)) | |
638 | goto out; | |
639 | ||
46bbdfa4 | 640 | blacklist = !!pcie_aspm_sanity_check(pdev); |
ddc9753f | 641 | |
7d715a6c SL |
642 | mutex_lock(&aspm_lock); |
643 | ||
644 | link_state = kzalloc(sizeof(*link_state), GFP_KERNEL); | |
645 | if (!link_state) | |
646 | goto unlock_out; | |
7d715a6c | 647 | |
46bbdfa4 SL |
648 | link_state->downstream_has_switch = pcie_aspm_downstream_has_switch(pdev); |
649 | INIT_LIST_HEAD(&link_state->children); | |
650 | INIT_LIST_HEAD(&link_state->link); | |
651 | if (pdev->bus->self) {/* this is a switch */ | |
652 | struct pcie_link_state *parent_link_state; | |
7d715a6c | 653 | |
46bbdfa4 SL |
654 | parent_link_state = pdev->bus->parent->self->link_state; |
655 | if (!parent_link_state) { | |
656 | kfree(link_state); | |
657 | goto unlock_out; | |
658 | } | |
659 | list_add(&link_state->link, &parent_link_state->children); | |
660 | link_state->parent = parent_link_state; | |
661 | } | |
7d715a6c | 662 | |
46bbdfa4 | 663 | pdev->link_state = link_state; |
7d715a6c | 664 | |
46bbdfa4 SL |
665 | if (!blacklist) { |
666 | pcie_aspm_configure_common_clock(pdev); | |
667 | pcie_aspm_cap_init(pdev); | |
668 | } else { | |
669 | link_state->enabled_state = PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1; | |
670 | link_state->bios_aspm_state = 0; | |
671 | /* Set support state to 0, so we will disable ASPM later */ | |
672 | link_state->support_state = 0; | |
673 | } | |
7d715a6c SL |
674 | |
675 | link_state->pdev = pdev; | |
676 | list_add(&link_state->sibiling, &link_list); | |
677 | ||
46bbdfa4 SL |
678 | if (link_state->downstream_has_switch) { |
679 | /* | |
680 | * If link has switch, delay the link config. The leaf link | |
681 | * initialization will config the whole hierarchy. but we must | |
682 | * make sure BIOS doesn't set unsupported link state | |
683 | **/ | |
684 | state = pcie_aspm_check_state(pdev, link_state->bios_aspm_state); | |
685 | __pcie_aspm_config_link(pdev, state); | |
686 | } else | |
687 | __pcie_aspm_configure_link_state(pdev, | |
688 | policy_to_aspm_state(pdev)); | |
689 | ||
690 | pcie_check_clock_pm(pdev, blacklist); | |
691 | ||
7d715a6c SL |
692 | unlock_out: |
693 | if (error) | |
694 | free_link_state(pdev); | |
695 | mutex_unlock(&aspm_lock); | |
696 | out: | |
697 | up_read(&pci_bus_sem); | |
698 | } | |
699 | ||
700 | /* @pdev: the endpoint device */ | |
701 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
702 | { | |
703 | struct pci_dev *parent = pdev->bus->self; | |
704 | struct pcie_link_state *link_state = parent->link_state; | |
705 | ||
706 | if (aspm_disabled || !pdev->is_pcie || !parent || !link_state) | |
707 | return; | |
708 | if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
709 | parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
710 | return; | |
711 | down_read(&pci_bus_sem); | |
712 | mutex_lock(&aspm_lock); | |
713 | ||
714 | /* | |
715 | * All PCIe functions are in one slot, remove one function will remove | |
716 | * the the whole slot, so just wait | |
717 | */ | |
718 | if (!list_empty(&parent->subordinate->devices)) | |
719 | goto out; | |
720 | ||
721 | /* All functions are removed, so just disable ASPM for the link */ | |
722 | __pcie_aspm_config_one_dev(parent, 0); | |
723 | list_del(&link_state->sibiling); | |
46bbdfa4 | 724 | list_del(&link_state->link); |
7d715a6c SL |
725 | /* Clock PM is for endpoint device */ |
726 | ||
727 | free_link_state(parent); | |
728 | out: | |
729 | mutex_unlock(&aspm_lock); | |
730 | up_read(&pci_bus_sem); | |
731 | } | |
732 | ||
733 | /* @pdev: the root port or switch downstream port */ | |
734 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
735 | { | |
736 | struct pcie_link_state *link_state = pdev->link_state; | |
737 | ||
738 | if (aspm_disabled || !pdev->is_pcie || !pdev->link_state) | |
739 | return; | |
740 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
741 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
742 | return; | |
743 | /* | |
744 | * devices changed PM state, we should recheck if latency meets all | |
745 | * functions' requirement | |
746 | */ | |
747 | pcie_aspm_configure_link_state(pdev, link_state->enabled_state); | |
748 | } | |
749 | ||
750 | /* | |
751 | * pci_disable_link_state - disable pci device's link state, so the link will | |
752 | * never enter specific states | |
753 | */ | |
754 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
755 | { | |
756 | struct pci_dev *parent = pdev->bus->self; | |
757 | struct pcie_link_state *link_state; | |
758 | ||
759 | if (aspm_disabled || !pdev->is_pcie) | |
760 | return; | |
761 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
762 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
763 | parent = pdev; | |
764 | if (!parent || !parent->link_state) | |
765 | return; | |
766 | ||
767 | down_read(&pci_bus_sem); | |
768 | mutex_lock(&aspm_lock); | |
769 | link_state = parent->link_state; | |
770 | link_state->support_state &= | |
771 | ~(state & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1)); | |
772 | if (state & PCIE_LINK_STATE_CLKPM) | |
773 | link_state->clk_pm_capable = 0; | |
774 | ||
775 | __pcie_aspm_configure_link_state(parent, link_state->enabled_state); | |
776 | if (!link_state->clk_pm_capable && link_state->clk_pm_enabled) | |
777 | pcie_set_clock_pm(parent, 0); | |
778 | mutex_unlock(&aspm_lock); | |
779 | up_read(&pci_bus_sem); | |
780 | } | |
781 | EXPORT_SYMBOL(pci_disable_link_state); | |
782 | ||
783 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
784 | { | |
785 | int i; | |
786 | struct pci_dev *pdev; | |
787 | struct pcie_link_state *link_state; | |
788 | ||
789 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
790 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
791 | break; | |
792 | if (i >= ARRAY_SIZE(policy_str)) | |
793 | return -EINVAL; | |
794 | if (i == aspm_policy) | |
795 | return 0; | |
796 | ||
797 | down_read(&pci_bus_sem); | |
798 | mutex_lock(&aspm_lock); | |
799 | aspm_policy = i; | |
800 | list_for_each_entry(link_state, &link_list, sibiling) { | |
801 | pdev = link_state->pdev; | |
802 | __pcie_aspm_configure_link_state(pdev, | |
803 | policy_to_aspm_state(pdev)); | |
804 | if (link_state->clk_pm_capable && | |
805 | link_state->clk_pm_enabled != policy_to_clkpm_state(pdev)) | |
806 | pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev)); | |
807 | ||
808 | } | |
809 | mutex_unlock(&aspm_lock); | |
810 | up_read(&pci_bus_sem); | |
811 | return 0; | |
812 | } | |
813 | ||
814 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
815 | { | |
816 | int i, cnt = 0; | |
817 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
818 | if (i == aspm_policy) | |
819 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
820 | else | |
821 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
822 | return cnt; | |
823 | } | |
824 | ||
825 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
826 | NULL, 0644); | |
827 | ||
828 | #ifdef CONFIG_PCIEASPM_DEBUG | |
829 | static ssize_t link_state_show(struct device *dev, | |
830 | struct device_attribute *attr, | |
831 | char *buf) | |
832 | { | |
833 | struct pci_dev *pci_device = to_pci_dev(dev); | |
834 | struct pcie_link_state *link_state = pci_device->link_state; | |
835 | ||
836 | return sprintf(buf, "%d\n", link_state->enabled_state); | |
837 | } | |
838 | ||
839 | static ssize_t link_state_store(struct device *dev, | |
840 | struct device_attribute *attr, | |
841 | const char *buf, | |
842 | size_t n) | |
843 | { | |
844 | struct pci_dev *pci_device = to_pci_dev(dev); | |
845 | int state; | |
846 | ||
847 | if (n < 1) | |
848 | return -EINVAL; | |
849 | state = buf[0]-'0'; | |
850 | if (state >= 0 && state <= 3) { | |
851 | /* setup link aspm state */ | |
852 | pcie_aspm_configure_link_state(pci_device, state); | |
853 | return n; | |
854 | } | |
855 | ||
856 | return -EINVAL; | |
857 | } | |
858 | ||
859 | static ssize_t clk_ctl_show(struct device *dev, | |
860 | struct device_attribute *attr, | |
861 | char *buf) | |
862 | { | |
863 | struct pci_dev *pci_device = to_pci_dev(dev); | |
864 | struct pcie_link_state *link_state = pci_device->link_state; | |
865 | ||
866 | return sprintf(buf, "%d\n", link_state->clk_pm_enabled); | |
867 | } | |
868 | ||
869 | static ssize_t clk_ctl_store(struct device *dev, | |
870 | struct device_attribute *attr, | |
871 | const char *buf, | |
872 | size_t n) | |
873 | { | |
874 | struct pci_dev *pci_device = to_pci_dev(dev); | |
875 | int state; | |
876 | ||
877 | if (n < 1) | |
878 | return -EINVAL; | |
879 | state = buf[0]-'0'; | |
880 | ||
881 | down_read(&pci_bus_sem); | |
882 | mutex_lock(&aspm_lock); | |
883 | pcie_set_clock_pm(pci_device, !!state); | |
884 | mutex_unlock(&aspm_lock); | |
885 | up_read(&pci_bus_sem); | |
886 | ||
887 | return n; | |
888 | } | |
889 | ||
890 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
891 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
892 | ||
893 | static char power_group[] = "power"; | |
894 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
895 | { | |
896 | struct pcie_link_state *link_state = pdev->link_state; | |
897 | ||
898 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
899 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
900 | return; | |
901 | ||
902 | if (link_state->support_state) | |
903 | sysfs_add_file_to_group(&pdev->dev.kobj, | |
904 | &dev_attr_link_state.attr, power_group); | |
905 | if (link_state->clk_pm_capable) | |
906 | sysfs_add_file_to_group(&pdev->dev.kobj, | |
907 | &dev_attr_clk_ctl.attr, power_group); | |
908 | } | |
909 | ||
910 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
911 | { | |
912 | struct pcie_link_state *link_state = pdev->link_state; | |
913 | ||
914 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
915 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
916 | return; | |
917 | ||
918 | if (link_state->support_state) | |
919 | sysfs_remove_file_from_group(&pdev->dev.kobj, | |
920 | &dev_attr_link_state.attr, power_group); | |
921 | if (link_state->clk_pm_capable) | |
922 | sysfs_remove_file_from_group(&pdev->dev.kobj, | |
923 | &dev_attr_clk_ctl.attr, power_group); | |
924 | } | |
925 | #endif | |
926 | ||
927 | static int __init pcie_aspm_disable(char *str) | |
928 | { | |
d6d38574 SL |
929 | if (!strcmp(str, "off")) { |
930 | aspm_disabled = 1; | |
931 | printk(KERN_INFO "PCIe ASPM is disabled\n"); | |
932 | } else if (!strcmp(str, "force")) { | |
933 | aspm_force = 1; | |
934 | printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); | |
935 | } | |
7d715a6c SL |
936 | return 1; |
937 | } | |
938 | ||
d6d38574 | 939 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 940 | |
5fde244d SL |
941 | void pcie_no_aspm(void) |
942 | { | |
d6d38574 SL |
943 | if (!aspm_force) |
944 | aspm_disabled = 1; | |
5fde244d SL |
945 | } |
946 | ||
3e1b1600 AP |
947 | /** |
948 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
949 | * | |
950 | * Returns true if ASPM has not been disabled by the command-line option | |
951 | * pcie_aspm=off. | |
952 | **/ | |
953 | int pcie_aspm_enabled(void) | |
7d715a6c | 954 | { |
3e1b1600 | 955 | return !aspm_disabled; |
7d715a6c | 956 | } |
3e1b1600 | 957 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 958 |