Commit | Line | Data |
---|---|---|
7d715a6c SL |
1 | /* |
2 | * File: drivers/pci/pcie/aspm.c | |
3 | * Enabling PCIE link L0s/L1 state and Clock Power Management | |
4 | * | |
5 | * Copyright (C) 2007 Intel | |
6 | * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) | |
7 | * Copyright (C) Shaohua Li (shaohua.li@intel.com) | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/pci_regs.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/pm.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/slab.h> | |
2a42d9db | 19 | #include <linux/jiffies.h> |
987a4c78 | 20 | #include <linux/delay.h> |
7d715a6c SL |
21 | #include <linux/pci-aspm.h> |
22 | #include "../pci.h" | |
23 | ||
24 | #ifdef MODULE_PARAM_PREFIX | |
25 | #undef MODULE_PARAM_PREFIX | |
26 | #endif | |
27 | #define MODULE_PARAM_PREFIX "pcie_aspm." | |
28 | ||
b6c2e54d KK |
29 | struct aspm_latency { |
30 | u32 l0s; /* L0s latency (nsec) */ | |
31 | u32 l1; /* L1 latency (nsec) */ | |
7d715a6c SL |
32 | }; |
33 | ||
34 | struct pcie_link_state { | |
5cde89d8 KK |
35 | struct pci_dev *pdev; /* Upstream component of the Link */ |
36 | struct pcie_link_state *parent; /* pointer to the parent Link state */ | |
37 | struct list_head sibling; /* node in link_list */ | |
38 | struct list_head children; /* list of child link states */ | |
39 | struct list_head link; /* node in parent's children list */ | |
7d715a6c SL |
40 | |
41 | /* ASPM state */ | |
80bfdbe3 KK |
42 | u32 aspm_support:2; /* Supported ASPM state */ |
43 | u32 aspm_enabled:2; /* Enabled ASPM state */ | |
44 | u32 aspm_default:2; /* Default ASPM state by BIOS */ | |
45 | ||
4d246e45 KK |
46 | /* Clock PM state */ |
47 | u32 clkpm_capable:1; /* Clock PM capable? */ | |
48 | u32 clkpm_enabled:1; /* Current Clock PM state */ | |
49 | u32 clkpm_default:1; /* Default Clock PM state by BIOS */ | |
50 | ||
5cde89d8 KK |
51 | u32 has_switch:1; /* Downstream has switches? */ |
52 | ||
b6c2e54d KK |
53 | /* Latencies */ |
54 | struct aspm_latency latency; /* Exit latency */ | |
7d715a6c | 55 | /* |
b6c2e54d KK |
56 | * Endpoint acceptable latencies. A pcie downstream port only |
57 | * has one slot under it, so at most there are 8 functions. | |
7d715a6c | 58 | */ |
b6c2e54d | 59 | struct aspm_latency acceptable[8]; |
7d715a6c SL |
60 | }; |
61 | ||
d6d38574 | 62 | static int aspm_disabled, aspm_force; |
7d715a6c SL |
63 | static DEFINE_MUTEX(aspm_lock); |
64 | static LIST_HEAD(link_list); | |
65 | ||
66 | #define POLICY_DEFAULT 0 /* BIOS default setting */ | |
67 | #define POLICY_PERFORMANCE 1 /* high performance */ | |
68 | #define POLICY_POWERSAVE 2 /* high power saving */ | |
69 | static int aspm_policy; | |
70 | static const char *policy_str[] = { | |
71 | [POLICY_DEFAULT] = "default", | |
72 | [POLICY_PERFORMANCE] = "performance", | |
73 | [POLICY_POWERSAVE] = "powersave" | |
74 | }; | |
75 | ||
987a4c78 AP |
76 | #define LINK_RETRAIN_TIMEOUT HZ |
77 | ||
5aa63583 | 78 | static int policy_to_aspm_state(struct pcie_link_state *link) |
7d715a6c | 79 | { |
7d715a6c SL |
80 | switch (aspm_policy) { |
81 | case POLICY_PERFORMANCE: | |
82 | /* Disable ASPM and Clock PM */ | |
83 | return 0; | |
84 | case POLICY_POWERSAVE: | |
85 | /* Enable ASPM L0s/L1 */ | |
80bfdbe3 | 86 | return PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1; |
7d715a6c | 87 | case POLICY_DEFAULT: |
5aa63583 | 88 | return link->aspm_default; |
7d715a6c SL |
89 | } |
90 | return 0; | |
91 | } | |
92 | ||
5aa63583 | 93 | static int policy_to_clkpm_state(struct pcie_link_state *link) |
7d715a6c | 94 | { |
7d715a6c SL |
95 | switch (aspm_policy) { |
96 | case POLICY_PERFORMANCE: | |
97 | /* Disable ASPM and Clock PM */ | |
98 | return 0; | |
99 | case POLICY_POWERSAVE: | |
100 | /* Disable Clock PM */ | |
101 | return 1; | |
102 | case POLICY_DEFAULT: | |
5aa63583 | 103 | return link->clkpm_default; |
7d715a6c SL |
104 | } |
105 | return 0; | |
106 | } | |
107 | ||
5aa63583 | 108 | static void pcie_set_clock_pm(struct pcie_link_state *link, int enable) |
7d715a6c | 109 | { |
7d715a6c SL |
110 | int pos; |
111 | u16 reg16; | |
5aa63583 KK |
112 | struct pci_dev *child; |
113 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 114 | |
5aa63583 KK |
115 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
116 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
7d715a6c SL |
117 | if (!pos) |
118 | return; | |
5aa63583 | 119 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
120 | if (enable) |
121 | reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
122 | else | |
123 | reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
5aa63583 | 124 | pci_write_config_word(child, pos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 125 | } |
5aa63583 | 126 | link->clkpm_enabled = !!enable; |
7d715a6c SL |
127 | } |
128 | ||
8d349ace | 129 | static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 130 | { |
5aa63583 | 131 | int pos, capable = 1, enabled = 1; |
7d715a6c SL |
132 | u32 reg32; |
133 | u16 reg16; | |
5aa63583 KK |
134 | struct pci_dev *child; |
135 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c SL |
136 | |
137 | /* All functions should have the same cap and state, take the worst */ | |
5aa63583 KK |
138 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
139 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
7d715a6c SL |
140 | if (!pos) |
141 | return; | |
5aa63583 | 142 | pci_read_config_dword(child, pos + PCI_EXP_LNKCAP, ®32); |
7d715a6c SL |
143 | if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { |
144 | capable = 0; | |
145 | enabled = 0; | |
146 | break; | |
147 | } | |
5aa63583 | 148 | pci_read_config_word(child, pos + PCI_EXP_LNKCTL, ®16); |
7d715a6c SL |
149 | if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) |
150 | enabled = 0; | |
151 | } | |
5aa63583 KK |
152 | link->clkpm_enabled = enabled; |
153 | link->clkpm_default = enabled; | |
8d349ace | 154 | link->clkpm_capable = (blacklist) ? 0 : capable; |
46bbdfa4 SL |
155 | } |
156 | ||
5aa63583 | 157 | static bool pcie_aspm_downstream_has_switch(struct pcie_link_state *link) |
46bbdfa4 | 158 | { |
5aa63583 KK |
159 | struct pci_dev *child; |
160 | struct pci_bus *linkbus = link->pdev->subordinate; | |
46bbdfa4 | 161 | |
5aa63583 KK |
162 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
163 | if (child->pcie_type == PCI_EXP_TYPE_UPSTREAM) | |
46bbdfa4 SL |
164 | return true; |
165 | } | |
166 | return false; | |
7d715a6c SL |
167 | } |
168 | ||
169 | /* | |
170 | * pcie_aspm_configure_common_clock: check if the 2 ends of a link | |
171 | * could use common clock. If they are, configure them to use the | |
172 | * common clock. That will reduce the ASPM state exit latency. | |
173 | */ | |
5aa63583 | 174 | static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) |
7d715a6c | 175 | { |
5aa63583 KK |
176 | int ppos, cpos, same_clock = 1; |
177 | u16 reg16, parent_reg, child_reg[8]; | |
2a42d9db | 178 | unsigned long start_jiffies; |
5aa63583 KK |
179 | struct pci_dev *child, *parent = link->pdev; |
180 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 181 | /* |
5aa63583 | 182 | * All functions of a slot should have the same Slot Clock |
7d715a6c | 183 | * Configuration, so just check one function |
5aa63583 KK |
184 | */ |
185 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); | |
186 | BUG_ON(!child->is_pcie); | |
7d715a6c SL |
187 | |
188 | /* Check downstream component if bit Slot Clock Configuration is 1 */ | |
5aa63583 KK |
189 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); |
190 | pci_read_config_word(child, cpos + PCI_EXP_LNKSTA, ®16); | |
7d715a6c SL |
191 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
192 | same_clock = 0; | |
193 | ||
194 | /* Check upstream component if bit Slot Clock Configuration is 1 */ | |
5aa63583 KK |
195 | ppos = pci_find_capability(parent, PCI_CAP_ID_EXP); |
196 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); | |
7d715a6c SL |
197 | if (!(reg16 & PCI_EXP_LNKSTA_SLC)) |
198 | same_clock = 0; | |
199 | ||
200 | /* Configure downstream component, all functions */ | |
5aa63583 KK |
201 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
202 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
203 | pci_read_config_word(child, cpos + PCI_EXP_LNKCTL, ®16); | |
204 | child_reg[PCI_FUNC(child->devfn)] = reg16; | |
7d715a6c SL |
205 | if (same_clock) |
206 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
207 | else | |
208 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 209 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, reg16); |
7d715a6c SL |
210 | } |
211 | ||
212 | /* Configure upstream component */ | |
5aa63583 | 213 | pci_read_config_word(parent, ppos + PCI_EXP_LNKCTL, ®16); |
2a42d9db | 214 | parent_reg = reg16; |
7d715a6c SL |
215 | if (same_clock) |
216 | reg16 |= PCI_EXP_LNKCTL_CCC; | |
217 | else | |
218 | reg16 &= ~PCI_EXP_LNKCTL_CCC; | |
5aa63583 | 219 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 220 | |
5aa63583 | 221 | /* Retrain link */ |
7d715a6c | 222 | reg16 |= PCI_EXP_LNKCTL_RL; |
5aa63583 | 223 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, reg16); |
7d715a6c | 224 | |
5aa63583 | 225 | /* Wait for link training end. Break out after waiting for timeout */ |
2a42d9db | 226 | start_jiffies = jiffies; |
987a4c78 | 227 | for (;;) { |
5aa63583 | 228 | pci_read_config_word(parent, ppos + PCI_EXP_LNKSTA, ®16); |
7d715a6c SL |
229 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
230 | break; | |
987a4c78 AP |
231 | if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) |
232 | break; | |
233 | msleep(1); | |
7d715a6c | 234 | } |
5aa63583 KK |
235 | if (!(reg16 & PCI_EXP_LNKSTA_LT)) |
236 | return; | |
237 | ||
238 | /* Training failed. Restore common clock configurations */ | |
239 | dev_printk(KERN_ERR, &parent->dev, | |
240 | "ASPM: Could not configure common clock\n"); | |
241 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
242 | cpos = pci_find_capability(child, PCI_CAP_ID_EXP); | |
243 | pci_write_config_word(child, cpos + PCI_EXP_LNKCTL, | |
244 | child_reg[PCI_FUNC(child->devfn)]); | |
2a42d9db | 245 | } |
5aa63583 | 246 | pci_write_config_word(parent, ppos + PCI_EXP_LNKCTL, parent_reg); |
7d715a6c SL |
247 | } |
248 | ||
249 | /* | |
250 | * calc_L0S_latency: Convert L0s latency encoding to ns | |
251 | */ | |
252 | static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac) | |
253 | { | |
254 | unsigned int ns = 64; | |
255 | ||
256 | if (latency_encoding == 0x7) { | |
257 | if (ac) | |
258 | ns = -1U; | |
259 | else | |
260 | ns = 5*1000; /* > 4us */ | |
261 | } else | |
262 | ns *= (1 << latency_encoding); | |
263 | return ns; | |
264 | } | |
265 | ||
266 | /* | |
267 | * calc_L1_latency: Convert L1 latency encoding to ns | |
268 | */ | |
269 | static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac) | |
270 | { | |
271 | unsigned int ns = 1000; | |
272 | ||
273 | if (latency_encoding == 0x7) { | |
274 | if (ac) | |
275 | ns = -1U; | |
276 | else | |
277 | ns = 65*1000; /* > 64us */ | |
278 | } else | |
279 | ns *= (1 << latency_encoding); | |
280 | return ns; | |
281 | } | |
282 | ||
283 | static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state, | |
284 | unsigned int *l0s, unsigned int *l1, unsigned int *enabled) | |
285 | { | |
286 | int pos; | |
287 | u16 reg16; | |
288 | u32 reg32; | |
289 | unsigned int latency; | |
290 | ||
80bfdbe3 | 291 | *l0s = *l1 = *enabled = 0; |
7d715a6c SL |
292 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
293 | pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); | |
294 | *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; | |
295 | if (*state != PCIE_LINK_STATE_L0S && | |
296 | *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S)) | |
297 | *state = 0; | |
298 | if (*state == 0) | |
299 | return; | |
300 | ||
301 | latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; | |
302 | *l0s = calc_L0S_latency(latency, 0); | |
303 | if (*state & PCIE_LINK_STATE_L1) { | |
304 | latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; | |
305 | *l1 = calc_L1_latency(latency, 0); | |
306 | } | |
307 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
308 | *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1); | |
309 | } | |
310 | ||
8d349ace | 311 | static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) |
7d715a6c | 312 | { |
80bfdbe3 | 313 | u32 support, l0s, l1, enabled; |
5aa63583 KK |
314 | struct pci_dev *child, *parent = link->pdev; |
315 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 316 | |
8d349ace KK |
317 | if (blacklist) { |
318 | /* Set support state to 0, so we will disable ASPM later */ | |
319 | link->aspm_support = 0; | |
320 | link->aspm_default = 0; | |
321 | link->aspm_enabled = PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1; | |
322 | return; | |
323 | } | |
324 | ||
325 | /* Configure common clock before checking latencies */ | |
326 | pcie_aspm_configure_common_clock(link); | |
327 | ||
7d715a6c | 328 | /* upstream component states */ |
5aa63583 KK |
329 | pcie_aspm_get_cap_device(parent, &support, &l0s, &l1, &enabled); |
330 | link->aspm_support = support; | |
331 | link->latency.l0s = l0s; | |
332 | link->latency.l1 = l1; | |
333 | link->aspm_enabled = enabled; | |
80bfdbe3 | 334 | |
7d715a6c | 335 | /* downstream component states, all functions have the same setting */ |
5aa63583 KK |
336 | child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); |
337 | pcie_aspm_get_cap_device(child, &support, &l0s, &l1, &enabled); | |
338 | link->aspm_support &= support; | |
339 | link->latency.l0s = max_t(u32, link->latency.l0s, l0s); | |
340 | link->latency.l1 = max_t(u32, link->latency.l1, l1); | |
341 | ||
342 | if (!link->aspm_support) | |
7d715a6c | 343 | return; |
80bfdbe3 | 344 | |
5aa63583 KK |
345 | link->aspm_enabled &= link->aspm_support; |
346 | link->aspm_default = link->aspm_enabled; | |
7d715a6c SL |
347 | |
348 | /* ENDPOINT states*/ | |
5aa63583 | 349 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
7d715a6c SL |
350 | int pos; |
351 | u32 reg32; | |
352 | unsigned int latency; | |
b6c2e54d | 353 | struct aspm_latency *acceptable = |
5aa63583 | 354 | &link->acceptable[PCI_FUNC(child->devfn)]; |
7d715a6c | 355 | |
5aa63583 KK |
356 | if (child->pcie_type != PCI_EXP_TYPE_ENDPOINT && |
357 | child->pcie_type != PCI_EXP_TYPE_LEG_END) | |
7d715a6c SL |
358 | continue; |
359 | ||
5aa63583 KK |
360 | pos = pci_find_capability(child, PCI_CAP_ID_EXP); |
361 | pci_read_config_dword(child, pos + PCI_EXP_DEVCAP, ®32); | |
7d715a6c SL |
362 | latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; |
363 | latency = calc_L0S_latency(latency, 1); | |
b6c2e54d | 364 | acceptable->l0s = latency; |
5aa63583 | 365 | if (link->aspm_support & PCIE_LINK_STATE_L1) { |
7d715a6c SL |
366 | latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; |
367 | latency = calc_L1_latency(latency, 1); | |
b6c2e54d | 368 | acceptable->l1 = latency; |
7d715a6c SL |
369 | } |
370 | } | |
371 | } | |
372 | ||
f7ea3d7f KK |
373 | /** |
374 | * __pcie_aspm_check_state_one - check latency for endpoint device. | |
375 | * @endpoint: pointer to the struct pci_dev of endpoint device | |
376 | * | |
377 | * TBD: The latency from the endpoint to root complex vary per switch's | |
378 | * upstream link state above the device. Here we just do a simple check | |
379 | * which assumes all links above the device can be in L1 state, that | |
380 | * is we just consider the worst case. If switch's upstream link can't | |
381 | * be put into L0S/L1, then our check is too strictly. | |
382 | */ | |
383 | static u32 __pcie_aspm_check_state_one(struct pci_dev *endpoint, u32 state) | |
7d715a6c | 384 | { |
f7ea3d7f | 385 | u32 l1_switch_latency = 0; |
b6c2e54d | 386 | struct aspm_latency *acceptable; |
f7ea3d7f | 387 | struct pcie_link_state *link; |
7d715a6c | 388 | |
f7ea3d7f KK |
389 | link = endpoint->bus->self->link_state; |
390 | state &= link->aspm_support; | |
391 | acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)]; | |
7d715a6c | 392 | |
f7ea3d7f | 393 | while (link && state) { |
b6c2e54d | 394 | if ((state & PCIE_LINK_STATE_L0S) && |
f7ea3d7f | 395 | (link->latency.l0s > acceptable->l0s)) |
b6c2e54d | 396 | state &= ~PCIE_LINK_STATE_L0S; |
b6c2e54d | 397 | if ((state & PCIE_LINK_STATE_L1) && |
f7ea3d7f | 398 | (link->latency.l1 + l1_switch_latency > acceptable->l1)) |
b6c2e54d | 399 | state &= ~PCIE_LINK_STATE_L1; |
f7ea3d7f KK |
400 | link = link->parent; |
401 | /* | |
402 | * Every switch on the path to root complex need 1 | |
403 | * more microsecond for L1. Spec doesn't mention L0s. | |
404 | */ | |
405 | l1_switch_latency += 1000; | |
7d715a6c SL |
406 | } |
407 | return state; | |
408 | } | |
409 | ||
5aa63583 | 410 | static u32 pcie_aspm_check_state(struct pcie_link_state *link, u32 state) |
7d715a6c | 411 | { |
5aa63583 KK |
412 | pci_power_t power_state; |
413 | struct pci_dev *child; | |
414 | struct pci_bus *linkbus = link->pdev->subordinate; | |
7d715a6c | 415 | |
46bbdfa4 | 416 | /* If no child, ignore the link */ |
5aa63583 | 417 | if (list_empty(&linkbus->devices)) |
46bbdfa4 | 418 | return state; |
5aa63583 KK |
419 | |
420 | list_for_each_entry(child, &linkbus->devices, bus_list) { | |
421 | /* | |
422 | * If downstream component of a link is pci bridge, we | |
423 | * disable ASPM for now for the link | |
424 | */ | |
425 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) | |
426 | return 0; | |
427 | ||
428 | if ((child->pcie_type != PCI_EXP_TYPE_ENDPOINT && | |
429 | child->pcie_type != PCI_EXP_TYPE_LEG_END)) | |
7d715a6c SL |
430 | continue; |
431 | /* Device not in D0 doesn't need check latency */ | |
5aa63583 KK |
432 | power_state = child->current_state; |
433 | if (power_state == PCI_D1 || power_state == PCI_D2 || | |
434 | power_state == PCI_D3hot || power_state == PCI_D3cold) | |
7d715a6c | 435 | continue; |
5aa63583 | 436 | state = __pcie_aspm_check_state_one(child, state); |
7d715a6c SL |
437 | } |
438 | return state; | |
439 | } | |
440 | ||
441 | static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state) | |
442 | { | |
443 | u16 reg16; | |
444 | int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
445 | ||
446 | pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); | |
447 | reg16 &= ~0x3; | |
448 | reg16 |= state; | |
449 | pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); | |
450 | } | |
451 | ||
5aa63583 | 452 | static void __pcie_aspm_config_link(struct pcie_link_state *link, u32 state) |
7d715a6c | 453 | { |
5aa63583 KK |
454 | struct pci_dev *child, *parent = link->pdev; |
455 | struct pci_bus *linkbus = parent->subordinate; | |
7d715a6c | 456 | |
46bbdfa4 | 457 | /* If no child, disable the link */ |
5aa63583 | 458 | if (list_empty(&linkbus->devices)) |
46bbdfa4 | 459 | state = 0; |
7d715a6c | 460 | /* |
5aa63583 KK |
461 | * If the downstream component has pci bridge function, don't |
462 | * do ASPM now. | |
7d715a6c | 463 | */ |
5aa63583 KK |
464 | list_for_each_entry(child, &linkbus->devices, bus_list) { |
465 | if (child->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) | |
466 | return; | |
7d715a6c | 467 | } |
7d715a6c | 468 | /* |
5aa63583 KK |
469 | * Spec 2.0 suggests all functions should be configured the |
470 | * same setting for ASPM. Enabling ASPM L1 should be done in | |
471 | * upstream component first and then downstream, and vice | |
472 | * versa for disabling ASPM L1. Spec doesn't mention L0S. | |
7d715a6c SL |
473 | */ |
474 | if (state & PCIE_LINK_STATE_L1) | |
5aa63583 | 475 | __pcie_aspm_config_one_dev(parent, state); |
7d715a6c | 476 | |
5aa63583 KK |
477 | list_for_each_entry(child, &linkbus->devices, bus_list) |
478 | __pcie_aspm_config_one_dev(child, state); | |
7d715a6c SL |
479 | |
480 | if (!(state & PCIE_LINK_STATE_L1)) | |
5aa63583 | 481 | __pcie_aspm_config_one_dev(parent, state); |
7d715a6c | 482 | |
5aa63583 | 483 | link->aspm_enabled = state; |
7d715a6c SL |
484 | } |
485 | ||
46bbdfa4 SL |
486 | static struct pcie_link_state *get_root_port_link(struct pcie_link_state *link) |
487 | { | |
488 | struct pcie_link_state *root_port_link = link; | |
489 | while (root_port_link->parent) | |
490 | root_port_link = root_port_link->parent; | |
491 | return root_port_link; | |
492 | } | |
493 | ||
5aa63583 KK |
494 | /* Check the whole hierarchy, and configure each link in the hierarchy */ |
495 | static void __pcie_aspm_configure_link_state(struct pcie_link_state *link, | |
496 | u32 state) | |
7d715a6c | 497 | { |
5aa63583 | 498 | struct pcie_link_state *leaf, *root = get_root_port_link(link); |
7d715a6c | 499 | |
5aa63583 | 500 | state &= (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); |
7d715a6c | 501 | |
5aa63583 | 502 | /* Check all links who have specific root port link */ |
dc64cd11 | 503 | list_for_each_entry(leaf, &link_list, sibling) { |
46bbdfa4 | 504 | if (!list_empty(&leaf->children) || |
5aa63583 | 505 | get_root_port_link(leaf) != root) |
46bbdfa4 | 506 | continue; |
5aa63583 | 507 | state = pcie_aspm_check_state(leaf, state); |
46bbdfa4 | 508 | } |
5aa63583 KK |
509 | /* Check root port link too in case it hasn't children */ |
510 | state = pcie_aspm_check_state(root, state); | |
511 | if (link->aspm_enabled == state) | |
7d715a6c | 512 | return; |
46bbdfa4 | 513 | /* |
5aa63583 | 514 | * We must change the hierarchy. See comments in |
46bbdfa4 SL |
515 | * __pcie_aspm_config_link for the order |
516 | **/ | |
517 | if (state & PCIE_LINK_STATE_L1) { | |
dc64cd11 | 518 | list_for_each_entry(leaf, &link_list, sibling) { |
5aa63583 KK |
519 | if (get_root_port_link(leaf) == root) |
520 | __pcie_aspm_config_link(leaf, state); | |
46bbdfa4 SL |
521 | } |
522 | } else { | |
dc64cd11 | 523 | list_for_each_entry_reverse(leaf, &link_list, sibling) { |
5aa63583 KK |
524 | if (get_root_port_link(leaf) == root) |
525 | __pcie_aspm_config_link(leaf, state); | |
46bbdfa4 SL |
526 | } |
527 | } | |
7d715a6c SL |
528 | } |
529 | ||
530 | /* | |
531 | * pcie_aspm_configure_link_state: enable/disable PCI express link state | |
532 | * @pdev: the root port or switch downstream port | |
533 | */ | |
5aa63583 KK |
534 | static void pcie_aspm_configure_link_state(struct pcie_link_state *link, |
535 | u32 state) | |
7d715a6c SL |
536 | { |
537 | down_read(&pci_bus_sem); | |
538 | mutex_lock(&aspm_lock); | |
5aa63583 | 539 | __pcie_aspm_configure_link_state(link, state); |
7d715a6c SL |
540 | mutex_unlock(&aspm_lock); |
541 | up_read(&pci_bus_sem); | |
542 | } | |
543 | ||
5aa63583 | 544 | static void free_link_state(struct pcie_link_state *link) |
7d715a6c | 545 | { |
5aa63583 KK |
546 | link->pdev->link_state = NULL; |
547 | kfree(link); | |
7d715a6c SL |
548 | } |
549 | ||
ddc9753f SL |
550 | static int pcie_aspm_sanity_check(struct pci_dev *pdev) |
551 | { | |
552 | struct pci_dev *child_dev; | |
553 | int child_pos; | |
149e1637 | 554 | u32 reg32; |
ddc9753f SL |
555 | |
556 | /* | |
557 | * Some functions in a slot might not all be PCIE functions, very | |
558 | * strange. Disable ASPM for the whole slot | |
559 | */ | |
560 | list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { | |
561 | child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); | |
562 | if (!child_pos) | |
563 | return -EINVAL; | |
149e1637 SL |
564 | |
565 | /* | |
566 | * Disable ASPM for pre-1.1 PCIe device, we follow MS to use | |
567 | * RBER bit to determine if a function is 1.1 version device | |
568 | */ | |
569 | pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP, | |
570 | ®32); | |
e1f4f59d | 571 | if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { |
f393d9b1 VL |
572 | dev_printk(KERN_INFO, &child_dev->dev, "disabling ASPM" |
573 | " on pre-1.1 PCIe device. You can enable it" | |
574 | " with 'pcie_aspm=force'\n"); | |
149e1637 SL |
575 | return -EINVAL; |
576 | } | |
ddc9753f SL |
577 | } |
578 | return 0; | |
579 | } | |
580 | ||
8d349ace KK |
581 | static struct pcie_link_state *pcie_aspm_setup_link_state(struct pci_dev *pdev) |
582 | { | |
583 | struct pcie_link_state *link; | |
584 | int blacklist = !!pcie_aspm_sanity_check(pdev); | |
585 | ||
586 | link = kzalloc(sizeof(*link), GFP_KERNEL); | |
587 | if (!link) | |
588 | return NULL; | |
589 | INIT_LIST_HEAD(&link->sibling); | |
590 | INIT_LIST_HEAD(&link->children); | |
591 | INIT_LIST_HEAD(&link->link); | |
592 | link->pdev = pdev; | |
593 | link->has_switch = pcie_aspm_downstream_has_switch(link); | |
594 | if (pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) { | |
595 | struct pcie_link_state *parent; | |
596 | parent = pdev->bus->parent->self->link_state; | |
597 | if (!parent) { | |
598 | kfree(link); | |
599 | return NULL; | |
600 | } | |
601 | link->parent = parent; | |
602 | list_add(&link->link, &parent->children); | |
603 | } | |
604 | list_add(&link->sibling, &link_list); | |
605 | ||
606 | pdev->link_state = link; | |
607 | ||
608 | /* Check ASPM capability */ | |
609 | pcie_aspm_cap_init(link, blacklist); | |
610 | ||
611 | /* Check Clock PM capability */ | |
612 | pcie_clkpm_cap_init(link, blacklist); | |
613 | ||
614 | return link; | |
615 | } | |
616 | ||
7d715a6c SL |
617 | /* |
618 | * pcie_aspm_init_link_state: Initiate PCI express link state. | |
619 | * It is called after the pcie and its children devices are scaned. | |
620 | * @pdev: the root port or switch downstream port | |
621 | */ | |
622 | void pcie_aspm_init_link_state(struct pci_dev *pdev) | |
623 | { | |
8d349ace KK |
624 | u32 state; |
625 | struct pcie_link_state *link; | |
7d715a6c SL |
626 | |
627 | if (aspm_disabled || !pdev->is_pcie || pdev->link_state) | |
628 | return; | |
629 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 630 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) |
7d715a6c | 631 | return; |
8d349ace | 632 | |
8e822df7 SL |
633 | /* VIA has a strange chipset, root port is under a bridge */ |
634 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT && | |
8d349ace | 635 | pdev->bus->self) |
8e822df7 | 636 | return; |
8d349ace | 637 | |
7d715a6c SL |
638 | down_read(&pci_bus_sem); |
639 | if (list_empty(&pdev->subordinate->devices)) | |
640 | goto out; | |
641 | ||
642 | mutex_lock(&aspm_lock); | |
8d349ace KK |
643 | link = pcie_aspm_setup_link_state(pdev); |
644 | if (!link) | |
645 | goto unlock; | |
646 | /* | |
647 | * Setup initial ASPM state | |
648 | * | |
649 | * If link has switch, delay the link config. The leaf link | |
650 | * initialization will config the whole hierarchy. But we must | |
651 | * make sure BIOS doesn't set unsupported link state. | |
652 | */ | |
653 | if (link->has_switch) { | |
654 | state = pcie_aspm_check_state(link, link->aspm_default); | |
655 | __pcie_aspm_config_link(link, state); | |
46bbdfa4 | 656 | } else { |
8d349ace KK |
657 | state = policy_to_aspm_state(link); |
658 | __pcie_aspm_configure_link_state(link, state); | |
46bbdfa4 | 659 | } |
7d715a6c | 660 | |
8d349ace KK |
661 | /* Setup initial Clock PM state */ |
662 | state = (link->clkpm_capable) ? policy_to_clkpm_state(link) : 0; | |
663 | pcie_set_clock_pm(link, state); | |
664 | unlock: | |
7d715a6c SL |
665 | mutex_unlock(&aspm_lock); |
666 | out: | |
667 | up_read(&pci_bus_sem); | |
668 | } | |
669 | ||
670 | /* @pdev: the endpoint device */ | |
671 | void pcie_aspm_exit_link_state(struct pci_dev *pdev) | |
672 | { | |
673 | struct pci_dev *parent = pdev->bus->self; | |
674 | struct pcie_link_state *link_state = parent->link_state; | |
675 | ||
676 | if (aspm_disabled || !pdev->is_pcie || !parent || !link_state) | |
677 | return; | |
678 | if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
679 | parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
680 | return; | |
681 | down_read(&pci_bus_sem); | |
682 | mutex_lock(&aspm_lock); | |
683 | ||
684 | /* | |
685 | * All PCIe functions are in one slot, remove one function will remove | |
3419c75e | 686 | * the whole slot, so just wait until we are the last function left. |
7d715a6c | 687 | */ |
3419c75e | 688 | if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices)) |
7d715a6c SL |
689 | goto out; |
690 | ||
691 | /* All functions are removed, so just disable ASPM for the link */ | |
692 | __pcie_aspm_config_one_dev(parent, 0); | |
dc64cd11 | 693 | list_del(&link_state->sibling); |
46bbdfa4 | 694 | list_del(&link_state->link); |
7d715a6c SL |
695 | /* Clock PM is for endpoint device */ |
696 | ||
5aa63583 | 697 | free_link_state(link_state); |
7d715a6c SL |
698 | out: |
699 | mutex_unlock(&aspm_lock); | |
700 | up_read(&pci_bus_sem); | |
701 | } | |
702 | ||
703 | /* @pdev: the root port or switch downstream port */ | |
704 | void pcie_aspm_pm_state_change(struct pci_dev *pdev) | |
705 | { | |
706 | struct pcie_link_state *link_state = pdev->link_state; | |
707 | ||
708 | if (aspm_disabled || !pdev->is_pcie || !pdev->link_state) | |
709 | return; | |
710 | if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
711 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) | |
712 | return; | |
713 | /* | |
714 | * devices changed PM state, we should recheck if latency meets all | |
715 | * functions' requirement | |
716 | */ | |
5aa63583 | 717 | pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled); |
7d715a6c SL |
718 | } |
719 | ||
720 | /* | |
721 | * pci_disable_link_state - disable pci device's link state, so the link will | |
722 | * never enter specific states | |
723 | */ | |
724 | void pci_disable_link_state(struct pci_dev *pdev, int state) | |
725 | { | |
726 | struct pci_dev *parent = pdev->bus->self; | |
727 | struct pcie_link_state *link_state; | |
728 | ||
729 | if (aspm_disabled || !pdev->is_pcie) | |
730 | return; | |
731 | if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
732 | pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
733 | parent = pdev; | |
734 | if (!parent || !parent->link_state) | |
735 | return; | |
736 | ||
737 | down_read(&pci_bus_sem); | |
738 | mutex_lock(&aspm_lock); | |
739 | link_state = parent->link_state; | |
80bfdbe3 | 740 | link_state->aspm_support &= ~state; |
7d715a6c | 741 | if (state & PCIE_LINK_STATE_CLKPM) |
4d246e45 | 742 | link_state->clkpm_capable = 0; |
7d715a6c | 743 | |
5aa63583 | 744 | __pcie_aspm_configure_link_state(link_state, link_state->aspm_enabled); |
4d246e45 | 745 | if (!link_state->clkpm_capable && link_state->clkpm_enabled) |
5aa63583 | 746 | pcie_set_clock_pm(link_state, 0); |
7d715a6c SL |
747 | mutex_unlock(&aspm_lock); |
748 | up_read(&pci_bus_sem); | |
749 | } | |
750 | EXPORT_SYMBOL(pci_disable_link_state); | |
751 | ||
752 | static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) | |
753 | { | |
754 | int i; | |
7d715a6c SL |
755 | struct pcie_link_state *link_state; |
756 | ||
757 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
758 | if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) | |
759 | break; | |
760 | if (i >= ARRAY_SIZE(policy_str)) | |
761 | return -EINVAL; | |
762 | if (i == aspm_policy) | |
763 | return 0; | |
764 | ||
765 | down_read(&pci_bus_sem); | |
766 | mutex_lock(&aspm_lock); | |
767 | aspm_policy = i; | |
dc64cd11 | 768 | list_for_each_entry(link_state, &link_list, sibling) { |
5aa63583 KK |
769 | __pcie_aspm_configure_link_state(link_state, |
770 | policy_to_aspm_state(link_state)); | |
4d246e45 | 771 | if (link_state->clkpm_capable && |
5aa63583 KK |
772 | link_state->clkpm_enabled != policy_to_clkpm_state(link_state)) |
773 | pcie_set_clock_pm(link_state, | |
774 | policy_to_clkpm_state(link_state)); | |
7d715a6c SL |
775 | |
776 | } | |
777 | mutex_unlock(&aspm_lock); | |
778 | up_read(&pci_bus_sem); | |
779 | return 0; | |
780 | } | |
781 | ||
782 | static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) | |
783 | { | |
784 | int i, cnt = 0; | |
785 | for (i = 0; i < ARRAY_SIZE(policy_str); i++) | |
786 | if (i == aspm_policy) | |
787 | cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); | |
788 | else | |
789 | cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); | |
790 | return cnt; | |
791 | } | |
792 | ||
793 | module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, | |
794 | NULL, 0644); | |
795 | ||
796 | #ifdef CONFIG_PCIEASPM_DEBUG | |
797 | static ssize_t link_state_show(struct device *dev, | |
798 | struct device_attribute *attr, | |
799 | char *buf) | |
800 | { | |
801 | struct pci_dev *pci_device = to_pci_dev(dev); | |
802 | struct pcie_link_state *link_state = pci_device->link_state; | |
803 | ||
80bfdbe3 | 804 | return sprintf(buf, "%d\n", link_state->aspm_enabled); |
7d715a6c SL |
805 | } |
806 | ||
807 | static ssize_t link_state_store(struct device *dev, | |
808 | struct device_attribute *attr, | |
809 | const char *buf, | |
810 | size_t n) | |
811 | { | |
5aa63583 | 812 | struct pci_dev *pdev = to_pci_dev(dev); |
7d715a6c SL |
813 | int state; |
814 | ||
815 | if (n < 1) | |
816 | return -EINVAL; | |
817 | state = buf[0]-'0'; | |
818 | if (state >= 0 && state <= 3) { | |
819 | /* setup link aspm state */ | |
5aa63583 | 820 | pcie_aspm_configure_link_state(pdev->link_state, state); |
7d715a6c SL |
821 | return n; |
822 | } | |
823 | ||
824 | return -EINVAL; | |
825 | } | |
826 | ||
827 | static ssize_t clk_ctl_show(struct device *dev, | |
828 | struct device_attribute *attr, | |
829 | char *buf) | |
830 | { | |
831 | struct pci_dev *pci_device = to_pci_dev(dev); | |
832 | struct pcie_link_state *link_state = pci_device->link_state; | |
833 | ||
4d246e45 | 834 | return sprintf(buf, "%d\n", link_state->clkpm_enabled); |
7d715a6c SL |
835 | } |
836 | ||
837 | static ssize_t clk_ctl_store(struct device *dev, | |
838 | struct device_attribute *attr, | |
839 | const char *buf, | |
840 | size_t n) | |
841 | { | |
842 | struct pci_dev *pci_device = to_pci_dev(dev); | |
843 | int state; | |
844 | ||
845 | if (n < 1) | |
846 | return -EINVAL; | |
847 | state = buf[0]-'0'; | |
848 | ||
849 | down_read(&pci_bus_sem); | |
850 | mutex_lock(&aspm_lock); | |
5aa63583 | 851 | pcie_set_clock_pm(pci_device->link_state, !!state); |
7d715a6c SL |
852 | mutex_unlock(&aspm_lock); |
853 | up_read(&pci_bus_sem); | |
854 | ||
855 | return n; | |
856 | } | |
857 | ||
858 | static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); | |
859 | static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); | |
860 | ||
861 | static char power_group[] = "power"; | |
862 | void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) | |
863 | { | |
864 | struct pcie_link_state *link_state = pdev->link_state; | |
865 | ||
866 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
867 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
868 | return; | |
869 | ||
80bfdbe3 | 870 | if (link_state->aspm_support) |
7d715a6c SL |
871 | sysfs_add_file_to_group(&pdev->dev.kobj, |
872 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 873 | if (link_state->clkpm_capable) |
7d715a6c SL |
874 | sysfs_add_file_to_group(&pdev->dev.kobj, |
875 | &dev_attr_clk_ctl.attr, power_group); | |
876 | } | |
877 | ||
878 | void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) | |
879 | { | |
880 | struct pcie_link_state *link_state = pdev->link_state; | |
881 | ||
882 | if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && | |
883 | pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) || !link_state) | |
884 | return; | |
885 | ||
80bfdbe3 | 886 | if (link_state->aspm_support) |
7d715a6c SL |
887 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
888 | &dev_attr_link_state.attr, power_group); | |
4d246e45 | 889 | if (link_state->clkpm_capable) |
7d715a6c SL |
890 | sysfs_remove_file_from_group(&pdev->dev.kobj, |
891 | &dev_attr_clk_ctl.attr, power_group); | |
892 | } | |
893 | #endif | |
894 | ||
895 | static int __init pcie_aspm_disable(char *str) | |
896 | { | |
d6d38574 SL |
897 | if (!strcmp(str, "off")) { |
898 | aspm_disabled = 1; | |
899 | printk(KERN_INFO "PCIe ASPM is disabled\n"); | |
900 | } else if (!strcmp(str, "force")) { | |
901 | aspm_force = 1; | |
902 | printk(KERN_INFO "PCIe ASPM is forcedly enabled\n"); | |
903 | } | |
7d715a6c SL |
904 | return 1; |
905 | } | |
906 | ||
d6d38574 | 907 | __setup("pcie_aspm=", pcie_aspm_disable); |
7d715a6c | 908 | |
5fde244d SL |
909 | void pcie_no_aspm(void) |
910 | { | |
d6d38574 SL |
911 | if (!aspm_force) |
912 | aspm_disabled = 1; | |
5fde244d SL |
913 | } |
914 | ||
3e1b1600 AP |
915 | /** |
916 | * pcie_aspm_enabled - is PCIe ASPM enabled? | |
917 | * | |
918 | * Returns true if ASPM has not been disabled by the command-line option | |
919 | * pcie_aspm=off. | |
920 | **/ | |
921 | int pcie_aspm_enabled(void) | |
7d715a6c | 922 | { |
3e1b1600 | 923 | return !aspm_disabled; |
7d715a6c | 924 | } |
3e1b1600 | 925 | EXPORT_SYMBOL(pcie_aspm_enabled); |
7d715a6c | 926 |