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c7f48656 RW |
1 | /* |
2 | * PCIe Native PME support | |
3 | * | |
4 | * Copyright (C) 2007 - 2009 Intel Corp | |
5 | * Copyright (C) 2007 - 2009 Shaohua Li <shaohua.li@intel.com> | |
6 | * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc. | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License V2. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/pcieport_if.h> | |
21 | #include <linux/acpi.h> | |
22 | #include <linux/pci-acpi.h> | |
23 | #include <linux/pm_runtime.h> | |
24 | ||
25 | #include "../../pci.h" | |
26 | #include "pcie_pme.h" | |
27 | ||
28 | #define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ | |
29 | #define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ | |
30 | ||
31 | /* | |
32 | * If set, this switch will prevent the PCIe root port PME service driver from | |
33 | * being registered. Consequently, the interrupt-based PCIe PME signaling will | |
34 | * not be used by any PCIe root ports in that case. | |
35 | */ | |
36 | static bool pcie_pme_disabled; | |
37 | ||
38 | /* | |
39 | * The PCI Express Base Specification 2.0, Section 6.1.8, states the following: | |
40 | * "In order to maintain compatibility with non-PCI Express-aware system | |
41 | * software, system power management logic must be configured by firmware to use | |
42 | * the legacy mechanism of signaling PME by default. PCI Express-aware system | |
43 | * software must notify the firmware prior to enabling native, interrupt-based | |
44 | * PME signaling." However, if the platform doesn't provide us with a suitable | |
45 | * notification mechanism or the notification fails, it is not clear whether or | |
46 | * not we are supposed to use the interrupt-based PCIe PME signaling. The | |
47 | * switch below can be used to indicate the desired behaviour. When set, it | |
48 | * will make the kernel use the interrupt-based PCIe PME signaling regardless of | |
49 | * the platform notification status, although the kernel will attempt to notify | |
50 | * the platform anyway. When unset, it will prevent the kernel from using the | |
51 | * the interrupt-based PCIe PME signaling if the platform notification fails, | |
52 | * which is the default. | |
53 | */ | |
54 | static bool pcie_pme_force_enable; | |
55 | ||
c39fae14 RW |
56 | /* |
57 | * If this switch is set, MSI will not be used for PCIe PME signaling. This | |
58 | * causes the PCIe port driver to use INTx interrupts only, but it turns out | |
59 | * that using MSI for PCIe PME signaling doesn't play well with PCIe PME-based | |
60 | * wake-up from system sleep states. | |
61 | */ | |
62 | bool pcie_pme_msi_disabled; | |
63 | ||
c7f48656 RW |
64 | static int __init pcie_pme_setup(char *str) |
65 | { | |
66 | if (!strcmp(str, "off")) | |
67 | pcie_pme_disabled = true; | |
68 | else if (!strcmp(str, "force")) | |
69 | pcie_pme_force_enable = true; | |
c39fae14 RW |
70 | else if (!strcmp(str, "nomsi")) |
71 | pcie_pme_msi_disabled = true; | |
c7f48656 RW |
72 | return 1; |
73 | } | |
74 | __setup("pcie_pme=", pcie_pme_setup); | |
75 | ||
76 | /** | |
77 | * pcie_pme_platform_setup - Ensure that the kernel controls the PCIe PME. | |
78 | * @srv: PCIe PME root port service to use for carrying out the check. | |
79 | * | |
80 | * Notify the platform that the native PCIe PME is going to be used and return | |
81 | * 'true' if the control of the PCIe PME registers has been acquired from the | |
82 | * platform. | |
83 | */ | |
84 | static bool pcie_pme_platform_setup(struct pcie_device *srv) | |
85 | { | |
c39fae14 RW |
86 | if (!pcie_pme_platform_notify(srv)) |
87 | return true; | |
88 | return pcie_pme_force_enable; | |
c7f48656 RW |
89 | } |
90 | ||
91 | struct pcie_pme_service_data { | |
92 | spinlock_t lock; | |
93 | struct pcie_device *srv; | |
94 | struct work_struct work; | |
95 | bool noirq; /* Don't enable the PME interrupt used by this service. */ | |
96 | }; | |
97 | ||
98 | /** | |
99 | * pcie_pme_interrupt_enable - Enable/disable PCIe PME interrupt generation. | |
100 | * @dev: PCIe root port or event collector. | |
101 | * @enable: Enable or disable the interrupt. | |
102 | */ | |
103 | static void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable) | |
104 | { | |
105 | int rtctl_pos; | |
106 | u16 rtctl; | |
107 | ||
108 | rtctl_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTCTL; | |
109 | ||
110 | pci_read_config_word(dev, rtctl_pos, &rtctl); | |
111 | if (enable) | |
112 | rtctl |= PCI_EXP_RTCTL_PMEIE; | |
113 | else | |
114 | rtctl &= ~PCI_EXP_RTCTL_PMEIE; | |
115 | pci_write_config_word(dev, rtctl_pos, rtctl); | |
116 | } | |
117 | ||
118 | /** | |
119 | * pcie_pme_clear_status - Clear root port PME interrupt status. | |
120 | * @dev: PCIe root port or event collector. | |
121 | */ | |
122 | static void pcie_pme_clear_status(struct pci_dev *dev) | |
123 | { | |
124 | int rtsta_pos; | |
125 | u32 rtsta; | |
126 | ||
127 | rtsta_pos = pci_find_capability(dev, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA; | |
128 | ||
129 | pci_read_config_dword(dev, rtsta_pos, &rtsta); | |
130 | rtsta |= PCI_EXP_RTSTA_PME; | |
131 | pci_write_config_dword(dev, rtsta_pos, rtsta); | |
132 | } | |
133 | ||
134 | /** | |
135 | * pcie_pme_walk_bus - Scan a PCI bus for devices asserting PME#. | |
136 | * @bus: PCI bus to scan. | |
137 | * | |
138 | * Scan given PCI bus and all buses under it for devices asserting PME#. | |
139 | */ | |
140 | static bool pcie_pme_walk_bus(struct pci_bus *bus) | |
141 | { | |
142 | struct pci_dev *dev; | |
143 | bool ret = false; | |
144 | ||
145 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
146 | /* Skip PCIe devices in case we started from a root port. */ | |
147 | if (!dev->is_pcie && pci_check_pme_status(dev)) { | |
148 | pm_request_resume(&dev->dev); | |
149 | ret = true; | |
150 | } | |
151 | ||
152 | if (dev->subordinate && pcie_pme_walk_bus(dev->subordinate)) | |
153 | ret = true; | |
154 | } | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
159 | /** | |
160 | * pcie_pme_from_pci_bridge - Check if PCIe-PCI bridge generated a PME. | |
161 | * @bus: Secondary bus of the bridge. | |
162 | * @devfn: Device/function number to check. | |
163 | * | |
164 | * PME from PCI devices under a PCIe-PCI bridge may be converted to an in-band | |
165 | * PCIe PME message. In such that case the bridge should use the Requester ID | |
166 | * of device/function number 0 on its secondary bus. | |
167 | */ | |
168 | static bool pcie_pme_from_pci_bridge(struct pci_bus *bus, u8 devfn) | |
169 | { | |
170 | struct pci_dev *dev; | |
171 | bool found = false; | |
172 | ||
173 | if (devfn) | |
174 | return false; | |
175 | ||
176 | dev = pci_dev_get(bus->self); | |
177 | if (!dev) | |
178 | return false; | |
179 | ||
180 | if (dev->is_pcie && dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { | |
181 | down_read(&pci_bus_sem); | |
182 | if (pcie_pme_walk_bus(bus)) | |
183 | found = true; | |
184 | up_read(&pci_bus_sem); | |
185 | } | |
186 | ||
187 | pci_dev_put(dev); | |
188 | return found; | |
189 | } | |
190 | ||
191 | /** | |
192 | * pcie_pme_handle_request - Find device that generated PME and handle it. | |
193 | * @port: Root port or event collector that generated the PME interrupt. | |
194 | * @req_id: PCIe Requester ID of the device that generated the PME. | |
195 | */ | |
196 | static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id) | |
197 | { | |
198 | u8 busnr = req_id >> 8, devfn = req_id & 0xff; | |
199 | struct pci_bus *bus; | |
200 | struct pci_dev *dev; | |
201 | bool found = false; | |
202 | ||
203 | /* First, check if the PME is from the root port itself. */ | |
204 | if (port->devfn == devfn && port->bus->number == busnr) { | |
205 | if (pci_check_pme_status(port)) { | |
206 | pm_request_resume(&port->dev); | |
207 | found = true; | |
208 | } else { | |
209 | /* | |
210 | * Apparently, the root port generated the PME on behalf | |
211 | * of a non-PCIe device downstream. If this is done by | |
212 | * a root port, the Requester ID field in its status | |
213 | * register may contain either the root port's, or the | |
214 | * source device's information (PCI Express Base | |
215 | * Specification, Rev. 2.0, Section 6.1.9). | |
216 | */ | |
217 | down_read(&pci_bus_sem); | |
218 | found = pcie_pme_walk_bus(port->subordinate); | |
219 | up_read(&pci_bus_sem); | |
220 | } | |
221 | goto out; | |
222 | } | |
223 | ||
224 | /* Second, find the bus the source device is on. */ | |
225 | bus = pci_find_bus(pci_domain_nr(port->bus), busnr); | |
226 | if (!bus) | |
227 | goto out; | |
228 | ||
229 | /* Next, check if the PME is from a PCIe-PCI bridge. */ | |
230 | found = pcie_pme_from_pci_bridge(bus, devfn); | |
231 | if (found) | |
232 | goto out; | |
233 | ||
234 | /* Finally, try to find the PME source on the bus. */ | |
235 | down_read(&pci_bus_sem); | |
236 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
237 | pci_dev_get(dev); | |
238 | if (dev->devfn == devfn) { | |
239 | found = true; | |
240 | break; | |
241 | } | |
242 | pci_dev_put(dev); | |
243 | } | |
244 | up_read(&pci_bus_sem); | |
245 | ||
246 | if (found) { | |
247 | /* The device is there, but we have to check its PME status. */ | |
248 | found = pci_check_pme_status(dev); | |
249 | if (found) | |
250 | pm_request_resume(&dev->dev); | |
251 | pci_dev_put(dev); | |
252 | } else if (devfn) { | |
253 | /* | |
254 | * The device is not there, but we can still try to recover by | |
255 | * assuming that the PME was reported by a PCIe-PCI bridge that | |
256 | * used devfn different from zero. | |
257 | */ | |
258 | dev_dbg(&port->dev, "PME interrupt generated for " | |
259 | "non-existent device %02x:%02x.%d\n", | |
260 | busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
261 | found = pcie_pme_from_pci_bridge(bus, 0); | |
262 | } | |
263 | ||
264 | out: | |
265 | if (!found) | |
266 | dev_dbg(&port->dev, "Spurious native PME interrupt!\n"); | |
267 | } | |
268 | ||
269 | /** | |
270 | * pcie_pme_work_fn - Work handler for PCIe PME interrupt. | |
271 | * @work: Work structure giving access to service data. | |
272 | */ | |
273 | static void pcie_pme_work_fn(struct work_struct *work) | |
274 | { | |
275 | struct pcie_pme_service_data *data = | |
276 | container_of(work, struct pcie_pme_service_data, work); | |
277 | struct pci_dev *port = data->srv->port; | |
278 | int rtsta_pos; | |
279 | u32 rtsta; | |
280 | ||
281 | rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA; | |
282 | ||
283 | spin_lock_irq(&data->lock); | |
284 | ||
285 | for (;;) { | |
286 | if (data->noirq) | |
287 | break; | |
288 | ||
289 | pci_read_config_dword(port, rtsta_pos, &rtsta); | |
290 | if (rtsta & PCI_EXP_RTSTA_PME) { | |
291 | /* | |
292 | * Clear PME status of the port. If there are other | |
293 | * pending PMEs, the status will be set again. | |
294 | */ | |
295 | pcie_pme_clear_status(port); | |
296 | ||
297 | spin_unlock_irq(&data->lock); | |
298 | pcie_pme_handle_request(port, rtsta & 0xffff); | |
299 | spin_lock_irq(&data->lock); | |
300 | ||
301 | continue; | |
302 | } | |
303 | ||
304 | /* No need to loop if there are no more PMEs pending. */ | |
305 | if (!(rtsta & PCI_EXP_RTSTA_PENDING)) | |
306 | break; | |
307 | ||
308 | spin_unlock_irq(&data->lock); | |
309 | cpu_relax(); | |
310 | spin_lock_irq(&data->lock); | |
311 | } | |
312 | ||
313 | if (!data->noirq) | |
314 | pcie_pme_interrupt_enable(port, true); | |
315 | ||
316 | spin_unlock_irq(&data->lock); | |
317 | } | |
318 | ||
319 | /** | |
320 | * pcie_pme_irq - Interrupt handler for PCIe root port PME interrupt. | |
321 | * @irq: Interrupt vector. | |
322 | * @context: Interrupt context pointer. | |
323 | */ | |
324 | static irqreturn_t pcie_pme_irq(int irq, void *context) | |
325 | { | |
326 | struct pci_dev *port; | |
327 | struct pcie_pme_service_data *data; | |
328 | int rtsta_pos; | |
329 | u32 rtsta; | |
330 | unsigned long flags; | |
331 | ||
332 | port = ((struct pcie_device *)context)->port; | |
333 | data = get_service_data((struct pcie_device *)context); | |
334 | ||
335 | rtsta_pos = pci_find_capability(port, PCI_CAP_ID_EXP) + PCI_EXP_RTSTA; | |
336 | ||
337 | spin_lock_irqsave(&data->lock, flags); | |
338 | pci_read_config_dword(port, rtsta_pos, &rtsta); | |
339 | ||
340 | if (!(rtsta & PCI_EXP_RTSTA_PME)) { | |
341 | spin_unlock_irqrestore(&data->lock, flags); | |
342 | return IRQ_NONE; | |
343 | } | |
344 | ||
345 | pcie_pme_interrupt_enable(port, false); | |
346 | spin_unlock_irqrestore(&data->lock, flags); | |
347 | ||
348 | /* We don't use pm_wq, because it's freezable. */ | |
349 | schedule_work(&data->work); | |
350 | ||
351 | return IRQ_HANDLED; | |
352 | } | |
353 | ||
354 | /** | |
355 | * pcie_pme_set_native - Set the PME interrupt flag for given device. | |
356 | * @dev: PCI device to handle. | |
357 | * @ign: Ignored. | |
358 | */ | |
359 | static int pcie_pme_set_native(struct pci_dev *dev, void *ign) | |
360 | { | |
361 | dev_info(&dev->dev, "Signaling PME through PCIe PME interrupt\n"); | |
362 | ||
363 | device_set_run_wake(&dev->dev, true); | |
364 | dev->pme_interrupt = true; | |
365 | return 0; | |
366 | } | |
367 | ||
368 | /** | |
369 | * pcie_pme_mark_devices - Set the PME interrupt flag for devices below a port. | |
370 | * @port: PCIe root port or event collector to handle. | |
371 | * | |
372 | * For each device below given root port, including the port itself (or for each | |
373 | * root complex integrated endpoint if @port is a root complex event collector) | |
374 | * set the flag indicating that it can signal run-time wake-up events via PCIe | |
375 | * PME interrupts. | |
376 | */ | |
377 | static void pcie_pme_mark_devices(struct pci_dev *port) | |
378 | { | |
379 | pcie_pme_set_native(port, NULL); | |
380 | if (port->subordinate) { | |
381 | pci_walk_bus(port->subordinate, pcie_pme_set_native, NULL); | |
382 | } else { | |
383 | struct pci_bus *bus = port->bus; | |
384 | struct pci_dev *dev; | |
385 | ||
386 | /* Check if this is a root port event collector. */ | |
387 | if (port->pcie_type != PCI_EXP_TYPE_RC_EC || !bus) | |
388 | return; | |
389 | ||
390 | down_read(&pci_bus_sem); | |
391 | list_for_each_entry(dev, &bus->devices, bus_list) | |
392 | if (dev->is_pcie | |
393 | && dev->pcie_type == PCI_EXP_TYPE_RC_END) | |
394 | pcie_pme_set_native(dev, NULL); | |
395 | up_read(&pci_bus_sem); | |
396 | } | |
397 | } | |
398 | ||
399 | /** | |
400 | * pcie_pme_probe - Initialize PCIe PME service for given root port. | |
401 | * @srv: PCIe service to initialize. | |
402 | */ | |
403 | static int pcie_pme_probe(struct pcie_device *srv) | |
404 | { | |
405 | struct pci_dev *port; | |
406 | struct pcie_pme_service_data *data; | |
407 | int ret; | |
408 | ||
409 | if (!pcie_pme_platform_setup(srv)) | |
410 | return -EACCES; | |
411 | ||
412 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
413 | if (!data) | |
414 | return -ENOMEM; | |
415 | ||
416 | spin_lock_init(&data->lock); | |
417 | INIT_WORK(&data->work, pcie_pme_work_fn); | |
418 | data->srv = srv; | |
419 | set_service_data(srv, data); | |
420 | ||
421 | port = srv->port; | |
422 | pcie_pme_interrupt_enable(port, false); | |
423 | pcie_pme_clear_status(port); | |
424 | ||
425 | ret = request_irq(srv->irq, pcie_pme_irq, IRQF_SHARED, "PCIe PME", srv); | |
426 | if (ret) { | |
427 | kfree(data); | |
428 | } else { | |
429 | pcie_pme_mark_devices(port); | |
430 | pcie_pme_interrupt_enable(port, true); | |
431 | } | |
432 | ||
433 | return ret; | |
434 | } | |
435 | ||
436 | /** | |
437 | * pcie_pme_suspend - Suspend PCIe PME service device. | |
438 | * @srv: PCIe service device to suspend. | |
439 | */ | |
440 | static int pcie_pme_suspend(struct pcie_device *srv) | |
441 | { | |
442 | struct pcie_pme_service_data *data = get_service_data(srv); | |
443 | struct pci_dev *port = srv->port; | |
444 | ||
445 | spin_lock_irq(&data->lock); | |
446 | pcie_pme_interrupt_enable(port, false); | |
447 | pcie_pme_clear_status(port); | |
448 | data->noirq = true; | |
449 | spin_unlock_irq(&data->lock); | |
450 | ||
451 | synchronize_irq(srv->irq); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | /** | |
457 | * pcie_pme_resume - Resume PCIe PME service device. | |
458 | * @srv - PCIe service device to resume. | |
459 | */ | |
460 | static int pcie_pme_resume(struct pcie_device *srv) | |
461 | { | |
462 | struct pcie_pme_service_data *data = get_service_data(srv); | |
463 | struct pci_dev *port = srv->port; | |
464 | ||
465 | spin_lock_irq(&data->lock); | |
466 | data->noirq = false; | |
467 | pcie_pme_clear_status(port); | |
468 | pcie_pme_interrupt_enable(port, true); | |
469 | spin_unlock_irq(&data->lock); | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
474 | /** | |
475 | * pcie_pme_remove - Prepare PCIe PME service device for removal. | |
476 | * @srv - PCIe service device to resume. | |
477 | */ | |
478 | static void pcie_pme_remove(struct pcie_device *srv) | |
479 | { | |
480 | pcie_pme_suspend(srv); | |
481 | free_irq(srv->irq, srv); | |
482 | kfree(get_service_data(srv)); | |
483 | } | |
484 | ||
485 | static struct pcie_port_service_driver pcie_pme_driver = { | |
486 | .name = "pcie_pme", | |
487 | .port_type = PCI_EXP_TYPE_ROOT_PORT, | |
488 | .service = PCIE_PORT_SERVICE_PME, | |
489 | ||
490 | .probe = pcie_pme_probe, | |
491 | .suspend = pcie_pme_suspend, | |
492 | .resume = pcie_pme_resume, | |
493 | .remove = pcie_pme_remove, | |
494 | }; | |
495 | ||
496 | /** | |
497 | * pcie_pme_service_init - Register the PCIe PME service driver. | |
498 | */ | |
499 | static int __init pcie_pme_service_init(void) | |
500 | { | |
501 | return pcie_pme_disabled ? | |
502 | -ENODEV : pcie_port_service_register(&pcie_pme_driver); | |
503 | } | |
504 | ||
505 | module_init(pcie_pme_service_init); |