[deliverable/linux.git] / drivers / pci / pcie / portdrv_pci.c

/*
 * File:	portdrv_pci.c
 * Purpose:	PCI Express Port Bus Driver
 *
 * Copyright (C) 2004 Intel
 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/init.h>
#include <linux/pcieport_if.h>
#include <linux/aer.h>
#include <linux/dmi.h>
#include <linux/pci-aspm.h>

#include "portdrv.h"
#include "aer/aerdrv.h"

/*
 * Version Information
 */
#define DRIVER_VERSION "v1.0"
#define DRIVER_AUTHOR "tom.l.nguyen@intel.com"
#define DRIVER_DESC "PCIe Port Bus Driver"
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");

/* If this switch is set, PCIe port native services should not be enabled. */
bool pcie_ports_disabled;

/*
 * If this switch is set, ACPI _OSC will be used to determine whether or not to
 * enable PCIe port native services.
 */
bool pcie_ports_auto = true;

static int __init pcie_port_setup(char *str)
{
	if (!strncmp(str, "compat", 6)) {
		pcie_ports_disabled = true;
	} else if (!strncmp(str, "native", 6)) {
		pcie_ports_disabled = false;
		pcie_ports_auto = false;
	} else if (!strncmp(str, "auto", 4)) {
		pcie_ports_disabled = false;
		pcie_ports_auto = true;
	}

	return 1;
}
__setup("pcie_ports=", pcie_port_setup);

/* global data */

/**
 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
 * @dev: PCIe root port or event collector.
 */
void pcie_clear_root_pme_status(struct pci_dev *dev)
{
	int rtsta_pos;
	u32 rtsta;

	rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;

	pci_read_config_dword(dev, rtsta_pos, &rtsta);
	rtsta |= PCI_EXP_RTSTA_PME;
	pci_write_config_dword(dev, rtsta_pos, rtsta);
}

static int pcie_portdrv_restore_config(struct pci_dev *dev)
{
	int retval;

	retval = pci_enable_device(dev);
	if (retval)
		return retval;
	pci_set_master(dev);
	return 0;
}

#ifdef CONFIG_PM
static int pcie_port_resume_noirq(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);

	/*
	 * Some BIOSes forget to clear Root PME Status bits after system wakeup
	 * which breaks ACPI-based runtime wakeup on PCI Express, so clear those
	 * bits now just in case (shouldn't hurt).
	 */
	if(pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
		pcie_clear_root_pme_status(pdev);
	return 0;
}

#ifdef CONFIG_PM_RUNTIME
struct d3cold_info {
	bool no_d3cold;
	unsigned int d3cold_delay;
};

static int pci_dev_d3cold_info(struct pci_dev *pdev, void *data)
{
	struct d3cold_info *info = data;

	info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
				   info->d3cold_delay);
	if (pdev->no_d3cold)
		info->no_d3cold = true;
	return 0;
}

static int pcie_port_runtime_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct d3cold_info d3cold_info = {
		.no_d3cold	= false,
		.d3cold_delay	= PCI_PM_D3_WAIT,
	};

	/*
	 * If any subordinate device disable D3cold, we should not put
	 * the port into D3cold.  The D3cold delay of port should be
	 * the max of that of all subordinate devices.
	 */
	pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
	pdev->no_d3cold = d3cold_info.no_d3cold;
	pdev->d3cold_delay = d3cold_info.d3cold_delay;
	return 0;
}

static int pcie_port_runtime_resume(struct device *dev)
{
	return 0;
}

static int pcie_port_runtime_idle(struct device *dev)
{
	/* Delay for a short while to prevent too frequent suspend/resume */
	pm_schedule_suspend(dev, 10);
	return -EBUSY;
}
#else
#define pcie_port_runtime_suspend	NULL
#define pcie_port_runtime_resume	NULL
#define pcie_port_runtime_idle		NULL
#endif

static const struct dev_pm_ops pcie_portdrv_pm_ops = {
	.suspend	= pcie_port_device_suspend,
	.resume		= pcie_port_device_resume,
	.freeze		= pcie_port_device_suspend,
	.thaw		= pcie_port_device_resume,
	.poweroff	= pcie_port_device_suspend,
	.restore	= pcie_port_device_resume,
	.resume_noirq	= pcie_port_resume_noirq,
	.runtime_suspend = pcie_port_runtime_suspend,
	.runtime_resume = pcie_port_runtime_resume,
	.runtime_idle	= pcie_port_runtime_idle,
};

#define PCIE_PORTDRV_PM_OPS	(&pcie_portdrv_pm_ops)

#else /* !PM */

#define PCIE_PORTDRV_PM_OPS	NULL
#endif /* !PM */

/*
 * PCIe port runtime suspend is broken for some chipsets, so use a
 * black list to disable runtime PM for these chipsets.
 */
static const struct pci_device_id port_runtime_pm_black_list[] = {
	{ /* end: all zeroes */ }
};

/*
 * pcie_portdrv_probe - Probe PCI-Express port devices
 * @dev: PCI-Express port device being probed
 *
 * If detected invokes the pcie_port_device_register() method for
 * this port device.
 *
 */
static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
					const struct pci_device_id *id)
{
	int status;

	if (!pci_is_pcie(dev) ||
	    ((dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
	     (dev->pcie_type != PCI_EXP_TYPE_UPSTREAM) &&
	     (dev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)))
		return -ENODEV;

	if (!dev->irq && dev->pin) {
		dev_warn(&dev->dev, "device [%04x:%04x] has invalid IRQ; "
			 "check vendor BIOS\n", dev->vendor, dev->device);
	}
	status = pcie_port_device_register(dev);
	if (status)
		return status;

	pci_save_state(dev);
	/*
	 * D3cold may not work properly on some PCIe port, so disable
	 * it by default.
	 */
	dev->d3cold_allowed = false;
	if (!pci_match_id(port_runtime_pm_black_list, dev))
		pm_runtime_put_noidle(&dev->dev);

	return 0;
}

static void pcie_portdrv_remove(struct pci_dev *dev)
{
	if (!pci_match_id(port_runtime_pm_black_list, dev))
		pm_runtime_get_noresume(&dev->dev);
	pcie_port_device_remove(dev);
	pci_disable_device(dev);
}

static int error_detected_iter(struct device *device, void *data)
{
	struct pcie_device *pcie_device;
	struct pcie_port_service_driver *driver;
	struct aer_broadcast_data *result_data;
	pci_ers_result_t status;

	result_data = (struct aer_broadcast_data *) data;

	if (device->bus == &pcie_port_bus_type && device->driver) {
		driver = to_service_driver(device->driver);
		if (!driver ||
			!driver->err_handler ||
			!driver->err_handler->error_detected)
			return 0;

		pcie_device = to_pcie_device(device);

		/* Forward error detected message to service drivers */
		status = driver->err_handler->error_detected(
			pcie_device->port,
			result_data->state);
		result_data->result =
			merge_result(result_data->result, status);
	}

	return 0;
}

static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
					enum pci_channel_state error)
{
	struct aer_broadcast_data data = {error, PCI_ERS_RESULT_CAN_RECOVER};
	int ret;

	/* can not fail */
	ret = device_for_each_child(&dev->dev, &data, error_detected_iter);

	return data.result;
}

static int mmio_enabled_iter(struct device *device, void *data)
{
	struct pcie_device *pcie_device;
	struct pcie_port_service_driver *driver;
	pci_ers_result_t status, *result;

	result = (pci_ers_result_t *) data;

	if (device->bus == &pcie_port_bus_type && device->driver) {
		driver = to_service_driver(device->driver);
		if (driver &&
			driver->err_handler &&
			driver->err_handler->mmio_enabled) {
			pcie_device = to_pcie_device(device);

			/* Forward error message to service drivers */
			status = driver->err_handler->mmio_enabled(
					pcie_device->port);
			*result = merge_result(*result, status);
		}
	}

	return 0;
}

static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
{
	pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
	int retval;

	/* get true return value from &status */
	retval = device_for_each_child(&dev->dev, &status, mmio_enabled_iter);
	return status;
}

static int slot_reset_iter(struct device *device, void *data)
{
	struct pcie_device *pcie_device;
	struct pcie_port_service_driver *driver;
	pci_ers_result_t status, *result;

	result = (pci_ers_result_t *) data;

	if (device->bus == &pcie_port_bus_type && device->driver) {
		driver = to_service_driver(device->driver);
		if (driver &&
			driver->err_handler &&
			driver->err_handler->slot_reset) {
			pcie_device = to_pcie_device(device);

			/* Forward error message to service drivers */
			status = driver->err_handler->slot_reset(
					pcie_device->port);
			*result = merge_result(*result, status);
		}
	}

	return 0;
}

static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
{
	pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
	int retval;

	/* If fatal, restore cfg space for possible link reset at upstream */
	if (dev->error_state == pci_channel_io_frozen) {
		dev->state_saved = true;
		pci_restore_state(dev);
		pcie_portdrv_restore_config(dev);
		pci_enable_pcie_error_reporting(dev);
	}

	/* get true return value from &status */
	retval = device_for_each_child(&dev->dev, &status, slot_reset_iter);

	return status;
}

static int resume_iter(struct device *device, void *data)
{
	struct pcie_device *pcie_device;
	struct pcie_port_service_driver *driver;

	if (device->bus == &pcie_port_bus_type && device->driver) {
		driver = to_service_driver(device->driver);
		if (driver &&
			driver->err_handler &&
			driver->err_handler->resume) {
			pcie_device = to_pcie_device(device);

			/* Forward error message to service drivers */
			driver->err_handler->resume(pcie_device->port);
		}
	}

	return 0;
}

static void pcie_portdrv_err_resume(struct pci_dev *dev)
{
	int retval;
	/* nothing to do with error value, if it ever happens */
	retval = device_for_each_child(&dev->dev, NULL, resume_iter);
}

/*
 * LINUX Device Driver Model
 */
static const struct pci_device_id port_pci_ids[] = { {
	/* handle any PCI-Express port */
	PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0),
	}, { /* end: all zeroes */ }
};
MODULE_DEVICE_TABLE(pci, port_pci_ids);

static struct pci_error_handlers pcie_portdrv_err_handler = {
		.error_detected = pcie_portdrv_error_detected,
		.mmio_enabled = pcie_portdrv_mmio_enabled,
		.slot_reset = pcie_portdrv_slot_reset,
		.resume = pcie_portdrv_err_resume,
};

static struct pci_driver pcie_portdriver = {
	.name		= "pcieport",
	.id_table	= &port_pci_ids[0],

	.probe		= pcie_portdrv_probe,
	.remove		= pcie_portdrv_remove,

	.err_handler 	= &pcie_portdrv_err_handler,

	.driver.pm 	= PCIE_PORTDRV_PM_OPS,
};

static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
{
	pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
			d->ident);
	pcie_pme_disable_msi();
	return 0;
}

static struct dmi_system_id __initdata pcie_portdrv_dmi_table[] = {
	/*
	 * Boxes that should not use MSI for PCIe PME signaling.
	 */
	{
	 .callback = dmi_pcie_pme_disable_msi,
	 .ident = "MSI Wind U-100",
	 .matches = {
		     DMI_MATCH(DMI_SYS_VENDOR,
		     		"MICRO-STAR INTERNATIONAL CO., LTD"),
		     DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
		     },
	 },
	 {}
};

static int __init pcie_portdrv_init(void)
{
	int retval;

	if (pcie_ports_disabled)
		return pci_register_driver(&pcie_portdriver);

	dmi_check_system(pcie_portdrv_dmi_table);

	retval = pcie_port_bus_register();
	if (retval) {
		printk(KERN_WARNING "PCIE: bus_register error: %d\n", retval);
		goto out;
	}
	retval = pci_register_driver(&pcie_portdriver);
	if (retval)
		pcie_port_bus_unregister();
 out:
	return retval;
}

module_init(pcie_portdrv_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* File: portdrv_pci.c
	3	* Purpose: PCI Express Port Bus Driver
	4	*
	5	* Copyright (C) 2004 Intel
	6	* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/pci.h>
	11	#include <linux/kernel.h>
	12	#include <linux/errno.h>
	13	#include <linux/pm.h>
71a83bd7	14	#include <linux/pm_runtime.h>
1da177e4 LT	15	#include <linux/init.h>
1da177e4 LT	16	#include <linux/pcieport_if.h>
4bf3392e	17	#include <linux/aer.h>
c39fae14	18	#include <linux/dmi.h>
28eb5f27	19	#include <linux/pci-aspm.h>
1da177e4 LT	20
1da177e4 LT	21	#include "portdrv.h"
4bf3392e	22	#include "aer/aerdrv.h"
1da177e4 LT	23
	24	/*
	25	* Version Information
	26	*/
	27	#define DRIVER_VERSION "v1.0"
	28	#define DRIVER_AUTHOR "tom.l.nguyen@intel.com"
7e8af37a	29	#define DRIVER_DESC "PCIe Port Bus Driver"
1da177e4 LT	30	MODULE_AUTHOR(DRIVER_AUTHOR);
	31	MODULE_DESCRIPTION(DRIVER_DESC);
	32	MODULE_LICENSE("GPL");
	33
79dd9182 RW	34	/* If this switch is set, PCIe port native services should not be enabled. */
	35	bool pcie_ports_disabled;
	36
28eb5f27 RW	37	/*
	38	* If this switch is set, ACPI _OSC will be used to determine whether or not to
	39	* enable PCIe port native services.
	40	*/
	41	bool pcie_ports_auto = true;
	42
79dd9182 RW	43	static int __init pcie_port_setup(char *str)
79dd9182 RW	44	{
28eb5f27	45	if (!strncmp(str, "compat", 6)) {
79dd9182	46	pcie_ports_disabled = true;
28eb5f27 RW	47	} else if (!strncmp(str, "native", 6)) {
	48	pcie_ports_disabled = false;
	49	pcie_ports_auto = false;
	50	} else if (!strncmp(str, "auto", 4)) {
	51	pcie_ports_disabled = false;
	52	pcie_ports_auto = true;
	53	}
79dd9182 RW	54
	55	return 1;
	56	}
	57	__setup("pcie_ports=", pcie_port_setup);
	58
1da177e4	59	/* global data */
1da177e4	60
fe31e697 RW	61	/**
	62	* pcie_clear_root_pme_status - Clear root port PME interrupt status.
	63	* @dev: PCIe root port or event collector.
	64	*/
	65	void pcie_clear_root_pme_status(struct pci_dev *dev)
	66	{
	67	int rtsta_pos;
	68	u32 rtsta;
	69
	70	rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
	71
	72	pci_read_config_dword(dev, rtsta_pos, &rtsta);
	73	rtsta \|= PCI_EXP_RTSTA_PME;
	74	pci_write_config_dword(dev, rtsta_pos, rtsta);
	75	}
	76
4bf3392e ZY	77	static int pcie_portdrv_restore_config(struct pci_dev *dev)
	78	{
	79	int retval;
	80
4bf3392e ZY	81	retval = pci_enable_device(dev);
	82	if (retval)
	83	return retval;
	84	pci_set_master(dev);
	85	return 0;
	86	}
	87
0bed208e	88	#ifdef CONFIG_PM
fe31e697 RW	89	static int pcie_port_resume_noirq(struct device *dev)
	90	{
	91	struct pci_dev *pdev = to_pci_dev(dev);
	92
	93	/*
	94	* Some BIOSes forget to clear Root PME Status bits after system wakeup
	95	* which breaks ACPI-based runtime wakeup on PCI Express, so clear those
	96	* bits now just in case (shouldn't hurt).
	97	*/
	98	if(pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT)
	99	pcie_clear_root_pme_status(pdev);
	100	return 0;
	101	}
	102
71a83bd7	103	#ifdef CONFIG_PM_RUNTIME
448bd857 HY	104	struct d3cold_info {
	105	bool no_d3cold;
	106	unsigned int d3cold_delay;
	107	};
	108
	109	static int pci_dev_d3cold_info(struct pci_dev pdev, void data)
	110	{
	111	struct d3cold_info *info = data;
	112
	113	info->d3cold_delay = max_t(unsigned int, pdev->d3cold_delay,
	114	info->d3cold_delay);
	115	if (pdev->no_d3cold)
	116	info->no_d3cold = true;
	117	return 0;
	118	}
	119
	120	static int pcie_port_runtime_suspend(struct device *dev)
	121	{
	122	struct pci_dev *pdev = to_pci_dev(dev);
	123	struct d3cold_info d3cold_info = {
	124	.no_d3cold = false,
	125	.d3cold_delay = PCI_PM_D3_WAIT,
	126	};
	127
	128	/*
	129	* If any subordinate device disable D3cold, we should not put
	130	* the port into D3cold. The D3cold delay of port should be
	131	* the max of that of all subordinate devices.
	132	*/
	133	pci_walk_bus(pdev->subordinate, pci_dev_d3cold_info, &d3cold_info);
	134	pdev->no_d3cold = d3cold_info.no_d3cold;
	135	pdev->d3cold_delay = d3cold_info.d3cold_delay;
	136	return 0;
	137	}
	138
	139	static int pcie_port_runtime_resume(struct device *dev)
71a83bd7 ZY	140	{
	141	return 0;
	142	}
3d8387ef HY	143
	144	static int pcie_port_runtime_idle(struct device *dev)
	145	{
	146	/* Delay for a short while to prevent too frequent suspend/resume */
	147	pm_schedule_suspend(dev, 10);
	148	return -EBUSY;
	149	}
71a83bd7	150	#else
448bd857 HY	151	#define pcie_port_runtime_suspend NULL
448bd857 HY	152	#define pcie_port_runtime_resume NULL
3d8387ef	153	#define pcie_port_runtime_idle NULL
71a83bd7 ZY	154	#endif
71a83bd7 ZY	155
47145210	156	static const struct dev_pm_ops pcie_portdrv_pm_ops = {
3a3c244c RW	157	.suspend = pcie_port_device_suspend,
	158	.resume = pcie_port_device_resume,
	159	.freeze = pcie_port_device_suspend,
	160	.thaw = pcie_port_device_resume,
	161	.poweroff = pcie_port_device_suspend,
	162	.restore = pcie_port_device_resume,
fe31e697	163	.resume_noirq = pcie_port_resume_noirq,
448bd857 HY	164	.runtime_suspend = pcie_port_runtime_suspend,
448bd857 HY	165	.runtime_resume = pcie_port_runtime_resume,
3d8387ef	166	.runtime_idle = pcie_port_runtime_idle,
3a3c244c	167	};
4bf3392e	168
3a3c244c	169	#define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops)
a79d682f	170
3a3c244c RW	171	#else /* !PM */
	172
	173	#define PCIE_PORTDRV_PM_OPS NULL
	174	#endif /* !PM */
4bf3392e	175
71a83bd7 ZY	176	/*
	177	* PCIe port runtime suspend is broken for some chipsets, so use a
	178	* black list to disable runtime PM for these chipsets.
	179	*/
	180	static const struct pci_device_id port_runtime_pm_black_list[] = {
	181	{ /* end: all zeroes */ }
	182	};
	183
1da177e4 LT	184	/*
	185	* pcie_portdrv_probe - Probe PCI-Express port devices
	186	* @dev: PCI-Express port device being probed
	187	*
40da4186	188	* If detected invokes the pcie_port_device_register() method for
1da177e4 LT	189	* this port device.
	190	*
	191	*/
898294c9 KK	192	static int __devinit pcie_portdrv_probe(struct pci_dev *dev,
898294c9 KK	193	const struct pci_device_id *id)
1da177e4	194	{
898294c9	195	int status;
1da177e4	196
898294c9 KK	197	if (!pci_is_pcie(dev) \|\|
	198	((dev->pcie_type != PCI_EXP_TYPE_ROOT_PORT) &&
	199	(dev->pcie_type != PCI_EXP_TYPE_UPSTREAM) &&
	200	(dev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)))
	201	return -ENODEV;
1da177e4	202
40da4186	203	if (!dev->irq && dev->pin) {
34a2e15e	204	dev_warn(&dev->dev, "device [%04x:%04x] has invalid IRQ; "
34438ba6	205	"check vendor BIOS\n", dev->vendor, dev->device);
1da177e4	206	}
f118c0c3 RW	207	status = pcie_port_device_register(dev);
	208	if (status)
	209	return status;
1da177e4	210
87d2e2ec	211	pci_save_state(dev);
4f9c1397 HY	212	/*
	213	* D3cold may not work properly on some PCIe port, so disable
	214	* it by default.
	215	*/
	216	dev->d3cold_allowed = false;
71a83bd7 ZY	217	if (!pci_match_id(port_runtime_pm_black_list, dev))
71a83bd7 ZY	218	pm_runtime_put_noidle(&dev->dev);
4bf3392e	219
1da177e4 LT	220	return 0;
	221	}
	222
40da4186	223	static void pcie_portdrv_remove(struct pci_dev *dev)
1da177e4	224	{
71a83bd7 ZY	225	if (!pci_match_id(port_runtime_pm_black_list, dev))
71a83bd7 ZY	226	pm_runtime_get_noresume(&dev->dev);
1da177e4	227	pcie_port_device_remove(dev);
d8998719	228	pci_disable_device(dev);
1da177e4 LT	229	}
1da177e4 LT	230
4bf3392e	231	static int error_detected_iter(struct device device, void data)
60854838	232	{
4bf3392e ZY	233	struct pcie_device *pcie_device;
	234	struct pcie_port_service_driver *driver;
	235	struct aer_broadcast_data *result_data;
	236	pci_ers_result_t status;
	237
	238	result_data = (struct aer_broadcast_data *) data;
	239
	240	if (device->bus == &pcie_port_bus_type && device->driver) {
	241	driver = to_service_driver(device->driver);
	242	if (!driver \|\|
	243	!driver->err_handler \|\|
	244	!driver->err_handler->error_detected)
	245	return 0;
	246
	247	pcie_device = to_pcie_device(device);
	248
	249	/* Forward error detected message to service drivers */
	250	status = driver->err_handler->error_detected(
	251	pcie_device->port,
	252	result_data->state);
	253	result_data->result =
	254	merge_result(result_data->result, status);
	255	}
	256
	257	return 0;
60854838 HK	258	}
60854838 HK	259
4bf3392e ZY	260	static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
4bf3392e ZY	261	enum pci_channel_state error)
60854838	262	{
40da4186 HS	263	struct aer_broadcast_data data = {error, PCI_ERS_RESULT_CAN_RECOVER};
40da4186 HS	264	int ret;
4bf3392e	265
b19441af	266	/* can not fail */
40da4186	267	ret = device_for_each_child(&dev->dev, &data, error_detected_iter);
4bf3392e	268
40da4186	269	return data.result;
4bf3392e ZY	270	}
	271
	272	static int mmio_enabled_iter(struct device device, void data)
	273	{
	274	struct pcie_device *pcie_device;
	275	struct pcie_port_service_driver *driver;
	276	pci_ers_result_t status, *result;
	277
	278	result = (pci_ers_result_t *) data;
	279
	280	if (device->bus == &pcie_port_bus_type && device->driver) {
	281	driver = to_service_driver(device->driver);
	282	if (driver &&
	283	driver->err_handler &&
	284	driver->err_handler->mmio_enabled) {
	285	pcie_device = to_pcie_device(device);
	286
	287	/* Forward error message to service drivers */
	288	status = driver->err_handler->mmio_enabled(
	289	pcie_device->port);
	290	result = merge_result(result, status);
	291	}
	292	}
60854838	293
60854838 HK	294	return 0;
	295	}
	296
4bf3392e	297	static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
1da177e4	298	{
4bf3392e	299	pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
b19441af	300	int retval;
5823d100	301
b19441af GKH	302	/* get true return value from &status */
b19441af GKH	303	retval = device_for_each_child(&dev->dev, &status, mmio_enabled_iter);
4bf3392e	304	return status;
1da177e4 LT	305	}
1da177e4 LT	306
4bf3392e	307	static int slot_reset_iter(struct device device, void data)
1da177e4	308	{
4bf3392e ZY	309	struct pcie_device *pcie_device;
	310	struct pcie_port_service_driver *driver;
	311	pci_ers_result_t status, *result;
	312
	313	result = (pci_ers_result_t *) data;
	314
	315	if (device->bus == &pcie_port_bus_type && device->driver) {
	316	driver = to_service_driver(device->driver);
	317	if (driver &&
	318	driver->err_handler &&
	319	driver->err_handler->slot_reset) {
	320	pcie_device = to_pcie_device(device);
	321
	322	/* Forward error message to service drivers */
	323	status = driver->err_handler->slot_reset(
	324	pcie_device->port);
	325	result = merge_result(result, status);
	326	}
	327	}
	328
	329	return 0;
	330	}
	331
	332	static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
	333	{
029091df	334	pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED;
b19441af	335	int retval;
4bf3392e ZY	336
	337	/* If fatal, restore cfg space for possible link reset at upstream */
	338	if (dev->error_state == pci_channel_io_frozen) {
e9d82888	339	dev->state_saved = true;
a79d682f	340	pci_restore_state(dev);
4bf3392e ZY	341	pcie_portdrv_restore_config(dev);
	342	pci_enable_pcie_error_reporting(dev);
	343	}
	344
b19441af GKH	345	/* get true return value from &status */
b19441af GKH	346	retval = device_for_each_child(&dev->dev, &status, slot_reset_iter);
4bf3392e ZY	347
	348	return status;
	349	}
	350
	351	static int resume_iter(struct device device, void data)
	352	{
	353	struct pcie_device *pcie_device;
	354	struct pcie_port_service_driver *driver;
	355
	356	if (device->bus == &pcie_port_bus_type && device->driver) {
	357	driver = to_service_driver(device->driver);
	358	if (driver &&
	359	driver->err_handler &&
	360	driver->err_handler->resume) {
	361	pcie_device = to_pcie_device(device);
	362
	363	/* Forward error message to service drivers */
	364	driver->err_handler->resume(pcie_device->port);
	365	}
	366	}
	367
	368	return 0;
	369	}
	370
	371	static void pcie_portdrv_err_resume(struct pci_dev *dev)
	372	{
b19441af GKH	373	int retval;
	374	/* nothing to do with error value, if it ever happens */
	375	retval = device_for_each_child(&dev->dev, NULL, resume_iter);
1da177e4	376	}
1da177e4 LT	377
	378	/*
	379	* LINUX Device Driver Model
	380	*/
	381	static const struct pci_device_id port_pci_ids[] = { {
	382	/* handle any PCI-Express port */
	383	PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) \| 0x00), ~0),
	384	}, { /* end: all zeroes */ }
	385	};
	386	MODULE_DEVICE_TABLE(pci, port_pci_ids);
	387
4bf3392e ZY	388	static struct pci_error_handlers pcie_portdrv_err_handler = {
	389	.error_detected = pcie_portdrv_error_detected,
	390	.mmio_enabled = pcie_portdrv_mmio_enabled,
	391	.slot_reset = pcie_portdrv_slot_reset,
	392	.resume = pcie_portdrv_err_resume,
	393	};
	394
3603a6a3	395	static struct pci_driver pcie_portdriver = {
e3fb20f9	396	.name = "pcieport",
1da177e4 LT	397	.id_table = &port_pci_ids[0],
	398
	399	.probe = pcie_portdrv_probe,
	400	.remove = pcie_portdrv_remove,
	401
4bf3392e	402	.err_handler = &pcie_portdrv_err_handler,
3a3c244c RW	403
3a3c244c RW	404	.driver.pm = PCIE_PORTDRV_PM_OPS,
1da177e4 LT	405	};
1da177e4 LT	406
c39fae14 RW	407	static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
	408	{
	409	pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
	410	d->ident);
	411	pcie_pme_disable_msi();
	412	return 0;
	413	}
	414
	415	static struct dmi_system_id __initdata pcie_portdrv_dmi_table[] = {
	416	/*
	417	* Boxes that should not use MSI for PCIe PME signaling.
	418	*/
	419	{
	420	.callback = dmi_pcie_pme_disable_msi,
	421	.ident = "MSI Wind U-100",
	422	.matches = {
	423	DMI_MATCH(DMI_SYS_VENDOR,
	424	"MICRO-STAR INTERNATIONAL CO., LTD"),
	425	DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
	426	},
	427	},
	428	{}
	429	};
	430
1da177e4 LT	431	static int __init pcie_portdrv_init(void)
1da177e4 LT	432	{
20d51660	433	int retval;
1da177e4	434
fe31e697 RW	435	if (pcie_ports_disabled)
fe31e697 RW	436	return pci_register_driver(&pcie_portdriver);
79dd9182	437
c39fae14 RW	438	dmi_check_system(pcie_portdrv_dmi_table);
c39fae14 RW	439
20d51660 RD	440	retval = pcie_port_bus_register();
	441	if (retval) {
	442	printk(KERN_WARNING "PCIE: bus_register error: %d\n", retval);
	443	goto out;
	444	}
3603a6a3	445	retval = pci_register_driver(&pcie_portdriver);
1da177e4 LT	446	if (retval)
1da177e4 LT	447	pcie_port_bus_unregister();
20d51660	448	out:
1da177e4 LT	449	return retval;
	450	}
	451
1da177e4	452	module_init(pcie_portdrv_init);