Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * File: portdrv_pci.c | |
3 | * Purpose: PCI Express Port Bus Driver | |
a7dadf45 PG |
4 | * Author: Tom Nguyen <tom.l.nguyen@intel.com> |
5 | * Version: v1.0 | |
1da177e4 LT |
6 | * |
7 | * Copyright (C) 2004 Intel | |
8 | * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com) | |
9 | */ | |
10 | ||
1da177e4 LT |
11 | #include <linux/pci.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/pm.h> | |
71a83bd7 | 15 | #include <linux/pm_runtime.h> |
1da177e4 LT |
16 | #include <linux/init.h> |
17 | #include <linux/pcieport_if.h> | |
4bf3392e | 18 | #include <linux/aer.h> |
c39fae14 | 19 | #include <linux/dmi.h> |
28eb5f27 | 20 | #include <linux/pci-aspm.h> |
1da177e4 LT |
21 | |
22 | #include "portdrv.h" | |
4bf3392e | 23 | #include "aer/aerdrv.h" |
1da177e4 | 24 | |
79dd9182 RW |
25 | /* If this switch is set, PCIe port native services should not be enabled. */ |
26 | bool pcie_ports_disabled; | |
27 | ||
28eb5f27 RW |
28 | /* |
29 | * If this switch is set, ACPI _OSC will be used to determine whether or not to | |
30 | * enable PCIe port native services. | |
31 | */ | |
32 | bool pcie_ports_auto = true; | |
33 | ||
79dd9182 RW |
34 | static int __init pcie_port_setup(char *str) |
35 | { | |
28eb5f27 | 36 | if (!strncmp(str, "compat", 6)) { |
79dd9182 | 37 | pcie_ports_disabled = true; |
28eb5f27 RW |
38 | } else if (!strncmp(str, "native", 6)) { |
39 | pcie_ports_disabled = false; | |
40 | pcie_ports_auto = false; | |
41 | } else if (!strncmp(str, "auto", 4)) { | |
42 | pcie_ports_disabled = false; | |
43 | pcie_ports_auto = true; | |
44 | } | |
79dd9182 RW |
45 | |
46 | return 1; | |
47 | } | |
48 | __setup("pcie_ports=", pcie_port_setup); | |
49 | ||
1da177e4 | 50 | /* global data */ |
1da177e4 | 51 | |
fe31e697 RW |
52 | /** |
53 | * pcie_clear_root_pme_status - Clear root port PME interrupt status. | |
54 | * @dev: PCIe root port or event collector. | |
55 | */ | |
56 | void pcie_clear_root_pme_status(struct pci_dev *dev) | |
57 | { | |
2dcfaf85 | 58 | pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME); |
fe31e697 RW |
59 | } |
60 | ||
4bf3392e ZY |
61 | static int pcie_portdrv_restore_config(struct pci_dev *dev) |
62 | { | |
63 | int retval; | |
64 | ||
4bf3392e ZY |
65 | retval = pci_enable_device(dev); |
66 | if (retval) | |
67 | return retval; | |
68 | pci_set_master(dev); | |
69 | return 0; | |
70 | } | |
71 | ||
0bed208e | 72 | #ifdef CONFIG_PM |
fe31e697 RW |
73 | static int pcie_port_resume_noirq(struct device *dev) |
74 | { | |
75 | struct pci_dev *pdev = to_pci_dev(dev); | |
76 | ||
77 | /* | |
78 | * Some BIOSes forget to clear Root PME Status bits after system wakeup | |
79 | * which breaks ACPI-based runtime wakeup on PCI Express, so clear those | |
80 | * bits now just in case (shouldn't hurt). | |
81 | */ | |
62f87c0e | 82 | if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) |
fe31e697 RW |
83 | pcie_clear_root_pme_status(pdev); |
84 | return 0; | |
85 | } | |
86 | ||
006d44e4 MW |
87 | static int pcie_port_runtime_suspend(struct device *dev) |
88 | { | |
89 | return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY; | |
90 | } | |
91 | ||
92 | static int pcie_port_runtime_resume(struct device *dev) | |
93 | { | |
94 | return 0; | |
95 | } | |
96 | ||
97 | static int pcie_port_runtime_idle(struct device *dev) | |
98 | { | |
99 | /* | |
100 | * Assume the PCI core has set bridge_d3 whenever it thinks the port | |
101 | * should be good to go to D3. Everything else, including moving | |
102 | * the port to D3, is handled by the PCI core. | |
103 | */ | |
104 | return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY; | |
105 | } | |
106 | ||
47145210 | 107 | static const struct dev_pm_ops pcie_portdrv_pm_ops = { |
3a3c244c RW |
108 | .suspend = pcie_port_device_suspend, |
109 | .resume = pcie_port_device_resume, | |
110 | .freeze = pcie_port_device_suspend, | |
111 | .thaw = pcie_port_device_resume, | |
112 | .poweroff = pcie_port_device_suspend, | |
113 | .restore = pcie_port_device_resume, | |
fe31e697 | 114 | .resume_noirq = pcie_port_resume_noirq, |
006d44e4 MW |
115 | .runtime_suspend = pcie_port_runtime_suspend, |
116 | .runtime_resume = pcie_port_runtime_resume, | |
117 | .runtime_idle = pcie_port_runtime_idle, | |
3a3c244c | 118 | }; |
4bf3392e | 119 | |
3a3c244c | 120 | #define PCIE_PORTDRV_PM_OPS (&pcie_portdrv_pm_ops) |
a79d682f | 121 | |
3a3c244c RW |
122 | #else /* !PM */ |
123 | ||
124 | #define PCIE_PORTDRV_PM_OPS NULL | |
125 | #endif /* !PM */ | |
4bf3392e | 126 | |
1da177e4 LT |
127 | /* |
128 | * pcie_portdrv_probe - Probe PCI-Express port devices | |
129 | * @dev: PCI-Express port device being probed | |
130 | * | |
40da4186 | 131 | * If detected invokes the pcie_port_device_register() method for |
1da177e4 LT |
132 | * this port device. |
133 | * | |
134 | */ | |
15856ad5 | 135 | static int pcie_portdrv_probe(struct pci_dev *dev, |
898294c9 | 136 | const struct pci_device_id *id) |
1da177e4 | 137 | { |
898294c9 | 138 | int status; |
1da177e4 | 139 | |
898294c9 | 140 | if (!pci_is_pcie(dev) || |
62f87c0e YW |
141 | ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && |
142 | (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) && | |
143 | (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) | |
898294c9 | 144 | return -ENODEV; |
1da177e4 | 145 | |
f118c0c3 RW |
146 | status = pcie_port_device_register(dev); |
147 | if (status) | |
148 | return status; | |
1da177e4 | 149 | |
87d2e2ec | 150 | pci_save_state(dev); |
006d44e4 MW |
151 | |
152 | /* | |
153 | * Prevent runtime PM if the port is advertising support for PCIe | |
154 | * hotplug. Otherwise the BIOS hotplug SMI code might not be able | |
155 | * to enumerate devices behind this port properly (the port is | |
156 | * powered down preventing all config space accesses to the | |
157 | * subordinate devices). We can't be sure for native PCIe hotplug | |
158 | * either so prevent that as well. | |
159 | */ | |
160 | if (!dev->is_hotplug_bridge) { | |
161 | /* | |
162 | * Keep the port resumed 100ms to make sure things like | |
163 | * config space accesses from userspace (lspci) will not | |
164 | * cause the port to repeatedly suspend and resume. | |
165 | */ | |
166 | pm_runtime_set_autosuspend_delay(&dev->dev, 100); | |
167 | pm_runtime_use_autosuspend(&dev->dev); | |
168 | pm_runtime_mark_last_busy(&dev->dev); | |
169 | pm_runtime_put_autosuspend(&dev->dev); | |
170 | pm_runtime_allow(&dev->dev); | |
171 | } | |
172 | ||
1da177e4 LT |
173 | return 0; |
174 | } | |
175 | ||
40da4186 | 176 | static void pcie_portdrv_remove(struct pci_dev *dev) |
1da177e4 | 177 | { |
006d44e4 MW |
178 | if (!dev->is_hotplug_bridge) { |
179 | pm_runtime_forbid(&dev->dev); | |
180 | pm_runtime_get_noresume(&dev->dev); | |
181 | pm_runtime_dont_use_autosuspend(&dev->dev); | |
182 | } | |
183 | ||
1da177e4 LT |
184 | pcie_port_device_remove(dev); |
185 | } | |
186 | ||
4bf3392e | 187 | static int error_detected_iter(struct device *device, void *data) |
60854838 | 188 | { |
4bf3392e ZY |
189 | struct pcie_device *pcie_device; |
190 | struct pcie_port_service_driver *driver; | |
191 | struct aer_broadcast_data *result_data; | |
192 | pci_ers_result_t status; | |
193 | ||
194 | result_data = (struct aer_broadcast_data *) data; | |
195 | ||
196 | if (device->bus == &pcie_port_bus_type && device->driver) { | |
197 | driver = to_service_driver(device->driver); | |
198 | if (!driver || | |
199 | !driver->err_handler || | |
200 | !driver->err_handler->error_detected) | |
201 | return 0; | |
202 | ||
203 | pcie_device = to_pcie_device(device); | |
204 | ||
205 | /* Forward error detected message to service drivers */ | |
206 | status = driver->err_handler->error_detected( | |
207 | pcie_device->port, | |
208 | result_data->state); | |
209 | result_data->result = | |
210 | merge_result(result_data->result, status); | |
211 | } | |
212 | ||
213 | return 0; | |
60854838 HK |
214 | } |
215 | ||
4bf3392e ZY |
216 | static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev, |
217 | enum pci_channel_state error) | |
60854838 | 218 | { |
40da4186 | 219 | struct aer_broadcast_data data = {error, PCI_ERS_RESULT_CAN_RECOVER}; |
4bf3392e | 220 | |
b638d7e7 BH |
221 | /* get true return value from &data */ |
222 | device_for_each_child(&dev->dev, &data, error_detected_iter); | |
40da4186 | 223 | return data.result; |
4bf3392e ZY |
224 | } |
225 | ||
226 | static int mmio_enabled_iter(struct device *device, void *data) | |
227 | { | |
228 | struct pcie_device *pcie_device; | |
229 | struct pcie_port_service_driver *driver; | |
230 | pci_ers_result_t status, *result; | |
231 | ||
232 | result = (pci_ers_result_t *) data; | |
233 | ||
234 | if (device->bus == &pcie_port_bus_type && device->driver) { | |
235 | driver = to_service_driver(device->driver); | |
236 | if (driver && | |
237 | driver->err_handler && | |
238 | driver->err_handler->mmio_enabled) { | |
239 | pcie_device = to_pcie_device(device); | |
240 | ||
241 | /* Forward error message to service drivers */ | |
242 | status = driver->err_handler->mmio_enabled( | |
243 | pcie_device->port); | |
244 | *result = merge_result(*result, status); | |
245 | } | |
246 | } | |
60854838 | 247 | |
60854838 HK |
248 | return 0; |
249 | } | |
250 | ||
4bf3392e | 251 | static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev) |
1da177e4 | 252 | { |
4bf3392e | 253 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; |
5823d100 | 254 | |
b19441af | 255 | /* get true return value from &status */ |
b638d7e7 | 256 | device_for_each_child(&dev->dev, &status, mmio_enabled_iter); |
4bf3392e | 257 | return status; |
1da177e4 LT |
258 | } |
259 | ||
4bf3392e | 260 | static int slot_reset_iter(struct device *device, void *data) |
1da177e4 | 261 | { |
4bf3392e ZY |
262 | struct pcie_device *pcie_device; |
263 | struct pcie_port_service_driver *driver; | |
264 | pci_ers_result_t status, *result; | |
265 | ||
266 | result = (pci_ers_result_t *) data; | |
267 | ||
268 | if (device->bus == &pcie_port_bus_type && device->driver) { | |
269 | driver = to_service_driver(device->driver); | |
270 | if (driver && | |
271 | driver->err_handler && | |
272 | driver->err_handler->slot_reset) { | |
273 | pcie_device = to_pcie_device(device); | |
274 | ||
275 | /* Forward error message to service drivers */ | |
276 | status = driver->err_handler->slot_reset( | |
277 | pcie_device->port); | |
278 | *result = merge_result(*result, status); | |
279 | } | |
280 | } | |
281 | ||
282 | return 0; | |
283 | } | |
284 | ||
285 | static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev) | |
286 | { | |
029091df | 287 | pci_ers_result_t status = PCI_ERS_RESULT_RECOVERED; |
4bf3392e ZY |
288 | |
289 | /* If fatal, restore cfg space for possible link reset at upstream */ | |
290 | if (dev->error_state == pci_channel_io_frozen) { | |
e9d82888 | 291 | dev->state_saved = true; |
a79d682f | 292 | pci_restore_state(dev); |
4bf3392e ZY |
293 | pcie_portdrv_restore_config(dev); |
294 | pci_enable_pcie_error_reporting(dev); | |
295 | } | |
296 | ||
b19441af | 297 | /* get true return value from &status */ |
b638d7e7 | 298 | device_for_each_child(&dev->dev, &status, slot_reset_iter); |
4bf3392e ZY |
299 | return status; |
300 | } | |
301 | ||
302 | static int resume_iter(struct device *device, void *data) | |
303 | { | |
304 | struct pcie_device *pcie_device; | |
305 | struct pcie_port_service_driver *driver; | |
306 | ||
307 | if (device->bus == &pcie_port_bus_type && device->driver) { | |
308 | driver = to_service_driver(device->driver); | |
309 | if (driver && | |
310 | driver->err_handler && | |
311 | driver->err_handler->resume) { | |
312 | pcie_device = to_pcie_device(device); | |
313 | ||
314 | /* Forward error message to service drivers */ | |
315 | driver->err_handler->resume(pcie_device->port); | |
316 | } | |
317 | } | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
322 | static void pcie_portdrv_err_resume(struct pci_dev *dev) | |
323 | { | |
b638d7e7 | 324 | device_for_each_child(&dev->dev, NULL, resume_iter); |
1da177e4 | 325 | } |
1da177e4 LT |
326 | |
327 | /* | |
328 | * LINUX Device Driver Model | |
329 | */ | |
330 | static const struct pci_device_id port_pci_ids[] = { { | |
331 | /* handle any PCI-Express port */ | |
332 | PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0), | |
333 | }, { /* end: all zeroes */ } | |
334 | }; | |
1da177e4 | 335 | |
49453028 SH |
336 | static const struct pci_error_handlers pcie_portdrv_err_handler = { |
337 | .error_detected = pcie_portdrv_error_detected, | |
338 | .mmio_enabled = pcie_portdrv_mmio_enabled, | |
339 | .slot_reset = pcie_portdrv_slot_reset, | |
340 | .resume = pcie_portdrv_err_resume, | |
4bf3392e ZY |
341 | }; |
342 | ||
3603a6a3 | 343 | static struct pci_driver pcie_portdriver = { |
e3fb20f9 | 344 | .name = "pcieport", |
1da177e4 LT |
345 | .id_table = &port_pci_ids[0], |
346 | ||
347 | .probe = pcie_portdrv_probe, | |
348 | .remove = pcie_portdrv_remove, | |
349 | ||
f7625980 | 350 | .err_handler = &pcie_portdrv_err_handler, |
3a3c244c | 351 | |
f7625980 | 352 | .driver.pm = PCIE_PORTDRV_PM_OPS, |
1da177e4 LT |
353 | }; |
354 | ||
c39fae14 RW |
355 | static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d) |
356 | { | |
357 | pr_notice("%s detected: will not use MSI for PCIe PME signaling\n", | |
227f0647 | 358 | d->ident); |
c39fae14 RW |
359 | pcie_pme_disable_msi(); |
360 | return 0; | |
361 | } | |
362 | ||
363 | static struct dmi_system_id __initdata pcie_portdrv_dmi_table[] = { | |
364 | /* | |
365 | * Boxes that should not use MSI for PCIe PME signaling. | |
366 | */ | |
367 | { | |
368 | .callback = dmi_pcie_pme_disable_msi, | |
369 | .ident = "MSI Wind U-100", | |
370 | .matches = { | |
371 | DMI_MATCH(DMI_SYS_VENDOR, | |
f7625980 | 372 | "MICRO-STAR INTERNATIONAL CO., LTD"), |
c39fae14 RW |
373 | DMI_MATCH(DMI_PRODUCT_NAME, "U-100"), |
374 | }, | |
375 | }, | |
376 | {} | |
377 | }; | |
378 | ||
1da177e4 LT |
379 | static int __init pcie_portdrv_init(void) |
380 | { | |
20d51660 | 381 | int retval; |
1da177e4 | 382 | |
fe31e697 RW |
383 | if (pcie_ports_disabled) |
384 | return pci_register_driver(&pcie_portdriver); | |
79dd9182 | 385 | |
c39fae14 RW |
386 | dmi_check_system(pcie_portdrv_dmi_table); |
387 | ||
20d51660 RD |
388 | retval = pcie_port_bus_register(); |
389 | if (retval) { | |
390 | printk(KERN_WARNING "PCIE: bus_register error: %d\n", retval); | |
391 | goto out; | |
392 | } | |
3603a6a3 | 393 | retval = pci_register_driver(&pcie_portdriver); |
1da177e4 LT |
394 | if (retval) |
395 | pcie_port_bus_unregister(); | |
20d51660 | 396 | out: |
1da177e4 LT |
397 | return retval; |
398 | } | |
a7dadf45 | 399 | device_initcall(pcie_portdrv_init); |