Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
589fcc23 | 9 | #include <linux/pci_hotplug.h> |
1da177e4 LT |
10 | #include <linux/slab.h> |
11 | #include <linux/module.h> | |
12 | #include <linux/cpumask.h> | |
7d715a6c | 13 | #include <linux/pci-aspm.h> |
284f5f9d | 14 | #include <asm-generic/pci-bridge.h> |
bc56b9e0 | 15 | #include "pci.h" |
1da177e4 LT |
16 | |
17 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
18 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 | 19 | |
0b950f0f | 20 | static struct resource busn_resource = { |
67cdc827 YL |
21 | .name = "PCI busn", |
22 | .start = 0, | |
23 | .end = 255, | |
24 | .flags = IORESOURCE_BUS, | |
25 | }; | |
26 | ||
1da177e4 LT |
27 | /* Ugh. Need to stop exporting this to modules. */ |
28 | LIST_HEAD(pci_root_buses); | |
29 | EXPORT_SYMBOL(pci_root_buses); | |
30 | ||
5cc62c20 YL |
31 | static LIST_HEAD(pci_domain_busn_res_list); |
32 | ||
33 | struct pci_domain_busn_res { | |
34 | struct list_head list; | |
35 | struct resource res; | |
36 | int domain_nr; | |
37 | }; | |
38 | ||
39 | static struct resource *get_pci_domain_busn_res(int domain_nr) | |
40 | { | |
41 | struct pci_domain_busn_res *r; | |
42 | ||
43 | list_for_each_entry(r, &pci_domain_busn_res_list, list) | |
44 | if (r->domain_nr == domain_nr) | |
45 | return &r->res; | |
46 | ||
47 | r = kzalloc(sizeof(*r), GFP_KERNEL); | |
48 | if (!r) | |
49 | return NULL; | |
50 | ||
51 | r->domain_nr = domain_nr; | |
52 | r->res.start = 0; | |
53 | r->res.end = 0xff; | |
54 | r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; | |
55 | ||
56 | list_add_tail(&r->list, &pci_domain_busn_res_list); | |
57 | ||
58 | return &r->res; | |
59 | } | |
60 | ||
70308923 GKH |
61 | static int find_anything(struct device *dev, void *data) |
62 | { | |
63 | return 1; | |
64 | } | |
1da177e4 | 65 | |
ed4aaadb ZY |
66 | /* |
67 | * Some device drivers need know if pci is initiated. | |
68 | * Basically, we think pci is not initiated when there | |
70308923 | 69 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
70 | */ |
71 | int no_pci_devices(void) | |
72 | { | |
70308923 GKH |
73 | struct device *dev; |
74 | int no_devices; | |
ed4aaadb | 75 | |
70308923 GKH |
76 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
77 | no_devices = (dev == NULL); | |
78 | put_device(dev); | |
79 | return no_devices; | |
80 | } | |
ed4aaadb ZY |
81 | EXPORT_SYMBOL(no_pci_devices); |
82 | ||
1da177e4 LT |
83 | /* |
84 | * PCI Bus Class | |
85 | */ | |
fd7d1ced | 86 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 87 | { |
fd7d1ced | 88 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
89 | |
90 | if (pci_bus->bridge) | |
91 | put_device(pci_bus->bridge); | |
2fe2abf8 | 92 | pci_bus_remove_resources(pci_bus); |
98d9f30c | 93 | pci_release_bus_of_node(pci_bus); |
1da177e4 LT |
94 | kfree(pci_bus); |
95 | } | |
96 | ||
97 | static struct class pcibus_class = { | |
98 | .name = "pci_bus", | |
fd7d1ced | 99 | .dev_release = &release_pcibus_dev, |
56039e65 | 100 | .dev_groups = pcibus_groups, |
1da177e4 LT |
101 | }; |
102 | ||
103 | static int __init pcibus_class_init(void) | |
104 | { | |
105 | return class_register(&pcibus_class); | |
106 | } | |
107 | postcore_initcall(pcibus_class_init); | |
108 | ||
6ac665c6 | 109 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 110 | { |
6ac665c6 | 111 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
112 | if (!size) |
113 | return 0; | |
114 | ||
115 | /* Get the lowest of them to find the decode size, and | |
116 | from that the extent. */ | |
117 | size = (size & ~(size-1)) - 1; | |
118 | ||
119 | /* base == maxbase can be valid only if the BAR has | |
120 | already been programmed with all 1s. */ | |
121 | if (base == maxbase && ((base | size) & mask) != mask) | |
122 | return 0; | |
123 | ||
124 | return size; | |
125 | } | |
126 | ||
28c6821a | 127 | static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) |
6ac665c6 | 128 | { |
8d6a6a47 | 129 | u32 mem_type; |
28c6821a | 130 | unsigned long flags; |
8d6a6a47 | 131 | |
6ac665c6 | 132 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
28c6821a BH |
133 | flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; |
134 | flags |= IORESOURCE_IO; | |
135 | return flags; | |
6ac665c6 | 136 | } |
07eddf3d | 137 | |
28c6821a BH |
138 | flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
139 | flags |= IORESOURCE_MEM; | |
140 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
141 | flags |= IORESOURCE_PREFETCH; | |
07eddf3d | 142 | |
8d6a6a47 BH |
143 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
144 | switch (mem_type) { | |
145 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
146 | break; | |
147 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
0ff9514b | 148 | /* 1M mem BAR treated as 32-bit BAR */ |
8d6a6a47 BH |
149 | break; |
150 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
28c6821a BH |
151 | flags |= IORESOURCE_MEM_64; |
152 | break; | |
8d6a6a47 | 153 | default: |
0ff9514b | 154 | /* mem unknown type treated as 32-bit BAR */ |
8d6a6a47 BH |
155 | break; |
156 | } | |
28c6821a | 157 | return flags; |
07eddf3d YL |
158 | } |
159 | ||
808e34e2 ZK |
160 | #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) |
161 | ||
0b400c7e YZ |
162 | /** |
163 | * pci_read_base - read a PCI BAR | |
164 | * @dev: the PCI device | |
165 | * @type: type of the BAR | |
166 | * @res: resource buffer to be filled in | |
167 | * @pos: BAR position in the config space | |
168 | * | |
169 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 170 | */ |
0b400c7e | 171 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
3c78bc61 | 172 | struct resource *res, unsigned int pos) |
07eddf3d | 173 | { |
6ac665c6 | 174 | u32 l, sz, mask; |
23b13bc7 | 175 | u64 l64, sz64, mask64; |
253d2e54 | 176 | u16 orig_cmd; |
cf4d1cf5 | 177 | struct pci_bus_region region, inverted_region; |
26370fc6 | 178 | bool bar_too_big = false, bar_too_high = false, bar_invalid = false; |
6ac665c6 | 179 | |
1ed67439 | 180 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 181 | |
0ff9514b | 182 | /* No printks while decoding is disabled! */ |
253d2e54 JP |
183 | if (!dev->mmio_always_on) { |
184 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
808e34e2 ZK |
185 | if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { |
186 | pci_write_config_word(dev, PCI_COMMAND, | |
187 | orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); | |
188 | } | |
253d2e54 JP |
189 | } |
190 | ||
6ac665c6 MW |
191 | res->name = pci_name(dev); |
192 | ||
193 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 194 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
195 | pci_read_config_dword(dev, pos, &sz); |
196 | pci_write_config_dword(dev, pos, l); | |
197 | ||
198 | /* | |
199 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
200 | * If the BAR isn't implemented, all bits must be 0. If it's a |
201 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
202 | * 1 must be clear. | |
6ac665c6 | 203 | */ |
45aa23b4 | 204 | if (!sz || sz == 0xffffffff) |
6ac665c6 MW |
205 | goto fail; |
206 | ||
207 | /* | |
208 | * I don't know how l can have all bits set. Copied from old code. | |
209 | * Maybe it fixes a bug on some ancient platform. | |
210 | */ | |
211 | if (l == 0xffffffff) | |
212 | l = 0; | |
213 | ||
214 | if (type == pci_bar_unknown) { | |
28c6821a BH |
215 | res->flags = decode_bar(dev, l); |
216 | res->flags |= IORESOURCE_SIZEALIGN; | |
217 | if (res->flags & IORESOURCE_IO) { | |
6ac665c6 | 218 | l &= PCI_BASE_ADDRESS_IO_MASK; |
36e81648 | 219 | sz &= PCI_BASE_ADDRESS_IO_MASK; |
5aceca9d | 220 | mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
6ac665c6 MW |
221 | } else { |
222 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
36e81648 | 223 | sz &= PCI_BASE_ADDRESS_MEM_MASK; |
6ac665c6 MW |
224 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; |
225 | } | |
226 | } else { | |
227 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
228 | l &= PCI_ROM_ADDRESS_MASK; | |
36e81648 | 229 | sz &= PCI_ROM_ADDRESS_MASK; |
6ac665c6 MW |
230 | mask = (u32)PCI_ROM_ADDRESS_MASK; |
231 | } | |
232 | ||
28c6821a | 233 | if (res->flags & IORESOURCE_MEM_64) { |
23b13bc7 BH |
234 | l64 = l; |
235 | sz64 = sz; | |
236 | mask64 = mask | (u64)~0 << 32; | |
6ac665c6 MW |
237 | |
238 | pci_read_config_dword(dev, pos + 4, &l); | |
239 | pci_write_config_dword(dev, pos + 4, ~0); | |
240 | pci_read_config_dword(dev, pos + 4, &sz); | |
241 | pci_write_config_dword(dev, pos + 4, l); | |
242 | ||
243 | l64 |= ((u64)l << 32); | |
244 | sz64 |= ((u64)sz << 32); | |
245 | ||
246 | sz64 = pci_size(l64, sz64, mask64); | |
247 | ||
248 | if (!sz64) | |
249 | goto fail; | |
250 | ||
23b13bc7 BH |
251 | if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) && |
252 | sz64 > 0x100000000ULL) { | |
253 | res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; | |
254 | res->start = 0; | |
255 | res->end = 0; | |
0ff9514b | 256 | bar_too_big = true; |
23b13bc7 | 257 | goto out; |
c7dabef8 BH |
258 | } |
259 | ||
d1a313e4 | 260 | if ((sizeof(dma_addr_t) < 8) && l) { |
31e9dd25 | 261 | /* Above 32-bit boundary; try to reallocate */ |
c83bd900 | 262 | res->flags |= IORESOURCE_UNSET; |
72dc5601 BH |
263 | res->start = 0; |
264 | res->end = sz64; | |
31e9dd25 | 265 | bar_too_high = true; |
72dc5601 | 266 | goto out; |
6ac665c6 | 267 | } else { |
5bfa14ed BH |
268 | region.start = l64; |
269 | region.end = l64 + sz64; | |
6ac665c6 MW |
270 | } |
271 | } else { | |
45aa23b4 | 272 | sz = pci_size(l, sz, mask); |
6ac665c6 | 273 | |
45aa23b4 | 274 | if (!sz) |
6ac665c6 MW |
275 | goto fail; |
276 | ||
5bfa14ed BH |
277 | region.start = l; |
278 | region.end = l + sz; | |
6ac665c6 MW |
279 | } |
280 | ||
fc279850 YL |
281 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
282 | pcibios_resource_to_bus(dev->bus, &inverted_region, res); | |
cf4d1cf5 KH |
283 | |
284 | /* | |
285 | * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is | |
286 | * the corresponding resource address (the physical address used by | |
287 | * the CPU. Converting that resource address back to a bus address | |
288 | * should yield the original BAR value: | |
289 | * | |
290 | * resource_to_bus(bus_to_resource(A)) == A | |
291 | * | |
292 | * If it doesn't, CPU accesses to "bus_to_resource(A)" will not | |
293 | * be claimed by the device. | |
294 | */ | |
295 | if (inverted_region.start != region.start) { | |
cf4d1cf5 | 296 | res->flags |= IORESOURCE_UNSET; |
cf4d1cf5 | 297 | res->start = 0; |
26370fc6 BH |
298 | res->end = region.end - region.start; |
299 | bar_invalid = true; | |
cf4d1cf5 | 300 | } |
96ddef25 | 301 | |
0ff9514b BH |
302 | goto out; |
303 | ||
304 | ||
305 | fail: | |
306 | res->flags = 0; | |
307 | out: | |
808e34e2 ZK |
308 | if (!dev->mmio_always_on && |
309 | (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) | |
bbffe435 BH |
310 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); |
311 | ||
0ff9514b | 312 | if (bar_too_big) |
23b13bc7 BH |
313 | dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n", |
314 | pos, (unsigned long long) sz64); | |
31e9dd25 BH |
315 | if (bar_too_high) |
316 | dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n", | |
317 | pos, (unsigned long long) l64); | |
26370fc6 BH |
318 | if (bar_invalid) |
319 | dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n", | |
320 | pos, (unsigned long long) region.start); | |
31e9dd25 | 321 | if (res->flags) |
33963e30 | 322 | dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res); |
0ff9514b | 323 | |
28c6821a | 324 | return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; |
07eddf3d YL |
325 | } |
326 | ||
1da177e4 LT |
327 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
328 | { | |
6ac665c6 | 329 | unsigned int pos, reg; |
07eddf3d | 330 | |
6ac665c6 MW |
331 | for (pos = 0; pos < howmany; pos++) { |
332 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 333 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 334 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 335 | } |
6ac665c6 | 336 | |
1da177e4 | 337 | if (rom) { |
6ac665c6 | 338 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 339 | dev->rom_base_reg = rom; |
6ac665c6 MW |
340 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
341 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
342 | IORESOURCE_SIZEALIGN; | |
343 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
344 | } |
345 | } | |
346 | ||
15856ad5 | 347 | static void pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
348 | { |
349 | struct pci_dev *dev = child->self; | |
350 | u8 io_base_lo, io_limit_lo; | |
2b28ae19 | 351 | unsigned long io_mask, io_granularity, base, limit; |
5bfa14ed | 352 | struct pci_bus_region region; |
2b28ae19 BH |
353 | struct resource *res; |
354 | ||
355 | io_mask = PCI_IO_RANGE_MASK; | |
356 | io_granularity = 0x1000; | |
357 | if (dev->io_window_1k) { | |
358 | /* Support 1K I/O space granularity */ | |
359 | io_mask = PCI_IO_1K_RANGE_MASK; | |
360 | io_granularity = 0x400; | |
361 | } | |
1da177e4 | 362 | |
1da177e4 LT |
363 | res = child->resource[0]; |
364 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
365 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
2b28ae19 BH |
366 | base = (io_base_lo & io_mask) << 8; |
367 | limit = (io_limit_lo & io_mask) << 8; | |
1da177e4 LT |
368 | |
369 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
370 | u16 io_base_hi, io_limit_hi; | |
8f38eaca | 371 | |
1da177e4 LT |
372 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
373 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
8f38eaca BH |
374 | base |= ((unsigned long) io_base_hi << 16); |
375 | limit |= ((unsigned long) io_limit_hi << 16); | |
1da177e4 LT |
376 | } |
377 | ||
5dde383e | 378 | if (base <= limit) { |
1da177e4 | 379 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
5bfa14ed | 380 | region.start = base; |
2b28ae19 | 381 | region.end = limit + io_granularity - 1; |
fc279850 | 382 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 383 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 384 | } |
fa27b2d1 BH |
385 | } |
386 | ||
15856ad5 | 387 | static void pci_read_bridge_mmio(struct pci_bus *child) |
fa27b2d1 BH |
388 | { |
389 | struct pci_dev *dev = child->self; | |
390 | u16 mem_base_lo, mem_limit_lo; | |
391 | unsigned long base, limit; | |
5bfa14ed | 392 | struct pci_bus_region region; |
fa27b2d1 | 393 | struct resource *res; |
1da177e4 LT |
394 | |
395 | res = child->resource[1]; | |
396 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
397 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
8f38eaca BH |
398 | base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
399 | limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
5dde383e | 400 | if (base <= limit) { |
1da177e4 | 401 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
5bfa14ed BH |
402 | region.start = base; |
403 | region.end = limit + 0xfffff; | |
fc279850 | 404 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 405 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 | 406 | } |
fa27b2d1 BH |
407 | } |
408 | ||
15856ad5 | 409 | static void pci_read_bridge_mmio_pref(struct pci_bus *child) |
fa27b2d1 BH |
410 | { |
411 | struct pci_dev *dev = child->self; | |
412 | u16 mem_base_lo, mem_limit_lo; | |
413 | unsigned long base, limit; | |
5bfa14ed | 414 | struct pci_bus_region region; |
fa27b2d1 | 415 | struct resource *res; |
1da177e4 LT |
416 | |
417 | res = child->resource[2]; | |
418 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
419 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
8f38eaca BH |
420 | base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
421 | limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
1da177e4 LT |
422 | |
423 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
424 | u32 mem_base_hi, mem_limit_hi; | |
8f38eaca | 425 | |
1da177e4 LT |
426 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
427 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
428 | ||
429 | /* | |
430 | * Some bridges set the base > limit by default, and some | |
431 | * (broken) BIOSes do not initialize them. If we find | |
432 | * this, just assume they are not being used. | |
433 | */ | |
434 | if (mem_base_hi <= mem_limit_hi) { | |
435 | #if BITS_PER_LONG == 64 | |
8f38eaca BH |
436 | base |= ((unsigned long) mem_base_hi) << 32; |
437 | limit |= ((unsigned long) mem_limit_hi) << 32; | |
1da177e4 LT |
438 | #else |
439 | if (mem_base_hi || mem_limit_hi) { | |
227f0647 | 440 | dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n"); |
1da177e4 LT |
441 | return; |
442 | } | |
443 | #endif | |
444 | } | |
445 | } | |
5dde383e | 446 | if (base <= limit) { |
1f82de10 YL |
447 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
448 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
449 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
450 | res->flags |= IORESOURCE_MEM_64; | |
5bfa14ed BH |
451 | region.start = base; |
452 | region.end = limit + 0xfffff; | |
fc279850 | 453 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
c7dabef8 | 454 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
1da177e4 LT |
455 | } |
456 | } | |
457 | ||
15856ad5 | 458 | void pci_read_bridge_bases(struct pci_bus *child) |
fa27b2d1 BH |
459 | { |
460 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 461 | struct resource *res; |
fa27b2d1 BH |
462 | int i; |
463 | ||
464 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
465 | return; | |
466 | ||
b918c62e YL |
467 | dev_info(&dev->dev, "PCI bridge to %pR%s\n", |
468 | &child->busn_res, | |
fa27b2d1 BH |
469 | dev->transparent ? " (subtractive decode)" : ""); |
470 | ||
2fe2abf8 BH |
471 | pci_bus_remove_resources(child); |
472 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
473 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
474 | ||
fa27b2d1 BH |
475 | pci_read_bridge_io(child); |
476 | pci_read_bridge_mmio(child); | |
477 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
478 | |
479 | if (dev->transparent) { | |
2fe2abf8 | 480 | pci_bus_for_each_resource(child->parent, res, i) { |
d739a099 | 481 | if (res && res->flags) { |
2fe2abf8 BH |
482 | pci_bus_add_resource(child, res, |
483 | PCI_SUBTRACTIVE_DECODE); | |
2adf7516 BH |
484 | dev_printk(KERN_DEBUG, &dev->dev, |
485 | " bridge window %pR (subtractive decode)\n", | |
2fe2abf8 BH |
486 | res); |
487 | } | |
2adf7516 BH |
488 | } |
489 | } | |
fa27b2d1 BH |
490 | } |
491 | ||
670ba0c8 | 492 | static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) |
1da177e4 LT |
493 | { |
494 | struct pci_bus *b; | |
495 | ||
f5afe806 | 496 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
05013486 BH |
497 | if (!b) |
498 | return NULL; | |
499 | ||
500 | INIT_LIST_HEAD(&b->node); | |
501 | INIT_LIST_HEAD(&b->children); | |
502 | INIT_LIST_HEAD(&b->devices); | |
503 | INIT_LIST_HEAD(&b->slots); | |
504 | INIT_LIST_HEAD(&b->resources); | |
505 | b->max_bus_speed = PCI_SPEED_UNKNOWN; | |
506 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
670ba0c8 CM |
507 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
508 | if (parent) | |
509 | b->domain_nr = parent->domain_nr; | |
510 | #endif | |
1da177e4 LT |
511 | return b; |
512 | } | |
513 | ||
70efde2a JL |
514 | static void pci_release_host_bridge_dev(struct device *dev) |
515 | { | |
516 | struct pci_host_bridge *bridge = to_pci_host_bridge(dev); | |
517 | ||
518 | if (bridge->release_fn) | |
519 | bridge->release_fn(bridge); | |
520 | ||
521 | pci_free_resource_list(&bridge->windows); | |
522 | ||
523 | kfree(bridge); | |
524 | } | |
525 | ||
7b543663 YL |
526 | static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b) |
527 | { | |
528 | struct pci_host_bridge *bridge; | |
529 | ||
530 | bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); | |
05013486 BH |
531 | if (!bridge) |
532 | return NULL; | |
7b543663 | 533 | |
05013486 BH |
534 | INIT_LIST_HEAD(&bridge->windows); |
535 | bridge->bus = b; | |
7b543663 YL |
536 | return bridge; |
537 | } | |
538 | ||
0b950f0f | 539 | static const unsigned char pcix_bus_speed[] = { |
9be60ca0 MW |
540 | PCI_SPEED_UNKNOWN, /* 0 */ |
541 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
542 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
543 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
544 | PCI_SPEED_UNKNOWN, /* 4 */ | |
545 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
546 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
547 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
548 | PCI_SPEED_UNKNOWN, /* 8 */ | |
549 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
550 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
551 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
552 | PCI_SPEED_UNKNOWN, /* C */ | |
553 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
554 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
555 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
556 | }; | |
557 | ||
343e51ae | 558 | const unsigned char pcie_link_speed[] = { |
3749c51a MW |
559 | PCI_SPEED_UNKNOWN, /* 0 */ |
560 | PCIE_SPEED_2_5GT, /* 1 */ | |
561 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 562 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
563 | PCI_SPEED_UNKNOWN, /* 4 */ |
564 | PCI_SPEED_UNKNOWN, /* 5 */ | |
565 | PCI_SPEED_UNKNOWN, /* 6 */ | |
566 | PCI_SPEED_UNKNOWN, /* 7 */ | |
567 | PCI_SPEED_UNKNOWN, /* 8 */ | |
568 | PCI_SPEED_UNKNOWN, /* 9 */ | |
569 | PCI_SPEED_UNKNOWN, /* A */ | |
570 | PCI_SPEED_UNKNOWN, /* B */ | |
571 | PCI_SPEED_UNKNOWN, /* C */ | |
572 | PCI_SPEED_UNKNOWN, /* D */ | |
573 | PCI_SPEED_UNKNOWN, /* E */ | |
574 | PCI_SPEED_UNKNOWN /* F */ | |
575 | }; | |
576 | ||
577 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
578 | { | |
231afea1 | 579 | bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; |
3749c51a MW |
580 | } |
581 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
582 | ||
45b4cdd5 MW |
583 | static unsigned char agp_speeds[] = { |
584 | AGP_UNKNOWN, | |
585 | AGP_1X, | |
586 | AGP_2X, | |
587 | AGP_4X, | |
588 | AGP_8X | |
589 | }; | |
590 | ||
591 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
592 | { | |
593 | int index = 0; | |
594 | ||
595 | if (agpstat & 4) | |
596 | index = 3; | |
597 | else if (agpstat & 2) | |
598 | index = 2; | |
599 | else if (agpstat & 1) | |
600 | index = 1; | |
601 | else | |
602 | goto out; | |
f7625980 | 603 | |
45b4cdd5 MW |
604 | if (agp3) { |
605 | index += 2; | |
606 | if (index == 5) | |
607 | index = 0; | |
608 | } | |
609 | ||
610 | out: | |
611 | return agp_speeds[index]; | |
612 | } | |
613 | ||
9be60ca0 MW |
614 | static void pci_set_bus_speed(struct pci_bus *bus) |
615 | { | |
616 | struct pci_dev *bridge = bus->self; | |
617 | int pos; | |
618 | ||
45b4cdd5 MW |
619 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
620 | if (!pos) | |
621 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
622 | if (pos) { | |
623 | u32 agpstat, agpcmd; | |
624 | ||
625 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
626 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
627 | ||
628 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
629 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
630 | } | |
631 | ||
9be60ca0 MW |
632 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
633 | if (pos) { | |
634 | u16 status; | |
635 | enum pci_bus_speed max; | |
9be60ca0 | 636 | |
7793eeab BH |
637 | pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, |
638 | &status); | |
639 | ||
640 | if (status & PCI_X_SSTATUS_533MHZ) { | |
9be60ca0 | 641 | max = PCI_SPEED_133MHz_PCIX_533; |
7793eeab | 642 | } else if (status & PCI_X_SSTATUS_266MHZ) { |
9be60ca0 | 643 | max = PCI_SPEED_133MHz_PCIX_266; |
7793eeab | 644 | } else if (status & PCI_X_SSTATUS_133MHZ) { |
3c78bc61 | 645 | if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) |
9be60ca0 | 646 | max = PCI_SPEED_133MHz_PCIX_ECC; |
3c78bc61 | 647 | else |
9be60ca0 | 648 | max = PCI_SPEED_133MHz_PCIX; |
9be60ca0 MW |
649 | } else { |
650 | max = PCI_SPEED_66MHz_PCIX; | |
651 | } | |
652 | ||
653 | bus->max_bus_speed = max; | |
7793eeab BH |
654 | bus->cur_bus_speed = pcix_bus_speed[ |
655 | (status & PCI_X_SSTATUS_FREQ) >> 6]; | |
9be60ca0 MW |
656 | |
657 | return; | |
658 | } | |
659 | ||
fdfe1511 | 660 | if (pci_is_pcie(bridge)) { |
9be60ca0 MW |
661 | u32 linkcap; |
662 | u16 linksta; | |
663 | ||
59875ae4 | 664 | pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); |
231afea1 | 665 | bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; |
9be60ca0 | 666 | |
59875ae4 | 667 | pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); |
9be60ca0 MW |
668 | pcie_update_link_speed(bus, linksta); |
669 | } | |
670 | } | |
671 | ||
cbd4e055 AB |
672 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
673 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
674 | { |
675 | struct pci_bus *child; | |
676 | int i; | |
4f535093 | 677 | int ret; |
1da177e4 LT |
678 | |
679 | /* | |
680 | * Allocate a new bus, and inherit stuff from the parent.. | |
681 | */ | |
670ba0c8 | 682 | child = pci_alloc_bus(parent); |
1da177e4 LT |
683 | if (!child) |
684 | return NULL; | |
685 | ||
1da177e4 LT |
686 | child->parent = parent; |
687 | child->ops = parent->ops; | |
0cbdcfcf | 688 | child->msi = parent->msi; |
1da177e4 | 689 | child->sysdata = parent->sysdata; |
6e325a62 | 690 | child->bus_flags = parent->bus_flags; |
1da177e4 | 691 | |
fd7d1ced | 692 | /* initialize some portions of the bus device, but don't register it |
4f535093 | 693 | * now as the parent is not properly set up yet. |
fd7d1ced GKH |
694 | */ |
695 | child->dev.class = &pcibus_class; | |
1a927133 | 696 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
697 | |
698 | /* | |
699 | * Set up the primary, secondary and subordinate | |
700 | * bus numbers. | |
701 | */ | |
b918c62e YL |
702 | child->number = child->busn_res.start = busnr; |
703 | child->primary = parent->busn_res.start; | |
704 | child->busn_res.end = 0xff; | |
1da177e4 | 705 | |
4f535093 YL |
706 | if (!bridge) { |
707 | child->dev.parent = parent->bridge; | |
708 | goto add_dev; | |
709 | } | |
3789fa8a YZ |
710 | |
711 | child->self = bridge; | |
712 | child->bridge = get_device(&bridge->dev); | |
4f535093 | 713 | child->dev.parent = child->bridge; |
98d9f30c | 714 | pci_set_bus_of_node(child); |
9be60ca0 MW |
715 | pci_set_bus_speed(child); |
716 | ||
1da177e4 | 717 | /* Set up default resource pointers and names.. */ |
fde09c6d | 718 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
719 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
720 | child->resource[i]->name = child->name; | |
721 | } | |
722 | bridge->subordinate = child; | |
723 | ||
4f535093 YL |
724 | add_dev: |
725 | ret = device_register(&child->dev); | |
726 | WARN_ON(ret < 0); | |
727 | ||
10a95747 JL |
728 | pcibios_add_bus(child); |
729 | ||
4f535093 YL |
730 | /* Create legacy_io and legacy_mem files for this bus */ |
731 | pci_create_legacy_files(child); | |
732 | ||
1da177e4 LT |
733 | return child; |
734 | } | |
735 | ||
3c78bc61 RD |
736 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
737 | int busnr) | |
1da177e4 LT |
738 | { |
739 | struct pci_bus *child; | |
740 | ||
741 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 742 | if (child) { |
d71374da | 743 | down_write(&pci_bus_sem); |
1da177e4 | 744 | list_add_tail(&child->node, &parent->children); |
d71374da | 745 | up_write(&pci_bus_sem); |
e4ea9bb7 | 746 | } |
1da177e4 LT |
747 | return child; |
748 | } | |
b7fe9434 | 749 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 | 750 | |
f3dbd802 RJ |
751 | static void pci_enable_crs(struct pci_dev *pdev) |
752 | { | |
753 | u16 root_cap = 0; | |
754 | ||
755 | /* Enable CRS Software Visibility if supported */ | |
756 | pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); | |
757 | if (root_cap & PCI_EXP_RTCAP_CRSVIS) | |
758 | pcie_capability_set_word(pdev, PCI_EXP_RTCTL, | |
759 | PCI_EXP_RTCTL_CRSSVE); | |
760 | } | |
761 | ||
1da177e4 LT |
762 | /* |
763 | * If it's a bridge, configure it and scan the bus behind it. | |
764 | * For CardBus bridges, we don't scan behind as the devices will | |
765 | * be handled by the bridge driver itself. | |
766 | * | |
767 | * We need to process bridges in two passes -- first we scan those | |
768 | * already configured by the BIOS and after we are done with all of | |
769 | * them, we proceed to assigning numbers to the remaining buses in | |
770 | * order to avoid overlaps between old and new bus numbers. | |
771 | */ | |
15856ad5 | 772 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
773 | { |
774 | struct pci_bus *child; | |
775 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 776 | u32 buses, i, j = 0; |
1da177e4 | 777 | u16 bctl; |
99ddd552 | 778 | u8 primary, secondary, subordinate; |
a1c19894 | 779 | int broken = 0; |
1da177e4 LT |
780 | |
781 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
99ddd552 BH |
782 | primary = buses & 0xFF; |
783 | secondary = (buses >> 8) & 0xFF; | |
784 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 785 | |
99ddd552 BH |
786 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
787 | secondary, subordinate, pass); | |
1da177e4 | 788 | |
71f6bd4a YL |
789 | if (!primary && (primary != bus->number) && secondary && subordinate) { |
790 | dev_warn(&dev->dev, "Primary bus is hard wired to 0\n"); | |
791 | primary = bus->number; | |
792 | } | |
793 | ||
a1c19894 BH |
794 | /* Check if setup is sensible at all */ |
795 | if (!pass && | |
1965f66e | 796 | (primary != bus->number || secondary <= bus->number || |
12d87069 | 797 | secondary > subordinate)) { |
1965f66e YL |
798 | dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", |
799 | secondary, subordinate); | |
a1c19894 BH |
800 | broken = 1; |
801 | } | |
802 | ||
1da177e4 | 803 | /* Disable MasterAbortMode during probing to avoid reporting |
f7625980 | 804 | of bus errors (in some architectures) */ |
1da177e4 LT |
805 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); |
806 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
807 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
808 | ||
f3dbd802 RJ |
809 | pci_enable_crs(dev); |
810 | ||
99ddd552 BH |
811 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
812 | !is_cardbus && !broken) { | |
813 | unsigned int cmax; | |
1da177e4 LT |
814 | /* |
815 | * Bus already configured by firmware, process it in the first | |
816 | * pass and just note the configuration. | |
817 | */ | |
818 | if (pass) | |
bbe8f9a3 | 819 | goto out; |
1da177e4 LT |
820 | |
821 | /* | |
2ed85823 AN |
822 | * The bus might already exist for two reasons: Either we are |
823 | * rescanning the bus or the bus is reachable through more than | |
824 | * one bridge. The second case can happen with the i450NX | |
825 | * chipset. | |
1da177e4 | 826 | */ |
99ddd552 | 827 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 828 | if (!child) { |
99ddd552 | 829 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
830 | if (!child) |
831 | goto out; | |
99ddd552 | 832 | child->primary = primary; |
bc76b731 | 833 | pci_bus_insert_busn_res(child, secondary, subordinate); |
74710ded | 834 | child->bridge_ctl = bctl; |
1da177e4 LT |
835 | } |
836 | ||
1da177e4 | 837 | cmax = pci_scan_child_bus(child); |
c95b0bd6 AN |
838 | if (cmax > subordinate) |
839 | dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n", | |
840 | subordinate, cmax); | |
841 | /* subordinate should equal child->busn_res.end */ | |
842 | if (subordinate > max) | |
843 | max = subordinate; | |
1da177e4 LT |
844 | } else { |
845 | /* | |
846 | * We need to assign a number to this bus which we always | |
847 | * do in the second pass. | |
848 | */ | |
12f44f46 | 849 | if (!pass) { |
619c8c31 | 850 | if (pcibios_assign_all_busses() || broken || is_cardbus) |
12f44f46 IK |
851 | /* Temporarily disable forwarding of the |
852 | configuration cycles on all bridges in | |
853 | this bus segment to avoid possible | |
854 | conflicts in the second pass between two | |
855 | bridges programmed with overlapping | |
856 | bus ranges. */ | |
857 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
858 | buses & ~0xffffff); | |
bbe8f9a3 | 859 | goto out; |
12f44f46 | 860 | } |
1da177e4 LT |
861 | |
862 | /* Clear errors */ | |
863 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
864 | ||
7a0b33d4 BH |
865 | /* Prevent assigning a bus number that already exists. |
866 | * This can happen when a bridge is hot-plugged, so in | |
867 | * this case we only re-scan this bus. */ | |
b1a98b69 TC |
868 | child = pci_find_bus(pci_domain_nr(bus), max+1); |
869 | if (!child) { | |
9a4d7d87 | 870 | child = pci_add_new_bus(bus, dev, max+1); |
b1a98b69 TC |
871 | if (!child) |
872 | goto out; | |
12d87069 | 873 | pci_bus_insert_busn_res(child, max+1, 0xff); |
b1a98b69 | 874 | } |
9a4d7d87 | 875 | max++; |
1da177e4 LT |
876 | buses = (buses & 0xff000000) |
877 | | ((unsigned int)(child->primary) << 0) | |
b918c62e YL |
878 | | ((unsigned int)(child->busn_res.start) << 8) |
879 | | ((unsigned int)(child->busn_res.end) << 16); | |
1da177e4 LT |
880 | |
881 | /* | |
882 | * yenta.c forces a secondary latency timer of 176. | |
883 | * Copy that behaviour here. | |
884 | */ | |
885 | if (is_cardbus) { | |
886 | buses &= ~0xff000000; | |
887 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
888 | } | |
7c867c88 | 889 | |
1da177e4 LT |
890 | /* |
891 | * We need to blast all three values with a single write. | |
892 | */ | |
893 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
894 | ||
895 | if (!is_cardbus) { | |
11949255 | 896 | child->bridge_ctl = bctl; |
1da177e4 LT |
897 | max = pci_scan_child_bus(child); |
898 | } else { | |
899 | /* | |
900 | * For CardBus bridges, we leave 4 bus numbers | |
901 | * as cards with a PCI-to-PCI bridge can be | |
902 | * inserted later. | |
903 | */ | |
3c78bc61 | 904 | for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { |
49887941 | 905 | struct pci_bus *parent = bus; |
cc57450f RS |
906 | if (pci_find_bus(pci_domain_nr(bus), |
907 | max+i+1)) | |
908 | break; | |
49887941 DB |
909 | while (parent->parent) { |
910 | if ((!pcibios_assign_all_busses()) && | |
b918c62e YL |
911 | (parent->busn_res.end > max) && |
912 | (parent->busn_res.end <= max+i)) { | |
49887941 DB |
913 | j = 1; |
914 | } | |
915 | parent = parent->parent; | |
916 | } | |
917 | if (j) { | |
918 | /* | |
919 | * Often, there are two cardbus bridges | |
920 | * -- try to leave one valid bus number | |
921 | * for each one. | |
922 | */ | |
923 | i /= 2; | |
924 | break; | |
925 | } | |
926 | } | |
cc57450f | 927 | max += i; |
1da177e4 LT |
928 | } |
929 | /* | |
930 | * Set the subordinate bus number to its real value. | |
931 | */ | |
bc76b731 | 932 | pci_bus_update_busn_res_end(child, max); |
1da177e4 LT |
933 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
934 | } | |
935 | ||
cb3576fa GH |
936 | sprintf(child->name, |
937 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
938 | pci_domain_nr(bus), child->number); | |
1da177e4 | 939 | |
d55bef51 | 940 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 | 941 | while (bus->parent) { |
b918c62e YL |
942 | if ((child->busn_res.end > bus->busn_res.end) || |
943 | (child->number > bus->busn_res.end) || | |
49887941 | 944 | (child->number < bus->number) || |
b918c62e | 945 | (child->busn_res.end < bus->number)) { |
227f0647 | 946 | dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n", |
b918c62e YL |
947 | &child->busn_res, |
948 | (bus->number > child->busn_res.end && | |
949 | bus->busn_res.end < child->number) ? | |
a6f29a98 JP |
950 | "wholly" : "partially", |
951 | bus->self->transparent ? " transparent" : "", | |
865df576 | 952 | dev_name(&bus->dev), |
b918c62e | 953 | &bus->busn_res); |
49887941 DB |
954 | } |
955 | bus = bus->parent; | |
956 | } | |
957 | ||
bbe8f9a3 RB |
958 | out: |
959 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
960 | ||
1da177e4 LT |
961 | return max; |
962 | } | |
b7fe9434 | 963 | EXPORT_SYMBOL(pci_scan_bridge); |
1da177e4 LT |
964 | |
965 | /* | |
966 | * Read interrupt line and base address registers. | |
967 | * The architecture-dependent code can tweak these, of course. | |
968 | */ | |
969 | static void pci_read_irq(struct pci_dev *dev) | |
970 | { | |
971 | unsigned char irq; | |
972 | ||
973 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 974 | dev->pin = irq; |
1da177e4 LT |
975 | if (irq) |
976 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
977 | dev->irq = irq; | |
978 | } | |
979 | ||
bb209c82 | 980 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
981 | { |
982 | int pos; | |
983 | u16 reg16; | |
984 | ||
985 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
986 | if (!pos) | |
987 | return; | |
0efea000 | 988 | pdev->pcie_cap = pos; |
480b93b7 | 989 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
786e2288 | 990 | pdev->pcie_flags_reg = reg16; |
b03e7495 JM |
991 | pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); |
992 | pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; | |
480b93b7 YZ |
993 | } |
994 | ||
bb209c82 | 995 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 | 996 | { |
28760489 EB |
997 | u32 reg32; |
998 | ||
59875ae4 | 999 | pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); |
28760489 EB |
1000 | if (reg32 & PCI_EXP_SLTCAP_HPC) |
1001 | pdev->is_hotplug_bridge = 1; | |
1002 | } | |
1003 | ||
78916b00 AW |
1004 | /** |
1005 | * pci_ext_cfg_is_aliased - is ext config space just an alias of std config? | |
1006 | * @dev: PCI device | |
1007 | * | |
1008 | * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that | |
1009 | * when forwarding a type1 configuration request the bridge must check that | |
1010 | * the extended register address field is zero. The bridge is not permitted | |
1011 | * to forward the transactions and must handle it as an Unsupported Request. | |
1012 | * Some bridges do not follow this rule and simply drop the extended register | |
1013 | * bits, resulting in the standard config space being aliased, every 256 | |
1014 | * bytes across the entire configuration space. Test for this condition by | |
1015 | * comparing the first dword of each potential alias to the vendor/device ID. | |
1016 | * Known offenders: | |
1017 | * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) | |
1018 | * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) | |
1019 | */ | |
1020 | static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) | |
1021 | { | |
1022 | #ifdef CONFIG_PCI_QUIRKS | |
1023 | int pos; | |
1024 | u32 header, tmp; | |
1025 | ||
1026 | pci_read_config_dword(dev, PCI_VENDOR_ID, &header); | |
1027 | ||
1028 | for (pos = PCI_CFG_SPACE_SIZE; | |
1029 | pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { | |
1030 | if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL | |
1031 | || header != tmp) | |
1032 | return false; | |
1033 | } | |
1034 | ||
1035 | return true; | |
1036 | #else | |
1037 | return false; | |
1038 | #endif | |
1039 | } | |
1040 | ||
0b950f0f SH |
1041 | /** |
1042 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
1043 | * @dev: PCI device | |
1044 | * | |
1045 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1046 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1047 | * access it. Maybe we don't have a way to generate extended config space | |
1048 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1049 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1050 | * capability header. | |
1051 | */ | |
1052 | static int pci_cfg_space_size_ext(struct pci_dev *dev) | |
1053 | { | |
1054 | u32 status; | |
1055 | int pos = PCI_CFG_SPACE_SIZE; | |
1056 | ||
1057 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) | |
1058 | goto fail; | |
78916b00 | 1059 | if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev)) |
0b950f0f SH |
1060 | goto fail; |
1061 | ||
1062 | return PCI_CFG_SPACE_EXP_SIZE; | |
1063 | ||
1064 | fail: | |
1065 | return PCI_CFG_SPACE_SIZE; | |
1066 | } | |
1067 | ||
1068 | int pci_cfg_space_size(struct pci_dev *dev) | |
1069 | { | |
1070 | int pos; | |
1071 | u32 status; | |
1072 | u16 class; | |
1073 | ||
1074 | class = dev->class >> 8; | |
1075 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1076 | return pci_cfg_space_size_ext(dev); | |
1077 | ||
1078 | if (!pci_is_pcie(dev)) { | |
1079 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1080 | if (!pos) | |
1081 | goto fail; | |
1082 | ||
1083 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
1084 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
1085 | goto fail; | |
1086 | } | |
1087 | ||
1088 | return pci_cfg_space_size_ext(dev); | |
1089 | ||
1090 | fail: | |
1091 | return PCI_CFG_SPACE_SIZE; | |
1092 | } | |
1093 | ||
01abc2aa | 1094 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 1095 | |
1da177e4 LT |
1096 | /** |
1097 | * pci_setup_device - fill in class and map information of a device | |
1098 | * @dev: the device structure to fill | |
1099 | * | |
f7625980 | 1100 | * Initialize the device structure with information about the device's |
1da177e4 LT |
1101 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
1102 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
1103 | * Returns 0 on success and negative if unknown type of device (not normal, |
1104 | * bridge or CardBus). | |
1da177e4 | 1105 | */ |
480b93b7 | 1106 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
1107 | { |
1108 | u32 class; | |
480b93b7 YZ |
1109 | u8 hdr_type; |
1110 | struct pci_slot *slot; | |
bc577d2b | 1111 | int pos = 0; |
5bfa14ed BH |
1112 | struct pci_bus_region region; |
1113 | struct resource *res; | |
480b93b7 YZ |
1114 | |
1115 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
1116 | return -EIO; | |
1117 | ||
1118 | dev->sysdata = dev->bus->sysdata; | |
1119 | dev->dev.parent = dev->bus->bridge; | |
1120 | dev->dev.bus = &pci_bus_type; | |
1121 | dev->hdr_type = hdr_type & 0x7f; | |
1122 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
1123 | dev->error_state = pci_channel_io_normal; |
1124 | set_pcie_port_type(dev); | |
1125 | ||
1126 | list_for_each_entry(slot, &dev->bus->slots, list) | |
1127 | if (PCI_SLOT(dev->devfn) == slot->number) | |
1128 | dev->slot = slot; | |
1129 | ||
1130 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
1131 | set this higher, assuming the system even supports it. */ | |
1132 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 1133 | |
eebfcfb5 GKH |
1134 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
1135 | dev->bus->number, PCI_SLOT(dev->devfn), | |
1136 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
1137 | |
1138 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 1139 | dev->revision = class & 0xff; |
2dd8ba92 | 1140 | dev->class = class >> 8; /* upper 3 bytes */ |
1da177e4 | 1141 | |
2dd8ba92 YL |
1142 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n", |
1143 | dev->vendor, dev->device, dev->hdr_type, dev->class); | |
1da177e4 | 1144 | |
853346e4 YZ |
1145 | /* need to have dev->class ready */ |
1146 | dev->cfg_size = pci_cfg_space_size(dev); | |
1147 | ||
1da177e4 | 1148 | /* "Unknown power state" */ |
3fe9d19f | 1149 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
1150 | |
1151 | /* Early fixups, before probing the BARs */ | |
1152 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
1153 | /* device class may be changed after fixup */ |
1154 | class = dev->class >> 8; | |
1da177e4 LT |
1155 | |
1156 | switch (dev->hdr_type) { /* header type */ | |
1157 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
1158 | if (class == PCI_CLASS_BRIDGE_PCI) | |
1159 | goto bad; | |
1160 | pci_read_irq(dev); | |
1161 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
1162 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1163 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
1164 | |
1165 | /* | |
075eb9e3 BH |
1166 | * Do the ugly legacy mode stuff here rather than broken chip |
1167 | * quirk code. Legacy mode ATA controllers have fixed | |
1168 | * addresses. These are not always echoed in BAR0-3, and | |
1169 | * BAR0-3 in a few cases contain junk! | |
368c73d4 AC |
1170 | */ |
1171 | if (class == PCI_CLASS_STORAGE_IDE) { | |
1172 | u8 progif; | |
1173 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
1174 | if ((progif & 1) == 0) { | |
5bfa14ed BH |
1175 | region.start = 0x1F0; |
1176 | region.end = 0x1F7; | |
1177 | res = &dev->resource[0]; | |
1178 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1179 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1180 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n", |
1181 | res); | |
5bfa14ed BH |
1182 | region.start = 0x3F6; |
1183 | region.end = 0x3F6; | |
1184 | res = &dev->resource[1]; | |
1185 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1186 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1187 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n", |
1188 | res); | |
368c73d4 AC |
1189 | } |
1190 | if ((progif & 4) == 0) { | |
5bfa14ed BH |
1191 | region.start = 0x170; |
1192 | region.end = 0x177; | |
1193 | res = &dev->resource[2]; | |
1194 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1195 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1196 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n", |
1197 | res); | |
5bfa14ed BH |
1198 | region.start = 0x376; |
1199 | region.end = 0x376; | |
1200 | res = &dev->resource[3]; | |
1201 | res->flags = LEGACY_IO_RESOURCE; | |
fc279850 | 1202 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
075eb9e3 BH |
1203 | dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n", |
1204 | res); | |
368c73d4 AC |
1205 | } |
1206 | } | |
1da177e4 LT |
1207 | break; |
1208 | ||
1209 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1210 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1211 | goto bad; | |
1212 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1213 | decoding (i.e. transparent) bridge must have programming | |
f7625980 | 1214 | interface code of 0x01. */ |
3efd273b | 1215 | pci_read_irq(dev); |
1da177e4 LT |
1216 | dev->transparent = ((dev->class & 0xff) == 1); |
1217 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1218 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1219 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1220 | if (pos) { | |
1221 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1222 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1223 | } | |
1da177e4 LT |
1224 | break; |
1225 | ||
1226 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1227 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1228 | goto bad; | |
1229 | pci_read_irq(dev); | |
1230 | pci_read_bases(dev, 1, 0); | |
1231 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1232 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1233 | break; | |
1234 | ||
1235 | default: /* unknown header */ | |
227f0647 RD |
1236 | dev_err(&dev->dev, "unknown header type %02x, ignoring device\n", |
1237 | dev->hdr_type); | |
480b93b7 | 1238 | return -EIO; |
1da177e4 LT |
1239 | |
1240 | bad: | |
227f0647 RD |
1241 | dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n", |
1242 | dev->class, dev->hdr_type); | |
1da177e4 LT |
1243 | dev->class = PCI_CLASS_NOT_DEFINED; |
1244 | } | |
1245 | ||
1246 | /* We found a fine healthy device, go go go... */ | |
1247 | return 0; | |
1248 | } | |
1249 | ||
589fcc23 BH |
1250 | static struct hpp_type0 pci_default_type0 = { |
1251 | .revision = 1, | |
1252 | .cache_line_size = 8, | |
1253 | .latency_timer = 0x40, | |
1254 | .enable_serr = 0, | |
1255 | .enable_perr = 0, | |
1256 | }; | |
1257 | ||
1258 | static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp) | |
1259 | { | |
1260 | u16 pci_cmd, pci_bctl; | |
1261 | ||
c6285fc5 | 1262 | if (!hpp) |
589fcc23 | 1263 | hpp = &pci_default_type0; |
589fcc23 BH |
1264 | |
1265 | if (hpp->revision > 1) { | |
1266 | dev_warn(&dev->dev, | |
1267 | "PCI settings rev %d not supported; using defaults\n", | |
1268 | hpp->revision); | |
1269 | hpp = &pci_default_type0; | |
1270 | } | |
1271 | ||
1272 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); | |
1273 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer); | |
1274 | pci_read_config_word(dev, PCI_COMMAND, &pci_cmd); | |
1275 | if (hpp->enable_serr) | |
1276 | pci_cmd |= PCI_COMMAND_SERR; | |
589fcc23 BH |
1277 | if (hpp->enable_perr) |
1278 | pci_cmd |= PCI_COMMAND_PARITY; | |
589fcc23 BH |
1279 | pci_write_config_word(dev, PCI_COMMAND, pci_cmd); |
1280 | ||
1281 | /* Program bridge control value */ | |
1282 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
1283 | pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, | |
1284 | hpp->latency_timer); | |
1285 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl); | |
1286 | if (hpp->enable_serr) | |
1287 | pci_bctl |= PCI_BRIDGE_CTL_SERR; | |
589fcc23 BH |
1288 | if (hpp->enable_perr) |
1289 | pci_bctl |= PCI_BRIDGE_CTL_PARITY; | |
589fcc23 BH |
1290 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl); |
1291 | } | |
1292 | } | |
1293 | ||
1294 | static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp) | |
1295 | { | |
1296 | if (hpp) | |
1297 | dev_warn(&dev->dev, "PCI-X settings not supported\n"); | |
1298 | } | |
1299 | ||
1300 | static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp) | |
1301 | { | |
1302 | int pos; | |
1303 | u32 reg32; | |
1304 | ||
1305 | if (!hpp) | |
1306 | return; | |
1307 | ||
1308 | if (hpp->revision > 1) { | |
1309 | dev_warn(&dev->dev, "PCIe settings rev %d not supported\n", | |
1310 | hpp->revision); | |
1311 | return; | |
1312 | } | |
1313 | ||
302328c0 BH |
1314 | /* |
1315 | * Don't allow _HPX to change MPS or MRRS settings. We manage | |
1316 | * those to make sure they're consistent with the rest of the | |
1317 | * platform. | |
1318 | */ | |
1319 | hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD | | |
1320 | PCI_EXP_DEVCTL_READRQ; | |
1321 | hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD | | |
1322 | PCI_EXP_DEVCTL_READRQ); | |
1323 | ||
589fcc23 BH |
1324 | /* Initialize Device Control Register */ |
1325 | pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, | |
1326 | ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or); | |
1327 | ||
1328 | /* Initialize Link Control Register */ | |
1329 | if (dev->subordinate) | |
1330 | pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, | |
1331 | ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or); | |
1332 | ||
1333 | /* Find Advanced Error Reporting Enhanced Capability */ | |
1334 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); | |
1335 | if (!pos) | |
1336 | return; | |
1337 | ||
1338 | /* Initialize Uncorrectable Error Mask Register */ | |
1339 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); | |
1340 | reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; | |
1341 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); | |
1342 | ||
1343 | /* Initialize Uncorrectable Error Severity Register */ | |
1344 | pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); | |
1345 | reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; | |
1346 | pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); | |
1347 | ||
1348 | /* Initialize Correctable Error Mask Register */ | |
1349 | pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); | |
1350 | reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; | |
1351 | pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); | |
1352 | ||
1353 | /* Initialize Advanced Error Capabilities and Control Register */ | |
1354 | pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); | |
1355 | reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or; | |
1356 | pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); | |
1357 | ||
1358 | /* | |
1359 | * FIXME: The following two registers are not supported yet. | |
1360 | * | |
1361 | * o Secondary Uncorrectable Error Severity Register | |
1362 | * o Secondary Uncorrectable Error Mask Register | |
1363 | */ | |
1364 | } | |
1365 | ||
6cd33649 BH |
1366 | static void pci_configure_device(struct pci_dev *dev) |
1367 | { | |
1368 | struct hotplug_params hpp; | |
1369 | int ret; | |
1370 | ||
6cd33649 BH |
1371 | memset(&hpp, 0, sizeof(hpp)); |
1372 | ret = pci_get_hp_params(dev, &hpp); | |
1373 | if (ret) | |
1374 | return; | |
1375 | ||
1376 | program_hpp_type2(dev, hpp.t2); | |
1377 | program_hpp_type1(dev, hpp.t1); | |
1378 | program_hpp_type0(dev, hpp.t0); | |
1379 | } | |
1380 | ||
201de56e ZY |
1381 | static void pci_release_capabilities(struct pci_dev *dev) |
1382 | { | |
1383 | pci_vpd_release(dev); | |
d1b054da | 1384 | pci_iov_release(dev); |
f796841e | 1385 | pci_free_cap_save_buffers(dev); |
201de56e ZY |
1386 | } |
1387 | ||
1da177e4 LT |
1388 | /** |
1389 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1390 | * @dev: device that's been disconnected | |
1391 | * | |
1392 | * Will be called only by the device core when all users of this pci device are | |
1393 | * done. | |
1394 | */ | |
1395 | static void pci_release_dev(struct device *dev) | |
1396 | { | |
04480094 | 1397 | struct pci_dev *pci_dev; |
1da177e4 | 1398 | |
04480094 | 1399 | pci_dev = to_pci_dev(dev); |
201de56e | 1400 | pci_release_capabilities(pci_dev); |
98d9f30c | 1401 | pci_release_of_node(pci_dev); |
6ae32c53 | 1402 | pcibios_release_device(pci_dev); |
8b1fce04 | 1403 | pci_bus_put(pci_dev->bus); |
782a985d | 1404 | kfree(pci_dev->driver_override); |
1da177e4 LT |
1405 | kfree(pci_dev); |
1406 | } | |
1407 | ||
3c6e6ae7 | 1408 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus) |
65891215 ME |
1409 | { |
1410 | struct pci_dev *dev; | |
1411 | ||
1412 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1413 | if (!dev) | |
1414 | return NULL; | |
1415 | ||
65891215 | 1416 | INIT_LIST_HEAD(&dev->bus_list); |
88e7b167 | 1417 | dev->dev.type = &pci_dev_type; |
3c6e6ae7 | 1418 | dev->bus = pci_bus_get(bus); |
65891215 ME |
1419 | |
1420 | return dev; | |
1421 | } | |
3c6e6ae7 GZ |
1422 | EXPORT_SYMBOL(pci_alloc_dev); |
1423 | ||
efdc87da | 1424 | bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, |
3c78bc61 | 1425 | int crs_timeout) |
1da177e4 | 1426 | { |
1da177e4 LT |
1427 | int delay = 1; |
1428 | ||
efdc87da YL |
1429 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1430 | return false; | |
1da177e4 LT |
1431 | |
1432 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
efdc87da YL |
1433 | if (*l == 0xffffffff || *l == 0x00000000 || |
1434 | *l == 0x0000ffff || *l == 0xffff0000) | |
1435 | return false; | |
1da177e4 | 1436 | |
89665a6a RJ |
1437 | /* |
1438 | * Configuration Request Retry Status. Some root ports return the | |
1439 | * actual device ID instead of the synthetic ID (0xFFFF) required | |
1440 | * by the PCIe spec. Ignore the device ID and only check for | |
1441 | * (vendor id == 1). | |
1442 | */ | |
1443 | while ((*l & 0xffff) == 0x0001) { | |
efdc87da YL |
1444 | if (!crs_timeout) |
1445 | return false; | |
1446 | ||
1da177e4 LT |
1447 | msleep(delay); |
1448 | delay *= 2; | |
efdc87da YL |
1449 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) |
1450 | return false; | |
1da177e4 | 1451 | /* Card hasn't responded in 60 seconds? Must be stuck. */ |
efdc87da | 1452 | if (delay > crs_timeout) { |
227f0647 RD |
1453 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n", |
1454 | pci_domain_nr(bus), bus->number, PCI_SLOT(devfn), | |
1455 | PCI_FUNC(devfn)); | |
efdc87da | 1456 | return false; |
1da177e4 LT |
1457 | } |
1458 | } | |
1459 | ||
efdc87da YL |
1460 | return true; |
1461 | } | |
1462 | EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); | |
1463 | ||
1464 | /* | |
1465 | * Read the config data for a PCI device, sanity-check it | |
1466 | * and fill in the dev structure... | |
1467 | */ | |
1468 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) | |
1469 | { | |
1470 | struct pci_dev *dev; | |
1471 | u32 l; | |
1472 | ||
1473 | if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) | |
1474 | return NULL; | |
1475 | ||
8b1fce04 | 1476 | dev = pci_alloc_dev(bus); |
1da177e4 LT |
1477 | if (!dev) |
1478 | return NULL; | |
1479 | ||
1da177e4 | 1480 | dev->devfn = devfn; |
1da177e4 LT |
1481 | dev->vendor = l & 0xffff; |
1482 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1483 | |
98d9f30c BH |
1484 | pci_set_of_node(dev); |
1485 | ||
480b93b7 | 1486 | if (pci_setup_device(dev)) { |
8b1fce04 | 1487 | pci_bus_put(dev->bus); |
1da177e4 LT |
1488 | kfree(dev); |
1489 | return NULL; | |
1490 | } | |
1da177e4 LT |
1491 | |
1492 | return dev; | |
1493 | } | |
1494 | ||
201de56e ZY |
1495 | static void pci_init_capabilities(struct pci_dev *dev) |
1496 | { | |
1497 | /* MSI/MSI-X list */ | |
1498 | pci_msi_init_pci_dev(dev); | |
1499 | ||
63f4898a RW |
1500 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1501 | pci_allocate_cap_save_buffers(dev); | |
1502 | ||
201de56e ZY |
1503 | /* Power Management */ |
1504 | pci_pm_init(dev); | |
1505 | ||
1506 | /* Vital Product Data */ | |
1507 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1508 | |
1509 | /* Alternative Routing-ID Forwarding */ | |
31ab2476 | 1510 | pci_configure_ari(dev); |
d1b054da YZ |
1511 | |
1512 | /* Single Root I/O Virtualization */ | |
1513 | pci_iov_init(dev); | |
ae21ee65 AK |
1514 | |
1515 | /* Enable ACS P2P upstream forwarding */ | |
5d990b62 | 1516 | pci_enable_acs(dev); |
201de56e ZY |
1517 | } |
1518 | ||
96bde06a | 1519 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1520 | { |
4f535093 YL |
1521 | int ret; |
1522 | ||
6cd33649 BH |
1523 | pci_configure_device(dev); |
1524 | ||
cdb9b9f7 PM |
1525 | device_initialize(&dev->dev); |
1526 | dev->dev.release = pci_release_dev; | |
1da177e4 | 1527 | |
7629d19a | 1528 | set_dev_node(&dev->dev, pcibus_to_node(bus)); |
cdb9b9f7 | 1529 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1530 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1531 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1532 | |
4d57cdfa | 1533 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1534 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1535 | |
1da177e4 LT |
1536 | /* Fix up broken headers */ |
1537 | pci_fixup_device(pci_fixup_header, dev); | |
1538 | ||
2069ecfb YL |
1539 | /* moved out from quirk header fixup code */ |
1540 | pci_reassigndev_resource_alignment(dev); | |
1541 | ||
4b77b0a2 RW |
1542 | /* Clear the state_saved flag. */ |
1543 | dev->state_saved = false; | |
1544 | ||
201de56e ZY |
1545 | /* Initialize various capabilities */ |
1546 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1547 | |
1da177e4 LT |
1548 | /* |
1549 | * Add the device to our list of discovered devices | |
1550 | * and the bus list for fixup functions, etc. | |
1551 | */ | |
d71374da | 1552 | down_write(&pci_bus_sem); |
1da177e4 | 1553 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1554 | up_write(&pci_bus_sem); |
4f535093 | 1555 | |
4f535093 YL |
1556 | ret = pcibios_add_device(dev); |
1557 | WARN_ON(ret < 0); | |
1558 | ||
1559 | /* Notifier could use PCI capabilities */ | |
1560 | dev->match_driver = false; | |
1561 | ret = device_add(&dev->dev); | |
1562 | WARN_ON(ret < 0); | |
cdb9b9f7 PM |
1563 | } |
1564 | ||
10874f5a | 1565 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1566 | { |
1567 | struct pci_dev *dev; | |
1568 | ||
90bdb311 TP |
1569 | dev = pci_get_slot(bus, devfn); |
1570 | if (dev) { | |
1571 | pci_dev_put(dev); | |
1572 | return dev; | |
1573 | } | |
1574 | ||
cdb9b9f7 PM |
1575 | dev = pci_scan_device(bus, devfn); |
1576 | if (!dev) | |
1577 | return NULL; | |
1578 | ||
1579 | pci_device_add(dev, bus); | |
1da177e4 LT |
1580 | |
1581 | return dev; | |
1582 | } | |
b73e9687 | 1583 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 1584 | |
b1bd58e4 | 1585 | static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn) |
f07852d6 | 1586 | { |
b1bd58e4 YW |
1587 | int pos; |
1588 | u16 cap = 0; | |
1589 | unsigned next_fn; | |
4fb88c1a | 1590 | |
b1bd58e4 YW |
1591 | if (pci_ari_enabled(bus)) { |
1592 | if (!dev) | |
1593 | return 0; | |
1594 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
1595 | if (!pos) | |
1596 | return 0; | |
4fb88c1a | 1597 | |
b1bd58e4 YW |
1598 | pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); |
1599 | next_fn = PCI_ARI_CAP_NFN(cap); | |
1600 | if (next_fn <= fn) | |
1601 | return 0; /* protect against malformed list */ | |
f07852d6 | 1602 | |
b1bd58e4 YW |
1603 | return next_fn; |
1604 | } | |
1605 | ||
1606 | /* dev may be NULL for non-contiguous multifunction devices */ | |
1607 | if (!dev || dev->multifunction) | |
1608 | return (fn + 1) % 8; | |
f07852d6 | 1609 | |
f07852d6 MW |
1610 | return 0; |
1611 | } | |
1612 | ||
1613 | static int only_one_child(struct pci_bus *bus) | |
1614 | { | |
1615 | struct pci_dev *parent = bus->self; | |
284f5f9d | 1616 | |
f07852d6 MW |
1617 | if (!parent || !pci_is_pcie(parent)) |
1618 | return 0; | |
62f87c0e | 1619 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) |
284f5f9d | 1620 | return 1; |
62f87c0e | 1621 | if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM && |
284f5f9d | 1622 | !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) |
f07852d6 MW |
1623 | return 1; |
1624 | return 0; | |
1625 | } | |
1626 | ||
1da177e4 LT |
1627 | /** |
1628 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1629 | * @bus: PCI bus to scan | |
1630 | * @devfn: slot number to scan (must have zero function.) | |
1631 | * | |
1632 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1633 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1634 | * will not have is_added set. |
1b69dfc6 TP |
1635 | * |
1636 | * Returns the number of new devices found. | |
1da177e4 | 1637 | */ |
96bde06a | 1638 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1639 | { |
f07852d6 | 1640 | unsigned fn, nr = 0; |
1b69dfc6 | 1641 | struct pci_dev *dev; |
f07852d6 MW |
1642 | |
1643 | if (only_one_child(bus) && (devfn > 0)) | |
1644 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 1645 | |
1b69dfc6 | 1646 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
1647 | if (!dev) |
1648 | return 0; | |
1649 | if (!dev->is_added) | |
1b69dfc6 TP |
1650 | nr++; |
1651 | ||
b1bd58e4 | 1652 | for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) { |
f07852d6 MW |
1653 | dev = pci_scan_single_device(bus, devfn + fn); |
1654 | if (dev) { | |
1655 | if (!dev->is_added) | |
1656 | nr++; | |
1657 | dev->multifunction = 1; | |
1da177e4 LT |
1658 | } |
1659 | } | |
7d715a6c | 1660 | |
149e1637 SL |
1661 | /* only one slot has pcie device */ |
1662 | if (bus->self && nr) | |
7d715a6c SL |
1663 | pcie_aspm_init_link_state(bus->self); |
1664 | ||
1da177e4 LT |
1665 | return nr; |
1666 | } | |
b7fe9434 | 1667 | EXPORT_SYMBOL(pci_scan_slot); |
1da177e4 | 1668 | |
b03e7495 JM |
1669 | static int pcie_find_smpss(struct pci_dev *dev, void *data) |
1670 | { | |
1671 | u8 *smpss = data; | |
1672 | ||
1673 | if (!pci_is_pcie(dev)) | |
1674 | return 0; | |
1675 | ||
d4aa68f6 YW |
1676 | /* |
1677 | * We don't have a way to change MPS settings on devices that have | |
1678 | * drivers attached. A hot-added device might support only the minimum | |
1679 | * MPS setting (MPS=128). Therefore, if the fabric contains a bridge | |
1680 | * where devices may be hot-added, we limit the fabric MPS to 128 so | |
1681 | * hot-added devices will work correctly. | |
1682 | * | |
1683 | * However, if we hot-add a device to a slot directly below a Root | |
1684 | * Port, it's impossible for there to be other existing devices below | |
1685 | * the port. We don't limit the MPS in this case because we can | |
1686 | * reconfigure MPS on both the Root Port and the hot-added device, | |
1687 | * and there are no other devices involved. | |
1688 | * | |
1689 | * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. | |
b03e7495 | 1690 | */ |
d4aa68f6 YW |
1691 | if (dev->is_hotplug_bridge && |
1692 | pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) | |
b03e7495 JM |
1693 | *smpss = 0; |
1694 | ||
1695 | if (*smpss > dev->pcie_mpss) | |
1696 | *smpss = dev->pcie_mpss; | |
1697 | ||
1698 | return 0; | |
1699 | } | |
1700 | ||
1701 | static void pcie_write_mps(struct pci_dev *dev, int mps) | |
1702 | { | |
62f392ea | 1703 | int rc; |
b03e7495 JM |
1704 | |
1705 | if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { | |
62f392ea | 1706 | mps = 128 << dev->pcie_mpss; |
b03e7495 | 1707 | |
62f87c0e YW |
1708 | if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && |
1709 | dev->bus->self) | |
62f392ea | 1710 | /* For "Performance", the assumption is made that |
b03e7495 JM |
1711 | * downstream communication will never be larger than |
1712 | * the MRRS. So, the MPS only needs to be configured | |
1713 | * for the upstream communication. This being the case, | |
1714 | * walk from the top down and set the MPS of the child | |
1715 | * to that of the parent bus. | |
62f392ea JM |
1716 | * |
1717 | * Configure the device MPS with the smaller of the | |
1718 | * device MPSS or the bridge MPS (which is assumed to be | |
1719 | * properly configured at this point to the largest | |
1720 | * allowable MPS based on its parent bus). | |
b03e7495 | 1721 | */ |
62f392ea | 1722 | mps = min(mps, pcie_get_mps(dev->bus->self)); |
b03e7495 JM |
1723 | } |
1724 | ||
1725 | rc = pcie_set_mps(dev, mps); | |
1726 | if (rc) | |
1727 | dev_err(&dev->dev, "Failed attempting to set the MPS\n"); | |
1728 | } | |
1729 | ||
62f392ea | 1730 | static void pcie_write_mrrs(struct pci_dev *dev) |
b03e7495 | 1731 | { |
62f392ea | 1732 | int rc, mrrs; |
b03e7495 | 1733 | |
ed2888e9 JM |
1734 | /* In the "safe" case, do not configure the MRRS. There appear to be |
1735 | * issues with setting MRRS to 0 on a number of devices. | |
1736 | */ | |
ed2888e9 JM |
1737 | if (pcie_bus_config != PCIE_BUS_PERFORMANCE) |
1738 | return; | |
1739 | ||
ed2888e9 JM |
1740 | /* For Max performance, the MRRS must be set to the largest supported |
1741 | * value. However, it cannot be configured larger than the MPS the | |
62f392ea JM |
1742 | * device or the bus can support. This should already be properly |
1743 | * configured by a prior call to pcie_write_mps. | |
ed2888e9 | 1744 | */ |
62f392ea | 1745 | mrrs = pcie_get_mps(dev); |
b03e7495 JM |
1746 | |
1747 | /* MRRS is a R/W register. Invalid values can be written, but a | |
ed2888e9 | 1748 | * subsequent read will verify if the value is acceptable or not. |
b03e7495 JM |
1749 | * If the MRRS value provided is not acceptable (e.g., too large), |
1750 | * shrink the value until it is acceptable to the HW. | |
f7625980 | 1751 | */ |
b03e7495 JM |
1752 | while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { |
1753 | rc = pcie_set_readrq(dev, mrrs); | |
62f392ea JM |
1754 | if (!rc) |
1755 | break; | |
b03e7495 | 1756 | |
62f392ea | 1757 | dev_warn(&dev->dev, "Failed attempting to set the MRRS\n"); |
b03e7495 JM |
1758 | mrrs /= 2; |
1759 | } | |
62f392ea JM |
1760 | |
1761 | if (mrrs < 128) | |
227f0647 | 1762 | dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); |
b03e7495 JM |
1763 | } |
1764 | ||
5895af79 YW |
1765 | static void pcie_bus_detect_mps(struct pci_dev *dev) |
1766 | { | |
1767 | struct pci_dev *bridge = dev->bus->self; | |
1768 | int mps, p_mps; | |
1769 | ||
1770 | if (!bridge) | |
1771 | return; | |
1772 | ||
1773 | mps = pcie_get_mps(dev); | |
1774 | p_mps = pcie_get_mps(bridge); | |
1775 | ||
1776 | if (mps != p_mps) | |
1777 | dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", | |
1778 | mps, pci_name(bridge), p_mps); | |
1779 | } | |
1780 | ||
b03e7495 JM |
1781 | static int pcie_bus_configure_set(struct pci_dev *dev, void *data) |
1782 | { | |
a513a99a | 1783 | int mps, orig_mps; |
b03e7495 JM |
1784 | |
1785 | if (!pci_is_pcie(dev)) | |
1786 | return 0; | |
1787 | ||
5895af79 YW |
1788 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { |
1789 | pcie_bus_detect_mps(dev); | |
1790 | return 0; | |
1791 | } | |
1792 | ||
a513a99a JM |
1793 | mps = 128 << *(u8 *)data; |
1794 | orig_mps = pcie_get_mps(dev); | |
b03e7495 JM |
1795 | |
1796 | pcie_write_mps(dev, mps); | |
62f392ea | 1797 | pcie_write_mrrs(dev); |
b03e7495 | 1798 | |
227f0647 RD |
1799 | dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", |
1800 | pcie_get_mps(dev), 128 << dev->pcie_mpss, | |
a513a99a | 1801 | orig_mps, pcie_get_readrq(dev)); |
b03e7495 JM |
1802 | |
1803 | return 0; | |
1804 | } | |
1805 | ||
a513a99a | 1806 | /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down, |
b03e7495 JM |
1807 | * parents then children fashion. If this changes, then this code will not |
1808 | * work as designed. | |
1809 | */ | |
a58674ff | 1810 | void pcie_bus_configure_settings(struct pci_bus *bus) |
b03e7495 | 1811 | { |
1e358f94 | 1812 | u8 smpss = 0; |
b03e7495 | 1813 | |
a58674ff | 1814 | if (!bus->self) |
b03e7495 JM |
1815 | return; |
1816 | ||
b03e7495 | 1817 | if (!pci_is_pcie(bus->self)) |
5f39e670 JM |
1818 | return; |
1819 | ||
1820 | /* FIXME - Peer to peer DMA is possible, though the endpoint would need | |
3315472c | 1821 | * to be aware of the MPS of the destination. To work around this, |
5f39e670 JM |
1822 | * simply force the MPS of the entire system to the smallest possible. |
1823 | */ | |
1824 | if (pcie_bus_config == PCIE_BUS_PEER2PEER) | |
1825 | smpss = 0; | |
1826 | ||
b03e7495 | 1827 | if (pcie_bus_config == PCIE_BUS_SAFE) { |
a58674ff | 1828 | smpss = bus->self->pcie_mpss; |
5f39e670 | 1829 | |
b03e7495 JM |
1830 | pcie_find_smpss(bus->self, &smpss); |
1831 | pci_walk_bus(bus, pcie_find_smpss, &smpss); | |
1832 | } | |
1833 | ||
1834 | pcie_bus_configure_set(bus->self, &smpss); | |
1835 | pci_walk_bus(bus, pcie_bus_configure_set, &smpss); | |
1836 | } | |
debc3b77 | 1837 | EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); |
b03e7495 | 1838 | |
15856ad5 | 1839 | unsigned int pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 | 1840 | { |
b918c62e | 1841 | unsigned int devfn, pass, max = bus->busn_res.start; |
1da177e4 LT |
1842 | struct pci_dev *dev; |
1843 | ||
0207c356 | 1844 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
1845 | |
1846 | /* Go find them, Rover! */ | |
1847 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1848 | pci_scan_slot(bus, devfn); | |
1849 | ||
a28724b0 YZ |
1850 | /* Reserve buses for SR-IOV capability. */ |
1851 | max += pci_iov_bus_range(bus); | |
1852 | ||
1da177e4 LT |
1853 | /* |
1854 | * After performing arch-dependent fixup of the bus, look behind | |
1855 | * all PCI-to-PCI bridges on this bus. | |
1856 | */ | |
74710ded | 1857 | if (!bus->is_added) { |
0207c356 | 1858 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded | 1859 | pcibios_fixup_bus(bus); |
981cf9ea | 1860 | bus->is_added = 1; |
74710ded AC |
1861 | } |
1862 | ||
3c78bc61 | 1863 | for (pass = 0; pass < 2; pass++) |
1da177e4 | 1864 | list_for_each_entry(dev, &bus->devices, bus_list) { |
6788a51f | 1865 | if (pci_is_bridge(dev)) |
1da177e4 LT |
1866 | max = pci_scan_bridge(bus, dev, max, pass); |
1867 | } | |
1868 | ||
1869 | /* | |
1870 | * We've scanned the bus and so we know all about what's on | |
1871 | * the other side of any bridges that may be on this bus plus | |
1872 | * any devices. | |
1873 | * | |
1874 | * Return how far we've got finding sub-buses. | |
1875 | */ | |
0207c356 | 1876 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
1877 | return max; |
1878 | } | |
b7fe9434 | 1879 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1da177e4 | 1880 | |
6c0cc950 RW |
1881 | /** |
1882 | * pcibios_root_bridge_prepare - Platform-specific host bridge setup. | |
1883 | * @bridge: Host bridge to set up. | |
1884 | * | |
1885 | * Default empty implementation. Replace with an architecture-specific setup | |
1886 | * routine, if necessary. | |
1887 | */ | |
1888 | int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) | |
1889 | { | |
1890 | return 0; | |
1891 | } | |
1892 | ||
10a95747 JL |
1893 | void __weak pcibios_add_bus(struct pci_bus *bus) |
1894 | { | |
1895 | } | |
1896 | ||
1897 | void __weak pcibios_remove_bus(struct pci_bus *bus) | |
1898 | { | |
1899 | } | |
1900 | ||
166c6370 BH |
1901 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
1902 | struct pci_ops *ops, void *sysdata, struct list_head *resources) | |
1da177e4 | 1903 | { |
0efd5aab | 1904 | int error; |
5a21d70d | 1905 | struct pci_host_bridge *bridge; |
0207c356 | 1906 | struct pci_bus *b, *b2; |
0efd5aab | 1907 | struct pci_host_bridge_window *window, *n; |
a9d9f527 | 1908 | struct resource *res; |
0efd5aab BH |
1909 | resource_size_t offset; |
1910 | char bus_addr[64]; | |
1911 | char *fmt; | |
1da177e4 | 1912 | |
670ba0c8 | 1913 | b = pci_alloc_bus(NULL); |
1da177e4 | 1914 | if (!b) |
7b543663 | 1915 | return NULL; |
1da177e4 LT |
1916 | |
1917 | b->sysdata = sysdata; | |
1918 | b->ops = ops; | |
4f535093 | 1919 | b->number = b->busn_res.start = bus; |
670ba0c8 | 1920 | pci_bus_assign_domain_nr(b, parent); |
0207c356 BH |
1921 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
1922 | if (b2) { | |
1da177e4 | 1923 | /* If we already got to this bus through a different bridge, ignore it */ |
0207c356 | 1924 | dev_dbg(&b2->dev, "bus already known\n"); |
1da177e4 LT |
1925 | goto err_out; |
1926 | } | |
d71374da | 1927 | |
7b543663 YL |
1928 | bridge = pci_alloc_host_bridge(b); |
1929 | if (!bridge) | |
1930 | goto err_out; | |
1931 | ||
1932 | bridge->dev.parent = parent; | |
70efde2a | 1933 | bridge->dev.release = pci_release_host_bridge_dev; |
7b543663 | 1934 | dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
6c0cc950 | 1935 | error = pcibios_root_bridge_prepare(bridge); |
343df771 JL |
1936 | if (error) { |
1937 | kfree(bridge); | |
1938 | goto err_out; | |
1939 | } | |
6c0cc950 | 1940 | |
7b543663 | 1941 | error = device_register(&bridge->dev); |
343df771 JL |
1942 | if (error) { |
1943 | put_device(&bridge->dev); | |
1944 | goto err_out; | |
1945 | } | |
7b543663 | 1946 | b->bridge = get_device(&bridge->dev); |
a1e4d72c | 1947 | device_enable_async_suspend(b->bridge); |
98d9f30c | 1948 | pci_set_bus_of_node(b); |
1da177e4 | 1949 | |
0d358f22 YL |
1950 | if (!parent) |
1951 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1952 | ||
fd7d1ced GKH |
1953 | b->dev.class = &pcibus_class; |
1954 | b->dev.parent = b->bridge; | |
1a927133 | 1955 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1956 | error = device_register(&b->dev); |
1da177e4 LT |
1957 | if (error) |
1958 | goto class_dev_reg_err; | |
1da177e4 | 1959 | |
10a95747 JL |
1960 | pcibios_add_bus(b); |
1961 | ||
1da177e4 LT |
1962 | /* Create legacy_io and legacy_mem files for this bus */ |
1963 | pci_create_legacy_files(b); | |
1964 | ||
a9d9f527 BH |
1965 | if (parent) |
1966 | dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
1967 | else | |
1968 | printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev)); | |
1969 | ||
0efd5aab BH |
1970 | /* Add initial resources to the bus */ |
1971 | list_for_each_entry_safe(window, n, resources, list) { | |
1972 | list_move_tail(&window->list, &bridge->windows); | |
1973 | res = window->res; | |
1974 | offset = window->offset; | |
f848ffb1 YL |
1975 | if (res->flags & IORESOURCE_BUS) |
1976 | pci_bus_insert_busn_res(b, bus, res->end); | |
1977 | else | |
1978 | pci_bus_add_resource(b, res, 0); | |
0efd5aab BH |
1979 | if (offset) { |
1980 | if (resource_type(res) == IORESOURCE_IO) | |
1981 | fmt = " (bus address [%#06llx-%#06llx])"; | |
1982 | else | |
1983 | fmt = " (bus address [%#010llx-%#010llx])"; | |
1984 | snprintf(bus_addr, sizeof(bus_addr), fmt, | |
1985 | (unsigned long long) (res->start - offset), | |
1986 | (unsigned long long) (res->end - offset)); | |
1987 | } else | |
1988 | bus_addr[0] = '\0'; | |
1989 | dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr); | |
a9d9f527 BH |
1990 | } |
1991 | ||
a5390aa6 BH |
1992 | down_write(&pci_bus_sem); |
1993 | list_add_tail(&b->node, &pci_root_buses); | |
1994 | up_write(&pci_bus_sem); | |
1995 | ||
1da177e4 LT |
1996 | return b; |
1997 | ||
1da177e4 | 1998 | class_dev_reg_err: |
7b543663 YL |
1999 | put_device(&bridge->dev); |
2000 | device_unregister(&bridge->dev); | |
1da177e4 | 2001 | err_out: |
1da177e4 LT |
2002 | kfree(b); |
2003 | return NULL; | |
2004 | } | |
cdb9b9f7 | 2005 | |
98a35831 YL |
2006 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) |
2007 | { | |
2008 | struct resource *res = &b->busn_res; | |
2009 | struct resource *parent_res, *conflict; | |
2010 | ||
2011 | res->start = bus; | |
2012 | res->end = bus_max; | |
2013 | res->flags = IORESOURCE_BUS; | |
2014 | ||
2015 | if (!pci_is_root_bus(b)) | |
2016 | parent_res = &b->parent->busn_res; | |
2017 | else { | |
2018 | parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); | |
2019 | res->flags |= IORESOURCE_PCI_FIXED; | |
2020 | } | |
2021 | ||
ced04d15 | 2022 | conflict = request_resource_conflict(parent_res, res); |
98a35831 YL |
2023 | |
2024 | if (conflict) | |
2025 | dev_printk(KERN_DEBUG, &b->dev, | |
2026 | "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", | |
2027 | res, pci_is_root_bus(b) ? "domain " : "", | |
2028 | parent_res, conflict->name, conflict); | |
98a35831 YL |
2029 | |
2030 | return conflict == NULL; | |
2031 | } | |
2032 | ||
2033 | int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) | |
2034 | { | |
2035 | struct resource *res = &b->busn_res; | |
2036 | struct resource old_res = *res; | |
2037 | resource_size_t size; | |
2038 | int ret; | |
2039 | ||
2040 | if (res->start > bus_max) | |
2041 | return -EINVAL; | |
2042 | ||
2043 | size = bus_max - res->start + 1; | |
2044 | ret = adjust_resource(res, res->start, size); | |
2045 | dev_printk(KERN_DEBUG, &b->dev, | |
2046 | "busn_res: %pR end %s updated to %02x\n", | |
2047 | &old_res, ret ? "can not be" : "is", bus_max); | |
2048 | ||
2049 | if (!ret && !res->parent) | |
2050 | pci_bus_insert_busn_res(b, res->start, res->end); | |
2051 | ||
2052 | return ret; | |
2053 | } | |
2054 | ||
2055 | void pci_bus_release_busn_res(struct pci_bus *b) | |
2056 | { | |
2057 | struct resource *res = &b->busn_res; | |
2058 | int ret; | |
2059 | ||
2060 | if (!res->flags || !res->parent) | |
2061 | return; | |
2062 | ||
2063 | ret = release_resource(res); | |
2064 | dev_printk(KERN_DEBUG, &b->dev, | |
2065 | "busn_res: %pR %s released\n", | |
2066 | res, ret ? "can not be" : "is"); | |
2067 | } | |
2068 | ||
15856ad5 | 2069 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
a2ebb827 BH |
2070 | struct pci_ops *ops, void *sysdata, struct list_head *resources) |
2071 | { | |
4d99f524 YL |
2072 | struct pci_host_bridge_window *window; |
2073 | bool found = false; | |
a2ebb827 | 2074 | struct pci_bus *b; |
4d99f524 YL |
2075 | int max; |
2076 | ||
2077 | list_for_each_entry(window, resources, list) | |
2078 | if (window->res->flags & IORESOURCE_BUS) { | |
2079 | found = true; | |
2080 | break; | |
2081 | } | |
a2ebb827 BH |
2082 | |
2083 | b = pci_create_root_bus(parent, bus, ops, sysdata, resources); | |
2084 | if (!b) | |
2085 | return NULL; | |
2086 | ||
4d99f524 YL |
2087 | if (!found) { |
2088 | dev_info(&b->dev, | |
2089 | "No busn resource found for root bus, will use [bus %02x-ff]\n", | |
2090 | bus); | |
2091 | pci_bus_insert_busn_res(b, bus, 255); | |
2092 | } | |
2093 | ||
2094 | max = pci_scan_child_bus(b); | |
2095 | ||
2096 | if (!found) | |
2097 | pci_bus_update_busn_res_end(b, max); | |
2098 | ||
a2ebb827 BH |
2099 | pci_bus_add_devices(b); |
2100 | return b; | |
2101 | } | |
2102 | EXPORT_SYMBOL(pci_scan_root_bus); | |
2103 | ||
7e00fe2e | 2104 | /* Deprecated; use pci_scan_root_bus() instead */ |
15856ad5 | 2105 | struct pci_bus *pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
2106 | int bus, struct pci_ops *ops, void *sysdata) |
2107 | { | |
1e39ae9f | 2108 | LIST_HEAD(resources); |
cdb9b9f7 PM |
2109 | struct pci_bus *b; |
2110 | ||
1e39ae9f BH |
2111 | pci_add_resource(&resources, &ioport_resource); |
2112 | pci_add_resource(&resources, &iomem_resource); | |
857c3b66 | 2113 | pci_add_resource(&resources, &busn_resource); |
1e39ae9f | 2114 | b = pci_create_root_bus(parent, bus, ops, sysdata, &resources); |
cdb9b9f7 | 2115 | if (b) |
857c3b66 | 2116 | pci_scan_child_bus(b); |
1e39ae9f BH |
2117 | else |
2118 | pci_free_resource_list(&resources); | |
cdb9b9f7 PM |
2119 | return b; |
2120 | } | |
1da177e4 LT |
2121 | EXPORT_SYMBOL(pci_scan_bus_parented); |
2122 | ||
15856ad5 | 2123 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, |
de4b2f76 BH |
2124 | void *sysdata) |
2125 | { | |
2126 | LIST_HEAD(resources); | |
2127 | struct pci_bus *b; | |
2128 | ||
2129 | pci_add_resource(&resources, &ioport_resource); | |
2130 | pci_add_resource(&resources, &iomem_resource); | |
857c3b66 | 2131 | pci_add_resource(&resources, &busn_resource); |
de4b2f76 BH |
2132 | b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); |
2133 | if (b) { | |
857c3b66 | 2134 | pci_scan_child_bus(b); |
de4b2f76 BH |
2135 | pci_bus_add_devices(b); |
2136 | } else { | |
2137 | pci_free_resource_list(&resources); | |
2138 | } | |
2139 | return b; | |
2140 | } | |
2141 | EXPORT_SYMBOL(pci_scan_bus); | |
2142 | ||
2f320521 YL |
2143 | /** |
2144 | * pci_rescan_bus_bridge_resize - scan a PCI bus for devices. | |
2145 | * @bridge: PCI bridge for the bus to scan | |
2146 | * | |
2147 | * Scan a PCI bus and child buses for new devices, add them, | |
2148 | * and enable them, resizing bridge mmio/io resource if necessary | |
2149 | * and possible. The caller must ensure the child devices are already | |
2150 | * removed for resizing to occur. | |
2151 | * | |
2152 | * Returns the max number of subordinate bus discovered. | |
2153 | */ | |
10874f5a | 2154 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) |
2f320521 YL |
2155 | { |
2156 | unsigned int max; | |
2157 | struct pci_bus *bus = bridge->subordinate; | |
2158 | ||
2159 | max = pci_scan_child_bus(bus); | |
2160 | ||
2161 | pci_assign_unassigned_bridge_resources(bridge); | |
2162 | ||
2163 | pci_bus_add_devices(bus); | |
2164 | ||
2165 | return max; | |
2166 | } | |
2167 | ||
a5213a31 YL |
2168 | /** |
2169 | * pci_rescan_bus - scan a PCI bus for devices. | |
2170 | * @bus: PCI bus to scan | |
2171 | * | |
2172 | * Scan a PCI bus and child buses for new devices, adds them, | |
2173 | * and enables them. | |
2174 | * | |
2175 | * Returns the max number of subordinate bus discovered. | |
2176 | */ | |
10874f5a | 2177 | unsigned int pci_rescan_bus(struct pci_bus *bus) |
a5213a31 YL |
2178 | { |
2179 | unsigned int max; | |
2180 | ||
2181 | max = pci_scan_child_bus(bus); | |
2182 | pci_assign_unassigned_bus_resources(bus); | |
2183 | pci_bus_add_devices(bus); | |
2184 | ||
2185 | return max; | |
2186 | } | |
2187 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
2188 | ||
9d16947b RW |
2189 | /* |
2190 | * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal | |
2191 | * routines should always be executed under this mutex. | |
2192 | */ | |
2193 | static DEFINE_MUTEX(pci_rescan_remove_lock); | |
2194 | ||
2195 | void pci_lock_rescan_remove(void) | |
2196 | { | |
2197 | mutex_lock(&pci_rescan_remove_lock); | |
2198 | } | |
2199 | EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); | |
2200 | ||
2201 | void pci_unlock_rescan_remove(void) | |
2202 | { | |
2203 | mutex_unlock(&pci_rescan_remove_lock); | |
2204 | } | |
2205 | EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); | |
2206 | ||
3c78bc61 RD |
2207 | static int __init pci_sort_bf_cmp(const struct device *d_a, |
2208 | const struct device *d_b) | |
6b4b78fe | 2209 | { |
99178b03 GKH |
2210 | const struct pci_dev *a = to_pci_dev(d_a); |
2211 | const struct pci_dev *b = to_pci_dev(d_b); | |
2212 | ||
6b4b78fe MD |
2213 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
2214 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
2215 | ||
2216 | if (a->bus->number < b->bus->number) return -1; | |
2217 | else if (a->bus->number > b->bus->number) return 1; | |
2218 | ||
2219 | if (a->devfn < b->devfn) return -1; | |
2220 | else if (a->devfn > b->devfn) return 1; | |
2221 | ||
2222 | return 0; | |
2223 | } | |
2224 | ||
5ff580c1 | 2225 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 2226 | { |
99178b03 | 2227 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 2228 | } |