Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * probe.c - PCI detection and setup code | |
3 | */ | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/delay.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/pci.h> | |
9 | #include <linux/slab.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/cpumask.h> | |
7d715a6c | 12 | #include <linux/pci-aspm.h> |
bc56b9e0 | 13 | #include "pci.h" |
1da177e4 LT |
14 | |
15 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ | |
16 | #define CARDBUS_RESERVE_BUSNR 3 | |
1da177e4 LT |
17 | |
18 | /* Ugh. Need to stop exporting this to modules. */ | |
19 | LIST_HEAD(pci_root_buses); | |
20 | EXPORT_SYMBOL(pci_root_buses); | |
21 | ||
70308923 GKH |
22 | |
23 | static int find_anything(struct device *dev, void *data) | |
24 | { | |
25 | return 1; | |
26 | } | |
1da177e4 | 27 | |
ed4aaadb ZY |
28 | /* |
29 | * Some device drivers need know if pci is initiated. | |
30 | * Basically, we think pci is not initiated when there | |
70308923 | 31 | * is no device to be found on the pci_bus_type. |
ed4aaadb ZY |
32 | */ |
33 | int no_pci_devices(void) | |
34 | { | |
70308923 GKH |
35 | struct device *dev; |
36 | int no_devices; | |
ed4aaadb | 37 | |
70308923 GKH |
38 | dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything); |
39 | no_devices = (dev == NULL); | |
40 | put_device(dev); | |
41 | return no_devices; | |
42 | } | |
ed4aaadb ZY |
43 | EXPORT_SYMBOL(no_pci_devices); |
44 | ||
1da177e4 LT |
45 | /* |
46 | * PCI Bus Class | |
47 | */ | |
fd7d1ced | 48 | static void release_pcibus_dev(struct device *dev) |
1da177e4 | 49 | { |
fd7d1ced | 50 | struct pci_bus *pci_bus = to_pci_bus(dev); |
1da177e4 LT |
51 | |
52 | if (pci_bus->bridge) | |
53 | put_device(pci_bus->bridge); | |
2fe2abf8 | 54 | pci_bus_remove_resources(pci_bus); |
1da177e4 LT |
55 | kfree(pci_bus); |
56 | } | |
57 | ||
58 | static struct class pcibus_class = { | |
59 | .name = "pci_bus", | |
fd7d1ced | 60 | .dev_release = &release_pcibus_dev, |
b9d320fc | 61 | .dev_attrs = pcibus_dev_attrs, |
1da177e4 LT |
62 | }; |
63 | ||
64 | static int __init pcibus_class_init(void) | |
65 | { | |
66 | return class_register(&pcibus_class); | |
67 | } | |
68 | postcore_initcall(pcibus_class_init); | |
69 | ||
70 | /* | |
71 | * Translate the low bits of the PCI base | |
72 | * to the resource type | |
73 | */ | |
74 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) | |
75 | { | |
76 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) | |
77 | return IORESOURCE_IO; | |
78 | ||
79 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) | |
80 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
81 | ||
82 | return IORESOURCE_MEM; | |
83 | } | |
84 | ||
6ac665c6 | 85 | static u64 pci_size(u64 base, u64 maxbase, u64 mask) |
1da177e4 | 86 | { |
6ac665c6 | 87 | u64 size = mask & maxbase; /* Find the significant bits */ |
1da177e4 LT |
88 | if (!size) |
89 | return 0; | |
90 | ||
91 | /* Get the lowest of them to find the decode size, and | |
92 | from that the extent. */ | |
93 | size = (size & ~(size-1)) - 1; | |
94 | ||
95 | /* base == maxbase can be valid only if the BAR has | |
96 | already been programmed with all 1s. */ | |
97 | if (base == maxbase && ((base | size) & mask) != mask) | |
98 | return 0; | |
99 | ||
100 | return size; | |
101 | } | |
102 | ||
8d6a6a47 BH |
103 | static inline enum pci_bar_type decode_bar(struct pci_dev *dev, |
104 | struct resource *res, u32 bar) | |
6ac665c6 | 105 | { |
8d6a6a47 BH |
106 | u32 mem_type; |
107 | ||
6ac665c6 MW |
108 | if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { |
109 | res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; | |
110 | return pci_bar_io; | |
111 | } | |
07eddf3d | 112 | |
6ac665c6 | 113 | res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; |
07eddf3d | 114 | |
8d6a6a47 BH |
115 | mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; |
116 | switch (mem_type) { | |
117 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
118 | break; | |
119 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
120 | dev_info(&dev->dev, "1M mem BAR treated as 32-bit BAR\n"); | |
121 | break; | |
122 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
6ac665c6 | 123 | return pci_bar_mem64; |
8d6a6a47 BH |
124 | default: |
125 | dev_warn(&dev->dev, | |
126 | "mem unknown type %x treated as 32-bit BAR\n", | |
127 | mem_type); | |
128 | break; | |
129 | } | |
6ac665c6 | 130 | return pci_bar_mem32; |
07eddf3d YL |
131 | } |
132 | ||
0b400c7e YZ |
133 | /** |
134 | * pci_read_base - read a PCI BAR | |
135 | * @dev: the PCI device | |
136 | * @type: type of the BAR | |
137 | * @res: resource buffer to be filled in | |
138 | * @pos: BAR position in the config space | |
139 | * | |
140 | * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. | |
6ac665c6 | 141 | */ |
0b400c7e | 142 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
6ac665c6 | 143 | struct resource *res, unsigned int pos) |
07eddf3d | 144 | { |
6ac665c6 | 145 | u32 l, sz, mask; |
253d2e54 | 146 | u16 orig_cmd; |
6ac665c6 | 147 | |
1ed67439 | 148 | mask = type ? PCI_ROM_ADDRESS_MASK : ~0; |
6ac665c6 | 149 | |
253d2e54 JP |
150 | if (!dev->mmio_always_on) { |
151 | pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); | |
152 | pci_write_config_word(dev, PCI_COMMAND, | |
153 | orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); | |
154 | } | |
155 | ||
6ac665c6 MW |
156 | res->name = pci_name(dev); |
157 | ||
158 | pci_read_config_dword(dev, pos, &l); | |
1ed67439 | 159 | pci_write_config_dword(dev, pos, l | mask); |
6ac665c6 MW |
160 | pci_read_config_dword(dev, pos, &sz); |
161 | pci_write_config_dword(dev, pos, l); | |
162 | ||
253d2e54 JP |
163 | if (!dev->mmio_always_on) |
164 | pci_write_config_word(dev, PCI_COMMAND, orig_cmd); | |
165 | ||
6ac665c6 MW |
166 | /* |
167 | * All bits set in sz means the device isn't working properly. | |
45aa23b4 BH |
168 | * If the BAR isn't implemented, all bits must be 0. If it's a |
169 | * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit | |
170 | * 1 must be clear. | |
6ac665c6 | 171 | */ |
45aa23b4 | 172 | if (!sz || sz == 0xffffffff) |
6ac665c6 MW |
173 | goto fail; |
174 | ||
175 | /* | |
176 | * I don't know how l can have all bits set. Copied from old code. | |
177 | * Maybe it fixes a bug on some ancient platform. | |
178 | */ | |
179 | if (l == 0xffffffff) | |
180 | l = 0; | |
181 | ||
182 | if (type == pci_bar_unknown) { | |
8d6a6a47 | 183 | type = decode_bar(dev, res, l); |
6ac665c6 MW |
184 | res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN; |
185 | if (type == pci_bar_io) { | |
186 | l &= PCI_BASE_ADDRESS_IO_MASK; | |
5aceca9d | 187 | mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT; |
6ac665c6 MW |
188 | } else { |
189 | l &= PCI_BASE_ADDRESS_MEM_MASK; | |
190 | mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; | |
191 | } | |
192 | } else { | |
193 | res->flags |= (l & IORESOURCE_ROM_ENABLE); | |
194 | l &= PCI_ROM_ADDRESS_MASK; | |
195 | mask = (u32)PCI_ROM_ADDRESS_MASK; | |
196 | } | |
197 | ||
198 | if (type == pci_bar_mem64) { | |
199 | u64 l64 = l; | |
200 | u64 sz64 = sz; | |
201 | u64 mask64 = mask | (u64)~0 << 32; | |
202 | ||
203 | pci_read_config_dword(dev, pos + 4, &l); | |
204 | pci_write_config_dword(dev, pos + 4, ~0); | |
205 | pci_read_config_dword(dev, pos + 4, &sz); | |
206 | pci_write_config_dword(dev, pos + 4, l); | |
207 | ||
208 | l64 |= ((u64)l << 32); | |
209 | sz64 |= ((u64)sz << 32); | |
210 | ||
211 | sz64 = pci_size(l64, sz64, mask64); | |
212 | ||
213 | if (!sz64) | |
214 | goto fail; | |
215 | ||
cc5499c3 | 216 | if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) { |
865df576 BH |
217 | dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", |
218 | pos); | |
6ac665c6 | 219 | goto fail; |
c7dabef8 BH |
220 | } |
221 | ||
222 | res->flags |= IORESOURCE_MEM_64; | |
223 | if ((sizeof(resource_size_t) < 8) && l) { | |
6ac665c6 MW |
224 | /* Address above 32-bit boundary; disable the BAR */ |
225 | pci_write_config_dword(dev, pos, 0); | |
226 | pci_write_config_dword(dev, pos + 4, 0); | |
227 | res->start = 0; | |
228 | res->end = sz64; | |
229 | } else { | |
230 | res->start = l64; | |
231 | res->end = l64 + sz64; | |
c7dabef8 | 232 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", |
a369c791 | 233 | pos, res); |
6ac665c6 MW |
234 | } |
235 | } else { | |
45aa23b4 | 236 | sz = pci_size(l, sz, mask); |
6ac665c6 | 237 | |
45aa23b4 | 238 | if (!sz) |
6ac665c6 MW |
239 | goto fail; |
240 | ||
241 | res->start = l; | |
45aa23b4 | 242 | res->end = l + sz; |
f393d9b1 | 243 | |
c7dabef8 | 244 | dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res); |
6ac665c6 MW |
245 | } |
246 | ||
247 | out: | |
248 | return (type == pci_bar_mem64) ? 1 : 0; | |
249 | fail: | |
250 | res->flags = 0; | |
251 | goto out; | |
07eddf3d YL |
252 | } |
253 | ||
1da177e4 LT |
254 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
255 | { | |
6ac665c6 | 256 | unsigned int pos, reg; |
07eddf3d | 257 | |
6ac665c6 MW |
258 | for (pos = 0; pos < howmany; pos++) { |
259 | struct resource *res = &dev->resource[pos]; | |
1da177e4 | 260 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
6ac665c6 | 261 | pos += __pci_read_base(dev, pci_bar_unknown, res, reg); |
1da177e4 | 262 | } |
6ac665c6 | 263 | |
1da177e4 | 264 | if (rom) { |
6ac665c6 | 265 | struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; |
1da177e4 | 266 | dev->rom_base_reg = rom; |
6ac665c6 MW |
267 | res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | |
268 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE | | |
269 | IORESOURCE_SIZEALIGN; | |
270 | __pci_read_base(dev, pci_bar_mem32, res, rom); | |
1da177e4 LT |
271 | } |
272 | } | |
273 | ||
fa27b2d1 | 274 | static void __devinit pci_read_bridge_io(struct pci_bus *child) |
1da177e4 LT |
275 | { |
276 | struct pci_dev *dev = child->self; | |
277 | u8 io_base_lo, io_limit_lo; | |
1da177e4 LT |
278 | unsigned long base, limit; |
279 | struct resource *res; | |
1da177e4 | 280 | |
1da177e4 LT |
281 | res = child->resource[0]; |
282 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
283 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
284 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
285 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
286 | ||
287 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
288 | u16 io_base_hi, io_limit_hi; | |
289 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
290 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
291 | base |= (io_base_hi << 16); | |
292 | limit |= (io_limit_hi << 16); | |
293 | } | |
294 | ||
cd81e1ea | 295 | if (base && base <= limit) { |
1da177e4 | 296 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
9d265124 DY |
297 | if (!res->start) |
298 | res->start = base; | |
299 | if (!res->end) | |
300 | res->end = limit + 0xfff; | |
c7dabef8 | 301 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
cd81e1ea YL |
302 | } else { |
303 | dev_printk(KERN_DEBUG, &dev->dev, | |
7b8ff6da | 304 | " bridge window [io %#06lx-%#06lx] (disabled)\n", |
cd81e1ea | 305 | base, limit); |
1da177e4 | 306 | } |
fa27b2d1 BH |
307 | } |
308 | ||
309 | static void __devinit pci_read_bridge_mmio(struct pci_bus *child) | |
310 | { | |
311 | struct pci_dev *dev = child->self; | |
312 | u16 mem_base_lo, mem_limit_lo; | |
313 | unsigned long base, limit; | |
314 | struct resource *res; | |
1da177e4 LT |
315 | |
316 | res = child->resource[1]; | |
317 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
318 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
319 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
320 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
cd81e1ea | 321 | if (base && base <= limit) { |
1da177e4 LT |
322 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
323 | res->start = base; | |
324 | res->end = limit + 0xfffff; | |
c7dabef8 | 325 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
cd81e1ea YL |
326 | } else { |
327 | dev_printk(KERN_DEBUG, &dev->dev, | |
7b8ff6da | 328 | " bridge window [mem %#010lx-%#010lx] (disabled)\n", |
cd81e1ea | 329 | base, limit + 0xfffff); |
1da177e4 | 330 | } |
fa27b2d1 BH |
331 | } |
332 | ||
333 | static void __devinit pci_read_bridge_mmio_pref(struct pci_bus *child) | |
334 | { | |
335 | struct pci_dev *dev = child->self; | |
336 | u16 mem_base_lo, mem_limit_lo; | |
337 | unsigned long base, limit; | |
338 | struct resource *res; | |
1da177e4 LT |
339 | |
340 | res = child->resource[2]; | |
341 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
342 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
343 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
344 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
345 | ||
346 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
347 | u32 mem_base_hi, mem_limit_hi; | |
348 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
349 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
350 | ||
351 | /* | |
352 | * Some bridges set the base > limit by default, and some | |
353 | * (broken) BIOSes do not initialize them. If we find | |
354 | * this, just assume they are not being used. | |
355 | */ | |
356 | if (mem_base_hi <= mem_limit_hi) { | |
357 | #if BITS_PER_LONG == 64 | |
358 | base |= ((long) mem_base_hi) << 32; | |
359 | limit |= ((long) mem_limit_hi) << 32; | |
360 | #else | |
361 | if (mem_base_hi || mem_limit_hi) { | |
80ccba11 BH |
362 | dev_err(&dev->dev, "can't handle 64-bit " |
363 | "address space for bridge\n"); | |
1da177e4 LT |
364 | return; |
365 | } | |
366 | #endif | |
367 | } | |
368 | } | |
cd81e1ea | 369 | if (base && base <= limit) { |
1f82de10 YL |
370 | res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | |
371 | IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
372 | if (res->flags & PCI_PREF_RANGE_TYPE_64) | |
373 | res->flags |= IORESOURCE_MEM_64; | |
1da177e4 LT |
374 | res->start = base; |
375 | res->end = limit + 0xfffff; | |
c7dabef8 | 376 | dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res); |
cd81e1ea YL |
377 | } else { |
378 | dev_printk(KERN_DEBUG, &dev->dev, | |
7b8ff6da | 379 | " bridge window [mem %#010lx-%#010lx pref] (disabled)\n", |
cd81e1ea | 380 | base, limit + 0xfffff); |
1da177e4 LT |
381 | } |
382 | } | |
383 | ||
fa27b2d1 BH |
384 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
385 | { | |
386 | struct pci_dev *dev = child->self; | |
2fe2abf8 | 387 | struct resource *res; |
fa27b2d1 BH |
388 | int i; |
389 | ||
390 | if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ | |
391 | return; | |
392 | ||
393 | dev_info(&dev->dev, "PCI bridge to [bus %02x-%02x]%s\n", | |
394 | child->secondary, child->subordinate, | |
395 | dev->transparent ? " (subtractive decode)" : ""); | |
396 | ||
2fe2abf8 BH |
397 | pci_bus_remove_resources(child); |
398 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) | |
399 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; | |
400 | ||
fa27b2d1 BH |
401 | pci_read_bridge_io(child); |
402 | pci_read_bridge_mmio(child); | |
403 | pci_read_bridge_mmio_pref(child); | |
2adf7516 BH |
404 | |
405 | if (dev->transparent) { | |
2fe2abf8 BH |
406 | pci_bus_for_each_resource(child->parent, res, i) { |
407 | if (res) { | |
408 | pci_bus_add_resource(child, res, | |
409 | PCI_SUBTRACTIVE_DECODE); | |
2adf7516 BH |
410 | dev_printk(KERN_DEBUG, &dev->dev, |
411 | " bridge window %pR (subtractive decode)\n", | |
2fe2abf8 BH |
412 | res); |
413 | } | |
2adf7516 BH |
414 | } |
415 | } | |
fa27b2d1 BH |
416 | } |
417 | ||
96bde06a | 418 | static struct pci_bus * pci_alloc_bus(void) |
1da177e4 LT |
419 | { |
420 | struct pci_bus *b; | |
421 | ||
f5afe806 | 422 | b = kzalloc(sizeof(*b), GFP_KERNEL); |
1da177e4 | 423 | if (b) { |
1da177e4 LT |
424 | INIT_LIST_HEAD(&b->node); |
425 | INIT_LIST_HEAD(&b->children); | |
426 | INIT_LIST_HEAD(&b->devices); | |
f46753c5 | 427 | INIT_LIST_HEAD(&b->slots); |
2fe2abf8 | 428 | INIT_LIST_HEAD(&b->resources); |
3749c51a MW |
429 | b->max_bus_speed = PCI_SPEED_UNKNOWN; |
430 | b->cur_bus_speed = PCI_SPEED_UNKNOWN; | |
1da177e4 LT |
431 | } |
432 | return b; | |
433 | } | |
434 | ||
9be60ca0 MW |
435 | static unsigned char pcix_bus_speed[] = { |
436 | PCI_SPEED_UNKNOWN, /* 0 */ | |
437 | PCI_SPEED_66MHz_PCIX, /* 1 */ | |
438 | PCI_SPEED_100MHz_PCIX, /* 2 */ | |
439 | PCI_SPEED_133MHz_PCIX, /* 3 */ | |
440 | PCI_SPEED_UNKNOWN, /* 4 */ | |
441 | PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ | |
442 | PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ | |
443 | PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ | |
444 | PCI_SPEED_UNKNOWN, /* 8 */ | |
445 | PCI_SPEED_66MHz_PCIX_266, /* 9 */ | |
446 | PCI_SPEED_100MHz_PCIX_266, /* A */ | |
447 | PCI_SPEED_133MHz_PCIX_266, /* B */ | |
448 | PCI_SPEED_UNKNOWN, /* C */ | |
449 | PCI_SPEED_66MHz_PCIX_533, /* D */ | |
450 | PCI_SPEED_100MHz_PCIX_533, /* E */ | |
451 | PCI_SPEED_133MHz_PCIX_533 /* F */ | |
452 | }; | |
453 | ||
3749c51a MW |
454 | static unsigned char pcie_link_speed[] = { |
455 | PCI_SPEED_UNKNOWN, /* 0 */ | |
456 | PCIE_SPEED_2_5GT, /* 1 */ | |
457 | PCIE_SPEED_5_0GT, /* 2 */ | |
9dfd97fe | 458 | PCIE_SPEED_8_0GT, /* 3 */ |
3749c51a MW |
459 | PCI_SPEED_UNKNOWN, /* 4 */ |
460 | PCI_SPEED_UNKNOWN, /* 5 */ | |
461 | PCI_SPEED_UNKNOWN, /* 6 */ | |
462 | PCI_SPEED_UNKNOWN, /* 7 */ | |
463 | PCI_SPEED_UNKNOWN, /* 8 */ | |
464 | PCI_SPEED_UNKNOWN, /* 9 */ | |
465 | PCI_SPEED_UNKNOWN, /* A */ | |
466 | PCI_SPEED_UNKNOWN, /* B */ | |
467 | PCI_SPEED_UNKNOWN, /* C */ | |
468 | PCI_SPEED_UNKNOWN, /* D */ | |
469 | PCI_SPEED_UNKNOWN, /* E */ | |
470 | PCI_SPEED_UNKNOWN /* F */ | |
471 | }; | |
472 | ||
473 | void pcie_update_link_speed(struct pci_bus *bus, u16 linksta) | |
474 | { | |
475 | bus->cur_bus_speed = pcie_link_speed[linksta & 0xf]; | |
476 | } | |
477 | EXPORT_SYMBOL_GPL(pcie_update_link_speed); | |
478 | ||
45b4cdd5 MW |
479 | static unsigned char agp_speeds[] = { |
480 | AGP_UNKNOWN, | |
481 | AGP_1X, | |
482 | AGP_2X, | |
483 | AGP_4X, | |
484 | AGP_8X | |
485 | }; | |
486 | ||
487 | static enum pci_bus_speed agp_speed(int agp3, int agpstat) | |
488 | { | |
489 | int index = 0; | |
490 | ||
491 | if (agpstat & 4) | |
492 | index = 3; | |
493 | else if (agpstat & 2) | |
494 | index = 2; | |
495 | else if (agpstat & 1) | |
496 | index = 1; | |
497 | else | |
498 | goto out; | |
499 | ||
500 | if (agp3) { | |
501 | index += 2; | |
502 | if (index == 5) | |
503 | index = 0; | |
504 | } | |
505 | ||
506 | out: | |
507 | return agp_speeds[index]; | |
508 | } | |
509 | ||
510 | ||
9be60ca0 MW |
511 | static void pci_set_bus_speed(struct pci_bus *bus) |
512 | { | |
513 | struct pci_dev *bridge = bus->self; | |
514 | int pos; | |
515 | ||
45b4cdd5 MW |
516 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); |
517 | if (!pos) | |
518 | pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); | |
519 | if (pos) { | |
520 | u32 agpstat, agpcmd; | |
521 | ||
522 | pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); | |
523 | bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); | |
524 | ||
525 | pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); | |
526 | bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); | |
527 | } | |
528 | ||
9be60ca0 MW |
529 | pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); |
530 | if (pos) { | |
531 | u16 status; | |
532 | enum pci_bus_speed max; | |
533 | pci_read_config_word(bridge, pos + 2, &status); | |
534 | ||
535 | if (status & 0x8000) { | |
536 | max = PCI_SPEED_133MHz_PCIX_533; | |
537 | } else if (status & 0x4000) { | |
538 | max = PCI_SPEED_133MHz_PCIX_266; | |
539 | } else if (status & 0x0002) { | |
540 | if (((status >> 12) & 0x3) == 2) { | |
541 | max = PCI_SPEED_133MHz_PCIX_ECC; | |
542 | } else { | |
543 | max = PCI_SPEED_133MHz_PCIX; | |
544 | } | |
545 | } else { | |
546 | max = PCI_SPEED_66MHz_PCIX; | |
547 | } | |
548 | ||
549 | bus->max_bus_speed = max; | |
550 | bus->cur_bus_speed = pcix_bus_speed[(status >> 6) & 0xf]; | |
551 | ||
552 | return; | |
553 | } | |
554 | ||
555 | pos = pci_find_capability(bridge, PCI_CAP_ID_EXP); | |
556 | if (pos) { | |
557 | u32 linkcap; | |
558 | u16 linksta; | |
559 | ||
560 | pci_read_config_dword(bridge, pos + PCI_EXP_LNKCAP, &linkcap); | |
561 | bus->max_bus_speed = pcie_link_speed[linkcap & 0xf]; | |
562 | ||
563 | pci_read_config_word(bridge, pos + PCI_EXP_LNKSTA, &linksta); | |
564 | pcie_update_link_speed(bus, linksta); | |
565 | } | |
566 | } | |
567 | ||
568 | ||
cbd4e055 AB |
569 | static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, |
570 | struct pci_dev *bridge, int busnr) | |
1da177e4 LT |
571 | { |
572 | struct pci_bus *child; | |
573 | int i; | |
574 | ||
575 | /* | |
576 | * Allocate a new bus, and inherit stuff from the parent.. | |
577 | */ | |
578 | child = pci_alloc_bus(); | |
579 | if (!child) | |
580 | return NULL; | |
581 | ||
1da177e4 LT |
582 | child->parent = parent; |
583 | child->ops = parent->ops; | |
584 | child->sysdata = parent->sysdata; | |
6e325a62 | 585 | child->bus_flags = parent->bus_flags; |
1da177e4 | 586 | |
fd7d1ced GKH |
587 | /* initialize some portions of the bus device, but don't register it |
588 | * now as the parent is not properly set up yet. This device will get | |
589 | * registered later in pci_bus_add_devices() | |
590 | */ | |
591 | child->dev.class = &pcibus_class; | |
1a927133 | 592 | dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); |
1da177e4 LT |
593 | |
594 | /* | |
595 | * Set up the primary, secondary and subordinate | |
596 | * bus numbers. | |
597 | */ | |
598 | child->number = child->secondary = busnr; | |
599 | child->primary = parent->secondary; | |
600 | child->subordinate = 0xff; | |
601 | ||
3789fa8a YZ |
602 | if (!bridge) |
603 | return child; | |
604 | ||
605 | child->self = bridge; | |
606 | child->bridge = get_device(&bridge->dev); | |
607 | ||
9be60ca0 MW |
608 | pci_set_bus_speed(child); |
609 | ||
1da177e4 | 610 | /* Set up default resource pointers and names.. */ |
fde09c6d | 611 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
1da177e4 LT |
612 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
613 | child->resource[i]->name = child->name; | |
614 | } | |
615 | bridge->subordinate = child; | |
616 | ||
617 | return child; | |
618 | } | |
619 | ||
451124a7 | 620 | struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
1da177e4 LT |
621 | { |
622 | struct pci_bus *child; | |
623 | ||
624 | child = pci_alloc_child_bus(parent, dev, busnr); | |
e4ea9bb7 | 625 | if (child) { |
d71374da | 626 | down_write(&pci_bus_sem); |
1da177e4 | 627 | list_add_tail(&child->node, &parent->children); |
d71374da | 628 | up_write(&pci_bus_sem); |
e4ea9bb7 | 629 | } |
1da177e4 LT |
630 | return child; |
631 | } | |
632 | ||
96bde06a | 633 | static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max) |
26f674ae GKH |
634 | { |
635 | struct pci_bus *parent = child->parent; | |
12f44f46 IK |
636 | |
637 | /* Attempts to fix that up are really dangerous unless | |
638 | we're going to re-assign all bus numbers. */ | |
639 | if (!pcibios_assign_all_busses()) | |
640 | return; | |
641 | ||
26f674ae GKH |
642 | while (parent->parent && parent->subordinate < max) { |
643 | parent->subordinate = max; | |
644 | pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max); | |
645 | parent = parent->parent; | |
646 | } | |
647 | } | |
648 | ||
1da177e4 LT |
649 | /* |
650 | * If it's a bridge, configure it and scan the bus behind it. | |
651 | * For CardBus bridges, we don't scan behind as the devices will | |
652 | * be handled by the bridge driver itself. | |
653 | * | |
654 | * We need to process bridges in two passes -- first we scan those | |
655 | * already configured by the BIOS and after we are done with all of | |
656 | * them, we proceed to assigning numbers to the remaining buses in | |
657 | * order to avoid overlaps between old and new bus numbers. | |
658 | */ | |
0ab2b57f | 659 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) |
1da177e4 LT |
660 | { |
661 | struct pci_bus *child; | |
662 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); | |
49887941 | 663 | u32 buses, i, j = 0; |
1da177e4 | 664 | u16 bctl; |
99ddd552 | 665 | u8 primary, secondary, subordinate; |
a1c19894 | 666 | int broken = 0; |
1da177e4 LT |
667 | |
668 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); | |
99ddd552 BH |
669 | primary = buses & 0xFF; |
670 | secondary = (buses >> 8) & 0xFF; | |
671 | subordinate = (buses >> 16) & 0xFF; | |
1da177e4 | 672 | |
99ddd552 BH |
673 | dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", |
674 | secondary, subordinate, pass); | |
1da177e4 | 675 | |
a1c19894 BH |
676 | /* Check if setup is sensible at all */ |
677 | if (!pass && | |
99ddd552 | 678 | (primary != bus->number || secondary <= bus->number)) { |
a1c19894 BH |
679 | dev_dbg(&dev->dev, "bus configuration invalid, reconfiguring\n"); |
680 | broken = 1; | |
681 | } | |
682 | ||
1da177e4 LT |
683 | /* Disable MasterAbortMode during probing to avoid reporting |
684 | of bus errors (in some architectures) */ | |
685 | pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); | |
686 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, | |
687 | bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); | |
688 | ||
99ddd552 BH |
689 | if ((secondary || subordinate) && !pcibios_assign_all_busses() && |
690 | !is_cardbus && !broken) { | |
691 | unsigned int cmax; | |
1da177e4 LT |
692 | /* |
693 | * Bus already configured by firmware, process it in the first | |
694 | * pass and just note the configuration. | |
695 | */ | |
696 | if (pass) | |
bbe8f9a3 | 697 | goto out; |
1da177e4 LT |
698 | |
699 | /* | |
700 | * If we already got to this bus through a different bridge, | |
74710ded AC |
701 | * don't re-add it. This can happen with the i450NX chipset. |
702 | * | |
703 | * However, we continue to descend down the hierarchy and | |
704 | * scan remaining child buses. | |
1da177e4 | 705 | */ |
99ddd552 | 706 | child = pci_find_bus(pci_domain_nr(bus), secondary); |
74710ded | 707 | if (!child) { |
99ddd552 | 708 | child = pci_add_new_bus(bus, dev, secondary); |
74710ded AC |
709 | if (!child) |
710 | goto out; | |
99ddd552 BH |
711 | child->primary = primary; |
712 | child->subordinate = subordinate; | |
74710ded | 713 | child->bridge_ctl = bctl; |
1da177e4 LT |
714 | } |
715 | ||
1da177e4 LT |
716 | cmax = pci_scan_child_bus(child); |
717 | if (cmax > max) | |
718 | max = cmax; | |
719 | if (child->subordinate > max) | |
720 | max = child->subordinate; | |
721 | } else { | |
722 | /* | |
723 | * We need to assign a number to this bus which we always | |
724 | * do in the second pass. | |
725 | */ | |
12f44f46 | 726 | if (!pass) { |
a1c19894 | 727 | if (pcibios_assign_all_busses() || broken) |
12f44f46 IK |
728 | /* Temporarily disable forwarding of the |
729 | configuration cycles on all bridges in | |
730 | this bus segment to avoid possible | |
731 | conflicts in the second pass between two | |
732 | bridges programmed with overlapping | |
733 | bus ranges. */ | |
734 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, | |
735 | buses & ~0xffffff); | |
bbe8f9a3 | 736 | goto out; |
12f44f46 | 737 | } |
1da177e4 LT |
738 | |
739 | /* Clear errors */ | |
740 | pci_write_config_word(dev, PCI_STATUS, 0xffff); | |
741 | ||
cc57450f | 742 | /* Prevent assigning a bus number that already exists. |
b1a98b69 TC |
743 | * This can happen when a bridge is hot-plugged, so in |
744 | * this case we only re-scan this bus. */ | |
745 | child = pci_find_bus(pci_domain_nr(bus), max+1); | |
746 | if (!child) { | |
747 | child = pci_add_new_bus(bus, dev, ++max); | |
748 | if (!child) | |
749 | goto out; | |
750 | } | |
1da177e4 LT |
751 | buses = (buses & 0xff000000) |
752 | | ((unsigned int)(child->primary) << 0) | |
753 | | ((unsigned int)(child->secondary) << 8) | |
754 | | ((unsigned int)(child->subordinate) << 16); | |
755 | ||
756 | /* | |
757 | * yenta.c forces a secondary latency timer of 176. | |
758 | * Copy that behaviour here. | |
759 | */ | |
760 | if (is_cardbus) { | |
761 | buses &= ~0xff000000; | |
762 | buses |= CARDBUS_LATENCY_TIMER << 24; | |
763 | } | |
7c867c88 | 764 | |
1da177e4 LT |
765 | /* |
766 | * We need to blast all three values with a single write. | |
767 | */ | |
768 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | |
769 | ||
770 | if (!is_cardbus) { | |
11949255 | 771 | child->bridge_ctl = bctl; |
26f674ae GKH |
772 | /* |
773 | * Adjust subordinate busnr in parent buses. | |
774 | * We do this before scanning for children because | |
775 | * some devices may not be detected if the bios | |
776 | * was lazy. | |
777 | */ | |
778 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
779 | /* Now we can scan all subordinate buses... */ |
780 | max = pci_scan_child_bus(child); | |
e3ac86d8 KA |
781 | /* |
782 | * now fix it up again since we have found | |
783 | * the real value of max. | |
784 | */ | |
785 | pci_fixup_parent_subordinate_busnr(child, max); | |
1da177e4 LT |
786 | } else { |
787 | /* | |
788 | * For CardBus bridges, we leave 4 bus numbers | |
789 | * as cards with a PCI-to-PCI bridge can be | |
790 | * inserted later. | |
791 | */ | |
49887941 DB |
792 | for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) { |
793 | struct pci_bus *parent = bus; | |
cc57450f RS |
794 | if (pci_find_bus(pci_domain_nr(bus), |
795 | max+i+1)) | |
796 | break; | |
49887941 DB |
797 | while (parent->parent) { |
798 | if ((!pcibios_assign_all_busses()) && | |
799 | (parent->subordinate > max) && | |
800 | (parent->subordinate <= max+i)) { | |
801 | j = 1; | |
802 | } | |
803 | parent = parent->parent; | |
804 | } | |
805 | if (j) { | |
806 | /* | |
807 | * Often, there are two cardbus bridges | |
808 | * -- try to leave one valid bus number | |
809 | * for each one. | |
810 | */ | |
811 | i /= 2; | |
812 | break; | |
813 | } | |
814 | } | |
cc57450f | 815 | max += i; |
26f674ae | 816 | pci_fixup_parent_subordinate_busnr(child, max); |
1da177e4 LT |
817 | } |
818 | /* | |
819 | * Set the subordinate bus number to its real value. | |
820 | */ | |
821 | child->subordinate = max; | |
822 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); | |
823 | } | |
824 | ||
cb3576fa GH |
825 | sprintf(child->name, |
826 | (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), | |
827 | pci_domain_nr(bus), child->number); | |
1da177e4 | 828 | |
d55bef51 | 829 | /* Has only triggered on CardBus, fixup is in yenta_socket */ |
49887941 DB |
830 | while (bus->parent) { |
831 | if ((child->subordinate > bus->subordinate) || | |
832 | (child->number > bus->subordinate) || | |
833 | (child->number < bus->number) || | |
834 | (child->subordinate < bus->number)) { | |
865df576 BH |
835 | dev_info(&child->dev, "[bus %02x-%02x] %s " |
836 | "hidden behind%s bridge %s [bus %02x-%02x]\n", | |
d55bef51 BK |
837 | child->number, child->subordinate, |
838 | (bus->number > child->subordinate && | |
839 | bus->subordinate < child->number) ? | |
a6f29a98 JP |
840 | "wholly" : "partially", |
841 | bus->self->transparent ? " transparent" : "", | |
865df576 | 842 | dev_name(&bus->dev), |
d55bef51 | 843 | bus->number, bus->subordinate); |
49887941 DB |
844 | } |
845 | bus = bus->parent; | |
846 | } | |
847 | ||
bbe8f9a3 RB |
848 | out: |
849 | pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); | |
850 | ||
1da177e4 LT |
851 | return max; |
852 | } | |
853 | ||
854 | /* | |
855 | * Read interrupt line and base address registers. | |
856 | * The architecture-dependent code can tweak these, of course. | |
857 | */ | |
858 | static void pci_read_irq(struct pci_dev *dev) | |
859 | { | |
860 | unsigned char irq; | |
861 | ||
862 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); | |
ffeff788 | 863 | dev->pin = irq; |
1da177e4 LT |
864 | if (irq) |
865 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); | |
866 | dev->irq = irq; | |
867 | } | |
868 | ||
bb209c82 | 869 | void set_pcie_port_type(struct pci_dev *pdev) |
480b93b7 YZ |
870 | { |
871 | int pos; | |
872 | u16 reg16; | |
873 | ||
874 | pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); | |
875 | if (!pos) | |
876 | return; | |
877 | pdev->is_pcie = 1; | |
0efea000 | 878 | pdev->pcie_cap = pos; |
480b93b7 YZ |
879 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); |
880 | pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4; | |
881 | } | |
882 | ||
bb209c82 | 883 | void set_pcie_hotplug_bridge(struct pci_dev *pdev) |
28760489 EB |
884 | { |
885 | int pos; | |
886 | u16 reg16; | |
887 | u32 reg32; | |
888 | ||
06a1cbaf | 889 | pos = pci_pcie_cap(pdev); |
28760489 EB |
890 | if (!pos) |
891 | return; | |
892 | pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); | |
893 | if (!(reg16 & PCI_EXP_FLAGS_SLOT)) | |
894 | return; | |
895 | pci_read_config_dword(pdev, pos + PCI_EXP_SLTCAP, ®32); | |
896 | if (reg32 & PCI_EXP_SLTCAP_HPC) | |
897 | pdev->is_hotplug_bridge = 1; | |
898 | } | |
899 | ||
01abc2aa | 900 | #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
76e6a1d6 | 901 | |
1da177e4 LT |
902 | /** |
903 | * pci_setup_device - fill in class and map information of a device | |
904 | * @dev: the device structure to fill | |
905 | * | |
906 | * Initialize the device structure with information about the device's | |
907 | * vendor,class,memory and IO-space addresses,IRQ lines etc. | |
908 | * Called at initialisation of the PCI subsystem and by CardBus services. | |
480b93b7 YZ |
909 | * Returns 0 on success and negative if unknown type of device (not normal, |
910 | * bridge or CardBus). | |
1da177e4 | 911 | */ |
480b93b7 | 912 | int pci_setup_device(struct pci_dev *dev) |
1da177e4 LT |
913 | { |
914 | u32 class; | |
480b93b7 YZ |
915 | u8 hdr_type; |
916 | struct pci_slot *slot; | |
bc577d2b | 917 | int pos = 0; |
480b93b7 YZ |
918 | |
919 | if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type)) | |
920 | return -EIO; | |
921 | ||
922 | dev->sysdata = dev->bus->sysdata; | |
923 | dev->dev.parent = dev->bus->bridge; | |
924 | dev->dev.bus = &pci_bus_type; | |
925 | dev->hdr_type = hdr_type & 0x7f; | |
926 | dev->multifunction = !!(hdr_type & 0x80); | |
480b93b7 YZ |
927 | dev->error_state = pci_channel_io_normal; |
928 | set_pcie_port_type(dev); | |
929 | ||
930 | list_for_each_entry(slot, &dev->bus->slots, list) | |
931 | if (PCI_SLOT(dev->devfn) == slot->number) | |
932 | dev->slot = slot; | |
933 | ||
934 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) | |
935 | set this higher, assuming the system even supports it. */ | |
936 | dev->dma_mask = 0xffffffff; | |
1da177e4 | 937 | |
eebfcfb5 GKH |
938 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
939 | dev->bus->number, PCI_SLOT(dev->devfn), | |
940 | PCI_FUNC(dev->devfn)); | |
1da177e4 LT |
941 | |
942 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
b8a3a521 | 943 | dev->revision = class & 0xff; |
1da177e4 LT |
944 | class >>= 8; /* upper 3 bytes */ |
945 | dev->class = class; | |
946 | class >>= 8; | |
947 | ||
2c6413ae BH |
948 | dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %d class %#08x\n", |
949 | dev->vendor, dev->device, dev->hdr_type, class); | |
1da177e4 | 950 | |
853346e4 YZ |
951 | /* need to have dev->class ready */ |
952 | dev->cfg_size = pci_cfg_space_size(dev); | |
953 | ||
1da177e4 | 954 | /* "Unknown power state" */ |
3fe9d19f | 955 | dev->current_state = PCI_UNKNOWN; |
1da177e4 LT |
956 | |
957 | /* Early fixups, before probing the BARs */ | |
958 | pci_fixup_device(pci_fixup_early, dev); | |
f79b1b14 YZ |
959 | /* device class may be changed after fixup */ |
960 | class = dev->class >> 8; | |
1da177e4 LT |
961 | |
962 | switch (dev->hdr_type) { /* header type */ | |
963 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ | |
964 | if (class == PCI_CLASS_BRIDGE_PCI) | |
965 | goto bad; | |
966 | pci_read_irq(dev); | |
967 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); | |
968 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
969 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); | |
368c73d4 AC |
970 | |
971 | /* | |
972 | * Do the ugly legacy mode stuff here rather than broken chip | |
973 | * quirk code. Legacy mode ATA controllers have fixed | |
974 | * addresses. These are not always echoed in BAR0-3, and | |
975 | * BAR0-3 in a few cases contain junk! | |
976 | */ | |
977 | if (class == PCI_CLASS_STORAGE_IDE) { | |
978 | u8 progif; | |
979 | pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); | |
980 | if ((progif & 1) == 0) { | |
af1bff4f LT |
981 | dev->resource[0].start = 0x1F0; |
982 | dev->resource[0].end = 0x1F7; | |
983 | dev->resource[0].flags = LEGACY_IO_RESOURCE; | |
984 | dev->resource[1].start = 0x3F6; | |
985 | dev->resource[1].end = 0x3F6; | |
986 | dev->resource[1].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
987 | } |
988 | if ((progif & 4) == 0) { | |
af1bff4f LT |
989 | dev->resource[2].start = 0x170; |
990 | dev->resource[2].end = 0x177; | |
991 | dev->resource[2].flags = LEGACY_IO_RESOURCE; | |
992 | dev->resource[3].start = 0x376; | |
993 | dev->resource[3].end = 0x376; | |
994 | dev->resource[3].flags = LEGACY_IO_RESOURCE; | |
368c73d4 AC |
995 | } |
996 | } | |
1da177e4 LT |
997 | break; |
998 | ||
999 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ | |
1000 | if (class != PCI_CLASS_BRIDGE_PCI) | |
1001 | goto bad; | |
1002 | /* The PCI-to-PCI bridge spec requires that subtractive | |
1003 | decoding (i.e. transparent) bridge must have programming | |
1004 | interface code of 0x01. */ | |
3efd273b | 1005 | pci_read_irq(dev); |
1da177e4 LT |
1006 | dev->transparent = ((dev->class & 0xff) == 1); |
1007 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); | |
28760489 | 1008 | set_pcie_hotplug_bridge(dev); |
bc577d2b GB |
1009 | pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); |
1010 | if (pos) { | |
1011 | pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); | |
1012 | pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); | |
1013 | } | |
1da177e4 LT |
1014 | break; |
1015 | ||
1016 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ | |
1017 | if (class != PCI_CLASS_BRIDGE_CARDBUS) | |
1018 | goto bad; | |
1019 | pci_read_irq(dev); | |
1020 | pci_read_bases(dev, 1, 0); | |
1021 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); | |
1022 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); | |
1023 | break; | |
1024 | ||
1025 | default: /* unknown header */ | |
80ccba11 BH |
1026 | dev_err(&dev->dev, "unknown header type %02x, " |
1027 | "ignoring device\n", dev->hdr_type); | |
480b93b7 | 1028 | return -EIO; |
1da177e4 LT |
1029 | |
1030 | bad: | |
80ccba11 BH |
1031 | dev_err(&dev->dev, "ignoring class %02x (doesn't match header " |
1032 | "type %02x)\n", class, dev->hdr_type); | |
1da177e4 LT |
1033 | dev->class = PCI_CLASS_NOT_DEFINED; |
1034 | } | |
1035 | ||
1036 | /* We found a fine healthy device, go go go... */ | |
1037 | return 0; | |
1038 | } | |
1039 | ||
201de56e ZY |
1040 | static void pci_release_capabilities(struct pci_dev *dev) |
1041 | { | |
1042 | pci_vpd_release(dev); | |
d1b054da | 1043 | pci_iov_release(dev); |
201de56e ZY |
1044 | } |
1045 | ||
1da177e4 LT |
1046 | /** |
1047 | * pci_release_dev - free a pci device structure when all users of it are finished. | |
1048 | * @dev: device that's been disconnected | |
1049 | * | |
1050 | * Will be called only by the device core when all users of this pci device are | |
1051 | * done. | |
1052 | */ | |
1053 | static void pci_release_dev(struct device *dev) | |
1054 | { | |
1055 | struct pci_dev *pci_dev; | |
1056 | ||
1057 | pci_dev = to_pci_dev(dev); | |
201de56e | 1058 | pci_release_capabilities(pci_dev); |
1da177e4 LT |
1059 | kfree(pci_dev); |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * pci_cfg_space_size - get the configuration space size of the PCI device. | |
8f7020d3 | 1064 | * @dev: PCI device |
1da177e4 LT |
1065 | * |
1066 | * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices | |
1067 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | |
1068 | * access it. Maybe we don't have a way to generate extended config space | |
1069 | * accesses, or the device is behind a reverse Express bridge. So we try | |
1070 | * reading the dword at 0x100 which must either be 0 or a valid extended | |
1071 | * capability header. | |
1072 | */ | |
70b9f7dc | 1073 | int pci_cfg_space_size_ext(struct pci_dev *dev) |
1da177e4 | 1074 | { |
1da177e4 | 1075 | u32 status; |
557848c3 | 1076 | int pos = PCI_CFG_SPACE_SIZE; |
1da177e4 | 1077 | |
557848c3 | 1078 | if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) |
70b9f7dc YL |
1079 | goto fail; |
1080 | if (status == 0xffffffff) | |
1081 | goto fail; | |
1082 | ||
1083 | return PCI_CFG_SPACE_EXP_SIZE; | |
1084 | ||
1085 | fail: | |
1086 | return PCI_CFG_SPACE_SIZE; | |
1087 | } | |
1088 | ||
1089 | int pci_cfg_space_size(struct pci_dev *dev) | |
1090 | { | |
1091 | int pos; | |
1092 | u32 status; | |
dfadd9ed YL |
1093 | u16 class; |
1094 | ||
1095 | class = dev->class >> 8; | |
1096 | if (class == PCI_CLASS_BRIDGE_HOST) | |
1097 | return pci_cfg_space_size_ext(dev); | |
57741a77 | 1098 | |
06a1cbaf | 1099 | pos = pci_pcie_cap(dev); |
1da177e4 LT |
1100 | if (!pos) { |
1101 | pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); | |
1102 | if (!pos) | |
1103 | goto fail; | |
1104 | ||
1105 | pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); | |
1106 | if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))) | |
1107 | goto fail; | |
1108 | } | |
1109 | ||
70b9f7dc | 1110 | return pci_cfg_space_size_ext(dev); |
1da177e4 LT |
1111 | |
1112 | fail: | |
1113 | return PCI_CFG_SPACE_SIZE; | |
1114 | } | |
1115 | ||
1116 | static void pci_release_bus_bridge_dev(struct device *dev) | |
1117 | { | |
1118 | kfree(dev); | |
1119 | } | |
1120 | ||
65891215 ME |
1121 | struct pci_dev *alloc_pci_dev(void) |
1122 | { | |
1123 | struct pci_dev *dev; | |
1124 | ||
1125 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
1126 | if (!dev) | |
1127 | return NULL; | |
1128 | ||
65891215 ME |
1129 | INIT_LIST_HEAD(&dev->bus_list); |
1130 | ||
1131 | return dev; | |
1132 | } | |
1133 | EXPORT_SYMBOL(alloc_pci_dev); | |
1134 | ||
1da177e4 LT |
1135 | /* |
1136 | * Read the config data for a PCI device, sanity-check it | |
1137 | * and fill in the dev structure... | |
1138 | */ | |
7f7b5de2 | 1139 | static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) |
1da177e4 LT |
1140 | { |
1141 | struct pci_dev *dev; | |
1142 | u32 l; | |
1da177e4 LT |
1143 | int delay = 1; |
1144 | ||
1145 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
1146 | return NULL; | |
1147 | ||
1148 | /* some broken boards return 0 or ~0 if a slot is empty: */ | |
1149 | if (l == 0xffffffff || l == 0x00000000 || | |
1150 | l == 0x0000ffff || l == 0xffff0000) | |
1151 | return NULL; | |
1152 | ||
1153 | /* Configuration request Retry Status */ | |
1154 | while (l == 0xffff0001) { | |
1155 | msleep(delay); | |
1156 | delay *= 2; | |
1157 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) | |
1158 | return NULL; | |
1159 | /* Card hasn't responded in 60 seconds? Must be stuck. */ | |
1160 | if (delay > 60 * 1000) { | |
80ccba11 | 1161 | printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not " |
1da177e4 LT |
1162 | "responding\n", pci_domain_nr(bus), |
1163 | bus->number, PCI_SLOT(devfn), | |
1164 | PCI_FUNC(devfn)); | |
1165 | return NULL; | |
1166 | } | |
1167 | } | |
1168 | ||
bab41e9b | 1169 | dev = alloc_pci_dev(); |
1da177e4 LT |
1170 | if (!dev) |
1171 | return NULL; | |
1172 | ||
1da177e4 | 1173 | dev->bus = bus; |
1da177e4 | 1174 | dev->devfn = devfn; |
1da177e4 LT |
1175 | dev->vendor = l & 0xffff; |
1176 | dev->device = (l >> 16) & 0xffff; | |
cef354db | 1177 | |
480b93b7 | 1178 | if (pci_setup_device(dev)) { |
1da177e4 LT |
1179 | kfree(dev); |
1180 | return NULL; | |
1181 | } | |
1da177e4 LT |
1182 | |
1183 | return dev; | |
1184 | } | |
1185 | ||
201de56e ZY |
1186 | static void pci_init_capabilities(struct pci_dev *dev) |
1187 | { | |
1188 | /* MSI/MSI-X list */ | |
1189 | pci_msi_init_pci_dev(dev); | |
1190 | ||
63f4898a RW |
1191 | /* Buffers for saving PCIe and PCI-X capabilities */ |
1192 | pci_allocate_cap_save_buffers(dev); | |
1193 | ||
201de56e ZY |
1194 | /* Power Management */ |
1195 | pci_pm_init(dev); | |
eb9c39d0 | 1196 | platform_pci_wakeup_init(dev); |
201de56e ZY |
1197 | |
1198 | /* Vital Product Data */ | |
1199 | pci_vpd_pci22_init(dev); | |
58c3a727 YZ |
1200 | |
1201 | /* Alternative Routing-ID Forwarding */ | |
1202 | pci_enable_ari(dev); | |
d1b054da YZ |
1203 | |
1204 | /* Single Root I/O Virtualization */ | |
1205 | pci_iov_init(dev); | |
ae21ee65 AK |
1206 | |
1207 | /* Enable ACS P2P upstream forwarding */ | |
5d990b62 | 1208 | pci_enable_acs(dev); |
201de56e ZY |
1209 | } |
1210 | ||
96bde06a | 1211 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) |
1da177e4 | 1212 | { |
cdb9b9f7 PM |
1213 | device_initialize(&dev->dev); |
1214 | dev->dev.release = pci_release_dev; | |
1215 | pci_dev_get(dev); | |
1da177e4 | 1216 | |
cdb9b9f7 | 1217 | dev->dev.dma_mask = &dev->dma_mask; |
4d57cdfa | 1218 | dev->dev.dma_parms = &dev->dma_parms; |
cdb9b9f7 | 1219 | dev->dev.coherent_dma_mask = 0xffffffffull; |
1da177e4 | 1220 | |
4d57cdfa | 1221 | pci_set_dma_max_seg_size(dev, 65536); |
59fc67de | 1222 | pci_set_dma_seg_boundary(dev, 0xffffffff); |
4d57cdfa | 1223 | |
1da177e4 LT |
1224 | /* Fix up broken headers */ |
1225 | pci_fixup_device(pci_fixup_header, dev); | |
1226 | ||
4b77b0a2 RW |
1227 | /* Clear the state_saved flag. */ |
1228 | dev->state_saved = false; | |
1229 | ||
201de56e ZY |
1230 | /* Initialize various capabilities */ |
1231 | pci_init_capabilities(dev); | |
eb9d0fe4 | 1232 | |
1da177e4 LT |
1233 | /* |
1234 | * Add the device to our list of discovered devices | |
1235 | * and the bus list for fixup functions, etc. | |
1236 | */ | |
d71374da | 1237 | down_write(&pci_bus_sem); |
1da177e4 | 1238 | list_add_tail(&dev->bus_list, &bus->devices); |
d71374da | 1239 | up_write(&pci_bus_sem); |
cdb9b9f7 PM |
1240 | } |
1241 | ||
451124a7 | 1242 | struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn) |
cdb9b9f7 PM |
1243 | { |
1244 | struct pci_dev *dev; | |
1245 | ||
90bdb311 TP |
1246 | dev = pci_get_slot(bus, devfn); |
1247 | if (dev) { | |
1248 | pci_dev_put(dev); | |
1249 | return dev; | |
1250 | } | |
1251 | ||
cdb9b9f7 PM |
1252 | dev = pci_scan_device(bus, devfn); |
1253 | if (!dev) | |
1254 | return NULL; | |
1255 | ||
1256 | pci_device_add(dev, bus); | |
1da177e4 LT |
1257 | |
1258 | return dev; | |
1259 | } | |
b73e9687 | 1260 | EXPORT_SYMBOL(pci_scan_single_device); |
1da177e4 | 1261 | |
f07852d6 MW |
1262 | static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn) |
1263 | { | |
1264 | u16 cap; | |
4fb88c1a MW |
1265 | unsigned pos, next_fn; |
1266 | ||
1267 | if (!dev) | |
1268 | return 0; | |
1269 | ||
1270 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); | |
f07852d6 MW |
1271 | if (!pos) |
1272 | return 0; | |
1273 | pci_read_config_word(dev, pos + 4, &cap); | |
4fb88c1a MW |
1274 | next_fn = cap >> 8; |
1275 | if (next_fn <= fn) | |
1276 | return 0; | |
1277 | return next_fn; | |
f07852d6 MW |
1278 | } |
1279 | ||
1280 | static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn) | |
1281 | { | |
1282 | return (fn + 1) % 8; | |
1283 | } | |
1284 | ||
1285 | static unsigned no_next_fn(struct pci_dev *dev, unsigned fn) | |
1286 | { | |
1287 | return 0; | |
1288 | } | |
1289 | ||
1290 | static int only_one_child(struct pci_bus *bus) | |
1291 | { | |
1292 | struct pci_dev *parent = bus->self; | |
1293 | if (!parent || !pci_is_pcie(parent)) | |
1294 | return 0; | |
1295 | if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT || | |
1296 | parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) | |
1297 | return 1; | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1da177e4 LT |
1301 | /** |
1302 | * pci_scan_slot - scan a PCI slot on a bus for devices. | |
1303 | * @bus: PCI bus to scan | |
1304 | * @devfn: slot number to scan (must have zero function.) | |
1305 | * | |
1306 | * Scan a PCI slot on the specified PCI bus for devices, adding | |
1307 | * discovered devices to the @bus->devices list. New devices | |
8a1bc901 | 1308 | * will not have is_added set. |
1b69dfc6 TP |
1309 | * |
1310 | * Returns the number of new devices found. | |
1da177e4 | 1311 | */ |
96bde06a | 1312 | int pci_scan_slot(struct pci_bus *bus, int devfn) |
1da177e4 | 1313 | { |
f07852d6 | 1314 | unsigned fn, nr = 0; |
1b69dfc6 | 1315 | struct pci_dev *dev; |
f07852d6 MW |
1316 | unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn; |
1317 | ||
1318 | if (only_one_child(bus) && (devfn > 0)) | |
1319 | return 0; /* Already scanned the entire slot */ | |
1da177e4 | 1320 | |
1b69dfc6 | 1321 | dev = pci_scan_single_device(bus, devfn); |
4fb88c1a MW |
1322 | if (!dev) |
1323 | return 0; | |
1324 | if (!dev->is_added) | |
1b69dfc6 TP |
1325 | nr++; |
1326 | ||
f07852d6 MW |
1327 | if (pci_ari_enabled(bus)) |
1328 | next_fn = next_ari_fn; | |
4fb88c1a | 1329 | else if (dev->multifunction) |
f07852d6 MW |
1330 | next_fn = next_trad_fn; |
1331 | ||
1332 | for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) { | |
1333 | dev = pci_scan_single_device(bus, devfn + fn); | |
1334 | if (dev) { | |
1335 | if (!dev->is_added) | |
1336 | nr++; | |
1337 | dev->multifunction = 1; | |
1da177e4 LT |
1338 | } |
1339 | } | |
7d715a6c | 1340 | |
149e1637 SL |
1341 | /* only one slot has pcie device */ |
1342 | if (bus->self && nr) | |
7d715a6c SL |
1343 | pcie_aspm_init_link_state(bus->self); |
1344 | ||
1da177e4 LT |
1345 | return nr; |
1346 | } | |
1347 | ||
0ab2b57f | 1348 | unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
1da177e4 LT |
1349 | { |
1350 | unsigned int devfn, pass, max = bus->secondary; | |
1351 | struct pci_dev *dev; | |
1352 | ||
0207c356 | 1353 | dev_dbg(&bus->dev, "scanning bus\n"); |
1da177e4 LT |
1354 | |
1355 | /* Go find them, Rover! */ | |
1356 | for (devfn = 0; devfn < 0x100; devfn += 8) | |
1357 | pci_scan_slot(bus, devfn); | |
1358 | ||
a28724b0 YZ |
1359 | /* Reserve buses for SR-IOV capability. */ |
1360 | max += pci_iov_bus_range(bus); | |
1361 | ||
1da177e4 LT |
1362 | /* |
1363 | * After performing arch-dependent fixup of the bus, look behind | |
1364 | * all PCI-to-PCI bridges on this bus. | |
1365 | */ | |
74710ded | 1366 | if (!bus->is_added) { |
0207c356 | 1367 | dev_dbg(&bus->dev, "fixups for bus\n"); |
74710ded AC |
1368 | pcibios_fixup_bus(bus); |
1369 | if (pci_is_root_bus(bus)) | |
1370 | bus->is_added = 1; | |
1371 | } | |
1372 | ||
1da177e4 LT |
1373 | for (pass=0; pass < 2; pass++) |
1374 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1375 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1376 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1377 | max = pci_scan_bridge(bus, dev, max, pass); | |
1378 | } | |
1379 | ||
1380 | /* | |
1381 | * We've scanned the bus and so we know all about what's on | |
1382 | * the other side of any bridges that may be on this bus plus | |
1383 | * any devices. | |
1384 | * | |
1385 | * Return how far we've got finding sub-buses. | |
1386 | */ | |
0207c356 | 1387 | dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); |
1da177e4 LT |
1388 | return max; |
1389 | } | |
1390 | ||
96bde06a | 1391 | struct pci_bus * pci_create_bus(struct device *parent, |
cdb9b9f7 | 1392 | int bus, struct pci_ops *ops, void *sysdata) |
1da177e4 LT |
1393 | { |
1394 | int error; | |
0207c356 | 1395 | struct pci_bus *b, *b2; |
1da177e4 LT |
1396 | struct device *dev; |
1397 | ||
1398 | b = pci_alloc_bus(); | |
1399 | if (!b) | |
1400 | return NULL; | |
1401 | ||
6a3b3e26 | 1402 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); |
1da177e4 LT |
1403 | if (!dev){ |
1404 | kfree(b); | |
1405 | return NULL; | |
1406 | } | |
1407 | ||
1408 | b->sysdata = sysdata; | |
1409 | b->ops = ops; | |
1410 | ||
0207c356 BH |
1411 | b2 = pci_find_bus(pci_domain_nr(b), bus); |
1412 | if (b2) { | |
1da177e4 | 1413 | /* If we already got to this bus through a different bridge, ignore it */ |
0207c356 | 1414 | dev_dbg(&b2->dev, "bus already known\n"); |
1da177e4 LT |
1415 | goto err_out; |
1416 | } | |
d71374da ZY |
1417 | |
1418 | down_write(&pci_bus_sem); | |
1da177e4 | 1419 | list_add_tail(&b->node, &pci_root_buses); |
d71374da | 1420 | up_write(&pci_bus_sem); |
1da177e4 | 1421 | |
1da177e4 LT |
1422 | dev->parent = parent; |
1423 | dev->release = pci_release_bus_bridge_dev; | |
1a927133 | 1424 | dev_set_name(dev, "pci%04x:%02x", pci_domain_nr(b), bus); |
1da177e4 LT |
1425 | error = device_register(dev); |
1426 | if (error) | |
1427 | goto dev_reg_err; | |
1428 | b->bridge = get_device(dev); | |
a1e4d72c | 1429 | device_enable_async_suspend(b->bridge); |
1da177e4 | 1430 | |
0d358f22 YL |
1431 | if (!parent) |
1432 | set_dev_node(b->bridge, pcibus_to_node(b)); | |
1433 | ||
fd7d1ced GKH |
1434 | b->dev.class = &pcibus_class; |
1435 | b->dev.parent = b->bridge; | |
1a927133 | 1436 | dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus); |
fd7d1ced | 1437 | error = device_register(&b->dev); |
1da177e4 LT |
1438 | if (error) |
1439 | goto class_dev_reg_err; | |
1da177e4 LT |
1440 | |
1441 | /* Create legacy_io and legacy_mem files for this bus */ | |
1442 | pci_create_legacy_files(b); | |
1443 | ||
1da177e4 LT |
1444 | b->number = b->secondary = bus; |
1445 | b->resource[0] = &ioport_resource; | |
1446 | b->resource[1] = &iomem_resource; | |
1447 | ||
1da177e4 LT |
1448 | return b; |
1449 | ||
1da177e4 LT |
1450 | class_dev_reg_err: |
1451 | device_unregister(dev); | |
1452 | dev_reg_err: | |
d71374da | 1453 | down_write(&pci_bus_sem); |
1da177e4 | 1454 | list_del(&b->node); |
d71374da | 1455 | up_write(&pci_bus_sem); |
1da177e4 LT |
1456 | err_out: |
1457 | kfree(dev); | |
1458 | kfree(b); | |
1459 | return NULL; | |
1460 | } | |
cdb9b9f7 | 1461 | |
0ab2b57f | 1462 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, |
cdb9b9f7 PM |
1463 | int bus, struct pci_ops *ops, void *sysdata) |
1464 | { | |
1465 | struct pci_bus *b; | |
1466 | ||
1467 | b = pci_create_bus(parent, bus, ops, sysdata); | |
1468 | if (b) | |
1469 | b->subordinate = pci_scan_child_bus(b); | |
1470 | return b; | |
1471 | } | |
1da177e4 LT |
1472 | EXPORT_SYMBOL(pci_scan_bus_parented); |
1473 | ||
1474 | #ifdef CONFIG_HOTPLUG | |
3ed4fd96 AC |
1475 | /** |
1476 | * pci_rescan_bus - scan a PCI bus for devices. | |
1477 | * @bus: PCI bus to scan | |
1478 | * | |
1479 | * Scan a PCI bus and child buses for new devices, adds them, | |
1480 | * and enables them. | |
1481 | * | |
1482 | * Returns the max number of subordinate bus discovered. | |
1483 | */ | |
5446a6bd | 1484 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) |
3ed4fd96 AC |
1485 | { |
1486 | unsigned int max; | |
1487 | struct pci_dev *dev; | |
1488 | ||
1489 | max = pci_scan_child_bus(bus); | |
1490 | ||
705b1aaa | 1491 | down_read(&pci_bus_sem); |
3ed4fd96 AC |
1492 | list_for_each_entry(dev, &bus->devices, bus_list) |
1493 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1494 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1495 | if (dev->subordinate) | |
1496 | pci_bus_size_bridges(dev->subordinate); | |
705b1aaa | 1497 | up_read(&pci_bus_sem); |
3ed4fd96 AC |
1498 | |
1499 | pci_bus_assign_resources(bus); | |
1500 | pci_enable_bridges(bus); | |
1501 | pci_bus_add_devices(bus); | |
1502 | ||
1503 | return max; | |
1504 | } | |
1505 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1506 | ||
1da177e4 | 1507 | EXPORT_SYMBOL(pci_add_new_bus); |
1da177e4 LT |
1508 | EXPORT_SYMBOL(pci_scan_slot); |
1509 | EXPORT_SYMBOL(pci_scan_bridge); | |
1da177e4 LT |
1510 | EXPORT_SYMBOL_GPL(pci_scan_child_bus); |
1511 | #endif | |
6b4b78fe | 1512 | |
99178b03 | 1513 | static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b) |
6b4b78fe | 1514 | { |
99178b03 GKH |
1515 | const struct pci_dev *a = to_pci_dev(d_a); |
1516 | const struct pci_dev *b = to_pci_dev(d_b); | |
1517 | ||
6b4b78fe MD |
1518 | if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; |
1519 | else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; | |
1520 | ||
1521 | if (a->bus->number < b->bus->number) return -1; | |
1522 | else if (a->bus->number > b->bus->number) return 1; | |
1523 | ||
1524 | if (a->devfn < b->devfn) return -1; | |
1525 | else if (a->devfn > b->devfn) return 1; | |
1526 | ||
1527 | return 0; | |
1528 | } | |
1529 | ||
5ff580c1 | 1530 | void __init pci_sort_breadthfirst(void) |
6b4b78fe | 1531 | { |
99178b03 | 1532 | bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); |
6b4b78fe | 1533 | } |