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OneNAND: Write oob area with aligned size, mtd->oobsize
[deliverable/linux.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
25be5e6c 24#include <linux/acpi.h>
bc56b9e0 25#include "pci.h"
1da177e4
LT		 26
27/* Deal with broken BIOS'es that neglect to enable passive release,
28 which can cause problems in combination with the 82441FX/PPro MTRRs */
29static void __devinit quirk_passive_release(struct pci_dev *dev)
30{
31 struct pci_dev *d = NULL;
32 unsigned char dlc;
33
34 /* We have to make sure a particular bit is set in the PIIX3
35 ISA bridge, so we have to go out and find it. */
36 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
37 pci_read_config_byte(d, 0x82, &dlc);
38 if (!(dlc & 1<<1)) {
39 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
40 dlc |= 1<<1;
41 pci_write_config_byte(d, 0x82, dlc);
42 }
43 }
44}
45DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
46
47/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
48 but VIA don't answer queries. If you happen to have good contacts at VIA
49 ask them for me please -- Alan
50
51 This appears to be BIOS not version dependent. So presumably there is a
52 chipset level fix */
53int isa_dma_bridge_buggy; /* Exported */
54
55static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
56{
57 if (!isa_dma_bridge_buggy) {
58 isa_dma_bridge_buggy=1;
59 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
60 }
61}
62 /*
63 * Its not totally clear which chipsets are the problematic ones
64 * We know 82C586 and 82C596 variants are affected.
65 */
66DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
68DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
69DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
70DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
71DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
72DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
73
74int pci_pci_problems;
75
76/*
77 * Chipsets where PCI->PCI transfers vanish or hang
78 */
79static void __devinit quirk_nopcipci(struct pci_dev *dev)
80{
81 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
82 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
83 pci_pci_problems |= PCIPCI_FAIL;
84 }
85}
86DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
87DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
88
89/*
90 * Triton requires workarounds to be used by the drivers
91 */
92static void __devinit quirk_triton(struct pci_dev *dev)
93{
94 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
95 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
96 pci_pci_problems |= PCIPCI_TRITON;
97 }
98}
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
103
104/*
105 * VIA Apollo KT133 needs PCI latency patch
106 * Made according to a windows driver based patch by George E. Breese
107 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
108 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
109 * the info on which Mr Breese based his work.
110 *
111 * Updated based on further information from the site and also on
112 * information provided by VIA
113 */
114static void __devinit quirk_vialatency(struct pci_dev *dev)
115{
116 struct pci_dev *p;
117 u8 rev;
118 u8 busarb;
119 /* Ok we have a potential problem chipset here. Now see if we have
120 a buggy southbridge */
121
122 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
123 if (p!=NULL) {
124 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
125 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
126 /* Check for buggy part revisions */
127 if (rev < 0x40 || rev > 0x42)
128 goto exit;
129 } else {
130 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
131 if (p==NULL) /* No problem parts */
132 goto exit;
133 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
134 /* Check for buggy part revisions */
135 if (rev < 0x10 || rev > 0x12)
136 goto exit;
137 }
138
139 /*
140 * Ok we have the problem. Now set the PCI master grant to
141 * occur every master grant. The apparent bug is that under high
142 * PCI load (quite common in Linux of course) you can get data
143 * loss when the CPU is held off the bus for 3 bus master requests
144 * This happens to include the IDE controllers....
145 *
146 * VIA only apply this fix when an SB Live! is present but under
147 * both Linux and Windows this isnt enough, and we have seen
148 * corruption without SB Live! but with things like 3 UDMA IDE
149 * controllers. So we ignore that bit of the VIA recommendation..
150 */
151
152 pci_read_config_byte(dev, 0x76, &busarb);
153 /* Set bit 4 and bi 5 of byte 76 to 0x01
154 "Master priority rotation on every PCI master grant */
155 busarb &= ~(1<<5);
156 busarb |= (1<<4);
157 pci_write_config_byte(dev, 0x76, busarb);
158 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
159exit:
160 pci_dev_put(p);
161}
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
165
166/*
167 * VIA Apollo VP3 needs ETBF on BT848/878
168 */
169static void __devinit quirk_viaetbf(struct pci_dev *dev)
170{
171 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
172 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
173 pci_pci_problems |= PCIPCI_VIAETBF;
174 }
175}
176DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
177
178static void __devinit quirk_vsfx(struct pci_dev *dev)
179{
180 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
181 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
182 pci_pci_problems |= PCIPCI_VSFX;
183 }
184}
185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
186
187/*
188 * Ali Magik requires workarounds to be used by the drivers
189 * that DMA to AGP space. Latency must be set to 0xA and triton
190 * workaround applied too
191 * [Info kindly provided by ALi]
192 */
193static void __init quirk_alimagik(struct pci_dev *dev)
194{
195 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
196 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
197 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
198 }
199}
200DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
201DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
202
203/*
204 * Natoma has some interesting boundary conditions with Zoran stuff
205 * at least
206 */
207static void __devinit quirk_natoma(struct pci_dev *dev)
208{
209 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
210 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
211 pci_pci_problems |= PCIPCI_NATOMA;
212 }
213}
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
220
221/*
222 * This chip can cause PCI parity errors if config register 0xA0 is read
223 * while DMAs are occurring.
224 */
225static void __devinit quirk_citrine(struct pci_dev *dev)
226{
227 dev->cfg_size = 0xA0;
228}
229DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
230
231/*
232 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
233 * If it's needed, re-allocate the region.
234 */
235static void __devinit quirk_s3_64M(struct pci_dev *dev)
236{
237 struct resource *r = &dev->resource[0];
238
239 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
240 r->start = 0;
241 r->end = 0x3ffffff;
242 }
243}
244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
246
6693e74a
LT		 247static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
248 unsigned size, int nr, const char *name)
1da177e4
LT		 249{
250 region &= ~(size-1);
251 if (region) {
085ae41f 252 struct pci_bus_region bus_region;
1da177e4
LT		 253 struct resource *res = dev->resource + nr;
254
255 res->name = pci_name(dev);
256 res->start = region;
257 res->end = region + size - 1;
258 res->flags = IORESOURCE_IO;
085ae41f
DM		 259
260 /* Convert from PCI bus to resource space. */
261 bus_region.start = res->start;
262 bus_region.end = res->end;
263 pcibios_bus_to_resource(dev, res, &bus_region);
264
1da177e4 265 pci_claim_resource(dev, nr);
6693e74a 266 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 267 }
268}
269
270/*
271 * ATI Northbridge setups MCE the processor if you even
272 * read somewhere between 0x3b0->0x3bb or read 0x3d3
273 */
274static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
275{
276 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
277 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
278 request_region(0x3b0, 0x0C, "RadeonIGP");
279 request_region(0x3d3, 0x01, "RadeonIGP");
280}
281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
282
283/*
284 * Let's make the southbridge information explicit instead
285 * of having to worry about people probing the ACPI areas,
286 * for example.. (Yes, it happens, and if you read the wrong
287 * ACPI register it will put the machine to sleep with no
288 * way of waking it up again. Bummer).
289 *
290 * ALI M7101: Two IO regions pointed to by words at
291 * 0xE0 (64 bytes of ACPI registers)
292 * 0xE2 (32 bytes of SMB registers)
293 */
294static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
295{
296 u16 region;
297
298 pci_read_config_word(dev, 0xE0, &region);
6693e74a 299 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 300 pci_read_config_word(dev, 0xE2, &region);
6693e74a 301 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 302}
303DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
304
6693e74a
LT		 305static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
306{
307 u32 devres;
308 u32 mask, size, base;
309
310 pci_read_config_dword(dev, port, &devres);
311 if ((devres & enable) != enable)
312 return;
313 mask = (devres >> 16) & 15;
314 base = devres & 0xffff;
315 size = 16;
316 for (;;) {
317 unsigned bit = size >> 1;
318 if ((bit & mask) == bit)
319 break;
320 size = bit;
321 }
322 /*
323 * For now we only print it out. Eventually we'll want to
324 * reserve it (at least if it's in the 0x1000+ range), but
325 * let's get enough confirmation reports first.
326 */
327 base &= -size;
328 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
329}
330
331static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
332{
333 u32 devres;
334 u32 mask, size, base;
335
336 pci_read_config_dword(dev, port, &devres);
337 if ((devres & enable) != enable)
338 return;
339 base = devres & 0xffff0000;
340 mask = (devres & 0x3f) << 16;
341 size = 128 << 16;
342 for (;;) {
343 unsigned bit = size >> 1;
344 if ((bit & mask) == bit)
345 break;
346 size = bit;
347 }
348 /*
349 * For now we only print it out. Eventually we'll want to
350 * reserve it, but let's get enough confirmation reports first.
351 */
352 base &= -size;
353 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
354}
355
1da177e4
LT		 356/*
357 * PIIX4 ACPI: Two IO regions pointed to by longwords at
358 * 0x40 (64 bytes of ACPI registers)
08db2a70 359 * 0x90 (16 bytes of SMB registers)
6693e74a 360 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 361 */
362static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
363{
6693e74a 364 u32 region, res_a;
1da177e4
LT		 365
366 pci_read_config_dword(dev, 0x40, &region);
6693e74a 367 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 368 pci_read_config_dword(dev, 0x90, &region);
08db2a70 369 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 370
371 /* Device resource A has enables for some of the other ones */
372 pci_read_config_dword(dev, 0x5c, &res_a);
373
374 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
375 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
376
377 /* Device resource D is just bitfields for static resources */
378
379 /* Device 12 enabled? */
380 if (res_a & (1 << 29)) {
381 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
382 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
383 }
384 /* Device 13 enabled? */
385 if (res_a & (1 << 30)) {
386 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
387 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
388 }
389 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
390 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 391}
392DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
393
394/*
395 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
396 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
397 * 0x58 (64 bytes of GPIO I/O space)
398 */
399static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
400{
401 u32 region;
402
403 pci_read_config_dword(dev, 0x40, &region);
6693e74a 404 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 405
406 pci_read_config_dword(dev, 0x58, &region);
6693e74a 407 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 408}
409DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
411DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
412DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
413DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
414DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 418DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 419
2cea752f
M		 420static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
421{
422 u32 region;
423
424 pci_read_config_dword(dev, 0x40, &region);
425 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
426
427 pci_read_config_dword(dev, 0x48, &region);
428 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
429}
430DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
431
1da177e4
LT		 432/*
433 * VIA ACPI: One IO region pointed to by longword at
434 * 0x48 or 0x20 (256 bytes of ACPI registers)
435 */
436static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
437{
438 u8 rev;
439 u32 region;
440
441 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
442 if (rev & 0x10) {
443 pci_read_config_dword(dev, 0x48, &region);
444 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 445 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 446 }
447}
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
449
450/*
451 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
452 * 0x48 (256 bytes of ACPI registers)
453 * 0x70 (128 bytes of hardware monitoring register)
454 * 0x90 (16 bytes of SMB registers)
455 */
456static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
457{
458 u16 hm;
459 u32 smb;
460
461 quirk_vt82c586_acpi(dev);
462
463 pci_read_config_word(dev, 0x70, &hm);
464 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 465 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 466
467 pci_read_config_dword(dev, 0x90, &smb);
468 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 469 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 470}
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
472
6d85f29b
IK		 473/*
474 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
475 * 0x88 (128 bytes of power management registers)
476 * 0xd0 (16 bytes of SMB registers)
477 */
478static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
479{
480 u16 pm, smb;
481
482 pci_read_config_word(dev, 0x88, &pm);
483 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 484 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 485
486 pci_read_config_word(dev, 0xd0, &smb);
487 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 488 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 489}
490DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
491
1da177e4
LT		 492
493#ifdef CONFIG_X86_IO_APIC
494
495#include <asm/io_apic.h>
496
497/*
498 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
499 * devices to the external APIC.
500 *
501 * TODO: When we have device-specific interrupt routers,
502 * this code will go away from quirks.
503 */
504static void __devinit quirk_via_ioapic(struct pci_dev *dev)
505{
506 u8 tmp;
507
508 if (nr_ioapics < 1)
509 tmp = 0; /* nothing routed to external APIC */
510 else
511 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
512
513 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
514 tmp == 0 ? "Disa" : "Ena");
515
516 /* Offset 0x58: External APIC IRQ output control */
517 pci_write_config_byte (dev, 0x58, tmp);
518}
519DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
520
a1740913
KW		 521/*
522 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
523 * This leads to doubled level interrupt rates.
524 * Set this bit to get rid of cycle wastage.
525 * Otherwise uncritical.
526 */
527static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
528{
529 u8 misc_control2;
530#define BYPASS_APIC_DEASSERT 8
531
532 pci_read_config_byte(dev, 0x5B, &misc_control2);
533 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
534 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
535 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
536 }
537}
538DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
539
1da177e4
LT		 540/*
541 * The AMD io apic can hang the box when an apic irq is masked.
542 * We check all revs >= B0 (yet not in the pre production!) as the bug
543 * is currently marked NoFix
544 *
545 * We have multiple reports of hangs with this chipset that went away with
546 * noapic specified. For the moment we assume its the errata. We may be wrong
547 * of course. However the advice is demonstrably good even if so..
548 */
549static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
550{
551 u8 rev;
552
553 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
554 if (rev >= 0x02) {
555 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
556 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
557 }
558}
559DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
560
561static void __init quirk_ioapic_rmw(struct pci_dev *dev)
562{
563 if (dev->devfn == 0 && dev->bus->number == 0)
564 sis_apic_bug = 1;
565}
566DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
567
568int pci_msi_quirk;
569
570#define AMD8131_revA0 0x01
571#define AMD8131_revB0 0x11
572#define AMD8131_MISC 0x40
573#define AMD8131_NIOAMODE_BIT 0
574static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
575{
576 unsigned char revid, tmp;
577
6e325a62
MT		 578 if (dev->subordinate) {
579 printk(KERN_WARNING "PCI: MSI quirk detected. "
580 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
581 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
582 }
1da177e4
LT		 583
584 if (nr_ioapics == 0)
585 return;
586
587 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
588 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
589 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
590 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
591 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
592 pci_write_config_byte( dev, AMD8131_MISC, tmp);
593 }
594}
5da594b1 595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4 596
1e062767
NS		 597static void __init quirk_svw_msi(struct pci_dev *dev)
598{
599 pci_msi_quirk = 1;
600 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
601}
602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
1da177e4
LT		 603#endif /* CONFIG_X86_IO_APIC */
604
605
1da177e4
LT		 606/*
607 * FIXME: it is questionable that quirk_via_acpi
608 * is needed. It shows up as an ISA bridge, and does not
609 * support the PCI_INTERRUPT_LINE register at all. Therefore
610 * it seems like setting the pci_dev's 'irq' to the
611 * value of the ACPI SCI interrupt is only done for convenience.
612 * -jgarzik
613 */
614static void __devinit quirk_via_acpi(struct pci_dev *d)
615{
616 /*
617 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
618 */
619 u8 irq;
620 pci_read_config_byte(d, 0x42, &irq);
621 irq &= 0xf;
622 if (irq && (irq != 2))
623 d->irq = irq;
624}
625DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
626DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
627
93cffffa
BH		 628/*
629 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
630 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
631 * when written, it makes an internal connection to the PIC.
632 * For these devices, this register is defined to be 4 bits wide.
633 * Normally this is fine. However for IO-APIC motherboards, or
634 * non-x86 architectures (yes Via exists on PPC among other places),
635 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
636 * interrupts delivered properly.
637 */
638static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 639{
640 u8 irq, new_irq;
641
25be5e6c
LB		 642 new_irq = dev->irq & 0xf;
643 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
644 if (new_irq != irq) {
75cf7456 645 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 646 pci_name(dev), irq, new_irq);
647 udelay(15); /* unknown if delay really needed */
648 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
649 }
650}
75cf7456
CW		 651DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
652DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
653DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
25be5e6c 654
1da177e4
LT		 655/*
656 * VIA VT82C598 has its device ID settable and many BIOSes
657 * set it to the ID of VT82C597 for backward compatibility.
658 * We need to switch it off to be able to recognize the real
659 * type of the chip.
660 */
661static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
662{
663 pci_write_config_byte(dev, 0xfc, 0);
664 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
665}
666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
667
668/*
669 * CardBus controllers have a legacy base address that enables them
670 * to respond as i82365 pcmcia controllers. We don't want them to
671 * do this even if the Linux CardBus driver is not loaded, because
672 * the Linux i82365 driver does not (and should not) handle CardBus.
673 */
674static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
675{
676 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
677 return;
678 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
679}
680DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
681
682/*
683 * Following the PCI ordering rules is optional on the AMD762. I'm not
684 * sure what the designers were smoking but let's not inhale...
685 *
686 * To be fair to AMD, it follows the spec by default, its BIOS people
687 * who turn it off!
688 */
689static void __devinit quirk_amd_ordering(struct pci_dev *dev)
690{
691 u32 pcic;
692 pci_read_config_dword(dev, 0x4C, &pcic);
693 if ((pcic&6)!=6) {
694 pcic |= 6;
695 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
696 pci_write_config_dword(dev, 0x4C, pcic);
697 pci_read_config_dword(dev, 0x84, &pcic);
698 pcic |= (1<<23); /* Required in this mode */
699 pci_write_config_dword(dev, 0x84, pcic);
700 }
701}
702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
703
704/*
705 * DreamWorks provided workaround for Dunord I-3000 problem
706 *
707 * This card decodes and responds to addresses not apparently
708 * assigned to it. We force a larger allocation to ensure that
709 * nothing gets put too close to it.
710 */
711static void __devinit quirk_dunord ( struct pci_dev * dev )
712{
713 struct resource *r = &dev->resource [1];
714 r->start = 0;
715 r->end = 0xffffff;
716}
717DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
718
719/*
720 * i82380FB mobile docking controller: its PCI-to-PCI bridge
721 * is subtractive decoding (transparent), and does indicate this
722 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
723 * instead of 0x01.
724 */
725static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
726{
727 dev->transparent = 1;
728}
729DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
730DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
731
732/*
733 * Common misconfiguration of the MediaGX/Geode PCI master that will
734 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
735 * datasheets found at http://www.national.com/ds/GX for info on what
736 * these bits do. <christer@weinigel.se>
737 */
738static void __init quirk_mediagx_master(struct pci_dev *dev)
739{
740 u8 reg;
741 pci_read_config_byte(dev, 0x41, &reg);
742 if (reg & 2) {
743 reg &= ~2;
744 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
745 pci_write_config_byte(dev, 0x41, reg);
746 }
747}
748DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
749
750/*
751 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
752 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
753 * secondary channels respectively). If the device reports Compatible mode
754 * but does use BAR0-3 for address decoding, we assume that firmware has
755 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
756 * Exceptions (if they exist) must be handled in chip/architecture specific
757 * fixups.
758 *
759 * Note: for non x86 people. You may need an arch specific quirk to handle
760 * moving IDE devices to native mode as well. Some plug in card devices power
761 * up in compatible mode and assume the BIOS will adjust them.
762 *
763 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
764 * we do now ? We don't want is pci_enable_device to come along
765 * and assign new resources. Both approaches work for that.
766 */
767static void __devinit quirk_ide_bases(struct pci_dev *dev)
768{
769 struct resource *res;
770 int first_bar = 2, last_bar = 0;
771
772 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
773 return;
774
775 res = &dev->resource[0];
776
777 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
778 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
779 res[0].start = res[0].end = res[0].flags = 0;
780 res[1].start = res[1].end = res[1].flags = 0;
781 first_bar = 0;
782 last_bar = 1;
783 }
784
785 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
786 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
787 res[2].start = res[2].end = res[2].flags = 0;
788 res[3].start = res[3].end = res[3].flags = 0;
789 last_bar = 3;
790 }
791
792 if (!last_bar)
793 return;
794
795 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
796 first_bar, last_bar, pci_name(dev));
797}
798DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
799
800/*
801 * Ensure C0 rev restreaming is off. This is normally done by
802 * the BIOS but in the odd case it is not the results are corruption
803 * hence the presence of a Linux check
804 */
805static void __init quirk_disable_pxb(struct pci_dev *pdev)
806{
807 u16 config;
808 u8 rev;
809
810 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
811 if (rev != 0x04) /* Only C0 requires this */
812 return;
813 pci_read_config_word(pdev, 0x40, &config);
814 if (config & (1<<6)) {
815 config &= ~(1<<6);
816 pci_write_config_word(pdev, 0x40, config);
817 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
818 }
819}
820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
821
1da177e4
LT		 822
823/*
824 * Serverworks CSB5 IDE does not fully support native mode
825 */
826static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
827{
828 u8 prog;
829 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
830 if (prog & 5) {
831 prog &= ~5;
832 pdev->class &= ~5;
833 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
834 /* need to re-assign BARs for compat mode */
835 quirk_ide_bases(pdev);
836 }
837}
838DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
839
840/*
841 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
842 */
843static void __init quirk_ide_samemode(struct pci_dev *pdev)
844{
845 u8 prog;
846
847 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
848
849 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
850 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
851 prog &= ~5;
852 pdev->class &= ~5;
853 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
854 /* need to re-assign BARs for compat mode */
855 quirk_ide_bases(pdev);
856 }
857}
858DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
859
860/* This was originally an Alpha specific thing, but it really fits here.
861 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
862 */
863static void __init quirk_eisa_bridge(struct pci_dev *dev)
864{
865 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
866}
867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
868
7daa0c4f
JG		 869/*
870 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
871 * when a PCI-Soundcard is added. The BIOS only gives Options
872 * "Disabled" and "AUTO". This Quirk Sets the corresponding
873 * Register-Value to enable the Soundcard.
874 */
875static void __init k8t_sound_hostbridge(struct pci_dev *dev)
876{
877 unsigned char val;
878
879 printk(KERN_INFO "PCI: Quirk-MSI-K8T Soundcard On\n");
880 pci_read_config_byte(dev, 0x50, &val);
881 if (val == 0x88 || val == 0xc8) {
882 pci_write_config_byte(dev, 0x50, val & (~0x40));
883
884 /* Verify the Change for Status output */
885 pci_read_config_byte(dev, 0x50, &val);
886 if (val & 0x40)
887 printk(KERN_INFO "PCI: MSI-K8T soundcard still off\n");
888 else
889 printk(KERN_INFO "PCI: MSI-K8T soundcard on\n");
890 } else {
891 printk(KERN_INFO "PCI: Unexpected Value in PCI-Register: "
892 "no Change!\n");
893 }
894
895}
896DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
897
1da177e4
LT		 898/*
899 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
900 * is not activated. The myth is that Asus said that they do not want the
901 * users to be irritated by just another PCI Device in the Win98 device
902 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
903 * package 2.7.0 for details)
904 *
905 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
906 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
907 * becomes necessary to do this tweak in two steps -- I've chosen the Host
908 * bridge as trigger.
909 */
910static int __initdata asus_hides_smbus = 0;
911
912static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
913{
914 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
915 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
916 switch(dev->subsystem_device) {
a00db371 917 case 0x8025: /* P4B-LX */
1da177e4
LT		 918 case 0x8070: /* P4B */
919 case 0x8088: /* P4B533 */
920 case 0x1626: /* L3C notebook */
921 asus_hides_smbus = 1;
922 }
923 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
924 switch(dev->subsystem_device) {
925 case 0x80b1: /* P4GE-V */
926 case 0x80b2: /* P4PE */
927 case 0x8093: /* P4B533-V */
928 asus_hides_smbus = 1;
929 }
930 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
931 switch(dev->subsystem_device) {
932 case 0x8030: /* P4T533 */
933 asus_hides_smbus = 1;
934 }
935 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
936 switch (dev->subsystem_device) {
937 case 0x8070: /* P4G8X Deluxe */
938 asus_hides_smbus = 1;
939 }
940 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
941 switch (dev->subsystem_device) {
942 case 0x1751: /* M2N notebook */
943 case 0x1821: /* M5N notebook */
944 asus_hides_smbus = 1;
945 }
946 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
947 switch (dev->subsystem_device) {
948 case 0x184b: /* W1N notebook */
949 case 0x186a: /* M6Ne notebook */
950 asus_hides_smbus = 1;
951 }
acc06632
M		 952 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
953 switch (dev->subsystem_device) {
954 case 0x1882: /* M6V notebook */
2d1e1c75 955 case 0x1977: /* A6VA notebook */
acc06632
M		 956 asus_hides_smbus = 1;
957 }
958 }
1da177e4
LT		 959 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
960 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
961 switch(dev->subsystem_device) {
962 case 0x088C: /* HP Compaq nc8000 */
963 case 0x0890: /* HP Compaq nc6000 */
964 asus_hides_smbus = 1;
965 }
966 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
967 switch (dev->subsystem_device) {
968 case 0x12bc: /* HP D330L */
e3b1bd57 969 case 0x12bd: /* HP D530 */
1da177e4
LT		 970 asus_hides_smbus = 1;
971 }
3c0a654e 972 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
973 switch (dev->subsystem_device) {
974 case 0x099c: /* HP Compaq nx6110 */
975 asus_hides_smbus = 1;
976 }
977 }
1da177e4
LT		 978 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
979 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
980 switch(dev->subsystem_device) {
981 case 0x0001: /* Toshiba Satellite A40 */
982 asus_hides_smbus = 1;
983 }
e96e2f14
DG		 984 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
985 switch(dev->subsystem_device) {
986 case 0x0001: /* Toshiba Tecra M2 */
987 asus_hides_smbus = 1;
988 }
1da177e4
LT		 989 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
990 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
991 switch(dev->subsystem_device) {
992 case 0xC00C: /* Samsung P35 notebook */
993 asus_hides_smbus = 1;
994 }
c87f883e
RIZ		 995 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
996 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
997 switch(dev->subsystem_device) {
998 case 0x0058: /* Compaq Evo N620c */
999 asus_hides_smbus = 1;
1000 }
1da177e4
LT		 1001 }
1002}
1003DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1004DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1005DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1006DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1007DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1008DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1009DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1010DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1011
1012static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1013{
1014 u16 val;
1015
1016 if (likely(!asus_hides_smbus))
1017 return;
1018
1019 pci_read_config_word(dev, 0xF2, &val);
1020 if (val & 0x8) {
1021 pci_write_config_word(dev, 0xF2, val & (~0x8));
1022 pci_read_config_word(dev, 0xF2, &val);
1023 if (val & 0x8)
1024 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1025 else
1026 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1027 }
1028}
1029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1033DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
2d1e1c75 1034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc );
1da177e4 1035
acc06632
M		 1036static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1037{
1038 u32 val, rcba;
1039 void __iomem *base;
1040
1041 if (likely(!asus_hides_smbus))
1042 return;
1043 pci_read_config_dword(dev, 0xF0, &rcba);
1044 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1045 if (base == NULL) return;
1046 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1047 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1048 iounmap(base);
1049 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1050}
1051DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1052
1da177e4
LT		 1053/*
1054 * SiS 96x south bridge: BIOS typically hides SMBus device...
1055 */
1056static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1057{
1058 u8 val = 0;
1059 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1060 pci_read_config_byte(dev, 0x77, &val);
1061 pci_write_config_byte(dev, 0x77, val & ~0x10);
1062 pci_read_config_byte(dev, 0x77, &val);
1063}
1064
1da177e4
LT		 1065/*
1066 * ... This is further complicated by the fact that some SiS96x south
1067 * bridges pretend to be 85C503/5513 instead. In that case see if we
1068 * spotted a compatible north bridge to make sure.
1069 * (pci_find_device doesn't work yet)
1070 *
1071 * We can also enable the sis96x bit in the discovery register..
1072 */
1073static int __devinitdata sis_96x_compatible = 0;
1074
1075#define SIS_DETECT_REGISTER 0x40
1076
1077static void __init quirk_sis_503(struct pci_dev *dev)
1078{
1079 u8 reg;
1080 u16 devid;
1081
1082 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1083 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1084 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1085 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1086 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1087 return;
1088 }
1089
1090 /* Make people aware that we changed the config.. */
1091 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1092
1093 /*
1094 * Ok, it now shows up as a 96x.. The 96x quirks are after
1095 * the 503 quirk in the quirk table, so they'll automatically
1096 * run and enable things like the SMBus device
1097 */
1098 dev->device = devid;
1099}
1100
1101static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1102{
1103 sis_96x_compatible = 1;
1104}
1105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1107DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1108DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1109DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1110DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1111
1112DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1113/*
1114 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1115 * and MC97 modem controller are disabled when a second PCI soundcard is
1116 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1117 * -- bjd
1118 */
1119static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1120{
1121 u8 val;
1122 int asus_hides_ac97 = 0;
1123
1124 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1125 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1126 asus_hides_ac97 = 1;
1127 }
1128
1129 if (!asus_hides_ac97)
1130 return;
1131
1132 pci_read_config_byte(dev, 0x50, &val);
1133 if (val & 0xc0) {
1134 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1135 pci_read_config_byte(dev, 0x50, &val);
1136 if (val & 0xc0)
1137 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1138 else
1139 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1140 }
1141}
1142DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1143
1da177e4
LT		 1144
1145DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1146DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1148DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1149
1150#ifdef CONFIG_X86_IO_APIC
1151static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1152{
1153 int i;
1154
1155 if ((pdev->class >> 8) != 0xff00)
1156 return;
1157
1158 /* the first BAR is the location of the IO APIC...we must
1159 * not touch this (and it's already covered by the fixmap), so
1160 * forcibly insert it into the resource tree */
1161 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1162 insert_resource(&iomem_resource, &pdev->resource[0]);
1163
1164 /* The next five BARs all seem to be rubbish, so just clean
1165 * them out */
1166 for (i=1; i < 6; i++) {
1167 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1168 }
1169
1170}
1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1172#endif
1173
2bd0fa3b
JB		 1174enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1175/* Defaults to combined */
1176static enum ide_combined_type combined_mode;
1177
1178static int __init combined_setup(char *str)
1179{
1180 if (!strncmp(str, "ide", 3))
1181 combined_mode = IDE;
1182 else if (!strncmp(str, "libata", 6))
1183 combined_mode = LIBATA;
1184 else /* "combined" or anything else defaults to old behavior */
1185 combined_mode = COMBINED;
1186
1187 return 1;
1188}
1189__setup("combined_mode=", combined_setup);
1190
cc675230 1191#ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1da177e4
LT		 1192static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1193{
1194 u8 prog, comb, tmp;
1195 int ich = 0;
1196
1197 /*
1198 * Narrow down to Intel SATA PCI devices.
1199 */
1200 switch (pdev->device) {
1201 /* PCI ids taken from drivers/scsi/ata_piix.c */
1202 case 0x24d1:
1203 case 0x24df:
1204 case 0x25a3:
1205 case 0x25b0:
1206 ich = 5;
1207 break;
1208 case 0x2651:
1209 case 0x2652:
1210 case 0x2653:
c368ca4e 1211 case 0x2680: /* ESB2 */
1da177e4
LT		 1212 ich = 6;
1213 break;
1214 case 0x27c0:
1215 case 0x27c4:
1216 ich = 7;
1217 break;
012b265f
JG		 1218 case 0x2828: /* ICH8M */
1219 ich = 8;
1220 break;
1da177e4
LT		 1221 default:
1222 /* we do not handle this PCI device */
1223 return;
1224 }
1225
1226 /*
1227 * Read combined mode register.
1228 */
1229 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1230
1231 if (ich == 5) {
1232 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1233 if (tmp == 0x4) /* bits 10x */
1234 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1235 else if (tmp == 0x6) /* bits 11x */
1236 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1237 else
1238 return; /* not in combined mode */
1239 } else {
012b265f 1240 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1241 tmp &= 0x3; /* interesting bits 1:0 */
1242 if (tmp & (1 << 0))
1243 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1244 else if (tmp & (1 << 1))
1245 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1246 else
1247 return; /* not in combined mode */
1248 }
1249
1250 /*
1251 * Read programming interface register.
1252 * (Tells us if it's legacy or native mode)
1253 */
1254 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1255
1256 /* if SATA port is in native mode, we're ok. */
1257 if (prog & comb)
1258 return;
1259
2bd0fa3b
JB		 1260 /* Don't reserve any so the IDE driver can get them (but only if
1261 * combined_mode=ide).
1262 */
1263 if (combined_mode == IDE)
1264 return;
1265
1266 /* Grab them both for libata if combined_mode=libata. */
1267 if (combined_mode == LIBATA) {
1268 request_region(0x1f0, 8, "libata"); /* port 0 */
1269 request_region(0x170, 8, "libata"); /* port 1 */
1270 return;
1271 }
1272
1da177e4
LT		 1273 /* SATA port is in legacy mode. Reserve port so that
1274 * IDE driver does not attempt to use it. If request_region
1275 * fails, it will be obvious at boot time, so we don't bother
1276 * checking return values.
1277 */
1278 if (comb == (1 << 0))
1279 request_region(0x1f0, 8, "libata"); /* port 0 */
1280 else
1281 request_region(0x170, 8, "libata"); /* port 1 */
1282}
1283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
cc675230 1284#endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1da177e4
LT		 1285
1286
1287int pcie_mch_quirk;
1288
1289static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1290{
1291 pcie_mch_quirk = 1;
1292}
1293DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1294DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1295DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1296
4602b88d
KA		 1297
1298/*
1299 * It's possible for the MSI to get corrupted if shpc and acpi
1300 * are used together on certain PXH-based systems.
1301 */
1302static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1303{
1304 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1305 PCI_CAP_ID_MSI);
1306 dev->no_msi = 1;
1307
1308 printk(KERN_WARNING "PCI: PXH quirk detected, "
1309 "disabling MSI for SHPC device\n");
1310}
1311DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1312DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1313DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1314DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1315DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1316
1317
c408a379
KA		 1318/*
1319 * Fixup the cardbus bridges on the IBM Dock II docking station
1320 */
1321static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1322{
1323 u32 val;
1324
1325 /*
1326 * tie the 2 interrupt pins to INTA, and configure the
1327 * multifunction routing register to handle this.
1328 */
1329 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1330 (dev->subsystem_device == 0x0148)) {
1331 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1332 "applying quirk\n");
1333 pci_read_config_dword(dev, 0x8c, &val);
1334 val = ((val & 0xffffff00) | 0x1002);
1335 pci_write_config_dword(dev, 0x8c, val);
1336 pci_read_config_dword(dev, 0x80, &val);
1337 val = ((val & 0x00ffff00) | 0x2864c077);
1338 pci_write_config_dword(dev, 0x80, val);
1339 }
1340}
1341
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1343 quirk_ibm_dock2_cardbus);
1344
1da177e4
LT		 1345static void __devinit quirk_netmos(struct pci_dev *dev)
1346{
1347 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1348 unsigned int num_serial = dev->subsystem_device & 0xf;
1349
1350 /*
1351 * These Netmos parts are multiport serial devices with optional
1352 * parallel ports. Even when parallel ports are present, they
1353 * are identified as class SERIAL, which means the serial driver
1354 * will claim them. To prevent this, mark them as class OTHER.
1355 * These combo devices should be claimed by parport_serial.
1356 *
1357 * The subdevice ID is of the form 0x00PS, where <P> is the number
1358 * of parallel ports and <S> is the number of serial ports.
1359 */
1360 switch (dev->device) {
1361 case PCI_DEVICE_ID_NETMOS_9735:
1362 case PCI_DEVICE_ID_NETMOS_9745:
1363 case PCI_DEVICE_ID_NETMOS_9835:
1364 case PCI_DEVICE_ID_NETMOS_9845:
1365 case PCI_DEVICE_ID_NETMOS_9855:
1366 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1367 num_parallel) {
1368 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1369 "%u serial); changing class SERIAL to OTHER "
1370 "(use parport_serial)\n",
1371 dev->device, num_parallel, num_serial);
1372 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1373 (dev->class & 0xff);
1374 }
1375 }
1376}
1377DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1378
a5312e28
IK		 1379
1380static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1381{
1382 /* rev 1 ncr53c810 chips don't set the class at all which means
1383 * they don't get their resources remapped. Fix that here.
1384 */
1385
1386 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1387 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1388 dev->class = PCI_CLASS_STORAGE_SCSI;
1389 }
1390}
1391DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1392
1393
1da177e4
LT		 1394static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1395{
1396 while (f < end) {
1397 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1398 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1399 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1400 f->hook(dev);
1401 }
1402 f++;
1403 }
1404}
1405
1406extern struct pci_fixup __start_pci_fixups_early[];
1407extern struct pci_fixup __end_pci_fixups_early[];
1408extern struct pci_fixup __start_pci_fixups_header[];
1409extern struct pci_fixup __end_pci_fixups_header[];
1410extern struct pci_fixup __start_pci_fixups_final[];
1411extern struct pci_fixup __end_pci_fixups_final[];
1412extern struct pci_fixup __start_pci_fixups_enable[];
1413extern struct pci_fixup __end_pci_fixups_enable[];
1414
1415
1416void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1417{
1418 struct pci_fixup *start, *end;
1419
1420 switch(pass) {
1421 case pci_fixup_early:
1422 start = __start_pci_fixups_early;
1423 end = __end_pci_fixups_early;
1424 break;
1425
1426 case pci_fixup_header:
1427 start = __start_pci_fixups_header;
1428 end = __end_pci_fixups_header;
1429 break;
1430
1431 case pci_fixup_final:
1432 start = __start_pci_fixups_final;
1433 end = __end_pci_fixups_final;
1434 break;
1435
1436 case pci_fixup_enable:
1437 start = __start_pci_fixups_enable;
1438 end = __end_pci_fixups_enable;
1439 break;
1440
1441 default:
1442 /* stupid compiler warning, you would think with an enum... */
1443 return;
1444 }
1445 pci_do_fixups(dev, start, end);
1446}
1447
9d265124
DY		 1448/* Enable 1k I/O space granularity on the Intel P64H2 */
1449static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1450{
1451 u16 en1k;
1452 u8 io_base_lo, io_limit_lo;
1453 unsigned long base, limit;
1454 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1455
1456 pci_read_config_word(dev, 0x40, &en1k);
1457
1458 if (en1k & 0x200) {
1459 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1460
1461 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1462 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1463 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1464 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1465
1466 if (base <= limit) {
1467 res->start = base;
1468 res->end = limit + 0x3ff;
1469 }
1470 }
1471}
1472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1473
1da177e4
LT		 1474EXPORT_SYMBOL(pcie_mch_quirk);
1475#ifdef CONFIG_HOTPLUG
1476EXPORT_SYMBOL(pci_fixup_device);
1477#endif
Linux kernel - Deliverables
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