Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for many known PCI hardware | |
3 | * bugs. Devices present only on certain architectures (host | |
4 | * bridges et cetera) should be handled in arch-specific code. | |
5 | * | |
6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. | |
7 | * | |
8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
9 | * | |
7586269c DB |
10 | * Init/reset quirks for USB host controllers should be in the |
11 | * USB quirks file, where their drivers can access reuse it. | |
12 | * | |
1da177e4 LT |
13 | * The bridge optimization stuff has been removed. If you really |
14 | * have a silly BIOS which is unable to set your host bridge right, | |
15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
25be5e6c | 23 | #include <linux/acpi.h> |
9f23ed3b | 24 | #include <linux/kallsyms.h> |
75e07fc3 | 25 | #include <linux/dmi.h> |
649426ef | 26 | #include <linux/pci-aspm.h> |
32a9a682 | 27 | #include <linux/ioport.h> |
93177a74 | 28 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 29 | #include "pci.h" |
1da177e4 | 30 | |
32a9a682 | 31 | /* |
0cdbe30f YS |
32 | * This quirk function disables memory decoding and releases memory resources |
33 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
32a9a682 YS |
34 | * It also rounds up size to specified alignment. |
35 | * Later on, the kernel will assign page-aligned memory resource back | |
0cdbe30f | 36 | * to the device. |
32a9a682 YS |
37 | */ |
38 | static void __devinit quirk_resource_alignment(struct pci_dev *dev) | |
39 | { | |
40 | int i; | |
41 | struct resource *r; | |
42 | resource_size_t align, size; | |
0cdbe30f | 43 | u16 command; |
32a9a682 YS |
44 | |
45 | if (!pci_is_reassigndev(dev)) | |
46 | return; | |
47 | ||
48 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
49 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
50 | dev_warn(&dev->dev, | |
51 | "Can't reassign resources to host bridge.\n"); | |
52 | return; | |
53 | } | |
54 | ||
0cdbe30f YS |
55 | dev_info(&dev->dev, |
56 | "Disabling memory decoding and releasing memory resources.\n"); | |
57 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
58 | command &= ~PCI_COMMAND_MEMORY; | |
59 | pci_write_config_word(dev, PCI_COMMAND, command); | |
32a9a682 YS |
60 | |
61 | align = pci_specified_resource_alignment(dev); | |
62 | for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { | |
63 | r = &dev->resource[i]; | |
64 | if (!(r->flags & IORESOURCE_MEM)) | |
65 | continue; | |
66 | size = resource_size(r); | |
67 | if (size < align) { | |
68 | size = align; | |
69 | dev_info(&dev->dev, | |
70 | "Rounding up size of resource #%d to %#llx.\n", | |
71 | i, (unsigned long long)size); | |
72 | } | |
73 | r->end = size - 1; | |
74 | r->start = 0; | |
75 | } | |
76 | /* Need to disable bridge's resource window, | |
77 | * to enable the kernel to reassign new resource | |
78 | * window later on. | |
79 | */ | |
80 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
81 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
82 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
83 | r = &dev->resource[i]; | |
84 | if (!(r->flags & IORESOURCE_MEM)) | |
85 | continue; | |
86 | r->end = resource_size(r) - 1; | |
87 | r->start = 0; | |
88 | } | |
89 | pci_disable_bridge_window(dev); | |
90 | } | |
91 | } | |
92 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); | |
93 | ||
bd8481e1 DT |
94 | /* The Mellanox Tavor device gives false positive parity errors |
95 | * Mark this device with a broken_parity_status, to allow | |
96 | * PCI scanning code to "skip" this now blacklisted device. | |
97 | */ | |
98 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) | |
99 | { | |
100 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
101 | } | |
102 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); | |
103 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); | |
104 | ||
1da177e4 LT |
105 | /* Deal with broken BIOS'es that neglect to enable passive release, |
106 | which can cause problems in combination with the 82441FX/PPro MTRRs */ | |
1597cacb | 107 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
108 | { |
109 | struct pci_dev *d = NULL; | |
110 | unsigned char dlc; | |
111 | ||
112 | /* We have to make sure a particular bit is set in the PIIX3 | |
113 | ISA bridge, so we have to go out and find it. */ | |
114 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { | |
115 | pci_read_config_byte(d, 0x82, &dlc); | |
116 | if (!(dlc & 1<<1)) { | |
999da9fd | 117 | dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); |
1da177e4 LT |
118 | dlc |= 1<<1; |
119 | pci_write_config_byte(d, 0x82, dlc); | |
120 | } | |
121 | } | |
122 | } | |
652c538e AM |
123 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
124 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 LT |
125 | |
126 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround | |
127 | but VIA don't answer queries. If you happen to have good contacts at VIA | |
128 | ask them for me please -- Alan | |
129 | ||
130 | This appears to be BIOS not version dependent. So presumably there is a | |
131 | chipset level fix */ | |
1da177e4 LT |
132 | |
133 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) | |
134 | { | |
135 | if (!isa_dma_bridge_buggy) { | |
136 | isa_dma_bridge_buggy=1; | |
f0fda801 | 137 | dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); |
1da177e4 LT |
138 | } |
139 | } | |
140 | /* | |
141 | * Its not totally clear which chipsets are the problematic ones | |
142 | * We know 82C586 and 82C596 variants are affected. | |
143 | */ | |
652c538e AM |
144 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
145 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
146 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
147 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); | |
148 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); | |
149 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
150 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
1da177e4 | 151 | |
1da177e4 LT |
152 | /* |
153 | * Chipsets where PCI->PCI transfers vanish or hang | |
154 | */ | |
155 | static void __devinit quirk_nopcipci(struct pci_dev *dev) | |
156 | { | |
157 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { | |
f0fda801 | 158 | dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); |
1da177e4 LT |
159 | pci_pci_problems |= PCIPCI_FAIL; |
160 | } | |
161 | } | |
652c538e AM |
162 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
163 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 AC |
164 | |
165 | static void __devinit quirk_nopciamd(struct pci_dev *dev) | |
166 | { | |
167 | u8 rev; | |
168 | pci_read_config_byte(dev, 0x08, &rev); | |
169 | if (rev == 0x13) { | |
170 | /* Erratum 24 */ | |
f0fda801 | 171 | dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
236561e5 AC |
172 | pci_pci_problems |= PCIAGP_FAIL; |
173 | } | |
174 | } | |
652c538e | 175 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 LT |
176 | |
177 | /* | |
178 | * Triton requires workarounds to be used by the drivers | |
179 | */ | |
180 | static void __devinit quirk_triton(struct pci_dev *dev) | |
181 | { | |
182 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { | |
f0fda801 | 183 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
184 | pci_pci_problems |= PCIPCI_TRITON; |
185 | } | |
186 | } | |
652c538e AM |
187 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
188 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
189 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
190 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
191 | |
192 | /* | |
193 | * VIA Apollo KT133 needs PCI latency patch | |
194 | * Made according to a windows driver based patch by George E. Breese | |
195 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
196 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for | |
197 | * the info on which Mr Breese based his work. | |
198 | * | |
199 | * Updated based on further information from the site and also on | |
200 | * information provided by VIA | |
201 | */ | |
1597cacb | 202 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
203 | { |
204 | struct pci_dev *p; | |
1da177e4 LT |
205 | u8 busarb; |
206 | /* Ok we have a potential problem chipset here. Now see if we have | |
207 | a buggy southbridge */ | |
208 | ||
209 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); | |
210 | if (p!=NULL) { | |
1da177e4 LT |
211 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
212 | /* Check for buggy part revisions */ | |
2b1afa87 | 213 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
214 | goto exit; |
215 | } else { | |
216 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
217 | if (p==NULL) /* No problem parts */ | |
218 | goto exit; | |
1da177e4 | 219 | /* Check for buggy part revisions */ |
2b1afa87 | 220 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
221 | goto exit; |
222 | } | |
223 | ||
224 | /* | |
225 | * Ok we have the problem. Now set the PCI master grant to | |
226 | * occur every master grant. The apparent bug is that under high | |
227 | * PCI load (quite common in Linux of course) you can get data | |
228 | * loss when the CPU is held off the bus for 3 bus master requests | |
229 | * This happens to include the IDE controllers.... | |
230 | * | |
231 | * VIA only apply this fix when an SB Live! is present but under | |
232 | * both Linux and Windows this isnt enough, and we have seen | |
233 | * corruption without SB Live! but with things like 3 UDMA IDE | |
234 | * controllers. So we ignore that bit of the VIA recommendation.. | |
235 | */ | |
236 | ||
237 | pci_read_config_byte(dev, 0x76, &busarb); | |
238 | /* Set bit 4 and bi 5 of byte 76 to 0x01 | |
239 | "Master priority rotation on every PCI master grant */ | |
240 | busarb &= ~(1<<5); | |
241 | busarb |= (1<<4); | |
242 | pci_write_config_byte(dev, 0x76, busarb); | |
f0fda801 | 243 | dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); |
1da177e4 LT |
244 | exit: |
245 | pci_dev_put(p); | |
246 | } | |
652c538e AM |
247 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
248 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
249 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 250 | /* Must restore this on a resume from RAM */ |
652c538e AM |
251 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
252 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
253 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 LT |
254 | |
255 | /* | |
256 | * VIA Apollo VP3 needs ETBF on BT848/878 | |
257 | */ | |
258 | static void __devinit quirk_viaetbf(struct pci_dev *dev) | |
259 | { | |
260 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { | |
f0fda801 | 261 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
262 | pci_pci_problems |= PCIPCI_VIAETBF; |
263 | } | |
264 | } | |
652c538e | 265 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 LT |
266 | |
267 | static void __devinit quirk_vsfx(struct pci_dev *dev) | |
268 | { | |
269 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { | |
f0fda801 | 270 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
271 | pci_pci_problems |= PCIPCI_VSFX; |
272 | } | |
273 | } | |
652c538e | 274 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
275 | |
276 | /* | |
277 | * Ali Magik requires workarounds to be used by the drivers | |
278 | * that DMA to AGP space. Latency must be set to 0xA and triton | |
279 | * workaround applied too | |
280 | * [Info kindly provided by ALi] | |
281 | */ | |
282 | static void __init quirk_alimagik(struct pci_dev *dev) | |
283 | { | |
284 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { | |
f0fda801 | 285 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
286 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
287 | } | |
288 | } | |
652c538e AM |
289 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
290 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 LT |
291 | |
292 | /* | |
293 | * Natoma has some interesting boundary conditions with Zoran stuff | |
294 | * at least | |
295 | */ | |
296 | static void __devinit quirk_natoma(struct pci_dev *dev) | |
297 | { | |
298 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { | |
f0fda801 | 299 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
300 | pci_pci_problems |= PCIPCI_NATOMA; |
301 | } | |
302 | } | |
652c538e AM |
303 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
304 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
305 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
306 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
307 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
308 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
309 | |
310 | /* | |
311 | * This chip can cause PCI parity errors if config register 0xA0 is read | |
312 | * while DMAs are occurring. | |
313 | */ | |
314 | static void __devinit quirk_citrine(struct pci_dev *dev) | |
315 | { | |
316 | dev->cfg_size = 0xA0; | |
317 | } | |
652c538e | 318 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 LT |
319 | |
320 | /* | |
321 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. | |
322 | * If it's needed, re-allocate the region. | |
323 | */ | |
324 | static void __devinit quirk_s3_64M(struct pci_dev *dev) | |
325 | { | |
326 | struct resource *r = &dev->resource[0]; | |
327 | ||
328 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
329 | r->start = 0; | |
330 | r->end = 0x3ffffff; | |
331 | } | |
332 | } | |
652c538e AM |
333 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
334 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 335 | |
73d2eaac AS |
336 | /* |
337 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS | |
338 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. | |
339 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k | |
340 | * (which conflicts w/ BAR1's memory range). | |
341 | */ | |
342 | static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) | |
343 | { | |
344 | if (pci_resource_len(dev, 0) != 8) { | |
345 | struct resource *res = &dev->resource[0]; | |
346 | res->end = res->start + 8 - 1; | |
347 | dev_info(&dev->dev, "CS5536 ISA bridge bug detected " | |
348 | "(incorrect header); workaround applied.\n"); | |
349 | } | |
350 | } | |
351 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); | |
352 | ||
6693e74a LT |
353 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
354 | unsigned size, int nr, const char *name) | |
1da177e4 LT |
355 | { |
356 | region &= ~(size-1); | |
357 | if (region) { | |
085ae41f | 358 | struct pci_bus_region bus_region; |
1da177e4 LT |
359 | struct resource *res = dev->resource + nr; |
360 | ||
361 | res->name = pci_name(dev); | |
362 | res->start = region; | |
363 | res->end = region + size - 1; | |
364 | res->flags = IORESOURCE_IO; | |
085ae41f DM |
365 | |
366 | /* Convert from PCI bus to resource space. */ | |
367 | bus_region.start = res->start; | |
368 | bus_region.end = res->end; | |
369 | pcibios_bus_to_resource(dev, res, &bus_region); | |
370 | ||
f967a443 BH |
371 | if (pci_claim_resource(dev, nr) == 0) |
372 | dev_info(&dev->dev, "quirk: %pR claimed by %s\n", | |
373 | res, name); | |
1da177e4 LT |
374 | } |
375 | } | |
376 | ||
377 | /* | |
378 | * ATI Northbridge setups MCE the processor if you even | |
379 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 | |
380 | */ | |
381 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) | |
382 | { | |
f0fda801 | 383 | dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
1da177e4 LT |
384 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
385 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
386 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
387 | } | |
652c538e | 388 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 LT |
389 | |
390 | /* | |
391 | * Let's make the southbridge information explicit instead | |
392 | * of having to worry about people probing the ACPI areas, | |
393 | * for example.. (Yes, it happens, and if you read the wrong | |
394 | * ACPI register it will put the machine to sleep with no | |
395 | * way of waking it up again. Bummer). | |
396 | * | |
397 | * ALI M7101: Two IO regions pointed to by words at | |
398 | * 0xE0 (64 bytes of ACPI registers) | |
399 | * 0xE2 (32 bytes of SMB registers) | |
400 | */ | |
401 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) | |
402 | { | |
403 | u16 region; | |
404 | ||
405 | pci_read_config_word(dev, 0xE0, ®ion); | |
6693e74a | 406 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
1da177e4 | 407 | pci_read_config_word(dev, 0xE2, ®ion); |
6693e74a | 408 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
1da177e4 | 409 | } |
652c538e | 410 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 411 | |
6693e74a LT |
412 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
413 | { | |
414 | u32 devres; | |
415 | u32 mask, size, base; | |
416 | ||
417 | pci_read_config_dword(dev, port, &devres); | |
418 | if ((devres & enable) != enable) | |
419 | return; | |
420 | mask = (devres >> 16) & 15; | |
421 | base = devres & 0xffff; | |
422 | size = 16; | |
423 | for (;;) { | |
424 | unsigned bit = size >> 1; | |
425 | if ((bit & mask) == bit) | |
426 | break; | |
427 | size = bit; | |
428 | } | |
429 | /* | |
430 | * For now we only print it out. Eventually we'll want to | |
431 | * reserve it (at least if it's in the 0x1000+ range), but | |
432 | * let's get enough confirmation reports first. | |
433 | */ | |
434 | base &= -size; | |
f0fda801 | 435 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
436 | } |
437 | ||
438 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
439 | { | |
440 | u32 devres; | |
441 | u32 mask, size, base; | |
442 | ||
443 | pci_read_config_dword(dev, port, &devres); | |
444 | if ((devres & enable) != enable) | |
445 | return; | |
446 | base = devres & 0xffff0000; | |
447 | mask = (devres & 0x3f) << 16; | |
448 | size = 128 << 16; | |
449 | for (;;) { | |
450 | unsigned bit = size >> 1; | |
451 | if ((bit & mask) == bit) | |
452 | break; | |
453 | size = bit; | |
454 | } | |
455 | /* | |
456 | * For now we only print it out. Eventually we'll want to | |
457 | * reserve it, but let's get enough confirmation reports first. | |
458 | */ | |
459 | base &= -size; | |
f0fda801 | 460 | dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
461 | } |
462 | ||
1da177e4 LT |
463 | /* |
464 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
465 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 466 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 467 | * and a few strange programmable PIIX4 device resources. |
1da177e4 LT |
468 | */ |
469 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) | |
470 | { | |
6693e74a | 471 | u32 region, res_a; |
1da177e4 LT |
472 | |
473 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 474 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
1da177e4 | 475 | pci_read_config_dword(dev, 0x90, ®ion); |
08db2a70 | 476 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
6693e74a LT |
477 | |
478 | /* Device resource A has enables for some of the other ones */ | |
479 | pci_read_config_dword(dev, 0x5c, &res_a); | |
480 | ||
481 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
482 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
483 | ||
484 | /* Device resource D is just bitfields for static resources */ | |
485 | ||
486 | /* Device 12 enabled? */ | |
487 | if (res_a & (1 << 29)) { | |
488 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
489 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
490 | } | |
491 | /* Device 13 enabled? */ | |
492 | if (res_a & (1 << 30)) { | |
493 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
494 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
495 | } | |
496 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
497 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 498 | } |
652c538e AM |
499 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
500 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 LT |
501 | |
502 | /* | |
503 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
504 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
505 | * 0x58 (64 bytes of GPIO I/O space) | |
506 | */ | |
507 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) | |
508 | { | |
509 | u32 region; | |
510 | ||
511 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 512 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
1da177e4 LT |
513 | |
514 | pci_read_config_dword(dev, 0x58, ®ion); | |
6693e74a | 515 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
1da177e4 | 516 | } |
652c538e AM |
517 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
518 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
519 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
520 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
521 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
522 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
523 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
524 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
525 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
526 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 527 | |
894886e5 | 528 | static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f M |
529 | { |
530 | u32 region; | |
531 | ||
532 | pci_read_config_dword(dev, 0x40, ®ion); | |
533 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); | |
534 | ||
535 | pci_read_config_dword(dev, 0x48, ®ion); | |
536 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); | |
537 | } | |
894886e5 LT |
538 | |
539 | static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) | |
540 | { | |
541 | u32 val; | |
542 | u32 size, base; | |
543 | ||
544 | pci_read_config_dword(dev, reg, &val); | |
545 | ||
546 | /* Enabled? */ | |
547 | if (!(val & 1)) | |
548 | return; | |
549 | base = val & 0xfffc; | |
550 | if (dynsize) { | |
551 | /* | |
552 | * This is not correct. It is 16, 32 or 64 bytes depending on | |
553 | * register D31:F0:ADh bits 5:4. | |
554 | * | |
555 | * But this gets us at least _part_ of it. | |
556 | */ | |
557 | size = 16; | |
558 | } else { | |
559 | size = 128; | |
560 | } | |
561 | base &= ~(size-1); | |
562 | ||
563 | /* Just print it out for now. We should reserve it after more debugging */ | |
564 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); | |
565 | } | |
566 | ||
567 | static void __devinit quirk_ich6_lpc(struct pci_dev *dev) | |
568 | { | |
569 | /* Shared ACPI/GPIO decode with all ICH6+ */ | |
570 | ich6_lpc_acpi_gpio(dev); | |
571 | ||
572 | /* ICH6-specific generic IO decode */ | |
573 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); | |
574 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); | |
575 | } | |
576 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); | |
577 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); | |
578 | ||
579 | static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) | |
580 | { | |
581 | u32 val; | |
582 | u32 mask, base; | |
583 | ||
584 | pci_read_config_dword(dev, reg, &val); | |
585 | ||
586 | /* Enabled? */ | |
587 | if (!(val & 1)) | |
588 | return; | |
589 | ||
590 | /* | |
591 | * IO base in bits 15:2, mask in bits 23:18, both | |
592 | * are dword-based | |
593 | */ | |
594 | base = val & 0xfffc; | |
595 | mask = (val >> 16) & 0xfc; | |
596 | mask |= 3; | |
597 | ||
598 | /* Just print it out for now. We should reserve it after more debugging */ | |
599 | dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); | |
600 | } | |
601 | ||
602 | /* ICH7-10 has the same common LPC generic IO decode registers */ | |
603 | static void __devinit quirk_ich7_lpc(struct pci_dev *dev) | |
604 | { | |
605 | /* We share the common ACPI/DPIO decode with ICH6 */ | |
606 | ich6_lpc_acpi_gpio(dev); | |
607 | ||
608 | /* And have 4 ICH7+ generic decodes */ | |
609 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); | |
610 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); | |
611 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); | |
612 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); | |
613 | } | |
614 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); | |
615 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); | |
616 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); | |
617 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); | |
618 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); | |
619 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); | |
620 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); | |
621 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); | |
622 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); | |
623 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); | |
624 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); | |
625 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); | |
626 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); | |
2cea752f | 627 | |
1da177e4 LT |
628 | /* |
629 | * VIA ACPI: One IO region pointed to by longword at | |
630 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
631 | */ | |
632 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) | |
633 | { | |
1da177e4 LT |
634 | u32 region; |
635 | ||
651472fb | 636 | if (dev->revision & 0x10) { |
1da177e4 LT |
637 | pci_read_config_dword(dev, 0x48, ®ion); |
638 | region &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 639 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
1da177e4 LT |
640 | } |
641 | } | |
652c538e | 642 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
643 | |
644 | /* | |
645 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
646 | * 0x48 (256 bytes of ACPI registers) | |
647 | * 0x70 (128 bytes of hardware monitoring register) | |
648 | * 0x90 (16 bytes of SMB registers) | |
649 | */ | |
650 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) | |
651 | { | |
652 | u16 hm; | |
653 | u32 smb; | |
654 | ||
655 | quirk_vt82c586_acpi(dev); | |
656 | ||
657 | pci_read_config_word(dev, 0x70, &hm); | |
658 | hm &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 659 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
1da177e4 LT |
660 | |
661 | pci_read_config_dword(dev, 0x90, &smb); | |
662 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 663 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
1da177e4 | 664 | } |
652c538e | 665 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 666 | |
6d85f29b IK |
667 | /* |
668 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
669 | * 0x88 (128 bytes of power management registers) | |
670 | * 0xd0 (16 bytes of SMB registers) | |
671 | */ | |
672 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) | |
673 | { | |
674 | u16 pm, smb; | |
675 | ||
676 | pci_read_config_word(dev, 0x88, &pm); | |
677 | pm &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 678 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
6d85f29b IK |
679 | |
680 | pci_read_config_word(dev, 0xd0, &smb); | |
681 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 682 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
6d85f29b IK |
683 | } |
684 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
685 | ||
1f56f4a2 GB |
686 | /* |
687 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: | |
688 | * Disable fast back-to-back on the secondary bus segment | |
689 | */ | |
690 | static void __devinit quirk_xio2000a(struct pci_dev *dev) | |
691 | { | |
692 | struct pci_dev *pdev; | |
693 | u16 command; | |
694 | ||
695 | dev_warn(&dev->dev, "TI XIO2000a quirk detected; " | |
696 | "secondary bus fast back-to-back transfers disabled\n"); | |
697 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { | |
698 | pci_read_config_word(pdev, PCI_COMMAND, &command); | |
699 | if (command & PCI_COMMAND_FAST_BACK) | |
700 | pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); | |
701 | } | |
702 | } | |
703 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, | |
704 | quirk_xio2000a); | |
1da177e4 LT |
705 | |
706 | #ifdef CONFIG_X86_IO_APIC | |
707 | ||
708 | #include <asm/io_apic.h> | |
709 | ||
710 | /* | |
711 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
712 | * devices to the external APIC. | |
713 | * | |
714 | * TODO: When we have device-specific interrupt routers, | |
715 | * this code will go away from quirks. | |
716 | */ | |
1597cacb | 717 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
718 | { |
719 | u8 tmp; | |
720 | ||
721 | if (nr_ioapics < 1) | |
722 | tmp = 0; /* nothing routed to external APIC */ | |
723 | else | |
724 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
725 | ||
f0fda801 | 726 | dev_info(&dev->dev, "%sbling VIA external APIC routing\n", |
1da177e4 LT |
727 | tmp == 0 ? "Disa" : "Ena"); |
728 | ||
729 | /* Offset 0x58: External APIC IRQ output control */ | |
730 | pci_write_config_byte (dev, 0x58, tmp); | |
731 | } | |
652c538e | 732 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e | 733 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4 | 734 | |
a1740913 KW |
735 | /* |
736 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. | |
737 | * This leads to doubled level interrupt rates. | |
738 | * Set this bit to get rid of cycle wastage. | |
739 | * Otherwise uncritical. | |
740 | */ | |
1597cacb | 741 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
742 | { |
743 | u8 misc_control2; | |
744 | #define BYPASS_APIC_DEASSERT 8 | |
745 | ||
746 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
747 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
f0fda801 | 748 | dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
a1740913 KW |
749 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
750 | } | |
751 | } | |
752 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
e1a2a51e | 753 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 754 | |
1da177e4 LT |
755 | /* |
756 | * The AMD io apic can hang the box when an apic irq is masked. | |
757 | * We check all revs >= B0 (yet not in the pre production!) as the bug | |
758 | * is currently marked NoFix | |
759 | * | |
760 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 761 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4 LT |
762 | * of course. However the advice is demonstrably good even if so.. |
763 | */ | |
764 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) | |
765 | { | |
44c10138 | 766 | if (dev->revision >= 0x02) { |
f0fda801 | 767 | dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
768 | dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); | |
1da177e4 LT |
769 | } |
770 | } | |
652c538e | 771 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
772 | |
773 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) | |
774 | { | |
775 | if (dev->devfn == 0 && dev->bus->number == 0) | |
776 | sis_apic_bug = 1; | |
777 | } | |
652c538e | 778 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); |
1da177e4 LT |
779 | #endif /* CONFIG_X86_IO_APIC */ |
780 | ||
d556ad4b PO |
781 | /* |
782 | * Some settings of MMRBC can lead to data corruption so block changes. | |
783 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
784 | */ | |
785 | static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) | |
786 | { | |
aa288d4d | 787 | if (dev->subordinate && dev->revision <= 0x12) { |
f0fda801 | 788 | dev_info(&dev->dev, "AMD8131 rev %x detected; " |
789 | "disabling PCI-X MMRBC\n", dev->revision); | |
d556ad4b PO |
790 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
791 | } | |
792 | } | |
793 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 794 | |
1da177e4 LT |
795 | /* |
796 | * FIXME: it is questionable that quirk_via_acpi | |
797 | * is needed. It shows up as an ISA bridge, and does not | |
798 | * support the PCI_INTERRUPT_LINE register at all. Therefore | |
799 | * it seems like setting the pci_dev's 'irq' to the | |
800 | * value of the ACPI SCI interrupt is only done for convenience. | |
801 | * -jgarzik | |
802 | */ | |
803 | static void __devinit quirk_via_acpi(struct pci_dev *d) | |
804 | { | |
805 | /* | |
806 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 | |
807 | */ | |
808 | u8 irq; | |
809 | pci_read_config_byte(d, 0x42, &irq); | |
810 | irq &= 0xf; | |
811 | if (irq && (irq != 2)) | |
812 | d->irq = irq; | |
813 | } | |
652c538e AM |
814 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
815 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 816 | |
09d6029f DD |
817 | |
818 | /* | |
1597cacb | 819 | * VIA bridges which have VLink |
09d6029f | 820 | */ |
1597cacb | 821 | |
c06bb5d4 JD |
822 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
823 | ||
824 | static void quirk_via_bridge(struct pci_dev *dev) | |
825 | { | |
826 | /* See what bridge we have and find the device ranges */ | |
827 | switch (dev->device) { | |
828 | case PCI_DEVICE_ID_VIA_82C686: | |
cb7468ef JD |
829 | /* The VT82C686 is special, it attaches to PCI and can have |
830 | any device number. All its subdevices are functions of | |
831 | that single device. */ | |
832 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); | |
833 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
834 | break; |
835 | case PCI_DEVICE_ID_VIA_8237: | |
836 | case PCI_DEVICE_ID_VIA_8237A: | |
837 | via_vlink_dev_lo = 15; | |
838 | break; | |
839 | case PCI_DEVICE_ID_VIA_8235: | |
840 | via_vlink_dev_lo = 16; | |
841 | break; | |
842 | case PCI_DEVICE_ID_VIA_8231: | |
843 | case PCI_DEVICE_ID_VIA_8233_0: | |
844 | case PCI_DEVICE_ID_VIA_8233A: | |
845 | case PCI_DEVICE_ID_VIA_8233C_0: | |
846 | via_vlink_dev_lo = 17; | |
847 | break; | |
848 | } | |
849 | } | |
850 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
851 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
852 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
853 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
854 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
855 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
856 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
857 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 858 | |
1597cacb AC |
859 | /** |
860 | * quirk_via_vlink - VIA VLink IRQ number update | |
861 | * @dev: PCI device | |
862 | * | |
863 | * If the device we are dealing with is on a PIC IRQ we need to | |
864 | * ensure that the IRQ line register which usually is not relevant | |
865 | * for PCI cards, is actually written so that interrupts get sent | |
c06bb5d4 JD |
866 | * to the right place. |
867 | * We only do this on systems where a VIA south bridge was detected, | |
868 | * and only for VIA devices on the motherboard (see quirk_via_bridge | |
869 | * above). | |
1597cacb AC |
870 | */ |
871 | ||
872 | static void quirk_via_vlink(struct pci_dev *dev) | |
25be5e6c LB |
873 | { |
874 | u8 irq, new_irq; | |
875 | ||
c06bb5d4 JD |
876 | /* Check if we have VLink at all */ |
877 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
878 | return; |
879 | ||
880 | new_irq = dev->irq; | |
881 | ||
882 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
883 | if (!new_irq || new_irq > 15) | |
884 | return; | |
885 | ||
1597cacb | 886 | /* Internal device ? */ |
c06bb5d4 JD |
887 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
888 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
889 | return; |
890 | ||
891 | /* This is an internal VLink device on a PIC interrupt. The BIOS | |
892 | ought to have set this but may not have, so we redo it */ | |
893 | ||
25be5e6c LB |
894 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
895 | if (new_irq != irq) { | |
f0fda801 | 896 | dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", |
897 | irq, new_irq); | |
25be5e6c LB |
898 | udelay(15); /* unknown if delay really needed */ |
899 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
900 | } | |
901 | } | |
1597cacb | 902 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 903 | |
1da177e4 LT |
904 | /* |
905 | * VIA VT82C598 has its device ID settable and many BIOSes | |
906 | * set it to the ID of VT82C597 for backward compatibility. | |
907 | * We need to switch it off to be able to recognize the real | |
908 | * type of the chip. | |
909 | */ | |
910 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) | |
911 | { | |
912 | pci_write_config_byte(dev, 0xfc, 0); | |
913 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
914 | } | |
652c538e | 915 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
916 | |
917 | /* | |
918 | * CardBus controllers have a legacy base address that enables them | |
919 | * to respond as i82365 pcmcia controllers. We don't want them to | |
920 | * do this even if the Linux CardBus driver is not loaded, because | |
921 | * the Linux i82365 driver does not (and should not) handle CardBus. | |
922 | */ | |
1597cacb | 923 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 LT |
924 | { |
925 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) | |
926 | return; | |
927 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); | |
928 | } | |
929 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); | |
e1a2a51e | 930 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
1da177e4 LT |
931 | |
932 | /* | |
933 | * Following the PCI ordering rules is optional on the AMD762. I'm not | |
934 | * sure what the designers were smoking but let's not inhale... | |
935 | * | |
936 | * To be fair to AMD, it follows the spec by default, its BIOS people | |
937 | * who turn it off! | |
938 | */ | |
1597cacb | 939 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
940 | { |
941 | u32 pcic; | |
942 | pci_read_config_dword(dev, 0x4C, &pcic); | |
943 | if ((pcic&6)!=6) { | |
944 | pcic |= 6; | |
f0fda801 | 945 | dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1da177e4 LT |
946 | pci_write_config_dword(dev, 0x4C, pcic); |
947 | pci_read_config_dword(dev, 0x84, &pcic); | |
948 | pcic |= (1<<23); /* Required in this mode */ | |
949 | pci_write_config_dword(dev, 0x84, pcic); | |
950 | } | |
951 | } | |
652c538e | 952 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e | 953 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4 LT |
954 | |
955 | /* | |
956 | * DreamWorks provided workaround for Dunord I-3000 problem | |
957 | * | |
958 | * This card decodes and responds to addresses not apparently | |
959 | * assigned to it. We force a larger allocation to ensure that | |
960 | * nothing gets put too close to it. | |
961 | */ | |
962 | static void __devinit quirk_dunord ( struct pci_dev * dev ) | |
963 | { | |
964 | struct resource *r = &dev->resource [1]; | |
965 | r->start = 0; | |
966 | r->end = 0xffffff; | |
967 | } | |
652c538e | 968 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
969 | |
970 | /* | |
971 | * i82380FB mobile docking controller: its PCI-to-PCI bridge | |
972 | * is subtractive decoding (transparent), and does indicate this | |
973 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 | |
974 | * instead of 0x01. | |
975 | */ | |
976 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) | |
977 | { | |
978 | dev->transparent = 1; | |
979 | } | |
652c538e AM |
980 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
981 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
982 | |
983 | /* | |
984 | * Common misconfiguration of the MediaGX/Geode PCI master that will | |
985 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 | |
986 | * datasheets found at http://www.national.com/ds/GX for info on what | |
987 | * these bits do. <christer@weinigel.se> | |
988 | */ | |
1597cacb | 989 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
990 | { |
991 | u8 reg; | |
992 | pci_read_config_byte(dev, 0x41, ®); | |
993 | if (reg & 2) { | |
994 | reg &= ~2; | |
f0fda801 | 995 | dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
1da177e4 LT |
996 | pci_write_config_byte(dev, 0x41, reg); |
997 | } | |
998 | } | |
652c538e AM |
999 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1000 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 1001 | |
1da177e4 LT |
1002 | /* |
1003 | * Ensure C0 rev restreaming is off. This is normally done by | |
1004 | * the BIOS but in the odd case it is not the results are corruption | |
1005 | * hence the presence of a Linux check | |
1006 | */ | |
1597cacb | 1007 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
1008 | { |
1009 | u16 config; | |
1da177e4 | 1010 | |
44c10138 | 1011 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
1012 | return; |
1013 | pci_read_config_word(pdev, 0x40, &config); | |
1014 | if (config & (1<<6)) { | |
1015 | config &= ~(1<<6); | |
1016 | pci_write_config_word(pdev, 0x40, config); | |
f0fda801 | 1017 | dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1da177e4 LT |
1018 | } |
1019 | } | |
652c538e | 1020 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e | 1021 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4 | 1022 | |
05a7d22b | 1023 | static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a | 1024 | { |
5deab536 | 1025 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
05a7d22b | 1026 | u8 tmp; |
ab17443a | 1027 | |
05a7d22b CC |
1028 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
1029 | if (tmp == 0x01) { | |
ab17443a CH |
1030 | pci_read_config_byte(pdev, 0x40, &tmp); |
1031 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
1032 | pci_write_config_byte(pdev, 0x9, 1); | |
1033 | pci_write_config_byte(pdev, 0xa, 6); | |
1034 | pci_write_config_byte(pdev, 0x40, tmp); | |
1035 | ||
c9f89475 | 1036 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
05a7d22b | 1037 | dev_info(&pdev->dev, "set SATA to AHCI mode\n"); |
ab17443a CH |
1038 | } |
1039 | } | |
05a7d22b | 1040 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1041 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b | 1042 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1043 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
5deab536 SH |
1044 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1045 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); | |
ab17443a | 1046 | |
1da177e4 LT |
1047 | /* |
1048 | * Serverworks CSB5 IDE does not fully support native mode | |
1049 | */ | |
1050 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) | |
1051 | { | |
1052 | u8 prog; | |
1053 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1054 | if (prog & 5) { | |
1055 | prog &= ~5; | |
1056 | pdev->class &= ~5; | |
1057 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 1058 | /* PCI layer will sort out resources */ |
1da177e4 LT |
1059 | } |
1060 | } | |
652c538e | 1061 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 LT |
1062 | |
1063 | /* | |
1064 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same | |
1065 | */ | |
1066 | static void __init quirk_ide_samemode(struct pci_dev *pdev) | |
1067 | { | |
1068 | u8 prog; | |
1069 | ||
1070 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1071 | ||
1072 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
f0fda801 | 1073 | dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); |
1da177e4 LT |
1074 | prog &= ~5; |
1075 | pdev->class &= ~5; | |
1076 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
1077 | } |
1078 | } | |
368c73d4 | 1079 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 | 1080 | |
979b1791 AC |
1081 | /* |
1082 | * Some ATA devices break if put into D3 | |
1083 | */ | |
1084 | ||
1085 | static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) | |
1086 | { | |
1087 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ | |
1088 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
1089 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; | |
1090 | } | |
1091 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); | |
1092 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); | |
7a661c6f AC |
1093 | /* ALi loses some register settings that we cannot then restore */ |
1094 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3); | |
1095 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures | |
1096 | occur when mode detecting */ | |
1097 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3); | |
979b1791 | 1098 | |
1da177e4 LT |
1099 | /* This was originally an Alpha specific thing, but it really fits here. |
1100 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. | |
1101 | */ | |
1102 | static void __init quirk_eisa_bridge(struct pci_dev *dev) | |
1103 | { | |
1104 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
1105 | } | |
652c538e | 1106 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 | 1107 | |
7daa0c4f | 1108 | |
1da177e4 LT |
1109 | /* |
1110 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
1111 | * is not activated. The myth is that Asus said that they do not want the | |
1112 | * users to be irritated by just another PCI Device in the Win98 device | |
1113 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors | |
1114 | * package 2.7.0 for details) | |
1115 | * | |
1116 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC | |
1117 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 1118 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1119 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
1120 | * |
1121 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
1122 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
1123 | * was done by SMM code, which could cause unsynchronized concurrent | |
1124 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
1125 | * should be very careful when adding new entries: if SMM is accessing the | |
1126 | * Intel SMBus, this is a very good reason to leave it hidden. | |
a99acc83 JD |
1127 | * |
1128 | * Likewise, many recent laptops use ACPI for thermal management. If the | |
1129 | * ACPI DSDT code accesses the SMBus, then Linux should not access it | |
1130 | * natively, and keeping the SMBus hidden is the right thing to do. If you | |
1131 | * are about to add an entry in the table below, please first disassemble | |
1132 | * the DSDT and double-check that there is no code accessing the SMBus. | |
1da177e4 | 1133 | */ |
9d24a81e | 1134 | static int asus_hides_smbus; |
1da177e4 LT |
1135 | |
1136 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) | |
1137 | { | |
1138 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1139 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
1140 | switch(dev->subsystem_device) { | |
a00db371 | 1141 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
1142 | case 0x8070: /* P4B */ |
1143 | case 0x8088: /* P4B533 */ | |
1144 | case 0x1626: /* L3C notebook */ | |
1145 | asus_hides_smbus = 1; | |
1146 | } | |
2f2d39d2 | 1147 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1da177e4 LT |
1148 | switch(dev->subsystem_device) { |
1149 | case 0x80b1: /* P4GE-V */ | |
1150 | case 0x80b2: /* P4PE */ | |
1151 | case 0x8093: /* P4B533-V */ | |
1152 | asus_hides_smbus = 1; | |
1153 | } | |
2f2d39d2 | 1154 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1da177e4 LT |
1155 | switch(dev->subsystem_device) { |
1156 | case 0x8030: /* P4T533 */ | |
1157 | asus_hides_smbus = 1; | |
1158 | } | |
2f2d39d2 | 1159 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
1160 | switch (dev->subsystem_device) { |
1161 | case 0x8070: /* P4G8X Deluxe */ | |
1162 | asus_hides_smbus = 1; | |
1163 | } | |
2f2d39d2 | 1164 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
1165 | switch (dev->subsystem_device) { |
1166 | case 0x80c9: /* PU-DLS */ | |
1167 | asus_hides_smbus = 1; | |
1168 | } | |
2f2d39d2 | 1169 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1170 | switch (dev->subsystem_device) { |
1171 | case 0x1751: /* M2N notebook */ | |
1172 | case 0x1821: /* M5N notebook */ | |
4096ed0f | 1173 | case 0x1897: /* A6L notebook */ |
1da177e4 LT |
1174 | asus_hides_smbus = 1; |
1175 | } | |
2f2d39d2 | 1176 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1177 | switch (dev->subsystem_device) { |
1178 | case 0x184b: /* W1N notebook */ | |
1179 | case 0x186a: /* M6Ne notebook */ | |
1180 | asus_hides_smbus = 1; | |
1181 | } | |
2f2d39d2 | 1182 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1183 | switch (dev->subsystem_device) { |
1184 | case 0x80f2: /* P4P800-X */ | |
1185 | asus_hides_smbus = 1; | |
1186 | } | |
2f2d39d2 | 1187 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1188 | switch (dev->subsystem_device) { |
1189 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1190 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1191 | asus_hides_smbus = 1; |
1192 | } | |
1da177e4 LT |
1193 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1194 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1195 | switch(dev->subsystem_device) { | |
1196 | case 0x088C: /* HP Compaq nc8000 */ | |
1197 | case 0x0890: /* HP Compaq nc6000 */ | |
1198 | asus_hides_smbus = 1; | |
1199 | } | |
2f2d39d2 | 1200 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1201 | switch (dev->subsystem_device) { |
1202 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1203 | case 0x12bd: /* HP D530 */ |
74c57428 | 1204 | case 0x006a: /* HP Compaq nx9500 */ |
1da177e4 LT |
1205 | asus_hides_smbus = 1; |
1206 | } | |
677cc644 JD |
1207 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1208 | switch (dev->subsystem_device) { | |
1209 | case 0x12bf: /* HP xw4100 */ | |
1210 | asus_hides_smbus = 1; | |
1211 | } | |
1da177e4 LT |
1212 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1213 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1214 | switch(dev->subsystem_device) { | |
1215 | case 0xC00C: /* Samsung P35 notebook */ | |
1216 | asus_hides_smbus = 1; | |
1217 | } | |
c87f883e RIZ |
1218 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1219 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1220 | switch(dev->subsystem_device) { | |
1221 | case 0x0058: /* Compaq Evo N620c */ | |
1222 | asus_hides_smbus = 1; | |
1223 | } | |
d7698edc | 1224 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
1225 | switch(dev->subsystem_device) { | |
1226 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ | |
1227 | /* Motherboard doesn't have Host bridge | |
1228 | * subvendor/subdevice IDs, therefore checking | |
1229 | * its on-board VGA controller */ | |
1230 | asus_hides_smbus = 1; | |
1231 | } | |
8293b0f6 | 1232 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
10260d9a JD |
1233 | switch(dev->subsystem_device) { |
1234 | case 0x00b8: /* Compaq Evo D510 CMT */ | |
1235 | case 0x00b9: /* Compaq Evo D510 SFF */ | |
6b5096e4 | 1236 | case 0x00ba: /* Compaq Evo D510 USDT */ |
8293b0f6 DS |
1237 | /* Motherboard doesn't have Host bridge |
1238 | * subvendor/subdevice IDs and on-board VGA | |
1239 | * controller is disabled if an AGP card is | |
1240 | * inserted, therefore checking USB UHCI | |
1241 | * Controller #1 */ | |
10260d9a JD |
1242 | asus_hides_smbus = 1; |
1243 | } | |
27e46859 KH |
1244 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1245 | switch (dev->subsystem_device) { | |
1246 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ | |
1247 | /* Motherboard doesn't have host bridge | |
1248 | * subvendor/subdevice IDs, therefore checking | |
1249 | * its on-board VGA controller */ | |
1250 | asus_hides_smbus = 1; | |
1251 | } | |
1da177e4 LT |
1252 | } |
1253 | } | |
652c538e AM |
1254 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1255 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1256 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1257 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1258 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1259 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1260 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1261 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1262 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1263 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1264 | ||
1265 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
8293b0f6 | 1266 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e46859 | 1267 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edc | 1268 | |
1597cacb | 1269 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1270 | { |
1271 | u16 val; | |
1272 | ||
1273 | if (likely(!asus_hides_smbus)) | |
1274 | return; | |
1275 | ||
1276 | pci_read_config_word(dev, 0xF2, &val); | |
1277 | if (val & 0x8) { | |
1278 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1279 | pci_read_config_word(dev, 0xF2, &val); | |
1280 | if (val & 0x8) | |
f0fda801 | 1281 | dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
1da177e4 | 1282 | else |
f0fda801 | 1283 | dev_info(&dev->dev, "Enabled i801 SMBus device\n"); |
1da177e4 LT |
1284 | } |
1285 | } | |
652c538e AM |
1286 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1287 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1288 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1289 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1290 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1291 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1292 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
e1a2a51e RW |
1293 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1294 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1295 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1296 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1297 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1298 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1299 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb | 1300 | |
e1a2a51e RW |
1301 | /* It appears we just have one such device. If not, we have a warning */ |
1302 | static void __iomem *asus_rcba_base; | |
1303 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) | |
acc06632 | 1304 | { |
e1a2a51e | 1305 | u32 rcba; |
acc06632 M |
1306 | |
1307 | if (likely(!asus_hides_smbus)) | |
1308 | return; | |
e1a2a51e RW |
1309 | WARN_ON(asus_rcba_base); |
1310 | ||
acc06632 | 1311 | pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e RW |
1312 | /* use bits 31:14, 16 kB aligned */ |
1313 | asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); | |
1314 | if (asus_rcba_base == NULL) | |
1315 | return; | |
1316 | } | |
1317 | ||
1318 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) | |
1319 | { | |
1320 | u32 val; | |
1321 | ||
1322 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1323 | return; | |
1324 | /* read the Function Disable register, dword mode only */ | |
1325 | val = readl(asus_rcba_base + 0x3418); | |
1326 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ | |
1327 | } | |
1328 | ||
1329 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) | |
1330 | { | |
1331 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1332 | return; | |
1333 | iounmap(asus_rcba_base); | |
1334 | asus_rcba_base = NULL; | |
f0fda801 | 1335 | dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); |
acc06632 | 1336 | } |
e1a2a51e RW |
1337 | |
1338 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
1339 | { | |
1340 | asus_hides_smbus_lpc_ich6_suspend(dev); | |
1341 | asus_hides_smbus_lpc_ich6_resume_early(dev); | |
1342 | asus_hides_smbus_lpc_ich6_resume(dev); | |
1343 | } | |
652c538e | 1344 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e RW |
1345 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1346 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); | |
1347 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); | |
ce007ea5 | 1348 | |
1da177e4 LT |
1349 | /* |
1350 | * SiS 96x south bridge: BIOS typically hides SMBus device... | |
1351 | */ | |
1597cacb | 1352 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1353 | { |
1354 | u8 val = 0; | |
1da177e4 | 1355 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 | 1356 | if (val & 0x10) { |
f0fda801 | 1357 | dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); |
2f5c33b3 MH |
1358 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
1359 | } | |
1da177e4 | 1360 | } |
652c538e AM |
1361 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1362 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1363 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1364 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
e1a2a51e RW |
1365 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1366 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1367 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1368 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1369 | |
1da177e4 LT |
1370 | /* |
1371 | * ... This is further complicated by the fact that some SiS96x south | |
1372 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1373 | * spotted a compatible north bridge to make sure. | |
1374 | * (pci_find_device doesn't work yet) | |
1375 | * | |
1376 | * We can also enable the sis96x bit in the discovery register.. | |
1377 | */ | |
1da177e4 LT |
1378 | #define SIS_DETECT_REGISTER 0x40 |
1379 | ||
1597cacb | 1380 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1381 | { |
1382 | u8 reg; | |
1383 | u16 devid; | |
1384 | ||
1385 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1386 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1387 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1388 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1389 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1390 | return; | |
1391 | } | |
1392 | ||
1da177e4 | 1393 | /* |
2f5c33b3 MH |
1394 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
1395 | * hand in case it has already been processed. | |
1396 | * (depends on link order, which is apparently not guaranteed) | |
1da177e4 LT |
1397 | */ |
1398 | dev->device = devid; | |
2f5c33b3 | 1399 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1400 | } |
652c538e | 1401 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e | 1402 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4 | 1403 | |
1da177e4 | 1404 | |
e5548e96 BJD |
1405 | /* |
1406 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1407 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1408 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1409 | * -- bjd | |
1410 | */ | |
1597cacb | 1411 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1412 | { |
1413 | u8 val; | |
1414 | int asus_hides_ac97 = 0; | |
1415 | ||
1416 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1417 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1418 | asus_hides_ac97 = 1; | |
1419 | } | |
1420 | ||
1421 | if (!asus_hides_ac97) | |
1422 | return; | |
1423 | ||
1424 | pci_read_config_byte(dev, 0x50, &val); | |
1425 | if (val & 0xc0) { | |
1426 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1427 | pci_read_config_byte(dev, 0x50, &val); | |
1428 | if (val & 0xc0) | |
f0fda801 | 1429 | dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
e5548e96 | 1430 | else |
f0fda801 | 1431 | dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); |
e5548e96 BJD |
1432 | } |
1433 | } | |
652c538e | 1434 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e | 1435 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacb | 1436 | |
77967052 | 1437 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1438 | |
1439 | /* | |
1440 | * If we are using libata we can drive this chip properly but must | |
1441 | * do this early on to make the additional device appear during | |
1442 | * the PCI scanning. | |
1443 | */ | |
5ee2ae7f | 1444 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1445 | { |
e34bb370 | 1446 | u32 conf1, conf5, class; |
15e0c694 AC |
1447 | u8 hdr; |
1448 | ||
1449 | /* Only poke fn 0 */ | |
1450 | if (PCI_FUNC(pdev->devfn)) | |
1451 | return; | |
1452 | ||
5ee2ae7f TH |
1453 | pci_read_config_dword(pdev, 0x40, &conf1); |
1454 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1455 | |
5ee2ae7f TH |
1456 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1457 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1458 | ||
1459 | switch (pdev->device) { | |
4daedcfe TH |
1460 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
1461 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ | |
5ee2ae7f TH |
1462 | /* The controller should be in single function ahci mode */ |
1463 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1464 | break; | |
1465 | ||
1466 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1467 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1468 | /* Redirect IDE second PATA port to the right spot */ | |
1469 | conf5 |= (1 << 24); | |
1470 | /* Fall through */ | |
1471 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1472 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
1473 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ | |
1474 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1475 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1476 | break; |
1477 | ||
1478 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1479 | /* The controller should be in single function IDE mode */ | |
1480 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1481 | break; | |
15e0c694 | 1482 | } |
5ee2ae7f TH |
1483 | |
1484 | pci_write_config_dword(pdev, 0x40, conf1); | |
1485 | pci_write_config_dword(pdev, 0x80, conf5); | |
1486 | ||
1487 | /* Update pdev accordingly */ | |
1488 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1489 | pdev->hdr_type = hdr & 0x7f; | |
1490 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1491 | |
1492 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1493 | pdev->class = class >> 8; | |
15e0c694 | 1494 | } |
5ee2ae7f TH |
1495 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1496 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1497 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
5ee2ae7f TH |
1498 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
1499 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); | |
1500 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1501 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
e1a2a51e RW |
1502 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1503 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1504 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
e1a2a51e RW |
1505 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
1506 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); | |
1507 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1508 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
15e0c694 AC |
1509 | |
1510 | #endif | |
1511 | ||
1da177e4 LT |
1512 | #ifdef CONFIG_X86_IO_APIC |
1513 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) | |
1514 | { | |
1515 | int i; | |
1516 | ||
1517 | if ((pdev->class >> 8) != 0xff00) | |
1518 | return; | |
1519 | ||
1520 | /* the first BAR is the location of the IO APIC...we must | |
1521 | * not touch this (and it's already covered by the fixmap), so | |
1522 | * forcibly insert it into the resource tree */ | |
1523 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) | |
1524 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1525 | ||
1526 | /* The next five BARs all seem to be rubbish, so just clean | |
1527 | * them out */ | |
1528 | for (i=1; i < 6; i++) { | |
1529 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); | |
1530 | } | |
1531 | ||
1532 | } | |
652c538e | 1533 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1534 | #endif |
1535 | ||
1da177e4 LT |
1536 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) |
1537 | { | |
0ba379ec EB |
1538 | pci_msi_off(pdev); |
1539 | pdev->no_msi = 1; | |
1da177e4 | 1540 | } |
652c538e AM |
1541 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1542 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1543 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1544 | |
4602b88d KA |
1545 | |
1546 | /* | |
1547 | * It's possible for the MSI to get corrupted if shpc and acpi | |
1548 | * are used together on certain PXH-based systems. | |
1549 | */ | |
1550 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) | |
1551 | { | |
f5f2b131 | 1552 | pci_msi_off(dev); |
4602b88d | 1553 | dev->no_msi = 1; |
f0fda801 | 1554 | dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
4602b88d KA |
1555 | } |
1556 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1557 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1558 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1559 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1560 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1561 | ||
ffadcc2f KCA |
1562 | /* |
1563 | * Some Intel PCI Express chipsets have trouble with downstream | |
1564 | * device power management. | |
1565 | */ | |
1566 | static void quirk_intel_pcie_pm(struct pci_dev * dev) | |
1567 | { | |
1568 | pci_pm_d3_delay = 120; | |
1569 | dev->no_d1d2 = 1; | |
1570 | } | |
1571 | ||
1572 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); | |
1573 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1574 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1575 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1576 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1578 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1579 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1580 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1581 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1582 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1583 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1584 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1585 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1586 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1587 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1588 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1589 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1590 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1591 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1592 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1593 | |
426b3b8d | 1594 | #ifdef CONFIG_X86_IO_APIC |
e1d3a908 SA |
1595 | /* |
1596 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, | |
1597 | * remap the original interrupt in the linux kernel to the boot interrupt, so | |
1598 | * that a PCI device's interrupt handler is installed on the boot interrupt | |
1599 | * line instead. | |
1600 | */ | |
1601 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) | |
1602 | { | |
41b9eb26 | 1603 | if (noioapicquirk || noioapicreroute) |
e1d3a908 SA |
1604 | return; |
1605 | ||
1606 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; | |
fdcdaf6c BH |
1607 | dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", |
1608 | dev->vendor, dev->device); | |
e1d3a908 | 1609 | } |
88d1dce3 OD |
1610 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
1611 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1612 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1613 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1614 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1615 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1616 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1617 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
1618 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); | |
1619 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1620 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1621 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1622 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1623 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1624 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1625 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
e1d3a908 | 1626 | |
426b3b8d SA |
1627 | /* |
1628 | * On some chipsets we can disable the generation of legacy INTx boot | |
1629 | * interrupts. | |
1630 | */ | |
1631 | ||
1632 | /* | |
1633 | * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no | |
1634 | * 300641-004US, section 5.7.3. | |
1635 | */ | |
1636 | #define INTEL_6300_IOAPIC_ABAR 0x40 | |
1637 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) | |
1638 | ||
1639 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) | |
1640 | { | |
1641 | u16 pci_config_word; | |
1642 | ||
1643 | if (noioapicquirk) | |
1644 | return; | |
1645 | ||
1646 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); | |
1647 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
1648 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); | |
1649 | ||
fdcdaf6c BH |
1650 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1651 | dev->vendor, dev->device); | |
426b3b8d | 1652 | } |
88d1dce3 OD |
1653 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
1654 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); | |
77251188 OD |
1655 | |
1656 | /* | |
1657 | * disable boot interrupts on HT-1000 | |
1658 | */ | |
1659 | #define BC_HT1000_FEATURE_REG 0x64 | |
1660 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) | |
1661 | #define BC_HT1000_MAP_IDX 0xC00 | |
1662 | #define BC_HT1000_MAP_DATA 0xC01 | |
1663 | ||
1664 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) | |
1665 | { | |
1666 | u32 pci_config_dword; | |
1667 | u8 irq; | |
1668 | ||
1669 | if (noioapicquirk) | |
1670 | return; | |
1671 | ||
1672 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); | |
1673 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | | |
1674 | BC_HT1000_PIC_REGS_ENABLE); | |
1675 | ||
1676 | for (irq = 0x10; irq < 0x10 + 32; irq++) { | |
1677 | outb(irq, BC_HT1000_MAP_IDX); | |
1678 | outb(0x00, BC_HT1000_MAP_DATA); | |
1679 | } | |
1680 | ||
1681 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); | |
1682 | ||
fdcdaf6c BH |
1683 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1684 | dev->vendor, dev->device); | |
77251188 | 1685 | } |
88d1dce3 OD |
1686 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
1687 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); | |
542622da OD |
1688 | |
1689 | /* | |
1690 | * disable boot interrupts on AMD and ATI chipsets | |
1691 | */ | |
1692 | /* | |
1693 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 | |
1694 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode | |
1695 | * (due to an erratum). | |
1696 | */ | |
1697 | #define AMD_813X_MISC 0x40 | |
1698 | #define AMD_813X_NOIOAMODE (1<<0) | |
4fd8bdc5 | 1699 | #define AMD_813X_REV_B1 0x12 |
bbe19443 | 1700 | #define AMD_813X_REV_B2 0x13 |
542622da OD |
1701 | |
1702 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) | |
1703 | { | |
1704 | u32 pci_config_dword; | |
1705 | ||
1706 | if (noioapicquirk) | |
1707 | return; | |
4fd8bdc5 SA |
1708 | if ((dev->revision == AMD_813X_REV_B1) || |
1709 | (dev->revision == AMD_813X_REV_B2)) | |
bbe19443 | 1710 | return; |
542622da OD |
1711 | |
1712 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); | |
1713 | pci_config_dword &= ~AMD_813X_NOIOAMODE; | |
1714 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); | |
1715 | ||
fdcdaf6c BH |
1716 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1717 | dev->vendor, dev->device); | |
542622da | 1718 | } |
4fd8bdc5 SA |
1719 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
1720 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
1721 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
1722 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
542622da OD |
1723 | |
1724 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 | |
1725 | ||
1726 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) | |
1727 | { | |
1728 | u16 pci_config_word; | |
1729 | ||
1730 | if (noioapicquirk) | |
1731 | return; | |
1732 | ||
1733 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); | |
1734 | if (!pci_config_word) { | |
fdcdaf6c BH |
1735 | dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " |
1736 | "already disabled\n", dev->vendor, dev->device); | |
542622da OD |
1737 | return; |
1738 | } | |
1739 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); | |
fdcdaf6c BH |
1740 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1741 | dev->vendor, dev->device); | |
542622da | 1742 | } |
88d1dce3 OD |
1743 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
1744 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); | |
426b3b8d SA |
1745 | #endif /* CONFIG_X86_IO_APIC */ |
1746 | ||
33dced2e SS |
1747 | /* |
1748 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
1749 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
1750 | * Re-allocate the region if needed... | |
1751 | */ | |
1752 | static void __init quirk_tc86c001_ide(struct pci_dev *dev) | |
1753 | { | |
1754 | struct resource *r = &dev->resource[0]; | |
1755 | ||
1756 | if (r->start & 0x8) { | |
1757 | r->start = 0; | |
1758 | r->end = 0xf; | |
1759 | } | |
1760 | } | |
1761 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
1762 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
1763 | quirk_tc86c001_ide); | |
1764 | ||
1da177e4 LT |
1765 | static void __devinit quirk_netmos(struct pci_dev *dev) |
1766 | { | |
1767 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
1768 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
1769 | ||
1770 | /* | |
1771 | * These Netmos parts are multiport serial devices with optional | |
1772 | * parallel ports. Even when parallel ports are present, they | |
1773 | * are identified as class SERIAL, which means the serial driver | |
1774 | * will claim them. To prevent this, mark them as class OTHER. | |
1775 | * These combo devices should be claimed by parport_serial. | |
1776 | * | |
1777 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
1778 | * of parallel ports and <S> is the number of serial ports. | |
1779 | */ | |
1780 | switch (dev->device) { | |
4c9c1686 JS |
1781 | case PCI_DEVICE_ID_NETMOS_9835: |
1782 | /* Well, this rule doesn't hold for the following 9835 device */ | |
1783 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | |
1784 | dev->subsystem_device == 0x0299) | |
1785 | return; | |
1da177e4 LT |
1786 | case PCI_DEVICE_ID_NETMOS_9735: |
1787 | case PCI_DEVICE_ID_NETMOS_9745: | |
1da177e4 LT |
1788 | case PCI_DEVICE_ID_NETMOS_9845: |
1789 | case PCI_DEVICE_ID_NETMOS_9855: | |
1790 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && | |
1791 | num_parallel) { | |
f0fda801 | 1792 | dev_info(&dev->dev, "Netmos %04x (%u parallel, " |
1da177e4 LT |
1793 | "%u serial); changing class SERIAL to OTHER " |
1794 | "(use parport_serial)\n", | |
1795 | dev->device, num_parallel, num_serial); | |
1796 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
1797 | (dev->class & 0xff); | |
1798 | } | |
1799 | } | |
1800 | } | |
1801 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); | |
1802 | ||
16a74744 BH |
1803 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
1804 | { | |
e64aeccb | 1805 | u16 command, pmcsr; |
16a74744 BH |
1806 | u8 __iomem *csr; |
1807 | u8 cmd_hi; | |
e64aeccb | 1808 | int pm; |
16a74744 BH |
1809 | |
1810 | switch (dev->device) { | |
1811 | /* PCI IDs taken from drivers/net/e100.c */ | |
1812 | case 0x1029: | |
1813 | case 0x1030 ... 0x1034: | |
1814 | case 0x1038 ... 0x103E: | |
1815 | case 0x1050 ... 0x1057: | |
1816 | case 0x1059: | |
1817 | case 0x1064 ... 0x106B: | |
1818 | case 0x1091 ... 0x1095: | |
1819 | case 0x1209: | |
1820 | case 0x1229: | |
1821 | case 0x2449: | |
1822 | case 0x2459: | |
1823 | case 0x245D: | |
1824 | case 0x27DC: | |
1825 | break; | |
1826 | default: | |
1827 | return; | |
1828 | } | |
1829 | ||
1830 | /* | |
1831 | * Some firmware hands off the e100 with interrupts enabled, | |
1832 | * which can cause a flood of interrupts if packets are | |
1833 | * received before the driver attaches to the device. So | |
1834 | * disable all e100 interrupts here. The driver will | |
1835 | * re-enable them when it's ready. | |
1836 | */ | |
1837 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 1838 | |
1bef7dc0 | 1839 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
1840 | return; |
1841 | ||
e64aeccb IK |
1842 | /* |
1843 | * Check that the device is in the D0 power state. If it's not, | |
1844 | * there is no point to look any further. | |
1845 | */ | |
1846 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1847 | if (pm) { | |
1848 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); | |
1849 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) | |
1850 | return; | |
1851 | } | |
1852 | ||
1bef7dc0 BH |
1853 | /* Convert from PCI bus to resource space. */ |
1854 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 | 1855 | if (!csr) { |
f0fda801 | 1856 | dev_warn(&dev->dev, "Can't map e100 registers\n"); |
16a74744 BH |
1857 | return; |
1858 | } | |
1859 | ||
1860 | cmd_hi = readb(csr + 3); | |
1861 | if (cmd_hi == 0) { | |
f0fda801 | 1862 | dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " |
1863 | "disabling\n"); | |
16a74744 BH |
1864 | writeb(1, csr + 3); |
1865 | } | |
1866 | ||
1867 | iounmap(csr); | |
1868 | } | |
4e68fc97 | 1869 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
a5312e28 | 1870 | |
649426ef AD |
1871 | /* |
1872 | * The 82575 and 82598 may experience data corruption issues when transitioning | |
1873 | * out of L0S. To prevent this we need to disable L0S on the pci-e link | |
1874 | */ | |
1875 | static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) | |
1876 | { | |
1877 | dev_info(&dev->dev, "Disabling L0s\n"); | |
1878 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); | |
1879 | } | |
1880 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | |
1881 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | |
1882 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | |
1883 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | |
1884 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | |
1885 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | |
1886 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | |
1887 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | |
1888 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | |
1889 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | |
1890 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | |
1891 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | |
1892 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | |
1893 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | |
1894 | ||
a5312e28 IK |
1895 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
1896 | { | |
1897 | /* rev 1 ncr53c810 chips don't set the class at all which means | |
1898 | * they don't get their resources remapped. Fix that here. | |
1899 | */ | |
1900 | ||
1901 | if (dev->class == PCI_CLASS_NOT_DEFINED) { | |
f0fda801 | 1902 | dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); |
a5312e28 IK |
1903 | dev->class = PCI_CLASS_STORAGE_SCSI; |
1904 | } | |
1905 | } | |
1906 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
1907 | ||
9d265124 DY |
1908 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
1909 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) | |
1910 | { | |
1911 | u16 en1k; | |
1912 | u8 io_base_lo, io_limit_lo; | |
1913 | unsigned long base, limit; | |
1914 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1915 | ||
1916 | pci_read_config_word(dev, 0x40, &en1k); | |
1917 | ||
1918 | if (en1k & 0x200) { | |
f0fda801 | 1919 | dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); |
9d265124 DY |
1920 | |
1921 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
1922 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
1923 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1924 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1925 | ||
1926 | if (base <= limit) { | |
1927 | res->start = base; | |
1928 | res->end = limit + 0x3ff; | |
1929 | } | |
1930 | } | |
1931 | } | |
1932 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); | |
1933 | ||
15a260d5 DY |
1934 | /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 |
1935 | * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() | |
1936 | * in drivers/pci/setup-bus.c | |
1937 | */ | |
1938 | static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) | |
1939 | { | |
1940 | u16 en1k, iobl_adr, iobl_adr_1k; | |
1941 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1942 | ||
1943 | pci_read_config_word(dev, 0x40, &en1k); | |
1944 | ||
1945 | if (en1k & 0x200) { | |
1946 | pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); | |
1947 | ||
1948 | iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); | |
1949 | ||
1950 | if (iobl_adr != iobl_adr_1k) { | |
f0fda801 | 1951 | dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", |
15a260d5 DY |
1952 | iobl_adr,iobl_adr_1k); |
1953 | pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); | |
1954 | } | |
1955 | } | |
1956 | } | |
1957 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); | |
1958 | ||
cf34a8e0 BG |
1959 | /* Under some circumstances, AER is not linked with extended capabilities. |
1960 | * Force it to be linked by setting the corresponding control bit in the | |
1961 | * config space. | |
1962 | */ | |
1597cacb | 1963 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
1964 | { |
1965 | uint8_t b; | |
1966 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { | |
1967 | if (!(b & 0x20)) { | |
1968 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
f0fda801 | 1969 | dev_info(&dev->dev, |
1970 | "Linking AER extended capability\n"); | |
cf34a8e0 BG |
1971 | } |
1972 | } | |
1973 | } | |
1974 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
1975 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
e1a2a51e | 1976 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacb | 1977 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e0 | 1978 | |
53a9bf42 TY |
1979 | static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
1980 | { | |
1981 | /* | |
1982 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
1983 | * which causes unspecified timing errors with a VT6212L on the PCI | |
ca846392 TY |
1984 | * bus leading to USB2.0 packet loss. |
1985 | * | |
1986 | * This quirk is only enabled if a second (on the external PCI bus) | |
1987 | * VT6212L is found -- the CX700 core itself also contains a USB | |
1988 | * host controller with the same PCI ID as the VT6212L. | |
53a9bf42 TY |
1989 | */ |
1990 | ||
ca846392 TY |
1991 | /* Count VT6212L instances */ |
1992 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, | |
1993 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); | |
53a9bf42 | 1994 | uint8_t b; |
ca846392 TY |
1995 | |
1996 | /* p should contain the first (internal) VT6212L -- see if we have | |
1997 | an external one by searching again */ | |
1998 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); | |
1999 | if (!p) | |
2000 | return; | |
2001 | pci_dev_put(p); | |
2002 | ||
53a9bf42 TY |
2003 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { |
2004 | if (b & 0x40) { | |
2005 | /* Turn off PCI Bus Parking */ | |
2006 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
2007 | ||
bc043274 TY |
2008 | dev_info(&dev->dev, |
2009 | "Disabling VIA CX700 PCI parking\n"); | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { | |
2014 | if (b != 0) { | |
53a9bf42 TY |
2015 | /* Turn off PCI Master read caching */ |
2016 | pci_write_config_byte(dev, 0x72, 0x0); | |
bc043274 TY |
2017 | |
2018 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ | |
53a9bf42 | 2019 | pci_write_config_byte(dev, 0x75, 0x1); |
bc043274 TY |
2020 | |
2021 | /* Disable "Read FIFO Timer" */ | |
53a9bf42 TY |
2022 | pci_write_config_byte(dev, 0x77, 0x0); |
2023 | ||
d6505a52 | 2024 | dev_info(&dev->dev, |
bc043274 | 2025 | "Disabling VIA CX700 PCI caching\n"); |
53a9bf42 TY |
2026 | } |
2027 | } | |
2028 | } | |
ca846392 | 2029 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
53a9bf42 | 2030 | |
99cb233d BL |
2031 | /* |
2032 | * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the | |
2033 | * VPD end tag will hang the device. This problem was initially | |
2034 | * observed when a vpd entry was created in sysfs | |
2035 | * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry | |
2036 | * will dump 32k of data. Reading a full 32k will cause an access | |
2037 | * beyond the VPD end tag causing the device to hang. Once the device | |
2038 | * is hung, the bnx2 driver will not be able to reset the device. | |
2039 | * We believe that it is legal to read beyond the end tag and | |
2040 | * therefore the solution is to limit the read/write length. | |
2041 | */ | |
2042 | static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) | |
2043 | { | |
9d82d8ea | 2044 | /* |
35405f25 DH |
2045 | * Only disable the VPD capability for 5706, 5706S, 5708, |
2046 | * 5708S and 5709 rev. A | |
9d82d8ea | 2047 | */ |
99cb233d | 2048 | if ((dev->device == PCI_DEVICE_ID_NX2_5706) || |
35405f25 | 2049 | (dev->device == PCI_DEVICE_ID_NX2_5706S) || |
99cb233d | 2050 | (dev->device == PCI_DEVICE_ID_NX2_5708) || |
9d82d8ea | 2051 | (dev->device == PCI_DEVICE_ID_NX2_5708S) || |
99cb233d BL |
2052 | ((dev->device == PCI_DEVICE_ID_NX2_5709) && |
2053 | (dev->revision & 0xf0) == 0x0)) { | |
2054 | if (dev->vpd) | |
2055 | dev->vpd->len = 0x80; | |
2056 | } | |
2057 | } | |
2058 | ||
bffadffd YZ |
2059 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2060 | PCI_DEVICE_ID_NX2_5706, | |
2061 | quirk_brcm_570x_limit_vpd); | |
2062 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2063 | PCI_DEVICE_ID_NX2_5706S, | |
2064 | quirk_brcm_570x_limit_vpd); | |
2065 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2066 | PCI_DEVICE_ID_NX2_5708, | |
2067 | quirk_brcm_570x_limit_vpd); | |
2068 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2069 | PCI_DEVICE_ID_NX2_5708S, | |
2070 | quirk_brcm_570x_limit_vpd); | |
2071 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2072 | PCI_DEVICE_ID_NX2_5709, | |
2073 | quirk_brcm_570x_limit_vpd); | |
2074 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2075 | PCI_DEVICE_ID_NX2_5709S, | |
2076 | quirk_brcm_570x_limit_vpd); | |
99cb233d | 2077 | |
26c56dc0 MM |
2078 | /* Originally in EDAC sources for i82875P: |
2079 | * Intel tells BIOS developers to hide device 6 which | |
2080 | * configures the overflow device access containing | |
2081 | * the DRBs - this is where we expose device 6. | |
2082 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm | |
2083 | */ | |
2084 | static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) | |
2085 | { | |
2086 | u8 reg; | |
2087 | ||
2088 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { | |
2089 | dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); | |
2090 | pci_write_config_byte(dev, 0xF4, reg | 0x02); | |
2091 | } | |
2092 | } | |
2093 | ||
2094 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, | |
2095 | quirk_unhide_mch_dev6); | |
2096 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, | |
2097 | quirk_unhide_mch_dev6); | |
2098 | ||
2099 | ||
3f79e107 | 2100 | #ifdef CONFIG_PCI_MSI |
ebdf7d39 TH |
2101 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
2102 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | |
2103 | * some other busses controlled by the chipset even if Linux is not | |
2104 | * aware of it. Instead of setting the flag on all busses in the | |
2105 | * machine, simply disable MSI globally. | |
3f79e107 | 2106 | */ |
ebdf7d39 | 2107 | static void __init quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 2108 | { |
88187dfa | 2109 | pci_no_msi(); |
f0fda801 | 2110 | dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); |
3f79e107 | 2111 | } |
ebdf7d39 TH |
2112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2113 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
2114 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
66d715c9 | 2115 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f | 2116 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd3 | 2117 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
3f79e107 BG |
2118 | |
2119 | /* Disable MSI on chipsets that are known to not support it */ | |
2120 | static void __devinit quirk_disable_msi(struct pci_dev *dev) | |
2121 | { | |
2122 | if (dev->subordinate) { | |
f0fda801 | 2123 | dev_warn(&dev->dev, "MSI quirk detected; " |
2124 | "subordinate MSI disabled\n"); | |
3f79e107 BG |
2125 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2126 | } | |
2127 | } | |
2128 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
5193d7a7 CL |
2129 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9602, quirk_disable_msi); |
2130 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASUSTEK, 0x9602, quirk_disable_msi); | |
2131 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AI, 0x9602, quirk_disable_msi); | |
134b3450 | 2132 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
9313ff45 | 2133 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
6397c75c BG |
2134 | |
2135 | /* Go through the list of Hypertransport capabilities and | |
2136 | * return 1 if a HT MSI capability is found and enabled */ | |
2137 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) | |
2138 | { | |
7a380507 ME |
2139 | int pos, ttl = 48; |
2140 | ||
2141 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2142 | while (pos && ttl--) { | |
2143 | u8 flags; | |
2144 | ||
2145 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2146 | &flags) == 0) | |
2147 | { | |
f0fda801 | 2148 | dev_info(&dev->dev, "Found %s HT MSI Mapping\n", |
7a380507 | 2149 | flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801 | 2150 | "enabled" : "disabled"); |
7a380507 | 2151 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75c | 2152 | } |
7a380507 ME |
2153 | |
2154 | pos = pci_find_next_ht_capability(dev, pos, | |
2155 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
2156 | } |
2157 | return 0; | |
2158 | } | |
2159 | ||
2160 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ | |
2161 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) | |
2162 | { | |
2163 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
f0fda801 | 2164 | dev_warn(&dev->dev, "MSI quirk detected; " |
2165 | "subordinate MSI disabled\n"); | |
6397c75c BG |
2166 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2167 | } | |
2168 | } | |
2169 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
2170 | quirk_msi_ht_cap); | |
6bae1d96 | 2171 | |
6397c75c BG |
2172 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
2173 | * MSI are supported if the MSI capability set in any of these mappings. | |
2174 | */ | |
2175 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) | |
2176 | { | |
2177 | struct pci_dev *pdev; | |
2178 | ||
2179 | if (!dev->subordinate) | |
2180 | return; | |
2181 | ||
2182 | /* check HT MSI cap on this chipset and the root one. | |
2183 | * a single one having MSI is enough to be sure that MSI are supported. | |
2184 | */ | |
11f242f0 | 2185 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
2186 | if (!pdev) |
2187 | return; | |
0c875c28 | 2188 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
f0fda801 | 2189 | dev_warn(&dev->dev, "MSI quirk detected; " |
2190 | "subordinate MSI disabled\n"); | |
6397c75c BG |
2191 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2192 | } | |
11f242f0 | 2193 | pci_dev_put(pdev); |
6397c75c BG |
2194 | } |
2195 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2196 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 | 2197 | |
415b6d0e BH |
2198 | /* Force enable MSI mapping capability on HT bridges */ |
2199 | static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) | |
9dc625e7 PC |
2200 | { |
2201 | int pos, ttl = 48; | |
2202 | ||
2203 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2204 | while (pos && ttl--) { | |
2205 | u8 flags; | |
2206 | ||
2207 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2208 | &flags) == 0) { | |
2209 | dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); | |
2210 | ||
2211 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2212 | flags | HT_MSI_FLAGS_ENABLE); | |
2213 | } | |
2214 | pos = pci_find_next_ht_capability(dev, pos, | |
2215 | HT_CAPTYPE_MSI_MAPPING); | |
2216 | } | |
2217 | } | |
415b6d0e BH |
2218 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2219 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
2220 | ht_enable_msi_mapping); | |
9dc625e7 | 2221 | |
e0ae4f55 YL |
2222 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2223 | ht_enable_msi_mapping); | |
2224 | ||
e4146bb9 | 2225 | /* The P5N32-SLI motherboards from Asus have a problem with msi |
75e07fc3 AP |
2226 | * for the MCP55 NIC. It is not yet determined whether the msi problem |
2227 | * also affects other devices. As for now, turn off msi for this device. | |
2228 | */ | |
2229 | static void __devinit nvenet_msi_disable(struct pci_dev *dev) | |
2230 | { | |
e4146bb9 BH |
2231 | if (dmi_name_in_vendors("P5N32-SLI PREMIUM") || |
2232 | dmi_name_in_vendors("P5N32-E SLI")) { | |
75e07fc3 | 2233 | dev_info(&dev->dev, |
e4146bb9 | 2234 | "Disabling msi for MCP55 NIC on P5N32-SLI\n"); |
75e07fc3 AP |
2235 | dev->no_msi = 1; |
2236 | } | |
2237 | } | |
2238 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2239 | PCI_DEVICE_ID_NVIDIA_NVENET_15, | |
2240 | nvenet_msi_disable); | |
2241 | ||
de745306 YL |
2242 | static int __devinit ht_check_msi_mapping(struct pci_dev *dev) |
2243 | { | |
2244 | int pos, ttl = 48; | |
2245 | int found = 0; | |
2246 | ||
2247 | /* check if there is HT MSI cap or enabled on this device */ | |
2248 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2249 | while (pos && ttl--) { | |
2250 | u8 flags; | |
2251 | ||
2252 | if (found < 1) | |
2253 | found = 1; | |
2254 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2255 | &flags) == 0) { | |
2256 | if (flags & HT_MSI_FLAGS_ENABLE) { | |
2257 | if (found < 2) { | |
2258 | found = 2; | |
2259 | break; | |
2260 | } | |
2261 | } | |
2262 | } | |
2263 | pos = pci_find_next_ht_capability(dev, pos, | |
2264 | HT_CAPTYPE_MSI_MAPPING); | |
2265 | } | |
2266 | ||
2267 | return found; | |
2268 | } | |
2269 | ||
2270 | static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) | |
2271 | { | |
2272 | struct pci_dev *dev; | |
2273 | int pos; | |
2274 | int i, dev_no; | |
2275 | int found = 0; | |
2276 | ||
2277 | dev_no = host_bridge->devfn >> 3; | |
2278 | for (i = dev_no + 1; i < 0x20; i++) { | |
2279 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); | |
2280 | if (!dev) | |
2281 | continue; | |
2282 | ||
2283 | /* found next host bridge ?*/ | |
2284 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2285 | if (pos != 0) { | |
2286 | pci_dev_put(dev); | |
2287 | break; | |
2288 | } | |
2289 | ||
2290 | if (ht_check_msi_mapping(dev)) { | |
2291 | found = 1; | |
2292 | pci_dev_put(dev); | |
2293 | break; | |
2294 | } | |
2295 | pci_dev_put(dev); | |
2296 | } | |
2297 | ||
2298 | return found; | |
2299 | } | |
2300 | ||
eeafda70 YL |
2301 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2302 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ | |
2303 | ||
2304 | static int __devinit is_end_of_ht_chain(struct pci_dev *dev) | |
2305 | { | |
2306 | int pos, ctrl_off; | |
2307 | int end = 0; | |
2308 | u16 flags, ctrl; | |
2309 | ||
2310 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2311 | ||
2312 | if (!pos) | |
2313 | goto out; | |
2314 | ||
2315 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); | |
2316 | ||
2317 | ctrl_off = ((flags >> 10) & 1) ? | |
2318 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; | |
2319 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); | |
2320 | ||
2321 | if (ctrl & (1 << 6)) | |
2322 | end = 1; | |
2323 | ||
2324 | out: | |
2325 | return end; | |
2326 | } | |
2327 | ||
1dec6b05 | 2328 | static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 PC |
2329 | { |
2330 | struct pci_dev *host_bridge; | |
1dec6b05 YL |
2331 | int pos; |
2332 | int i, dev_no; | |
2333 | int found = 0; | |
2334 | ||
2335 | dev_no = dev->devfn >> 3; | |
2336 | for (i = dev_no; i >= 0; i--) { | |
2337 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); | |
2338 | if (!host_bridge) | |
2339 | continue; | |
2340 | ||
2341 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2342 | if (pos != 0) { | |
2343 | found = 1; | |
2344 | break; | |
2345 | } | |
2346 | pci_dev_put(host_bridge); | |
2347 | } | |
2348 | ||
2349 | if (!found) | |
2350 | return; | |
2351 | ||
eeafda70 YL |
2352 | /* don't enable end_device/host_bridge with leaf directly here */ |
2353 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && | |
2354 | host_bridge_with_leaf(host_bridge)) | |
de745306 YL |
2355 | goto out; |
2356 | ||
1dec6b05 YL |
2357 | /* root did that ! */ |
2358 | if (msi_ht_cap_enabled(host_bridge)) | |
2359 | goto out; | |
2360 | ||
2361 | ht_enable_msi_mapping(dev); | |
2362 | ||
2363 | out: | |
2364 | pci_dev_put(host_bridge); | |
2365 | } | |
2366 | ||
2367 | static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) | |
2368 | { | |
2369 | int pos, ttl = 48; | |
2370 | ||
2371 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2372 | while (pos && ttl--) { | |
2373 | u8 flags; | |
2374 | ||
2375 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2376 | &flags) == 0) { | |
6a958d5b | 2377 | dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); |
1dec6b05 YL |
2378 | |
2379 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2380 | flags & ~HT_MSI_FLAGS_ENABLE); | |
2381 | } | |
2382 | pos = pci_find_next_ht_capability(dev, pos, | |
2383 | HT_CAPTYPE_MSI_MAPPING); | |
2384 | } | |
2385 | } | |
2386 | ||
de745306 | 2387 | static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b05 YL |
2388 | { |
2389 | struct pci_dev *host_bridge; | |
2390 | int pos; | |
2391 | int found; | |
2392 | ||
2393 | /* check if there is HT MSI cap or enabled on this device */ | |
2394 | found = ht_check_msi_mapping(dev); | |
2395 | ||
2396 | /* no HT MSI CAP */ | |
2397 | if (found == 0) | |
2398 | return; | |
9dc625e7 PC |
2399 | |
2400 | /* | |
2401 | * HT MSI mapping should be disabled on devices that are below | |
2402 | * a non-Hypertransport host bridge. Locate the host bridge... | |
2403 | */ | |
2404 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
2405 | if (host_bridge == NULL) { | |
2406 | dev_warn(&dev->dev, | |
2407 | "nv_msi_ht_cap_quirk didn't locate host bridge\n"); | |
2408 | return; | |
2409 | } | |
2410 | ||
2411 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2412 | if (pos != 0) { | |
2413 | /* Host bridge is to HT */ | |
1dec6b05 YL |
2414 | if (found == 1) { |
2415 | /* it is not enabled, try to enable it */ | |
de745306 YL |
2416 | if (all) |
2417 | ht_enable_msi_mapping(dev); | |
2418 | else | |
2419 | nv_ht_enable_msi_mapping(dev); | |
1dec6b05 | 2420 | } |
9dc625e7 PC |
2421 | return; |
2422 | } | |
2423 | ||
1dec6b05 YL |
2424 | /* HT MSI is not enabled */ |
2425 | if (found == 1) | |
2426 | return; | |
9dc625e7 | 2427 | |
1dec6b05 YL |
2428 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
2429 | ht_disable_msi_mapping(dev); | |
9dc625e7 | 2430 | } |
de745306 YL |
2431 | |
2432 | static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) | |
2433 | { | |
2434 | return __nv_msi_ht_cap_quirk(dev, 1); | |
2435 | } | |
2436 | ||
2437 | static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) | |
2438 | { | |
2439 | return __nv_msi_ht_cap_quirk(dev, 0); | |
2440 | } | |
2441 | ||
2442 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); | |
6dab62ee | 2443 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
de745306 YL |
2444 | |
2445 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); | |
6dab62ee | 2446 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
9dc625e7 | 2447 | |
ba698ad4 DM |
2448 | static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) |
2449 | { | |
2450 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2451 | } | |
4600c9d7 SH |
2452 | static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
2453 | { | |
2454 | struct pci_dev *p; | |
2455 | ||
2456 | /* SB700 MSI issue will be fixed at HW level from revision A21, | |
2457 | * we need check PCI REVISION ID of SMBus controller to get SB700 | |
2458 | * revision. | |
2459 | */ | |
2460 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2461 | NULL); | |
2462 | if (!p) | |
2463 | return; | |
2464 | ||
2465 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) | |
2466 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2467 | pci_dev_put(p); | |
2468 | } | |
ba698ad4 DM |
2469 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2470 | PCI_DEVICE_ID_TIGON3_5780, | |
2471 | quirk_msi_intx_disable_bug); | |
2472 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2473 | PCI_DEVICE_ID_TIGON3_5780S, | |
2474 | quirk_msi_intx_disable_bug); | |
2475 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2476 | PCI_DEVICE_ID_TIGON3_5714, | |
2477 | quirk_msi_intx_disable_bug); | |
2478 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2479 | PCI_DEVICE_ID_TIGON3_5714S, | |
2480 | quirk_msi_intx_disable_bug); | |
2481 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2482 | PCI_DEVICE_ID_TIGON3_5715, | |
2483 | quirk_msi_intx_disable_bug); | |
2484 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2485 | PCI_DEVICE_ID_TIGON3_5715S, | |
2486 | quirk_msi_intx_disable_bug); | |
2487 | ||
bc38b411 | 2488 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d7 | 2489 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2490 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d7 | 2491 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2492 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d7 | 2493 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2494 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d7 | 2495 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2496 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d7 | 2497 | quirk_msi_intx_disable_ati_bug); |
bc38b411 DM |
2498 | |
2499 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
2500 | quirk_msi_intx_disable_bug); | |
2501 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
2502 | quirk_msi_intx_disable_bug); | |
2503 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
2504 | quirk_msi_intx_disable_bug); | |
2505 | ||
3f79e107 | 2506 | #endif /* CONFIG_PCI_MSI */ |
3d137310 | 2507 | |
7eb93b17 YZ |
2508 | #ifdef CONFIG_PCI_IOV |
2509 | ||
2510 | /* | |
2511 | * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the | |
2512 | * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the | |
2513 | * old Flash Memory Space. | |
2514 | */ | |
2515 | static void __devinit quirk_i82576_sriov(struct pci_dev *dev) | |
2516 | { | |
2517 | int pos, flags; | |
2518 | u32 bar, start, size; | |
2519 | ||
2520 | if (PAGE_SIZE > 0x10000) | |
2521 | return; | |
2522 | ||
2523 | flags = pci_resource_flags(dev, 0); | |
2524 | if ((flags & PCI_BASE_ADDRESS_SPACE) != | |
2525 | PCI_BASE_ADDRESS_SPACE_MEMORY || | |
2526 | (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != | |
2527 | PCI_BASE_ADDRESS_MEM_TYPE_32) | |
2528 | return; | |
2529 | ||
2530 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); | |
2531 | if (!pos) | |
2532 | return; | |
2533 | ||
2534 | pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar); | |
2535 | if (bar & PCI_BASE_ADDRESS_MEM_MASK) | |
2536 | return; | |
2537 | ||
2538 | start = pci_resource_start(dev, 1); | |
2539 | size = pci_resource_len(dev, 1); | |
2540 | if (!start || size != 0x400000 || start & (size - 1)) | |
2541 | return; | |
2542 | ||
2543 | pci_resource_flags(dev, 1) = 0; | |
2544 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); | |
2545 | pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start); | |
2546 | pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2); | |
2547 | ||
2548 | dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n"); | |
2549 | } | |
2550 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov); | |
2551 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov); | |
2552 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov); | |
dcb4ea2e AD |
2553 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov); |
2554 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov); | |
6f1186be | 2555 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150d, quirk_i82576_sriov); |
7a0deb6b | 2556 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1518, quirk_i82576_sriov); |
7eb93b17 YZ |
2557 | |
2558 | #endif /* CONFIG_PCI_IOV */ | |
2559 | ||
3322340a FR |
2560 | /* Allow manual resource allocation for PCI hotplug bridges |
2561 | * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For | |
2562 | * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), | |
2563 | * kernel fails to allocate resources when hotplug device is | |
2564 | * inserted and PCI bus is rescanned. | |
2565 | */ | |
2566 | static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) | |
2567 | { | |
2568 | dev->is_hotplug_bridge = 1; | |
2569 | } | |
2570 | ||
2571 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); | |
2572 | ||
03cd8f7e ML |
2573 | /* |
2574 | * This is a quirk for the Ricoh MMC controller found as a part of | |
2575 | * some mulifunction chips. | |
2576 | ||
2577 | * This is very similiar and based on the ricoh_mmc driver written by | |
2578 | * Philip Langdale. Thank you for these magic sequences. | |
2579 | * | |
2580 | * These chips implement the four main memory card controllers (SD, MMC, MS, xD) | |
2581 | * and one or both of cardbus or firewire. | |
2582 | * | |
2583 | * It happens that they implement SD and MMC | |
2584 | * support as separate controllers (and PCI functions). The linux SDHCI | |
2585 | * driver supports MMC cards but the chip detects MMC cards in hardware | |
2586 | * and directs them to the MMC controller - so the SDHCI driver never sees | |
2587 | * them. | |
2588 | * | |
2589 | * To get around this, we must disable the useless MMC controller. | |
2590 | * At that point, the SDHCI controller will start seeing them | |
2591 | * It seems to be the case that the relevant PCI registers to deactivate the | |
2592 | * MMC controller live on PCI function 0, which might be the cardbus controller | |
2593 | * or the firewire controller, depending on the particular chip in question | |
2594 | * | |
2595 | * This has to be done early, because as soon as we disable the MMC controller | |
2596 | * other pci functions shift up one level, e.g. function #2 becomes function | |
2597 | * #1, and this will confuse the pci core. | |
2598 | */ | |
2599 | ||
2600 | #ifdef CONFIG_MMC_RICOH_MMC | |
2601 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) | |
2602 | { | |
2603 | /* disable via cardbus interface */ | |
2604 | u8 write_enable; | |
2605 | u8 write_target; | |
2606 | u8 disable; | |
2607 | ||
2608 | /* disable must be done via function #0 */ | |
2609 | if (PCI_FUNC(dev->devfn)) | |
2610 | return; | |
2611 | ||
2612 | pci_read_config_byte(dev, 0xB7, &disable); | |
2613 | if (disable & 0x02) | |
2614 | return; | |
2615 | ||
2616 | pci_read_config_byte(dev, 0x8E, &write_enable); | |
2617 | pci_write_config_byte(dev, 0x8E, 0xAA); | |
2618 | pci_read_config_byte(dev, 0x8D, &write_target); | |
2619 | pci_write_config_byte(dev, 0x8D, 0xB7); | |
2620 | pci_write_config_byte(dev, 0xB7, disable | 0x02); | |
2621 | pci_write_config_byte(dev, 0x8E, write_enable); | |
2622 | pci_write_config_byte(dev, 0x8D, write_target); | |
2623 | ||
2624 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); | |
2625 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); | |
2626 | } | |
2627 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2628 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2629 | ||
2630 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) | |
2631 | { | |
2632 | /* disable via firewire interface */ | |
2633 | u8 write_enable; | |
2634 | u8 disable; | |
2635 | ||
2636 | /* disable must be done via function #0 */ | |
2637 | if (PCI_FUNC(dev->devfn)) | |
2638 | return; | |
2639 | ||
2640 | pci_read_config_byte(dev, 0xCB, &disable); | |
2641 | ||
2642 | if (disable & 0x02) | |
2643 | return; | |
2644 | ||
2645 | pci_read_config_byte(dev, 0xCA, &write_enable); | |
2646 | pci_write_config_byte(dev, 0xCA, 0x57); | |
2647 | pci_write_config_byte(dev, 0xCB, disable | 0x02); | |
2648 | pci_write_config_byte(dev, 0xCA, write_enable); | |
2649 | ||
2650 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); | |
2651 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); | |
2652 | } | |
2653 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
2654 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
2655 | #endif /*CONFIG_MMC_RICOH_MMC*/ | |
2656 | ||
2657 | ||
bfb0f330 JB |
2658 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, |
2659 | struct pci_fixup *end) | |
3d137310 TP |
2660 | { |
2661 | while (f < end) { | |
2662 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && | |
bfb0f330 | 2663 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
c9bbb4ab | 2664 | dev_dbg(&dev->dev, "calling %pF\n", f->hook); |
3d137310 TP |
2665 | f->hook(dev); |
2666 | } | |
2667 | f++; | |
2668 | } | |
2669 | } | |
2670 | ||
2671 | extern struct pci_fixup __start_pci_fixups_early[]; | |
2672 | extern struct pci_fixup __end_pci_fixups_early[]; | |
2673 | extern struct pci_fixup __start_pci_fixups_header[]; | |
2674 | extern struct pci_fixup __end_pci_fixups_header[]; | |
2675 | extern struct pci_fixup __start_pci_fixups_final[]; | |
2676 | extern struct pci_fixup __end_pci_fixups_final[]; | |
2677 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
2678 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
2679 | extern struct pci_fixup __start_pci_fixups_resume[]; | |
2680 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
2681 | extern struct pci_fixup __start_pci_fixups_resume_early[]; | |
2682 | extern struct pci_fixup __end_pci_fixups_resume_early[]; | |
2683 | extern struct pci_fixup __start_pci_fixups_suspend[]; | |
2684 | extern struct pci_fixup __end_pci_fixups_suspend[]; | |
2685 | ||
2686 | ||
2687 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
2688 | { | |
2689 | struct pci_fixup *start, *end; | |
2690 | ||
2691 | switch(pass) { | |
2692 | case pci_fixup_early: | |
2693 | start = __start_pci_fixups_early; | |
2694 | end = __end_pci_fixups_early; | |
2695 | break; | |
2696 | ||
2697 | case pci_fixup_header: | |
2698 | start = __start_pci_fixups_header; | |
2699 | end = __end_pci_fixups_header; | |
2700 | break; | |
2701 | ||
2702 | case pci_fixup_final: | |
2703 | start = __start_pci_fixups_final; | |
2704 | end = __end_pci_fixups_final; | |
2705 | break; | |
2706 | ||
2707 | case pci_fixup_enable: | |
2708 | start = __start_pci_fixups_enable; | |
2709 | end = __end_pci_fixups_enable; | |
2710 | break; | |
2711 | ||
2712 | case pci_fixup_resume: | |
2713 | start = __start_pci_fixups_resume; | |
2714 | end = __end_pci_fixups_resume; | |
2715 | break; | |
2716 | ||
2717 | case pci_fixup_resume_early: | |
2718 | start = __start_pci_fixups_resume_early; | |
2719 | end = __end_pci_fixups_resume_early; | |
2720 | break; | |
2721 | ||
2722 | case pci_fixup_suspend: | |
2723 | start = __start_pci_fixups_suspend; | |
2724 | end = __end_pci_fixups_suspend; | |
2725 | break; | |
2726 | ||
2727 | default: | |
2728 | /* stupid compiler warning, you would think with an enum... */ | |
2729 | return; | |
2730 | } | |
2731 | pci_do_fixups(dev, start, end); | |
2732 | } | |
93177a74 | 2733 | EXPORT_SYMBOL(pci_fixup_device); |
8d86fb2c | 2734 | |
00010268 | 2735 | static int __init pci_apply_final_quirks(void) |
8d86fb2c DW |
2736 | { |
2737 | struct pci_dev *dev = NULL; | |
ac1aa47b JB |
2738 | u8 cls = 0; |
2739 | u8 tmp; | |
2740 | ||
2741 | if (pci_cache_line_size) | |
2742 | printk(KERN_DEBUG "PCI: CLS %u bytes\n", | |
2743 | pci_cache_line_size << 2); | |
8d86fb2c DW |
2744 | |
2745 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
2746 | pci_fixup_device(pci_fixup_final, dev); | |
ac1aa47b JB |
2747 | /* |
2748 | * If arch hasn't set it explicitly yet, use the CLS | |
2749 | * value shared by all PCI devices. If there's a | |
2750 | * mismatch, fall back to the default value. | |
2751 | */ | |
2752 | if (!pci_cache_line_size) { | |
2753 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); | |
2754 | if (!cls) | |
2755 | cls = tmp; | |
2756 | if (!tmp || cls == tmp) | |
2757 | continue; | |
2758 | ||
2759 | printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " | |
2760 | "using %u bytes\n", cls << 2, tmp << 2, | |
2761 | pci_dfl_cache_line_size << 2); | |
2762 | pci_cache_line_size = pci_dfl_cache_line_size; | |
2763 | } | |
2764 | } | |
2765 | if (!pci_cache_line_size) { | |
2766 | printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", | |
2767 | cls << 2, pci_dfl_cache_line_size << 2); | |
2820f333 | 2768 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
8d86fb2c DW |
2769 | } |
2770 | ||
2771 | return 0; | |
2772 | } | |
2773 | ||
cf6f3bf7 | 2774 | fs_initcall_sync(pci_apply_final_quirks); |
b9c3b266 DC |
2775 | |
2776 | /* | |
2777 | * Followings are device-specific reset methods which can be used to | |
2778 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are | |
2779 | * not available. | |
2780 | */ | |
aeb30016 DC |
2781 | static int reset_intel_generic_dev(struct pci_dev *dev, int probe) |
2782 | { | |
2783 | int pos; | |
2784 | ||
2785 | /* only implement PCI_CLASS_SERIAL_USB at present */ | |
2786 | if (dev->class == PCI_CLASS_SERIAL_USB) { | |
2787 | pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); | |
2788 | if (!pos) | |
2789 | return -ENOTTY; | |
2790 | ||
2791 | if (probe) | |
2792 | return 0; | |
2793 | ||
2794 | pci_write_config_byte(dev, pos + 0x4, 1); | |
2795 | msleep(100); | |
2796 | ||
2797 | return 0; | |
2798 | } else { | |
2799 | return -ENOTTY; | |
2800 | } | |
2801 | } | |
2802 | ||
c763e7b5 DC |
2803 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) |
2804 | { | |
2805 | int pos; | |
2806 | ||
2807 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
2808 | if (!pos) | |
2809 | return -ENOTTY; | |
2810 | ||
2811 | if (probe) | |
2812 | return 0; | |
2813 | ||
2814 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, | |
2815 | PCI_EXP_DEVCTL_BCR_FLR); | |
2816 | msleep(100); | |
2817 | ||
2818 | return 0; | |
2819 | } | |
2820 | ||
2821 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed | |
2822 | ||
5b889bf2 | 2823 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
c763e7b5 DC |
2824 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
2825 | reset_intel_82599_sfp_virtfn }, | |
aeb30016 DC |
2826 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
2827 | reset_intel_generic_dev }, | |
b9c3b266 DC |
2828 | { 0 } |
2829 | }; | |
5b889bf2 RW |
2830 | |
2831 | int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
2832 | { | |
df9d1e8a | 2833 | const struct pci_dev_reset_methods *i; |
5b889bf2 RW |
2834 | |
2835 | for (i = pci_dev_reset_methods; i->reset; i++) { | |
2836 | if ((i->vendor == dev->vendor || | |
2837 | i->vendor == (u16)PCI_ANY_ID) && | |
2838 | (i->device == dev->device || | |
2839 | i->device == (u16)PCI_ANY_ID)) | |
2840 | return i->reset(dev, probe); | |
2841 | } | |
2842 | ||
2843 | return -ENOTTY; | |
2844 | } |