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[PATCH] ub: suppress gcc warnings for pointer casts
[deliverable/linux.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
14
15#include <linux/config.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
25be5e6c 21#include <linux/acpi.h>
bc56b9e0 22#include "pci.h"
1da177e4
LT		 23
24/* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26static void __devinit quirk_passive_release(struct pci_dev *dev)
27{
28 struct pci_dev *d = NULL;
29 unsigned char dlc;
30
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
35 if (!(dlc & 1<<1)) {
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
37 dlc |= 1<<1;
38 pci_write_config_byte(d, 0x82, dlc);
39 }
40 }
41}
42DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
43
44/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
47
48 This appears to be BIOS not version dependent. So presumably there is a
49 chipset level fix */
50int isa_dma_bridge_buggy; /* Exported */
51
52static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
53{
54 if (!isa_dma_bridge_buggy) {
55 isa_dma_bridge_buggy=1;
56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
57 }
58}
59 /*
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
62 */
63DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
64DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
65DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
66DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
67DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
68DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
69DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
70
71int pci_pci_problems;
72
73/*
74 * Chipsets where PCI->PCI transfers vanish or hang
75 */
76static void __devinit quirk_nopcipci(struct pci_dev *dev)
77{
78 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems |= PCIPCI_FAIL;
81 }
82}
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
85
86/*
87 * Triton requires workarounds to be used by the drivers
88 */
89static void __devinit quirk_triton(struct pci_dev *dev)
90{
91 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_TRITON;
94 }
95}
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
100
101/*
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
107 *
108 * Updated based on further information from the site and also on
109 * information provided by VIA
110 */
111static void __devinit quirk_vialatency(struct pci_dev *dev)
112{
113 struct pci_dev *p;
114 u8 rev;
115 u8 busarb;
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
118
119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
120 if (p!=NULL) {
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev < 0x40 || rev > 0x42)
125 goto exit;
126 } else {
127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
128 if (p==NULL) /* No problem parts */
129 goto exit;
130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
131 /* Check for buggy part revisions */
132 if (rev < 0x10 || rev > 0x12)
133 goto exit;
134 }
135
136 /*
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
142 *
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
147 */
148
149 pci_read_config_byte(dev, 0x76, &busarb);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
152 busarb &= ~(1<<5);
153 busarb |= (1<<4);
154 pci_write_config_byte(dev, 0x76, busarb);
155 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
156exit:
157 pci_dev_put(p);
158}
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
162
163/*
164 * VIA Apollo VP3 needs ETBF on BT848/878
165 */
166static void __devinit quirk_viaetbf(struct pci_dev *dev)
167{
168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
170 pci_pci_problems |= PCIPCI_VIAETBF;
171 }
172}
173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
174
175static void __devinit quirk_vsfx(struct pci_dev *dev)
176{
177 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
179 pci_pci_problems |= PCIPCI_VSFX;
180 }
181}
182DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
183
184/*
185 * Ali Magik requires workarounds to be used by the drivers
186 * that DMA to AGP space. Latency must be set to 0xA and triton
187 * workaround applied too
188 * [Info kindly provided by ALi]
189 */
190static void __init quirk_alimagik(struct pci_dev *dev)
191{
192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
195 }
196}
197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
198DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
199
200/*
201 * Natoma has some interesting boundary conditions with Zoran stuff
202 * at least
203 */
204static void __devinit quirk_natoma(struct pci_dev *dev)
205{
206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_NATOMA;
209 }
210}
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
217
218/*
219 * This chip can cause PCI parity errors if config register 0xA0 is read
220 * while DMAs are occurring.
221 */
222static void __devinit quirk_citrine(struct pci_dev *dev)
223{
224 dev->cfg_size = 0xA0;
225}
226DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
227
228/*
229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
230 * If it's needed, re-allocate the region.
231 */
232static void __devinit quirk_s3_64M(struct pci_dev *dev)
233{
234 struct resource *r = &dev->resource[0];
235
236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
237 r->start = 0;
238 r->end = 0x3ffffff;
239 }
240}
241DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
242DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
243
6693e74a
LT		 244static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
245 unsigned size, int nr, const char *name)
1da177e4
LT		 246{
247 region &= ~(size-1);
248 if (region) {
085ae41f 249 struct pci_bus_region bus_region;
1da177e4
LT		 250 struct resource *res = dev->resource + nr;
251
252 res->name = pci_name(dev);
253 res->start = region;
254 res->end = region + size - 1;
255 res->flags = IORESOURCE_IO;
085ae41f
DM		 256
257 /* Convert from PCI bus to resource space. */
258 bus_region.start = res->start;
259 bus_region.end = res->end;
260 pcibios_bus_to_resource(dev, res, &bus_region);
261
1da177e4 262 pci_claim_resource(dev, nr);
6693e74a 263 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 264 }
265}
266
267/*
268 * ATI Northbridge setups MCE the processor if you even
269 * read somewhere between 0x3b0->0x3bb or read 0x3d3
270 */
271static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
272{
273 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
274 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
275 request_region(0x3b0, 0x0C, "RadeonIGP");
276 request_region(0x3d3, 0x01, "RadeonIGP");
277}
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
279
280/*
281 * Let's make the southbridge information explicit instead
282 * of having to worry about people probing the ACPI areas,
283 * for example.. (Yes, it happens, and if you read the wrong
284 * ACPI register it will put the machine to sleep with no
285 * way of waking it up again. Bummer).
286 *
287 * ALI M7101: Two IO regions pointed to by words at
288 * 0xE0 (64 bytes of ACPI registers)
289 * 0xE2 (32 bytes of SMB registers)
290 */
291static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
292{
293 u16 region;
294
295 pci_read_config_word(dev, 0xE0, &region);
6693e74a 296 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 297 pci_read_config_word(dev, 0xE2, &region);
6693e74a 298 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 299}
300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
301
6693e74a
LT		 302static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
303{
304 u32 devres;
305 u32 mask, size, base;
306
307 pci_read_config_dword(dev, port, &devres);
308 if ((devres & enable) != enable)
309 return;
310 mask = (devres >> 16) & 15;
311 base = devres & 0xffff;
312 size = 16;
313 for (;;) {
314 unsigned bit = size >> 1;
315 if ((bit & mask) == bit)
316 break;
317 size = bit;
318 }
319 /*
320 * For now we only print it out. Eventually we'll want to
321 * reserve it (at least if it's in the 0x1000+ range), but
322 * let's get enough confirmation reports first.
323 */
324 base &= -size;
325 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
326}
327
328static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
329{
330 u32 devres;
331 u32 mask, size, base;
332
333 pci_read_config_dword(dev, port, &devres);
334 if ((devres & enable) != enable)
335 return;
336 base = devres & 0xffff0000;
337 mask = (devres & 0x3f) << 16;
338 size = 128 << 16;
339 for (;;) {
340 unsigned bit = size >> 1;
341 if ((bit & mask) == bit)
342 break;
343 size = bit;
344 }
345 /*
346 * For now we only print it out. Eventually we'll want to
347 * reserve it, but let's get enough confirmation reports first.
348 */
349 base &= -size;
350 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
351}
352
1da177e4
LT		 353/*
354 * PIIX4 ACPI: Two IO regions pointed to by longwords at
355 * 0x40 (64 bytes of ACPI registers)
356 * 0x90 (32 bytes of SMB registers)
6693e74a 357 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 358 */
359static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
360{
6693e74a 361 u32 region, res_a;
1da177e4
LT		 362
363 pci_read_config_dword(dev, 0x40, &region);
6693e74a 364 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 365 pci_read_config_dword(dev, 0x90, &region);
6693e74a
LT		 366 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
367
368 /* Device resource A has enables for some of the other ones */
369 pci_read_config_dword(dev, 0x5c, &res_a);
370
371 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
372 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
373
374 /* Device resource D is just bitfields for static resources */
375
376 /* Device 12 enabled? */
377 if (res_a & (1 << 29)) {
378 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
379 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
380 }
381 /* Device 13 enabled? */
382 if (res_a & (1 << 30)) {
383 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
384 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
385 }
386 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
387 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 388}
389DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
390
391/*
392 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
393 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
394 * 0x58 (64 bytes of GPIO I/O space)
395 */
396static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
397{
398 u32 region;
399
400 pci_read_config_dword(dev, 0x40, &region);
6693e74a 401 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 402
403 pci_read_config_dword(dev, 0x58, &region);
6693e74a 404 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 405}
406DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
407DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
408DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
409DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
410DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
411DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
412DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
413DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
414DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 416
2cea752f
M		 417static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
418{
419 u32 region;
420
421 pci_read_config_dword(dev, 0x40, &region);
422 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
423
424 pci_read_config_dword(dev, 0x48, &region);
425 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
426}
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
428
1da177e4
LT		 429/*
430 * VIA ACPI: One IO region pointed to by longword at
431 * 0x48 or 0x20 (256 bytes of ACPI registers)
432 */
433static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
434{
435 u8 rev;
436 u32 region;
437
438 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
439 if (rev & 0x10) {
440 pci_read_config_dword(dev, 0x48, &region);
441 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 442 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 443 }
444}
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
446
447/*
448 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
449 * 0x48 (256 bytes of ACPI registers)
450 * 0x70 (128 bytes of hardware monitoring register)
451 * 0x90 (16 bytes of SMB registers)
452 */
453static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
454{
455 u16 hm;
456 u32 smb;
457
458 quirk_vt82c586_acpi(dev);
459
460 pci_read_config_word(dev, 0x70, &hm);
461 hm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 462 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c868 HW-mon");
1da177e4
LT		 463
464 pci_read_config_dword(dev, 0x90, &smb);
465 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 466 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c868 SMB");
1da177e4
LT		 467}
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
469
6d85f29b
IK		 470/*
471 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
472 * 0x88 (128 bytes of power management registers)
473 * 0xd0 (16 bytes of SMB registers)
474 */
475static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
476{
477 u16 pm, smb;
478
479 pci_read_config_word(dev, 0x88, &pm);
480 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 481 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 482
483 pci_read_config_word(dev, 0xd0, &smb);
484 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 485 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 486}
487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
488
1da177e4
LT		 489
490#ifdef CONFIG_X86_IO_APIC
491
492#include <asm/io_apic.h>
493
494/*
495 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
496 * devices to the external APIC.
497 *
498 * TODO: When we have device-specific interrupt routers,
499 * this code will go away from quirks.
500 */
501static void __devinit quirk_via_ioapic(struct pci_dev *dev)
502{
503 u8 tmp;
504
505 if (nr_ioapics < 1)
506 tmp = 0; /* nothing routed to external APIC */
507 else
508 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
509
510 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
511 tmp == 0 ? "Disa" : "Ena");
512
513 /* Offset 0x58: External APIC IRQ output control */
514 pci_write_config_byte (dev, 0x58, tmp);
515}
516DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
517
a1740913
KW		 518/*
519 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
520 * This leads to doubled level interrupt rates.
521 * Set this bit to get rid of cycle wastage.
522 * Otherwise uncritical.
523 */
524static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
525{
526 u8 misc_control2;
527#define BYPASS_APIC_DEASSERT 8
528
529 pci_read_config_byte(dev, 0x5B, &misc_control2);
530 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
531 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
532 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
533 }
534}
535DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
536
1da177e4
LT		 537/*
538 * The AMD io apic can hang the box when an apic irq is masked.
539 * We check all revs >= B0 (yet not in the pre production!) as the bug
540 * is currently marked NoFix
541 *
542 * We have multiple reports of hangs with this chipset that went away with
543 * noapic specified. For the moment we assume its the errata. We may be wrong
544 * of course. However the advice is demonstrably good even if so..
545 */
546static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
547{
548 u8 rev;
549
550 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
551 if (rev >= 0x02) {
552 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
553 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
554 }
555}
556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
557
558static void __init quirk_ioapic_rmw(struct pci_dev *dev)
559{
560 if (dev->devfn == 0 && dev->bus->number == 0)
561 sis_apic_bug = 1;
562}
563DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
564
565int pci_msi_quirk;
566
567#define AMD8131_revA0 0x01
568#define AMD8131_revB0 0x11
569#define AMD8131_MISC 0x40
570#define AMD8131_NIOAMODE_BIT 0
571static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
572{
573 unsigned char revid, tmp;
574
575 pci_msi_quirk = 1;
576 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
577
578 if (nr_ioapics == 0)
579 return;
580
581 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
582 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
583 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
584 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
585 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
586 pci_write_config_byte( dev, AMD8131_MISC, tmp);
587 }
588}
589DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
590
1e062767
NS		 591static void __init quirk_svw_msi(struct pci_dev *dev)
592{
593 pci_msi_quirk = 1;
594 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
595}
596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
1da177e4
LT		 597#endif /* CONFIG_X86_IO_APIC */
598
599
1da177e4
LT		 600/*
601 * FIXME: it is questionable that quirk_via_acpi
602 * is needed. It shows up as an ISA bridge, and does not
603 * support the PCI_INTERRUPT_LINE register at all. Therefore
604 * it seems like setting the pci_dev's 'irq' to the
605 * value of the ACPI SCI interrupt is only done for convenience.
606 * -jgarzik
607 */
608static void __devinit quirk_via_acpi(struct pci_dev *d)
609{
610 /*
611 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
612 */
613 u8 irq;
614 pci_read_config_byte(d, 0x42, &irq);
615 irq &= 0xf;
616 if (irq && (irq != 2))
617 d->irq = irq;
618}
619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
620DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
621
93cffffa
BH		 622/*
623 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
624 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
625 * when written, it makes an internal connection to the PIC.
626 * For these devices, this register is defined to be 4 bits wide.
627 * Normally this is fine. However for IO-APIC motherboards, or
628 * non-x86 architectures (yes Via exists on PPC among other places),
629 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
630 * interrupts delivered properly.
631 */
632static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 633{
634 u8 irq, new_irq;
635
25be5e6c
LB		 636 new_irq = dev->irq & 0xf;
637 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
638 if (new_irq != irq) {
93cffffa 639 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 640 pci_name(dev), irq, new_irq);
641 udelay(15); /* unknown if delay really needed */
642 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
643 }
644}
93cffffa 645DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq);
25be5e6c 646
1da177e4
LT		 647/*
648 * PIIX3 USB: We have to disable USB interrupts that are
649 * hardwired to PIRQD# and may be shared with an
650 * external device.
651 *
652 * Legacy Support Register (LEGSUP):
653 * bit13: USB PIRQ Enable (USBPIRQDEN),
654 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
655 *
656 * We mask out all r/wc bits, too.
657 */
658static void __devinit quirk_piix3_usb(struct pci_dev *dev)
659{
660 u16 legsup;
661
662 pci_read_config_word(dev, 0xc0, &legsup);
663 legsup &= 0x50ef;
664 pci_write_config_word(dev, 0xc0, legsup);
665}
666DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
667DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
668
669/*
670 * VIA VT82C598 has its device ID settable and many BIOSes
671 * set it to the ID of VT82C597 for backward compatibility.
672 * We need to switch it off to be able to recognize the real
673 * type of the chip.
674 */
675static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
676{
677 pci_write_config_byte(dev, 0xfc, 0);
678 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
679}
680DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
681
682/*
683 * CardBus controllers have a legacy base address that enables them
684 * to respond as i82365 pcmcia controllers. We don't want them to
685 * do this even if the Linux CardBus driver is not loaded, because
686 * the Linux i82365 driver does not (and should not) handle CardBus.
687 */
688static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
689{
690 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
691 return;
692 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
693}
694DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
695
696/*
697 * Following the PCI ordering rules is optional on the AMD762. I'm not
698 * sure what the designers were smoking but let's not inhale...
699 *
700 * To be fair to AMD, it follows the spec by default, its BIOS people
701 * who turn it off!
702 */
703static void __devinit quirk_amd_ordering(struct pci_dev *dev)
704{
705 u32 pcic;
706 pci_read_config_dword(dev, 0x4C, &pcic);
707 if ((pcic&6)!=6) {
708 pcic |= 6;
709 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
710 pci_write_config_dword(dev, 0x4C, pcic);
711 pci_read_config_dword(dev, 0x84, &pcic);
712 pcic |= (1<<23); /* Required in this mode */
713 pci_write_config_dword(dev, 0x84, pcic);
714 }
715}
716DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
717
718/*
719 * DreamWorks provided workaround for Dunord I-3000 problem
720 *
721 * This card decodes and responds to addresses not apparently
722 * assigned to it. We force a larger allocation to ensure that
723 * nothing gets put too close to it.
724 */
725static void __devinit quirk_dunord ( struct pci_dev * dev )
726{
727 struct resource *r = &dev->resource [1];
728 r->start = 0;
729 r->end = 0xffffff;
730}
731DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
732
733/*
734 * i82380FB mobile docking controller: its PCI-to-PCI bridge
735 * is subtractive decoding (transparent), and does indicate this
736 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
737 * instead of 0x01.
738 */
739static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
740{
741 dev->transparent = 1;
742}
743DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
745
746/*
747 * Common misconfiguration of the MediaGX/Geode PCI master that will
748 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
749 * datasheets found at http://www.national.com/ds/GX for info on what
750 * these bits do. <christer@weinigel.se>
751 */
752static void __init quirk_mediagx_master(struct pci_dev *dev)
753{
754 u8 reg;
755 pci_read_config_byte(dev, 0x41, &reg);
756 if (reg & 2) {
757 reg &= ~2;
758 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
759 pci_write_config_byte(dev, 0x41, reg);
760 }
761}
762DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
763
764/*
765 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
766 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
767 * secondary channels respectively). If the device reports Compatible mode
768 * but does use BAR0-3 for address decoding, we assume that firmware has
769 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
770 * Exceptions (if they exist) must be handled in chip/architecture specific
771 * fixups.
772 *
773 * Note: for non x86 people. You may need an arch specific quirk to handle
774 * moving IDE devices to native mode as well. Some plug in card devices power
775 * up in compatible mode and assume the BIOS will adjust them.
776 *
777 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
778 * we do now ? We don't want is pci_enable_device to come along
779 * and assign new resources. Both approaches work for that.
780 */
781static void __devinit quirk_ide_bases(struct pci_dev *dev)
782{
783 struct resource *res;
784 int first_bar = 2, last_bar = 0;
785
786 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
787 return;
788
789 res = &dev->resource[0];
790
791 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
792 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
793 res[0].start = res[0].end = res[0].flags = 0;
794 res[1].start = res[1].end = res[1].flags = 0;
795 first_bar = 0;
796 last_bar = 1;
797 }
798
799 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
800 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
801 res[2].start = res[2].end = res[2].flags = 0;
802 res[3].start = res[3].end = res[3].flags = 0;
803 last_bar = 3;
804 }
805
806 if (!last_bar)
807 return;
808
809 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
810 first_bar, last_bar, pci_name(dev));
811}
812DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
813
814/*
815 * Ensure C0 rev restreaming is off. This is normally done by
816 * the BIOS but in the odd case it is not the results are corruption
817 * hence the presence of a Linux check
818 */
819static void __init quirk_disable_pxb(struct pci_dev *pdev)
820{
821 u16 config;
822 u8 rev;
823
824 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
825 if (rev != 0x04) /* Only C0 requires this */
826 return;
827 pci_read_config_word(pdev, 0x40, &config);
828 if (config & (1<<6)) {
829 config &= ~(1<<6);
830 pci_write_config_word(pdev, 0x40, config);
831 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
832 }
833}
834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
835
1da177e4
LT		 836
837/*
838 * Serverworks CSB5 IDE does not fully support native mode
839 */
840static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
841{
842 u8 prog;
843 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
844 if (prog & 5) {
845 prog &= ~5;
846 pdev->class &= ~5;
847 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
848 /* need to re-assign BARs for compat mode */
849 quirk_ide_bases(pdev);
850 }
851}
852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
853
854/*
855 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
856 */
857static void __init quirk_ide_samemode(struct pci_dev *pdev)
858{
859 u8 prog;
860
861 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
862
863 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
864 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
865 prog &= ~5;
866 pdev->class &= ~5;
867 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
868 /* need to re-assign BARs for compat mode */
869 quirk_ide_bases(pdev);
870 }
871}
872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
873
874/* This was originally an Alpha specific thing, but it really fits here.
875 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
876 */
877static void __init quirk_eisa_bridge(struct pci_dev *dev)
878{
879 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
880}
881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
882
883/*
884 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
885 * is not activated. The myth is that Asus said that they do not want the
886 * users to be irritated by just another PCI Device in the Win98 device
887 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
888 * package 2.7.0 for details)
889 *
890 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
891 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
892 * becomes necessary to do this tweak in two steps -- I've chosen the Host
893 * bridge as trigger.
894 */
895static int __initdata asus_hides_smbus = 0;
896
897static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
898{
899 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
900 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
901 switch(dev->subsystem_device) {
a00db371 902 case 0x8025: /* P4B-LX */
1da177e4
LT		 903 case 0x8070: /* P4B */
904 case 0x8088: /* P4B533 */
905 case 0x1626: /* L3C notebook */
906 asus_hides_smbus = 1;
907 }
908 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
909 switch(dev->subsystem_device) {
910 case 0x80b1: /* P4GE-V */
911 case 0x80b2: /* P4PE */
912 case 0x8093: /* P4B533-V */
913 asus_hides_smbus = 1;
914 }
915 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
916 switch(dev->subsystem_device) {
917 case 0x8030: /* P4T533 */
918 asus_hides_smbus = 1;
919 }
920 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
921 switch (dev->subsystem_device) {
922 case 0x8070: /* P4G8X Deluxe */
923 asus_hides_smbus = 1;
924 }
925 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
926 switch (dev->subsystem_device) {
927 case 0x1751: /* M2N notebook */
928 case 0x1821: /* M5N notebook */
929 asus_hides_smbus = 1;
930 }
931 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
932 switch (dev->subsystem_device) {
933 case 0x184b: /* W1N notebook */
934 case 0x186a: /* M6Ne notebook */
935 asus_hides_smbus = 1;
936 }
acc06632
M		 937 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
938 switch (dev->subsystem_device) {
939 case 0x1882: /* M6V notebook */
940 asus_hides_smbus = 1;
941 }
942 }
1da177e4
LT		 943 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
944 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
945 switch(dev->subsystem_device) {
946 case 0x088C: /* HP Compaq nc8000 */
947 case 0x0890: /* HP Compaq nc6000 */
948 asus_hides_smbus = 1;
949 }
950 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
951 switch (dev->subsystem_device) {
952 case 0x12bc: /* HP D330L */
e3b1bd57 953 case 0x12bd: /* HP D530 */
1da177e4
LT		 954 asus_hides_smbus = 1;
955 }
956 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
957 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
958 switch(dev->subsystem_device) {
959 case 0x0001: /* Toshiba Satellite A40 */
960 asus_hides_smbus = 1;
961 }
e96e2f14
DG		 962 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
963 switch(dev->subsystem_device) {
964 case 0x0001: /* Toshiba Tecra M2 */
965 asus_hides_smbus = 1;
966 }
1da177e4
LT		 967 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
968 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
969 switch(dev->subsystem_device) {
970 case 0xC00C: /* Samsung P35 notebook */
971 asus_hides_smbus = 1;
972 }
c87f883e
RIZ		 973 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
974 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
975 switch(dev->subsystem_device) {
976 case 0x0058: /* Compaq Evo N620c */
977 asus_hides_smbus = 1;
978 }
1da177e4
LT		 979 }
980}
981DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
983DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
984DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
985DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
986DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
987DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 988DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 989
990static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
991{
992 u16 val;
993
994 if (likely(!asus_hides_smbus))
995 return;
996
997 pci_read_config_word(dev, 0xF2, &val);
998 if (val & 0x8) {
999 pci_write_config_word(dev, 0xF2, val & (~0x8));
1000 pci_read_config_word(dev, 0xF2, &val);
1001 if (val & 0x8)
1002 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1003 else
1004 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1005 }
1006}
1007DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1008DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1009DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1010DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1011DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
1012
acc06632
M		 1013static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1014{
1015 u32 val, rcba;
1016 void __iomem *base;
1017
1018 if (likely(!asus_hides_smbus))
1019 return;
1020 pci_read_config_dword(dev, 0xF0, &rcba);
1021 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1022 if (base == NULL) return;
1023 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1024 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1025 iounmap(base);
1026 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1027}
1028DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1029
1da177e4
LT		 1030/*
1031 * SiS 96x south bridge: BIOS typically hides SMBus device...
1032 */
1033static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1034{
1035 u8 val = 0;
1036 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1037 pci_read_config_byte(dev, 0x77, &val);
1038 pci_write_config_byte(dev, 0x77, val & ~0x10);
1039 pci_read_config_byte(dev, 0x77, &val);
1040}
1041
1042
1043#define UHCI_USBLEGSUP 0xc0 /* legacy support */
1044#define UHCI_USBCMD 0 /* command register */
1045#define UHCI_USBSTS 2 /* status register */
1046#define UHCI_USBINTR 4 /* interrupt register */
1047#define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
1048#define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
1049#define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
1050#define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
1051#define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
1052
1053#define OHCI_CONTROL 0x04
1054#define OHCI_CMDSTATUS 0x08
1055#define OHCI_INTRSTATUS 0x0c
1056#define OHCI_INTRENABLE 0x10
1057#define OHCI_INTRDISABLE 0x14
1058#define OHCI_OCR (1 << 3) /* ownership change request */
1059#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
1060#define OHCI_INTR_OC (1 << 30) /* ownership change */
1061
1062#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
1063#define EHCI_USBCMD 0 /* command register */
1064#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
1065#define EHCI_USBSTS 4 /* status register */
1066#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
1067#define EHCI_USBINTR 8 /* interrupt register */
1068#define EHCI_USBLEGSUP 0 /* legacy support register */
1069#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
1070#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
1071#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
1072#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
1073
1074int usb_early_handoff __devinitdata = 0;
1075static int __init usb_handoff_early(char *str)
1076{
1077 usb_early_handoff = 1;
1078 return 0;
1079}
1080__setup("usb-handoff", usb_handoff_early);
1081
1082static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
1083{
1084 unsigned long base = 0;
1085 int wait_time, delta;
1086 u16 val, sts;
1087 int i;
1088
1089 for (i = 0; i < PCI_ROM_RESOURCE; i++)
1090 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
1091 base = pci_resource_start(pdev, i);
1092 break;
1093 }
1094
1095 if (!base)
1096 return;
1097
1098 /*
1099 * stop controller
1100 */
1101 sts = inw(base + UHCI_USBSTS);
1102 val = inw(base + UHCI_USBCMD);
1103 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
1104 outw(val, base + UHCI_USBCMD);
1105
1106 /*
1107 * wait while it stops if it was running
1108 */
1109 if ((sts & UHCI_USBSTS_HALTED) == 0)
1110 {
1111 wait_time = 1000;
1112 delta = 100;
1113
1114 do {
1115 outw(0x1f, base + UHCI_USBSTS);
1116 udelay(delta);
1117 wait_time -= delta;
1118 val = inw(base + UHCI_USBSTS);
1119 if (val & UHCI_USBSTS_HALTED)
1120 break;
1121 } while (wait_time > 0);
1122 }
1123
1124 /*
1125 * disable interrupts & legacy support
1126 */
1127 outw(0, base + UHCI_USBINTR);
1128 outw(0x1f, base + UHCI_USBSTS);
1129 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
1130 if (val & 0xbf)
1131 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
1132
1133}
1134
1135static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
1136{
1137 void __iomem *base;
1138 int wait_time;
1139
1140 base = ioremap_nocache(pci_resource_start(pdev, 0),
1141 pci_resource_len(pdev, 0));
1142 if (base == NULL) return;
1143
1144 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
1145 wait_time = 500; /* 0.5 seconds */
1146 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
1147 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
1148 while (wait_time > 0 &&
1149 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
1150 wait_time -= 10;
1151 msleep(10);
1152 }
1153 }
1154
1155 /*
1156 * disable interrupts
1157 */
1158 writel(~(u32)0, base + OHCI_INTRDISABLE);
1159 writel(~(u32)0, base + OHCI_INTRSTATUS);
1160
1161 iounmap(base);
1162}
1163
1164static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
1165{
1166 int wait_time, delta;
1167 void __iomem *base, *op_reg_base;
1168 u32 hcc_params, val, temp;
1169 u8 cap_length;
1170
1171 base = ioremap_nocache(pci_resource_start(pdev, 0),
1172 pci_resource_len(pdev, 0));
1173 if (base == NULL) return;
1174
1175 cap_length = readb(base);
1176 op_reg_base = base + cap_length;
1177 hcc_params = readl(base + EHCI_HCC_PARAMS);
1178 hcc_params = (hcc_params >> 8) & 0xff;
1179 if (hcc_params) {
1180 pci_read_config_dword(pdev,
1181 hcc_params + EHCI_USBLEGSUP,
1182 &val);
1183 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
1184 /*
1185 * Ok, BIOS is in smm mode, try to hand off...
1186 */
1187 pci_read_config_dword(pdev,
1188 hcc_params + EHCI_USBLEGCTLSTS,
1189 &temp);
1190 pci_write_config_dword(pdev,
1191 hcc_params + EHCI_USBLEGCTLSTS,
1192 temp | EHCI_USBLEGCTLSTS_SOOE);
1193 val |= EHCI_USBLEGSUP_OS;
1194 pci_write_config_dword(pdev,
1195 hcc_params + EHCI_USBLEGSUP,
1196 val);
1197
1198 wait_time = 500;
1199 do {
1200 msleep(10);
1201 wait_time -= 10;
1202 pci_read_config_dword(pdev,
1203 hcc_params + EHCI_USBLEGSUP,
1204 &val);
1205 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1206 if (!wait_time) {
1207 /*
1208 * well, possibly buggy BIOS...
1209 */
1210 printk(KERN_WARNING "EHCI early BIOS handoff "
1211 "failed (BIOS bug ?)\n");
1212 pci_write_config_dword(pdev,
1213 hcc_params + EHCI_USBLEGSUP,
1214 EHCI_USBLEGSUP_OS);
1215 pci_write_config_dword(pdev,
1216 hcc_params + EHCI_USBLEGCTLSTS,
1217 0);
1218 }
1219 }
1220 }
1221
1222 /*
1223 * halt EHCI & disable its interrupts in any case
1224 */
1225 val = readl(op_reg_base + EHCI_USBSTS);
1226 if ((val & EHCI_USBSTS_HALTED) == 0) {
1227 val = readl(op_reg_base + EHCI_USBCMD);
1228 val &= ~EHCI_USBCMD_RUN;
1229 writel(val, op_reg_base + EHCI_USBCMD);
1230
1231 wait_time = 2000;
1232 delta = 100;
1233 do {
1234 writel(0x3f, op_reg_base + EHCI_USBSTS);
1235 udelay(delta);
1236 wait_time -= delta;
1237 val = readl(op_reg_base + EHCI_USBSTS);
1238 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1239 break;
1240 }
1241 } while (wait_time > 0);
1242 }
1243 writel(0, op_reg_base + EHCI_USBINTR);
1244 writel(0x3f, op_reg_base + EHCI_USBSTS);
1245
1246 iounmap(base);
1247
1248 return;
1249}
1250
1251
1252
1253static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1254{
1255 if (!usb_early_handoff)
1256 return;
1257
1258 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1259 quirk_usb_handoff_uhci(pdev);
1260 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1261 quirk_usb_handoff_ohci(pdev);
1262 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1263 quirk_usb_disable_ehci(pdev);
1264 }
1265
1266 return;
1267}
1268DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1269
1270/*
1271 * ... This is further complicated by the fact that some SiS96x south
1272 * bridges pretend to be 85C503/5513 instead. In that case see if we
1273 * spotted a compatible north bridge to make sure.
1274 * (pci_find_device doesn't work yet)
1275 *
1276 * We can also enable the sis96x bit in the discovery register..
1277 */
1278static int __devinitdata sis_96x_compatible = 0;
1279
1280#define SIS_DETECT_REGISTER 0x40
1281
1282static void __init quirk_sis_503(struct pci_dev *dev)
1283{
1284 u8 reg;
1285 u16 devid;
1286
1287 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1288 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1289 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1290 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1291 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1292 return;
1293 }
1294
1295 /* Make people aware that we changed the config.. */
1296 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1297
1298 /*
1299 * Ok, it now shows up as a 96x.. The 96x quirks are after
1300 * the 503 quirk in the quirk table, so they'll automatically
1301 * run and enable things like the SMBus device
1302 */
1303 dev->device = devid;
1304}
1305
1306static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1307{
1308 sis_96x_compatible = 1;
1309}
1310DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1312DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1313DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1316
1317DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1318
1319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1323
1324#ifdef CONFIG_X86_IO_APIC
1325static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1326{
1327 int i;
1328
1329 if ((pdev->class >> 8) != 0xff00)
1330 return;
1331
1332 /* the first BAR is the location of the IO APIC...we must
1333 * not touch this (and it's already covered by the fixmap), so
1334 * forcibly insert it into the resource tree */
1335 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1336 insert_resource(&iomem_resource, &pdev->resource[0]);
1337
1338 /* The next five BARs all seem to be rubbish, so just clean
1339 * them out */
1340 for (i=1; i < 6; i++) {
1341 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1342 }
1343
1344}
1345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1346#endif
1347
cc675230 1348#ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1da177e4
LT		 1349static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1350{
1351 u8 prog, comb, tmp;
1352 int ich = 0;
1353
1354 /*
1355 * Narrow down to Intel SATA PCI devices.
1356 */
1357 switch (pdev->device) {
1358 /* PCI ids taken from drivers/scsi/ata_piix.c */
1359 case 0x24d1:
1360 case 0x24df:
1361 case 0x25a3:
1362 case 0x25b0:
1363 ich = 5;
1364 break;
1365 case 0x2651:
1366 case 0x2652:
1367 case 0x2653:
c368ca4e 1368 case 0x2680: /* ESB2 */
1da177e4
LT		 1369 ich = 6;
1370 break;
1371 case 0x27c0:
1372 case 0x27c4:
1373 ich = 7;
1374 break;
1375 default:
1376 /* we do not handle this PCI device */
1377 return;
1378 }
1379
1380 /*
1381 * Read combined mode register.
1382 */
1383 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1384
1385 if (ich == 5) {
1386 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1387 if (tmp == 0x4) /* bits 10x */
1388 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1389 else if (tmp == 0x6) /* bits 11x */
1390 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1391 else
1392 return; /* not in combined mode */
1393 } else {
1394 WARN_ON((ich != 6) && (ich != 7));
1395 tmp &= 0x3; /* interesting bits 1:0 */
1396 if (tmp & (1 << 0))
1397 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1398 else if (tmp & (1 << 1))
1399 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1400 else
1401 return; /* not in combined mode */
1402 }
1403
1404 /*
1405 * Read programming interface register.
1406 * (Tells us if it's legacy or native mode)
1407 */
1408 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1409
1410 /* if SATA port is in native mode, we're ok. */
1411 if (prog & comb)
1412 return;
1413
1414 /* SATA port is in legacy mode. Reserve port so that
1415 * IDE driver does not attempt to use it. If request_region
1416 * fails, it will be obvious at boot time, so we don't bother
1417 * checking return values.
1418 */
1419 if (comb == (1 << 0))
1420 request_region(0x1f0, 8, "libata"); /* port 0 */
1421 else
1422 request_region(0x170, 8, "libata"); /* port 1 */
1423}
1424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
cc675230 1425#endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1da177e4
LT		 1426
1427
1428int pcie_mch_quirk;
1429
1430static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1431{
1432 pcie_mch_quirk = 1;
1433}
1434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1437
4602b88d
KA		 1438
1439/*
1440 * It's possible for the MSI to get corrupted if shpc and acpi
1441 * are used together on certain PXH-based systems.
1442 */
1443static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1444{
1445 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1446 PCI_CAP_ID_MSI);
1447 dev->no_msi = 1;
1448
1449 printk(KERN_WARNING "PCI: PXH quirk detected, "
1450 "disabling MSI for SHPC device\n");
1451}
1452DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1453DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1454DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1455DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1456DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1457
1458
1da177e4
LT		 1459static void __devinit quirk_netmos(struct pci_dev *dev)
1460{
1461 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1462 unsigned int num_serial = dev->subsystem_device & 0xf;
1463
1464 /*
1465 * These Netmos parts are multiport serial devices with optional
1466 * parallel ports. Even when parallel ports are present, they
1467 * are identified as class SERIAL, which means the serial driver
1468 * will claim them. To prevent this, mark them as class OTHER.
1469 * These combo devices should be claimed by parport_serial.
1470 *
1471 * The subdevice ID is of the form 0x00PS, where <P> is the number
1472 * of parallel ports and <S> is the number of serial ports.
1473 */
1474 switch (dev->device) {
1475 case PCI_DEVICE_ID_NETMOS_9735:
1476 case PCI_DEVICE_ID_NETMOS_9745:
1477 case PCI_DEVICE_ID_NETMOS_9835:
1478 case PCI_DEVICE_ID_NETMOS_9845:
1479 case PCI_DEVICE_ID_NETMOS_9855:
1480 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1481 num_parallel) {
1482 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1483 "%u serial); changing class SERIAL to OTHER "
1484 "(use parport_serial)\n",
1485 dev->device, num_parallel, num_serial);
1486 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1487 (dev->class & 0xff);
1488 }
1489 }
1490}
1491DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1492
1493static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1494{
1495 while (f < end) {
1496 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1497 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1498 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1499 f->hook(dev);
1500 }
1501 f++;
1502 }
1503}
1504
1505extern struct pci_fixup __start_pci_fixups_early[];
1506extern struct pci_fixup __end_pci_fixups_early[];
1507extern struct pci_fixup __start_pci_fixups_header[];
1508extern struct pci_fixup __end_pci_fixups_header[];
1509extern struct pci_fixup __start_pci_fixups_final[];
1510extern struct pci_fixup __end_pci_fixups_final[];
1511extern struct pci_fixup __start_pci_fixups_enable[];
1512extern struct pci_fixup __end_pci_fixups_enable[];
1513
1514
1515void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1516{
1517 struct pci_fixup *start, *end;
1518
1519 switch(pass) {
1520 case pci_fixup_early:
1521 start = __start_pci_fixups_early;
1522 end = __end_pci_fixups_early;
1523 break;
1524
1525 case pci_fixup_header:
1526 start = __start_pci_fixups_header;
1527 end = __end_pci_fixups_header;
1528 break;
1529
1530 case pci_fixup_final:
1531 start = __start_pci_fixups_final;
1532 end = __end_pci_fixups_final;
1533 break;
1534
1535 case pci_fixup_enable:
1536 start = __start_pci_fixups_enable;
1537 end = __end_pci_fixups_enable;
1538 break;
1539
1540 default:
1541 /* stupid compiler warning, you would think with an enum... */
1542 return;
1543 }
1544 pci_do_fixups(dev, start, end);
1545}
1546
1547EXPORT_SYMBOL(pcie_mch_quirk);
1548#ifdef CONFIG_HOTPLUG
1549EXPORT_SYMBOL(pci_fixup_device);
1550#endif
Linux kernel - Deliverables
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