Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for many known PCI hardware | |
3 | * bugs. Devices present only on certain architectures (host | |
4 | * bridges et cetera) should be handled in arch-specific code. | |
5 | * | |
6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. | |
7 | * | |
8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
9 | * | |
7586269c DB |
10 | * Init/reset quirks for USB host controllers should be in the |
11 | * USB quirks file, where their drivers can access reuse it. | |
12 | * | |
1da177e4 LT |
13 | * The bridge optimization stuff has been removed. If you really |
14 | * have a silly BIOS which is unable to set your host bridge right, | |
15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
25be5e6c | 23 | #include <linux/acpi.h> |
9f23ed3b | 24 | #include <linux/kallsyms.h> |
75e07fc3 | 25 | #include <linux/dmi.h> |
649426ef | 26 | #include <linux/pci-aspm.h> |
32a9a682 | 27 | #include <linux/ioport.h> |
bc56b9e0 | 28 | #include "pci.h" |
1da177e4 | 29 | |
3d137310 TP |
30 | int isa_dma_bridge_buggy; |
31 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
32 | int pci_pci_problems; | |
33 | EXPORT_SYMBOL(pci_pci_problems); | |
34 | int pcie_mch_quirk; | |
35 | EXPORT_SYMBOL(pcie_mch_quirk); | |
36 | ||
37 | #ifdef CONFIG_PCI_QUIRKS | |
32a9a682 | 38 | /* |
0cdbe30f YS |
39 | * This quirk function disables memory decoding and releases memory resources |
40 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
32a9a682 YS |
41 | * It also rounds up size to specified alignment. |
42 | * Later on, the kernel will assign page-aligned memory resource back | |
0cdbe30f | 43 | * to the device. |
32a9a682 YS |
44 | */ |
45 | static void __devinit quirk_resource_alignment(struct pci_dev *dev) | |
46 | { | |
47 | int i; | |
48 | struct resource *r; | |
49 | resource_size_t align, size; | |
0cdbe30f | 50 | u16 command; |
32a9a682 YS |
51 | |
52 | if (!pci_is_reassigndev(dev)) | |
53 | return; | |
54 | ||
55 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
56 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
57 | dev_warn(&dev->dev, | |
58 | "Can't reassign resources to host bridge.\n"); | |
59 | return; | |
60 | } | |
61 | ||
0cdbe30f YS |
62 | dev_info(&dev->dev, |
63 | "Disabling memory decoding and releasing memory resources.\n"); | |
64 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
65 | command &= ~PCI_COMMAND_MEMORY; | |
66 | pci_write_config_word(dev, PCI_COMMAND, command); | |
32a9a682 YS |
67 | |
68 | align = pci_specified_resource_alignment(dev); | |
69 | for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { | |
70 | r = &dev->resource[i]; | |
71 | if (!(r->flags & IORESOURCE_MEM)) | |
72 | continue; | |
73 | size = resource_size(r); | |
74 | if (size < align) { | |
75 | size = align; | |
76 | dev_info(&dev->dev, | |
77 | "Rounding up size of resource #%d to %#llx.\n", | |
78 | i, (unsigned long long)size); | |
79 | } | |
80 | r->end = size - 1; | |
81 | r->start = 0; | |
82 | } | |
83 | /* Need to disable bridge's resource window, | |
84 | * to enable the kernel to reassign new resource | |
85 | * window later on. | |
86 | */ | |
87 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
88 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
89 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
90 | r = &dev->resource[i]; | |
91 | if (!(r->flags & IORESOURCE_MEM)) | |
92 | continue; | |
93 | r->end = resource_size(r) - 1; | |
94 | r->start = 0; | |
95 | } | |
96 | pci_disable_bridge_window(dev); | |
97 | } | |
98 | } | |
99 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); | |
100 | ||
bd8481e1 DT |
101 | /* The Mellanox Tavor device gives false positive parity errors |
102 | * Mark this device with a broken_parity_status, to allow | |
103 | * PCI scanning code to "skip" this now blacklisted device. | |
104 | */ | |
105 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) | |
106 | { | |
107 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
108 | } | |
109 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); | |
110 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); | |
111 | ||
1da177e4 LT |
112 | /* Deal with broken BIOS'es that neglect to enable passive release, |
113 | which can cause problems in combination with the 82441FX/PPro MTRRs */ | |
1597cacb | 114 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
115 | { |
116 | struct pci_dev *d = NULL; | |
117 | unsigned char dlc; | |
118 | ||
119 | /* We have to make sure a particular bit is set in the PIIX3 | |
120 | ISA bridge, so we have to go out and find it. */ | |
121 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { | |
122 | pci_read_config_byte(d, 0x82, &dlc); | |
123 | if (!(dlc & 1<<1)) { | |
999da9fd | 124 | dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); |
1da177e4 LT |
125 | dlc |= 1<<1; |
126 | pci_write_config_byte(d, 0x82, dlc); | |
127 | } | |
128 | } | |
129 | } | |
652c538e AM |
130 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
131 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 LT |
132 | |
133 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround | |
134 | but VIA don't answer queries. If you happen to have good contacts at VIA | |
135 | ask them for me please -- Alan | |
136 | ||
137 | This appears to be BIOS not version dependent. So presumably there is a | |
138 | chipset level fix */ | |
1da177e4 LT |
139 | |
140 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) | |
141 | { | |
142 | if (!isa_dma_bridge_buggy) { | |
143 | isa_dma_bridge_buggy=1; | |
f0fda801 | 144 | dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); |
1da177e4 LT |
145 | } |
146 | } | |
147 | /* | |
148 | * Its not totally clear which chipsets are the problematic ones | |
149 | * We know 82C586 and 82C596 variants are affected. | |
150 | */ | |
652c538e AM |
151 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
152 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
153 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
154 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); | |
155 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); | |
156 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
157 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
1da177e4 | 158 | |
1da177e4 LT |
159 | /* |
160 | * Chipsets where PCI->PCI transfers vanish or hang | |
161 | */ | |
162 | static void __devinit quirk_nopcipci(struct pci_dev *dev) | |
163 | { | |
164 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { | |
f0fda801 | 165 | dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); |
1da177e4 LT |
166 | pci_pci_problems |= PCIPCI_FAIL; |
167 | } | |
168 | } | |
652c538e AM |
169 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
170 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 AC |
171 | |
172 | static void __devinit quirk_nopciamd(struct pci_dev *dev) | |
173 | { | |
174 | u8 rev; | |
175 | pci_read_config_byte(dev, 0x08, &rev); | |
176 | if (rev == 0x13) { | |
177 | /* Erratum 24 */ | |
f0fda801 | 178 | dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
236561e5 AC |
179 | pci_pci_problems |= PCIAGP_FAIL; |
180 | } | |
181 | } | |
652c538e | 182 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 LT |
183 | |
184 | /* | |
185 | * Triton requires workarounds to be used by the drivers | |
186 | */ | |
187 | static void __devinit quirk_triton(struct pci_dev *dev) | |
188 | { | |
189 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { | |
f0fda801 | 190 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
191 | pci_pci_problems |= PCIPCI_TRITON; |
192 | } | |
193 | } | |
652c538e AM |
194 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
195 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
196 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
197 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
198 | |
199 | /* | |
200 | * VIA Apollo KT133 needs PCI latency patch | |
201 | * Made according to a windows driver based patch by George E. Breese | |
202 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
203 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for | |
204 | * the info on which Mr Breese based his work. | |
205 | * | |
206 | * Updated based on further information from the site and also on | |
207 | * information provided by VIA | |
208 | */ | |
1597cacb | 209 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
210 | { |
211 | struct pci_dev *p; | |
1da177e4 LT |
212 | u8 busarb; |
213 | /* Ok we have a potential problem chipset here. Now see if we have | |
214 | a buggy southbridge */ | |
215 | ||
216 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); | |
217 | if (p!=NULL) { | |
1da177e4 LT |
218 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
219 | /* Check for buggy part revisions */ | |
2b1afa87 | 220 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
221 | goto exit; |
222 | } else { | |
223 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
224 | if (p==NULL) /* No problem parts */ | |
225 | goto exit; | |
1da177e4 | 226 | /* Check for buggy part revisions */ |
2b1afa87 | 227 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
228 | goto exit; |
229 | } | |
230 | ||
231 | /* | |
232 | * Ok we have the problem. Now set the PCI master grant to | |
233 | * occur every master grant. The apparent bug is that under high | |
234 | * PCI load (quite common in Linux of course) you can get data | |
235 | * loss when the CPU is held off the bus for 3 bus master requests | |
236 | * This happens to include the IDE controllers.... | |
237 | * | |
238 | * VIA only apply this fix when an SB Live! is present but under | |
239 | * both Linux and Windows this isnt enough, and we have seen | |
240 | * corruption without SB Live! but with things like 3 UDMA IDE | |
241 | * controllers. So we ignore that bit of the VIA recommendation.. | |
242 | */ | |
243 | ||
244 | pci_read_config_byte(dev, 0x76, &busarb); | |
245 | /* Set bit 4 and bi 5 of byte 76 to 0x01 | |
246 | "Master priority rotation on every PCI master grant */ | |
247 | busarb &= ~(1<<5); | |
248 | busarb |= (1<<4); | |
249 | pci_write_config_byte(dev, 0x76, busarb); | |
f0fda801 | 250 | dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); |
1da177e4 LT |
251 | exit: |
252 | pci_dev_put(p); | |
253 | } | |
652c538e AM |
254 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
255 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
256 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 257 | /* Must restore this on a resume from RAM */ |
652c538e AM |
258 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
259 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
260 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 LT |
261 | |
262 | /* | |
263 | * VIA Apollo VP3 needs ETBF on BT848/878 | |
264 | */ | |
265 | static void __devinit quirk_viaetbf(struct pci_dev *dev) | |
266 | { | |
267 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { | |
f0fda801 | 268 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
269 | pci_pci_problems |= PCIPCI_VIAETBF; |
270 | } | |
271 | } | |
652c538e | 272 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 LT |
273 | |
274 | static void __devinit quirk_vsfx(struct pci_dev *dev) | |
275 | { | |
276 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { | |
f0fda801 | 277 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
278 | pci_pci_problems |= PCIPCI_VSFX; |
279 | } | |
280 | } | |
652c538e | 281 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
282 | |
283 | /* | |
284 | * Ali Magik requires workarounds to be used by the drivers | |
285 | * that DMA to AGP space. Latency must be set to 0xA and triton | |
286 | * workaround applied too | |
287 | * [Info kindly provided by ALi] | |
288 | */ | |
289 | static void __init quirk_alimagik(struct pci_dev *dev) | |
290 | { | |
291 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { | |
f0fda801 | 292 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
293 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
294 | } | |
295 | } | |
652c538e AM |
296 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
297 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 LT |
298 | |
299 | /* | |
300 | * Natoma has some interesting boundary conditions with Zoran stuff | |
301 | * at least | |
302 | */ | |
303 | static void __devinit quirk_natoma(struct pci_dev *dev) | |
304 | { | |
305 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { | |
f0fda801 | 306 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
307 | pci_pci_problems |= PCIPCI_NATOMA; |
308 | } | |
309 | } | |
652c538e AM |
310 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
311 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
312 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
313 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
314 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
315 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
316 | |
317 | /* | |
318 | * This chip can cause PCI parity errors if config register 0xA0 is read | |
319 | * while DMAs are occurring. | |
320 | */ | |
321 | static void __devinit quirk_citrine(struct pci_dev *dev) | |
322 | { | |
323 | dev->cfg_size = 0xA0; | |
324 | } | |
652c538e | 325 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 LT |
326 | |
327 | /* | |
328 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. | |
329 | * If it's needed, re-allocate the region. | |
330 | */ | |
331 | static void __devinit quirk_s3_64M(struct pci_dev *dev) | |
332 | { | |
333 | struct resource *r = &dev->resource[0]; | |
334 | ||
335 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
336 | r->start = 0; | |
337 | r->end = 0x3ffffff; | |
338 | } | |
339 | } | |
652c538e AM |
340 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
341 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 342 | |
6693e74a LT |
343 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
344 | unsigned size, int nr, const char *name) | |
1da177e4 LT |
345 | { |
346 | region &= ~(size-1); | |
347 | if (region) { | |
085ae41f | 348 | struct pci_bus_region bus_region; |
1da177e4 LT |
349 | struct resource *res = dev->resource + nr; |
350 | ||
351 | res->name = pci_name(dev); | |
352 | res->start = region; | |
353 | res->end = region + size - 1; | |
354 | res->flags = IORESOURCE_IO; | |
085ae41f DM |
355 | |
356 | /* Convert from PCI bus to resource space. */ | |
357 | bus_region.start = res->start; | |
358 | bus_region.end = res->end; | |
359 | pcibios_bus_to_resource(dev, res, &bus_region); | |
360 | ||
1da177e4 | 361 | pci_claim_resource(dev, nr); |
f0fda801 | 362 | dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); |
1da177e4 LT |
363 | } |
364 | } | |
365 | ||
366 | /* | |
367 | * ATI Northbridge setups MCE the processor if you even | |
368 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 | |
369 | */ | |
370 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) | |
371 | { | |
f0fda801 | 372 | dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
1da177e4 LT |
373 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
374 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
375 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
376 | } | |
652c538e | 377 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 LT |
378 | |
379 | /* | |
380 | * Let's make the southbridge information explicit instead | |
381 | * of having to worry about people probing the ACPI areas, | |
382 | * for example.. (Yes, it happens, and if you read the wrong | |
383 | * ACPI register it will put the machine to sleep with no | |
384 | * way of waking it up again. Bummer). | |
385 | * | |
386 | * ALI M7101: Two IO regions pointed to by words at | |
387 | * 0xE0 (64 bytes of ACPI registers) | |
388 | * 0xE2 (32 bytes of SMB registers) | |
389 | */ | |
390 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) | |
391 | { | |
392 | u16 region; | |
393 | ||
394 | pci_read_config_word(dev, 0xE0, ®ion); | |
6693e74a | 395 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
1da177e4 | 396 | pci_read_config_word(dev, 0xE2, ®ion); |
6693e74a | 397 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
1da177e4 | 398 | } |
652c538e | 399 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 400 | |
6693e74a LT |
401 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
402 | { | |
403 | u32 devres; | |
404 | u32 mask, size, base; | |
405 | ||
406 | pci_read_config_dword(dev, port, &devres); | |
407 | if ((devres & enable) != enable) | |
408 | return; | |
409 | mask = (devres >> 16) & 15; | |
410 | base = devres & 0xffff; | |
411 | size = 16; | |
412 | for (;;) { | |
413 | unsigned bit = size >> 1; | |
414 | if ((bit & mask) == bit) | |
415 | break; | |
416 | size = bit; | |
417 | } | |
418 | /* | |
419 | * For now we only print it out. Eventually we'll want to | |
420 | * reserve it (at least if it's in the 0x1000+ range), but | |
421 | * let's get enough confirmation reports first. | |
422 | */ | |
423 | base &= -size; | |
f0fda801 | 424 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
425 | } |
426 | ||
427 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
428 | { | |
429 | u32 devres; | |
430 | u32 mask, size, base; | |
431 | ||
432 | pci_read_config_dword(dev, port, &devres); | |
433 | if ((devres & enable) != enable) | |
434 | return; | |
435 | base = devres & 0xffff0000; | |
436 | mask = (devres & 0x3f) << 16; | |
437 | size = 128 << 16; | |
438 | for (;;) { | |
439 | unsigned bit = size >> 1; | |
440 | if ((bit & mask) == bit) | |
441 | break; | |
442 | size = bit; | |
443 | } | |
444 | /* | |
445 | * For now we only print it out. Eventually we'll want to | |
446 | * reserve it, but let's get enough confirmation reports first. | |
447 | */ | |
448 | base &= -size; | |
f0fda801 | 449 | dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
450 | } |
451 | ||
1da177e4 LT |
452 | /* |
453 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
454 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 455 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 456 | * and a few strange programmable PIIX4 device resources. |
1da177e4 LT |
457 | */ |
458 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) | |
459 | { | |
6693e74a | 460 | u32 region, res_a; |
1da177e4 LT |
461 | |
462 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 463 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
1da177e4 | 464 | pci_read_config_dword(dev, 0x90, ®ion); |
08db2a70 | 465 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
6693e74a LT |
466 | |
467 | /* Device resource A has enables for some of the other ones */ | |
468 | pci_read_config_dword(dev, 0x5c, &res_a); | |
469 | ||
470 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
471 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
472 | ||
473 | /* Device resource D is just bitfields for static resources */ | |
474 | ||
475 | /* Device 12 enabled? */ | |
476 | if (res_a & (1 << 29)) { | |
477 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
478 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
479 | } | |
480 | /* Device 13 enabled? */ | |
481 | if (res_a & (1 << 30)) { | |
482 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
483 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
484 | } | |
485 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
486 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 487 | } |
652c538e AM |
488 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
489 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 LT |
490 | |
491 | /* | |
492 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
493 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
494 | * 0x58 (64 bytes of GPIO I/O space) | |
495 | */ | |
496 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) | |
497 | { | |
498 | u32 region; | |
499 | ||
500 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 501 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
1da177e4 LT |
502 | |
503 | pci_read_config_dword(dev, 0x58, ®ion); | |
6693e74a | 504 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
1da177e4 | 505 | } |
652c538e AM |
506 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
507 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
508 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
509 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
510 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
511 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
512 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
514 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
515 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 516 | |
894886e5 | 517 | static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f M |
518 | { |
519 | u32 region; | |
520 | ||
521 | pci_read_config_dword(dev, 0x40, ®ion); | |
522 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); | |
523 | ||
524 | pci_read_config_dword(dev, 0x48, ®ion); | |
525 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); | |
526 | } | |
894886e5 LT |
527 | |
528 | static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) | |
529 | { | |
530 | u32 val; | |
531 | u32 size, base; | |
532 | ||
533 | pci_read_config_dword(dev, reg, &val); | |
534 | ||
535 | /* Enabled? */ | |
536 | if (!(val & 1)) | |
537 | return; | |
538 | base = val & 0xfffc; | |
539 | if (dynsize) { | |
540 | /* | |
541 | * This is not correct. It is 16, 32 or 64 bytes depending on | |
542 | * register D31:F0:ADh bits 5:4. | |
543 | * | |
544 | * But this gets us at least _part_ of it. | |
545 | */ | |
546 | size = 16; | |
547 | } else { | |
548 | size = 128; | |
549 | } | |
550 | base &= ~(size-1); | |
551 | ||
552 | /* Just print it out for now. We should reserve it after more debugging */ | |
553 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); | |
554 | } | |
555 | ||
556 | static void __devinit quirk_ich6_lpc(struct pci_dev *dev) | |
557 | { | |
558 | /* Shared ACPI/GPIO decode with all ICH6+ */ | |
559 | ich6_lpc_acpi_gpio(dev); | |
560 | ||
561 | /* ICH6-specific generic IO decode */ | |
562 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); | |
563 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); | |
564 | } | |
565 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); | |
566 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); | |
567 | ||
568 | static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) | |
569 | { | |
570 | u32 val; | |
571 | u32 mask, base; | |
572 | ||
573 | pci_read_config_dword(dev, reg, &val); | |
574 | ||
575 | /* Enabled? */ | |
576 | if (!(val & 1)) | |
577 | return; | |
578 | ||
579 | /* | |
580 | * IO base in bits 15:2, mask in bits 23:18, both | |
581 | * are dword-based | |
582 | */ | |
583 | base = val & 0xfffc; | |
584 | mask = (val >> 16) & 0xfc; | |
585 | mask |= 3; | |
586 | ||
587 | /* Just print it out for now. We should reserve it after more debugging */ | |
588 | dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); | |
589 | } | |
590 | ||
591 | /* ICH7-10 has the same common LPC generic IO decode registers */ | |
592 | static void __devinit quirk_ich7_lpc(struct pci_dev *dev) | |
593 | { | |
594 | /* We share the common ACPI/DPIO decode with ICH6 */ | |
595 | ich6_lpc_acpi_gpio(dev); | |
596 | ||
597 | /* And have 4 ICH7+ generic decodes */ | |
598 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); | |
599 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); | |
600 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); | |
601 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); | |
602 | } | |
603 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); | |
604 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); | |
605 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); | |
606 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); | |
607 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); | |
608 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); | |
609 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); | |
610 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); | |
611 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); | |
612 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); | |
613 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); | |
614 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); | |
615 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); | |
2cea752f | 616 | |
1da177e4 LT |
617 | /* |
618 | * VIA ACPI: One IO region pointed to by longword at | |
619 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
620 | */ | |
621 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) | |
622 | { | |
1da177e4 LT |
623 | u32 region; |
624 | ||
651472fb | 625 | if (dev->revision & 0x10) { |
1da177e4 LT |
626 | pci_read_config_dword(dev, 0x48, ®ion); |
627 | region &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 628 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
1da177e4 LT |
629 | } |
630 | } | |
652c538e | 631 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
632 | |
633 | /* | |
634 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
635 | * 0x48 (256 bytes of ACPI registers) | |
636 | * 0x70 (128 bytes of hardware monitoring register) | |
637 | * 0x90 (16 bytes of SMB registers) | |
638 | */ | |
639 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) | |
640 | { | |
641 | u16 hm; | |
642 | u32 smb; | |
643 | ||
644 | quirk_vt82c586_acpi(dev); | |
645 | ||
646 | pci_read_config_word(dev, 0x70, &hm); | |
647 | hm &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 648 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
1da177e4 LT |
649 | |
650 | pci_read_config_dword(dev, 0x90, &smb); | |
651 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 652 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
1da177e4 | 653 | } |
652c538e | 654 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 655 | |
6d85f29b IK |
656 | /* |
657 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
658 | * 0x88 (128 bytes of power management registers) | |
659 | * 0xd0 (16 bytes of SMB registers) | |
660 | */ | |
661 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) | |
662 | { | |
663 | u16 pm, smb; | |
664 | ||
665 | pci_read_config_word(dev, 0x88, &pm); | |
666 | pm &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 667 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
6d85f29b IK |
668 | |
669 | pci_read_config_word(dev, 0xd0, &smb); | |
670 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 671 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
6d85f29b IK |
672 | } |
673 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
674 | ||
1da177e4 LT |
675 | |
676 | #ifdef CONFIG_X86_IO_APIC | |
677 | ||
678 | #include <asm/io_apic.h> | |
679 | ||
680 | /* | |
681 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
682 | * devices to the external APIC. | |
683 | * | |
684 | * TODO: When we have device-specific interrupt routers, | |
685 | * this code will go away from quirks. | |
686 | */ | |
1597cacb | 687 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
688 | { |
689 | u8 tmp; | |
690 | ||
691 | if (nr_ioapics < 1) | |
692 | tmp = 0; /* nothing routed to external APIC */ | |
693 | else | |
694 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
695 | ||
f0fda801 | 696 | dev_info(&dev->dev, "%sbling VIA external APIC routing\n", |
1da177e4 LT |
697 | tmp == 0 ? "Disa" : "Ena"); |
698 | ||
699 | /* Offset 0x58: External APIC IRQ output control */ | |
700 | pci_write_config_byte (dev, 0x58, tmp); | |
701 | } | |
652c538e | 702 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e | 703 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4 | 704 | |
a1740913 KW |
705 | /* |
706 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. | |
707 | * This leads to doubled level interrupt rates. | |
708 | * Set this bit to get rid of cycle wastage. | |
709 | * Otherwise uncritical. | |
710 | */ | |
1597cacb | 711 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
712 | { |
713 | u8 misc_control2; | |
714 | #define BYPASS_APIC_DEASSERT 8 | |
715 | ||
716 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
717 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
f0fda801 | 718 | dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
a1740913 KW |
719 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
720 | } | |
721 | } | |
722 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
e1a2a51e | 723 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 724 | |
1da177e4 LT |
725 | /* |
726 | * The AMD io apic can hang the box when an apic irq is masked. | |
727 | * We check all revs >= B0 (yet not in the pre production!) as the bug | |
728 | * is currently marked NoFix | |
729 | * | |
730 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 731 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4 LT |
732 | * of course. However the advice is demonstrably good even if so.. |
733 | */ | |
734 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) | |
735 | { | |
44c10138 | 736 | if (dev->revision >= 0x02) { |
f0fda801 | 737 | dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
738 | dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); | |
1da177e4 LT |
739 | } |
740 | } | |
652c538e | 741 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
742 | |
743 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) | |
744 | { | |
745 | if (dev->devfn == 0 && dev->bus->number == 0) | |
746 | sis_apic_bug = 1; | |
747 | } | |
652c538e | 748 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); |
1da177e4 LT |
749 | #endif /* CONFIG_X86_IO_APIC */ |
750 | ||
d556ad4b PO |
751 | /* |
752 | * Some settings of MMRBC can lead to data corruption so block changes. | |
753 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
754 | */ | |
755 | static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) | |
756 | { | |
aa288d4d | 757 | if (dev->subordinate && dev->revision <= 0x12) { |
f0fda801 | 758 | dev_info(&dev->dev, "AMD8131 rev %x detected; " |
759 | "disabling PCI-X MMRBC\n", dev->revision); | |
d556ad4b PO |
760 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
761 | } | |
762 | } | |
763 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 764 | |
1da177e4 LT |
765 | /* |
766 | * FIXME: it is questionable that quirk_via_acpi | |
767 | * is needed. It shows up as an ISA bridge, and does not | |
768 | * support the PCI_INTERRUPT_LINE register at all. Therefore | |
769 | * it seems like setting the pci_dev's 'irq' to the | |
770 | * value of the ACPI SCI interrupt is only done for convenience. | |
771 | * -jgarzik | |
772 | */ | |
773 | static void __devinit quirk_via_acpi(struct pci_dev *d) | |
774 | { | |
775 | /* | |
776 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 | |
777 | */ | |
778 | u8 irq; | |
779 | pci_read_config_byte(d, 0x42, &irq); | |
780 | irq &= 0xf; | |
781 | if (irq && (irq != 2)) | |
782 | d->irq = irq; | |
783 | } | |
652c538e AM |
784 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
785 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 786 | |
09d6029f DD |
787 | |
788 | /* | |
1597cacb | 789 | * VIA bridges which have VLink |
09d6029f | 790 | */ |
1597cacb | 791 | |
c06bb5d4 JD |
792 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
793 | ||
794 | static void quirk_via_bridge(struct pci_dev *dev) | |
795 | { | |
796 | /* See what bridge we have and find the device ranges */ | |
797 | switch (dev->device) { | |
798 | case PCI_DEVICE_ID_VIA_82C686: | |
cb7468ef JD |
799 | /* The VT82C686 is special, it attaches to PCI and can have |
800 | any device number. All its subdevices are functions of | |
801 | that single device. */ | |
802 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); | |
803 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
804 | break; |
805 | case PCI_DEVICE_ID_VIA_8237: | |
806 | case PCI_DEVICE_ID_VIA_8237A: | |
807 | via_vlink_dev_lo = 15; | |
808 | break; | |
809 | case PCI_DEVICE_ID_VIA_8235: | |
810 | via_vlink_dev_lo = 16; | |
811 | break; | |
812 | case PCI_DEVICE_ID_VIA_8231: | |
813 | case PCI_DEVICE_ID_VIA_8233_0: | |
814 | case PCI_DEVICE_ID_VIA_8233A: | |
815 | case PCI_DEVICE_ID_VIA_8233C_0: | |
816 | via_vlink_dev_lo = 17; | |
817 | break; | |
818 | } | |
819 | } | |
820 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
821 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
822 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
823 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
824 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
825 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
826 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
827 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 828 | |
1597cacb AC |
829 | /** |
830 | * quirk_via_vlink - VIA VLink IRQ number update | |
831 | * @dev: PCI device | |
832 | * | |
833 | * If the device we are dealing with is on a PIC IRQ we need to | |
834 | * ensure that the IRQ line register which usually is not relevant | |
835 | * for PCI cards, is actually written so that interrupts get sent | |
c06bb5d4 JD |
836 | * to the right place. |
837 | * We only do this on systems where a VIA south bridge was detected, | |
838 | * and only for VIA devices on the motherboard (see quirk_via_bridge | |
839 | * above). | |
1597cacb AC |
840 | */ |
841 | ||
842 | static void quirk_via_vlink(struct pci_dev *dev) | |
25be5e6c LB |
843 | { |
844 | u8 irq, new_irq; | |
845 | ||
c06bb5d4 JD |
846 | /* Check if we have VLink at all */ |
847 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
848 | return; |
849 | ||
850 | new_irq = dev->irq; | |
851 | ||
852 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
853 | if (!new_irq || new_irq > 15) | |
854 | return; | |
855 | ||
1597cacb | 856 | /* Internal device ? */ |
c06bb5d4 JD |
857 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
858 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
859 | return; |
860 | ||
861 | /* This is an internal VLink device on a PIC interrupt. The BIOS | |
862 | ought to have set this but may not have, so we redo it */ | |
863 | ||
25be5e6c LB |
864 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
865 | if (new_irq != irq) { | |
f0fda801 | 866 | dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", |
867 | irq, new_irq); | |
25be5e6c LB |
868 | udelay(15); /* unknown if delay really needed */ |
869 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
870 | } | |
871 | } | |
1597cacb | 872 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 873 | |
1da177e4 LT |
874 | /* |
875 | * VIA VT82C598 has its device ID settable and many BIOSes | |
876 | * set it to the ID of VT82C597 for backward compatibility. | |
877 | * We need to switch it off to be able to recognize the real | |
878 | * type of the chip. | |
879 | */ | |
880 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) | |
881 | { | |
882 | pci_write_config_byte(dev, 0xfc, 0); | |
883 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
884 | } | |
652c538e | 885 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
886 | |
887 | /* | |
888 | * CardBus controllers have a legacy base address that enables them | |
889 | * to respond as i82365 pcmcia controllers. We don't want them to | |
890 | * do this even if the Linux CardBus driver is not loaded, because | |
891 | * the Linux i82365 driver does not (and should not) handle CardBus. | |
892 | */ | |
1597cacb | 893 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 LT |
894 | { |
895 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) | |
896 | return; | |
897 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); | |
898 | } | |
899 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); | |
e1a2a51e | 900 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
1da177e4 LT |
901 | |
902 | /* | |
903 | * Following the PCI ordering rules is optional on the AMD762. I'm not | |
904 | * sure what the designers were smoking but let's not inhale... | |
905 | * | |
906 | * To be fair to AMD, it follows the spec by default, its BIOS people | |
907 | * who turn it off! | |
908 | */ | |
1597cacb | 909 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
910 | { |
911 | u32 pcic; | |
912 | pci_read_config_dword(dev, 0x4C, &pcic); | |
913 | if ((pcic&6)!=6) { | |
914 | pcic |= 6; | |
f0fda801 | 915 | dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1da177e4 LT |
916 | pci_write_config_dword(dev, 0x4C, pcic); |
917 | pci_read_config_dword(dev, 0x84, &pcic); | |
918 | pcic |= (1<<23); /* Required in this mode */ | |
919 | pci_write_config_dword(dev, 0x84, pcic); | |
920 | } | |
921 | } | |
652c538e | 922 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e | 923 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4 LT |
924 | |
925 | /* | |
926 | * DreamWorks provided workaround for Dunord I-3000 problem | |
927 | * | |
928 | * This card decodes and responds to addresses not apparently | |
929 | * assigned to it. We force a larger allocation to ensure that | |
930 | * nothing gets put too close to it. | |
931 | */ | |
932 | static void __devinit quirk_dunord ( struct pci_dev * dev ) | |
933 | { | |
934 | struct resource *r = &dev->resource [1]; | |
935 | r->start = 0; | |
936 | r->end = 0xffffff; | |
937 | } | |
652c538e | 938 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
939 | |
940 | /* | |
941 | * i82380FB mobile docking controller: its PCI-to-PCI bridge | |
942 | * is subtractive decoding (transparent), and does indicate this | |
943 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 | |
944 | * instead of 0x01. | |
945 | */ | |
946 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) | |
947 | { | |
948 | dev->transparent = 1; | |
949 | } | |
652c538e AM |
950 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
951 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
952 | |
953 | /* | |
954 | * Common misconfiguration of the MediaGX/Geode PCI master that will | |
955 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 | |
956 | * datasheets found at http://www.national.com/ds/GX for info on what | |
957 | * these bits do. <christer@weinigel.se> | |
958 | */ | |
1597cacb | 959 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
960 | { |
961 | u8 reg; | |
962 | pci_read_config_byte(dev, 0x41, ®); | |
963 | if (reg & 2) { | |
964 | reg &= ~2; | |
f0fda801 | 965 | dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
1da177e4 LT |
966 | pci_write_config_byte(dev, 0x41, reg); |
967 | } | |
968 | } | |
652c538e AM |
969 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
970 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 971 | |
1da177e4 LT |
972 | /* |
973 | * Ensure C0 rev restreaming is off. This is normally done by | |
974 | * the BIOS but in the odd case it is not the results are corruption | |
975 | * hence the presence of a Linux check | |
976 | */ | |
1597cacb | 977 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
978 | { |
979 | u16 config; | |
1da177e4 | 980 | |
44c10138 | 981 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
982 | return; |
983 | pci_read_config_word(pdev, 0x40, &config); | |
984 | if (config & (1<<6)) { | |
985 | config &= ~(1<<6); | |
986 | pci_write_config_word(pdev, 0x40, config); | |
f0fda801 | 987 | dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1da177e4 LT |
988 | } |
989 | } | |
652c538e | 990 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e | 991 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4 | 992 | |
05a7d22b | 993 | static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a | 994 | { |
05a7d22b CC |
995 | /* set sb600/sb700/sb800 sata to ahci mode */ |
996 | u8 tmp; | |
ab17443a | 997 | |
05a7d22b CC |
998 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
999 | if (tmp == 0x01) { | |
ab17443a CH |
1000 | pci_read_config_byte(pdev, 0x40, &tmp); |
1001 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
1002 | pci_write_config_byte(pdev, 0x9, 1); | |
1003 | pci_write_config_byte(pdev, 0xa, 6); | |
1004 | pci_write_config_byte(pdev, 0x40, tmp); | |
1005 | ||
c9f89475 | 1006 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
05a7d22b | 1007 | dev_info(&pdev->dev, "set SATA to AHCI mode\n"); |
ab17443a CH |
1008 | } |
1009 | } | |
05a7d22b | 1010 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1011 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b | 1012 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1013 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
ab17443a | 1014 | |
1da177e4 LT |
1015 | /* |
1016 | * Serverworks CSB5 IDE does not fully support native mode | |
1017 | */ | |
1018 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) | |
1019 | { | |
1020 | u8 prog; | |
1021 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1022 | if (prog & 5) { | |
1023 | prog &= ~5; | |
1024 | pdev->class &= ~5; | |
1025 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 1026 | /* PCI layer will sort out resources */ |
1da177e4 LT |
1027 | } |
1028 | } | |
652c538e | 1029 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 LT |
1030 | |
1031 | /* | |
1032 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same | |
1033 | */ | |
1034 | static void __init quirk_ide_samemode(struct pci_dev *pdev) | |
1035 | { | |
1036 | u8 prog; | |
1037 | ||
1038 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1039 | ||
1040 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
f0fda801 | 1041 | dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); |
1da177e4 LT |
1042 | prog &= ~5; |
1043 | pdev->class &= ~5; | |
1044 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
1045 | } |
1046 | } | |
368c73d4 | 1047 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 | 1048 | |
979b1791 AC |
1049 | /* |
1050 | * Some ATA devices break if put into D3 | |
1051 | */ | |
1052 | ||
1053 | static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) | |
1054 | { | |
1055 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ | |
1056 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
1057 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; | |
1058 | } | |
1059 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); | |
1060 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); | |
1061 | ||
1da177e4 LT |
1062 | /* This was originally an Alpha specific thing, but it really fits here. |
1063 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. | |
1064 | */ | |
1065 | static void __init quirk_eisa_bridge(struct pci_dev *dev) | |
1066 | { | |
1067 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
1068 | } | |
652c538e | 1069 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 | 1070 | |
7daa0c4f | 1071 | |
1da177e4 LT |
1072 | /* |
1073 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
1074 | * is not activated. The myth is that Asus said that they do not want the | |
1075 | * users to be irritated by just another PCI Device in the Win98 device | |
1076 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors | |
1077 | * package 2.7.0 for details) | |
1078 | * | |
1079 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC | |
1080 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 1081 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1082 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
1083 | * |
1084 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
1085 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
1086 | * was done by SMM code, which could cause unsynchronized concurrent | |
1087 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
1088 | * should be very careful when adding new entries: if SMM is accessing the | |
1089 | * Intel SMBus, this is a very good reason to leave it hidden. | |
a99acc83 JD |
1090 | * |
1091 | * Likewise, many recent laptops use ACPI for thermal management. If the | |
1092 | * ACPI DSDT code accesses the SMBus, then Linux should not access it | |
1093 | * natively, and keeping the SMBus hidden is the right thing to do. If you | |
1094 | * are about to add an entry in the table below, please first disassemble | |
1095 | * the DSDT and double-check that there is no code accessing the SMBus. | |
1da177e4 | 1096 | */ |
9d24a81e | 1097 | static int asus_hides_smbus; |
1da177e4 LT |
1098 | |
1099 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) | |
1100 | { | |
1101 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1102 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
1103 | switch(dev->subsystem_device) { | |
a00db371 | 1104 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
1105 | case 0x8070: /* P4B */ |
1106 | case 0x8088: /* P4B533 */ | |
1107 | case 0x1626: /* L3C notebook */ | |
1108 | asus_hides_smbus = 1; | |
1109 | } | |
2f2d39d2 | 1110 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1da177e4 LT |
1111 | switch(dev->subsystem_device) { |
1112 | case 0x80b1: /* P4GE-V */ | |
1113 | case 0x80b2: /* P4PE */ | |
1114 | case 0x8093: /* P4B533-V */ | |
1115 | asus_hides_smbus = 1; | |
1116 | } | |
2f2d39d2 | 1117 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1da177e4 LT |
1118 | switch(dev->subsystem_device) { |
1119 | case 0x8030: /* P4T533 */ | |
1120 | asus_hides_smbus = 1; | |
1121 | } | |
2f2d39d2 | 1122 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
1123 | switch (dev->subsystem_device) { |
1124 | case 0x8070: /* P4G8X Deluxe */ | |
1125 | asus_hides_smbus = 1; | |
1126 | } | |
2f2d39d2 | 1127 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
1128 | switch (dev->subsystem_device) { |
1129 | case 0x80c9: /* PU-DLS */ | |
1130 | asus_hides_smbus = 1; | |
1131 | } | |
2f2d39d2 | 1132 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1133 | switch (dev->subsystem_device) { |
1134 | case 0x1751: /* M2N notebook */ | |
1135 | case 0x1821: /* M5N notebook */ | |
4096ed0f | 1136 | case 0x1897: /* A6L notebook */ |
1da177e4 LT |
1137 | asus_hides_smbus = 1; |
1138 | } | |
2f2d39d2 | 1139 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1140 | switch (dev->subsystem_device) { |
1141 | case 0x184b: /* W1N notebook */ | |
1142 | case 0x186a: /* M6Ne notebook */ | |
1143 | asus_hides_smbus = 1; | |
1144 | } | |
2f2d39d2 | 1145 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1146 | switch (dev->subsystem_device) { |
1147 | case 0x80f2: /* P4P800-X */ | |
1148 | asus_hides_smbus = 1; | |
1149 | } | |
2f2d39d2 | 1150 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1151 | switch (dev->subsystem_device) { |
1152 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1153 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1154 | asus_hides_smbus = 1; |
1155 | } | |
1da177e4 LT |
1156 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1157 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1158 | switch(dev->subsystem_device) { | |
1159 | case 0x088C: /* HP Compaq nc8000 */ | |
1160 | case 0x0890: /* HP Compaq nc6000 */ | |
1161 | asus_hides_smbus = 1; | |
1162 | } | |
2f2d39d2 | 1163 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1164 | switch (dev->subsystem_device) { |
1165 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1166 | case 0x12bd: /* HP D530 */ |
74c57428 | 1167 | case 0x006a: /* HP Compaq nx9500 */ |
1da177e4 LT |
1168 | asus_hides_smbus = 1; |
1169 | } | |
677cc644 JD |
1170 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1171 | switch (dev->subsystem_device) { | |
1172 | case 0x12bf: /* HP xw4100 */ | |
1173 | asus_hides_smbus = 1; | |
1174 | } | |
1da177e4 LT |
1175 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1176 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1177 | switch(dev->subsystem_device) { | |
1178 | case 0xC00C: /* Samsung P35 notebook */ | |
1179 | asus_hides_smbus = 1; | |
1180 | } | |
c87f883e RIZ |
1181 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1182 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1183 | switch(dev->subsystem_device) { | |
1184 | case 0x0058: /* Compaq Evo N620c */ | |
1185 | asus_hides_smbus = 1; | |
1186 | } | |
d7698edc | 1187 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
1188 | switch(dev->subsystem_device) { | |
1189 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ | |
1190 | /* Motherboard doesn't have Host bridge | |
1191 | * subvendor/subdevice IDs, therefore checking | |
1192 | * its on-board VGA controller */ | |
1193 | asus_hides_smbus = 1; | |
1194 | } | |
8293b0f6 | 1195 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
10260d9a JD |
1196 | switch(dev->subsystem_device) { |
1197 | case 0x00b8: /* Compaq Evo D510 CMT */ | |
1198 | case 0x00b9: /* Compaq Evo D510 SFF */ | |
8293b0f6 DS |
1199 | /* Motherboard doesn't have Host bridge |
1200 | * subvendor/subdevice IDs and on-board VGA | |
1201 | * controller is disabled if an AGP card is | |
1202 | * inserted, therefore checking USB UHCI | |
1203 | * Controller #1 */ | |
10260d9a JD |
1204 | asus_hides_smbus = 1; |
1205 | } | |
27e46859 KH |
1206 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1207 | switch (dev->subsystem_device) { | |
1208 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ | |
1209 | /* Motherboard doesn't have host bridge | |
1210 | * subvendor/subdevice IDs, therefore checking | |
1211 | * its on-board VGA controller */ | |
1212 | asus_hides_smbus = 1; | |
1213 | } | |
1da177e4 LT |
1214 | } |
1215 | } | |
652c538e AM |
1216 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1217 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1218 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1219 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1220 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1221 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1222 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1223 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1224 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1225 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1226 | ||
1227 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
8293b0f6 | 1228 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e46859 | 1229 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edc | 1230 | |
1597cacb | 1231 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1232 | { |
1233 | u16 val; | |
1234 | ||
1235 | if (likely(!asus_hides_smbus)) | |
1236 | return; | |
1237 | ||
1238 | pci_read_config_word(dev, 0xF2, &val); | |
1239 | if (val & 0x8) { | |
1240 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1241 | pci_read_config_word(dev, 0xF2, &val); | |
1242 | if (val & 0x8) | |
f0fda801 | 1243 | dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
1da177e4 | 1244 | else |
f0fda801 | 1245 | dev_info(&dev->dev, "Enabled i801 SMBus device\n"); |
1da177e4 LT |
1246 | } |
1247 | } | |
652c538e AM |
1248 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1249 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1250 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1251 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1252 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1253 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1254 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
e1a2a51e RW |
1255 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1256 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1257 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1258 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1259 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1260 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1261 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb | 1262 | |
e1a2a51e RW |
1263 | /* It appears we just have one such device. If not, we have a warning */ |
1264 | static void __iomem *asus_rcba_base; | |
1265 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) | |
acc06632 | 1266 | { |
e1a2a51e | 1267 | u32 rcba; |
acc06632 M |
1268 | |
1269 | if (likely(!asus_hides_smbus)) | |
1270 | return; | |
e1a2a51e RW |
1271 | WARN_ON(asus_rcba_base); |
1272 | ||
acc06632 | 1273 | pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e RW |
1274 | /* use bits 31:14, 16 kB aligned */ |
1275 | asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); | |
1276 | if (asus_rcba_base == NULL) | |
1277 | return; | |
1278 | } | |
1279 | ||
1280 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) | |
1281 | { | |
1282 | u32 val; | |
1283 | ||
1284 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1285 | return; | |
1286 | /* read the Function Disable register, dword mode only */ | |
1287 | val = readl(asus_rcba_base + 0x3418); | |
1288 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ | |
1289 | } | |
1290 | ||
1291 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) | |
1292 | { | |
1293 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1294 | return; | |
1295 | iounmap(asus_rcba_base); | |
1296 | asus_rcba_base = NULL; | |
f0fda801 | 1297 | dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); |
acc06632 | 1298 | } |
e1a2a51e RW |
1299 | |
1300 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
1301 | { | |
1302 | asus_hides_smbus_lpc_ich6_suspend(dev); | |
1303 | asus_hides_smbus_lpc_ich6_resume_early(dev); | |
1304 | asus_hides_smbus_lpc_ich6_resume(dev); | |
1305 | } | |
652c538e | 1306 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e RW |
1307 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1308 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); | |
1309 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); | |
ce007ea5 | 1310 | |
1da177e4 LT |
1311 | /* |
1312 | * SiS 96x south bridge: BIOS typically hides SMBus device... | |
1313 | */ | |
1597cacb | 1314 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1315 | { |
1316 | u8 val = 0; | |
1da177e4 | 1317 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 | 1318 | if (val & 0x10) { |
f0fda801 | 1319 | dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); |
2f5c33b3 MH |
1320 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
1321 | } | |
1da177e4 | 1322 | } |
652c538e AM |
1323 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1324 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1325 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1326 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
e1a2a51e RW |
1327 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1328 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1329 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1330 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1331 | |
1da177e4 LT |
1332 | /* |
1333 | * ... This is further complicated by the fact that some SiS96x south | |
1334 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1335 | * spotted a compatible north bridge to make sure. | |
1336 | * (pci_find_device doesn't work yet) | |
1337 | * | |
1338 | * We can also enable the sis96x bit in the discovery register.. | |
1339 | */ | |
1da177e4 LT |
1340 | #define SIS_DETECT_REGISTER 0x40 |
1341 | ||
1597cacb | 1342 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1343 | { |
1344 | u8 reg; | |
1345 | u16 devid; | |
1346 | ||
1347 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1348 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1349 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1350 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1351 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1352 | return; | |
1353 | } | |
1354 | ||
1da177e4 | 1355 | /* |
2f5c33b3 MH |
1356 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
1357 | * hand in case it has already been processed. | |
1358 | * (depends on link order, which is apparently not guaranteed) | |
1da177e4 LT |
1359 | */ |
1360 | dev->device = devid; | |
2f5c33b3 | 1361 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1362 | } |
652c538e | 1363 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e | 1364 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4 | 1365 | |
1da177e4 | 1366 | |
e5548e96 BJD |
1367 | /* |
1368 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1369 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1370 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1371 | * -- bjd | |
1372 | */ | |
1597cacb | 1373 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1374 | { |
1375 | u8 val; | |
1376 | int asus_hides_ac97 = 0; | |
1377 | ||
1378 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1379 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1380 | asus_hides_ac97 = 1; | |
1381 | } | |
1382 | ||
1383 | if (!asus_hides_ac97) | |
1384 | return; | |
1385 | ||
1386 | pci_read_config_byte(dev, 0x50, &val); | |
1387 | if (val & 0xc0) { | |
1388 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1389 | pci_read_config_byte(dev, 0x50, &val); | |
1390 | if (val & 0xc0) | |
f0fda801 | 1391 | dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
e5548e96 | 1392 | else |
f0fda801 | 1393 | dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); |
e5548e96 BJD |
1394 | } |
1395 | } | |
652c538e | 1396 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e | 1397 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacb | 1398 | |
77967052 | 1399 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1400 | |
1401 | /* | |
1402 | * If we are using libata we can drive this chip properly but must | |
1403 | * do this early on to make the additional device appear during | |
1404 | * the PCI scanning. | |
1405 | */ | |
5ee2ae7f | 1406 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1407 | { |
e34bb370 | 1408 | u32 conf1, conf5, class; |
15e0c694 AC |
1409 | u8 hdr; |
1410 | ||
1411 | /* Only poke fn 0 */ | |
1412 | if (PCI_FUNC(pdev->devfn)) | |
1413 | return; | |
1414 | ||
5ee2ae7f TH |
1415 | pci_read_config_dword(pdev, 0x40, &conf1); |
1416 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1417 | |
5ee2ae7f TH |
1418 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1419 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1420 | ||
1421 | switch (pdev->device) { | |
1422 | case PCI_DEVICE_ID_JMICRON_JMB360: | |
1423 | /* The controller should be in single function ahci mode */ | |
1424 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1425 | break; | |
1426 | ||
1427 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1428 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1429 | /* Redirect IDE second PATA port to the right spot */ | |
1430 | conf5 |= (1 << 24); | |
1431 | /* Fall through */ | |
1432 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1433 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
1434 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ | |
1435 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1436 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1437 | break; |
1438 | ||
1439 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1440 | /* The controller should be in single function IDE mode */ | |
1441 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1442 | break; | |
15e0c694 | 1443 | } |
5ee2ae7f TH |
1444 | |
1445 | pci_write_config_dword(pdev, 0x40, conf1); | |
1446 | pci_write_config_dword(pdev, 0x80, conf5); | |
1447 | ||
1448 | /* Update pdev accordingly */ | |
1449 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1450 | pdev->hdr_type = hdr & 0x7f; | |
1451 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1452 | |
1453 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1454 | pdev->class = class >> 8; | |
15e0c694 | 1455 | } |
5ee2ae7f TH |
1456 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1457 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
1458 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); | |
1459 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); | |
1460 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1461 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
e1a2a51e RW |
1462 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1463 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
1464 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); | |
1465 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); | |
1466 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1467 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
15e0c694 AC |
1468 | |
1469 | #endif | |
1470 | ||
1da177e4 LT |
1471 | #ifdef CONFIG_X86_IO_APIC |
1472 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) | |
1473 | { | |
1474 | int i; | |
1475 | ||
1476 | if ((pdev->class >> 8) != 0xff00) | |
1477 | return; | |
1478 | ||
1479 | /* the first BAR is the location of the IO APIC...we must | |
1480 | * not touch this (and it's already covered by the fixmap), so | |
1481 | * forcibly insert it into the resource tree */ | |
1482 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) | |
1483 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1484 | ||
1485 | /* The next five BARs all seem to be rubbish, so just clean | |
1486 | * them out */ | |
1487 | for (i=1; i < 6; i++) { | |
1488 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); | |
1489 | } | |
1490 | ||
1491 | } | |
652c538e | 1492 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1493 | #endif |
1494 | ||
1da177e4 LT |
1495 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) |
1496 | { | |
1497 | pcie_mch_quirk = 1; | |
1498 | } | |
652c538e AM |
1499 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1500 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1501 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1502 | |
4602b88d KA |
1503 | |
1504 | /* | |
1505 | * It's possible for the MSI to get corrupted if shpc and acpi | |
1506 | * are used together on certain PXH-based systems. | |
1507 | */ | |
1508 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) | |
1509 | { | |
f5f2b131 | 1510 | pci_msi_off(dev); |
4602b88d | 1511 | dev->no_msi = 1; |
f0fda801 | 1512 | dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
4602b88d KA |
1513 | } |
1514 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1515 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1516 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1517 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1518 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1519 | ||
ffadcc2f KCA |
1520 | /* |
1521 | * Some Intel PCI Express chipsets have trouble with downstream | |
1522 | * device power management. | |
1523 | */ | |
1524 | static void quirk_intel_pcie_pm(struct pci_dev * dev) | |
1525 | { | |
1526 | pci_pm_d3_delay = 120; | |
1527 | dev->no_d1d2 = 1; | |
1528 | } | |
1529 | ||
1530 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); | |
1531 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1532 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1533 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1534 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1535 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1536 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1537 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1538 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1539 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1540 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1541 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1542 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1543 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1544 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1545 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1546 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1547 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1548 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1549 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1550 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1551 | |
426b3b8d | 1552 | #ifdef CONFIG_X86_IO_APIC |
e1d3a908 SA |
1553 | /* |
1554 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, | |
1555 | * remap the original interrupt in the linux kernel to the boot interrupt, so | |
1556 | * that a PCI device's interrupt handler is installed on the boot interrupt | |
1557 | * line instead. | |
1558 | */ | |
1559 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) | |
1560 | { | |
41b9eb26 | 1561 | if (noioapicquirk || noioapicreroute) |
e1d3a908 SA |
1562 | return; |
1563 | ||
1564 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; | |
1565 | ||
1566 | printk(KERN_INFO "PCI quirk: reroute interrupts for 0x%04x:0x%04x\n", | |
1567 | dev->vendor, dev->device); | |
1568 | return; | |
1569 | } | |
88d1dce3 OD |
1570 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
1571 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1572 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1573 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1574 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1575 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1576 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
1578 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); | |
1579 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1580 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1581 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1582 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1583 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1584 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1585 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
e1d3a908 | 1586 | |
426b3b8d SA |
1587 | /* |
1588 | * On some chipsets we can disable the generation of legacy INTx boot | |
1589 | * interrupts. | |
1590 | */ | |
1591 | ||
1592 | /* | |
1593 | * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no | |
1594 | * 300641-004US, section 5.7.3. | |
1595 | */ | |
1596 | #define INTEL_6300_IOAPIC_ABAR 0x40 | |
1597 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) | |
1598 | ||
1599 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) | |
1600 | { | |
1601 | u16 pci_config_word; | |
1602 | ||
1603 | if (noioapicquirk) | |
1604 | return; | |
1605 | ||
1606 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); | |
1607 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
1608 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); | |
1609 | ||
1610 | printk(KERN_INFO "disabled boot interrupt on device 0x%04x:0x%04x\n", | |
1611 | dev->vendor, dev->device); | |
1612 | } | |
88d1dce3 OD |
1613 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
1614 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); | |
77251188 OD |
1615 | |
1616 | /* | |
1617 | * disable boot interrupts on HT-1000 | |
1618 | */ | |
1619 | #define BC_HT1000_FEATURE_REG 0x64 | |
1620 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) | |
1621 | #define BC_HT1000_MAP_IDX 0xC00 | |
1622 | #define BC_HT1000_MAP_DATA 0xC01 | |
1623 | ||
1624 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) | |
1625 | { | |
1626 | u32 pci_config_dword; | |
1627 | u8 irq; | |
1628 | ||
1629 | if (noioapicquirk) | |
1630 | return; | |
1631 | ||
1632 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); | |
1633 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | | |
1634 | BC_HT1000_PIC_REGS_ENABLE); | |
1635 | ||
1636 | for (irq = 0x10; irq < 0x10 + 32; irq++) { | |
1637 | outb(irq, BC_HT1000_MAP_IDX); | |
1638 | outb(0x00, BC_HT1000_MAP_DATA); | |
1639 | } | |
1640 | ||
1641 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); | |
1642 | ||
1643 | printk(KERN_INFO "disabled boot interrupts on PCI device" | |
1644 | "0x%04x:0x%04x\n", dev->vendor, dev->device); | |
1645 | } | |
88d1dce3 OD |
1646 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
1647 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); | |
542622da OD |
1648 | |
1649 | /* | |
1650 | * disable boot interrupts on AMD and ATI chipsets | |
1651 | */ | |
1652 | /* | |
1653 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 | |
1654 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode | |
1655 | * (due to an erratum). | |
1656 | */ | |
1657 | #define AMD_813X_MISC 0x40 | |
1658 | #define AMD_813X_NOIOAMODE (1<<0) | |
bbe19443 | 1659 | #define AMD_813X_REV_B2 0x13 |
542622da OD |
1660 | |
1661 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) | |
1662 | { | |
1663 | u32 pci_config_dword; | |
1664 | ||
1665 | if (noioapicquirk) | |
1666 | return; | |
bbe19443 SA |
1667 | if (dev->revision == AMD_813X_REV_B2) |
1668 | return; | |
542622da OD |
1669 | |
1670 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); | |
1671 | pci_config_dword &= ~AMD_813X_NOIOAMODE; | |
1672 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); | |
1673 | ||
1674 | printk(KERN_INFO "disabled boot interrupts on PCI device " | |
1675 | "0x%04x:0x%04x\n", dev->vendor, dev->device); | |
1676 | } | |
88d1dce3 OD |
1677 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
1678 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
542622da OD |
1679 | |
1680 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 | |
1681 | ||
1682 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) | |
1683 | { | |
1684 | u16 pci_config_word; | |
1685 | ||
1686 | if (noioapicquirk) | |
1687 | return; | |
1688 | ||
1689 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); | |
1690 | if (!pci_config_word) { | |
1691 | printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x " | |
1692 | "already disabled\n", | |
1693 | dev->vendor, dev->device); | |
1694 | return; | |
1695 | } | |
1696 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); | |
1697 | printk(KERN_INFO "disabled boot interrupts on PCI device " | |
1698 | "0x%04x:0x%04x\n", dev->vendor, dev->device); | |
1699 | } | |
88d1dce3 OD |
1700 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
1701 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); | |
426b3b8d SA |
1702 | #endif /* CONFIG_X86_IO_APIC */ |
1703 | ||
33dced2e SS |
1704 | /* |
1705 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
1706 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
1707 | * Re-allocate the region if needed... | |
1708 | */ | |
1709 | static void __init quirk_tc86c001_ide(struct pci_dev *dev) | |
1710 | { | |
1711 | struct resource *r = &dev->resource[0]; | |
1712 | ||
1713 | if (r->start & 0x8) { | |
1714 | r->start = 0; | |
1715 | r->end = 0xf; | |
1716 | } | |
1717 | } | |
1718 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
1719 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
1720 | quirk_tc86c001_ide); | |
1721 | ||
1da177e4 LT |
1722 | static void __devinit quirk_netmos(struct pci_dev *dev) |
1723 | { | |
1724 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
1725 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
1726 | ||
1727 | /* | |
1728 | * These Netmos parts are multiport serial devices with optional | |
1729 | * parallel ports. Even when parallel ports are present, they | |
1730 | * are identified as class SERIAL, which means the serial driver | |
1731 | * will claim them. To prevent this, mark them as class OTHER. | |
1732 | * These combo devices should be claimed by parport_serial. | |
1733 | * | |
1734 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
1735 | * of parallel ports and <S> is the number of serial ports. | |
1736 | */ | |
1737 | switch (dev->device) { | |
4c9c1686 JS |
1738 | case PCI_DEVICE_ID_NETMOS_9835: |
1739 | /* Well, this rule doesn't hold for the following 9835 device */ | |
1740 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | |
1741 | dev->subsystem_device == 0x0299) | |
1742 | return; | |
1da177e4 LT |
1743 | case PCI_DEVICE_ID_NETMOS_9735: |
1744 | case PCI_DEVICE_ID_NETMOS_9745: | |
1da177e4 LT |
1745 | case PCI_DEVICE_ID_NETMOS_9845: |
1746 | case PCI_DEVICE_ID_NETMOS_9855: | |
1747 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && | |
1748 | num_parallel) { | |
f0fda801 | 1749 | dev_info(&dev->dev, "Netmos %04x (%u parallel, " |
1da177e4 LT |
1750 | "%u serial); changing class SERIAL to OTHER " |
1751 | "(use parport_serial)\n", | |
1752 | dev->device, num_parallel, num_serial); | |
1753 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
1754 | (dev->class & 0xff); | |
1755 | } | |
1756 | } | |
1757 | } | |
1758 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); | |
1759 | ||
16a74744 BH |
1760 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
1761 | { | |
e64aeccb | 1762 | u16 command, pmcsr; |
16a74744 BH |
1763 | u8 __iomem *csr; |
1764 | u8 cmd_hi; | |
e64aeccb | 1765 | int pm; |
16a74744 BH |
1766 | |
1767 | switch (dev->device) { | |
1768 | /* PCI IDs taken from drivers/net/e100.c */ | |
1769 | case 0x1029: | |
1770 | case 0x1030 ... 0x1034: | |
1771 | case 0x1038 ... 0x103E: | |
1772 | case 0x1050 ... 0x1057: | |
1773 | case 0x1059: | |
1774 | case 0x1064 ... 0x106B: | |
1775 | case 0x1091 ... 0x1095: | |
1776 | case 0x1209: | |
1777 | case 0x1229: | |
1778 | case 0x2449: | |
1779 | case 0x2459: | |
1780 | case 0x245D: | |
1781 | case 0x27DC: | |
1782 | break; | |
1783 | default: | |
1784 | return; | |
1785 | } | |
1786 | ||
1787 | /* | |
1788 | * Some firmware hands off the e100 with interrupts enabled, | |
1789 | * which can cause a flood of interrupts if packets are | |
1790 | * received before the driver attaches to the device. So | |
1791 | * disable all e100 interrupts here. The driver will | |
1792 | * re-enable them when it's ready. | |
1793 | */ | |
1794 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 1795 | |
1bef7dc0 | 1796 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
1797 | return; |
1798 | ||
e64aeccb IK |
1799 | /* |
1800 | * Check that the device is in the D0 power state. If it's not, | |
1801 | * there is no point to look any further. | |
1802 | */ | |
1803 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1804 | if (pm) { | |
1805 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); | |
1806 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) | |
1807 | return; | |
1808 | } | |
1809 | ||
1bef7dc0 BH |
1810 | /* Convert from PCI bus to resource space. */ |
1811 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 | 1812 | if (!csr) { |
f0fda801 | 1813 | dev_warn(&dev->dev, "Can't map e100 registers\n"); |
16a74744 BH |
1814 | return; |
1815 | } | |
1816 | ||
1817 | cmd_hi = readb(csr + 3); | |
1818 | if (cmd_hi == 0) { | |
f0fda801 | 1819 | dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " |
1820 | "disabling\n"); | |
16a74744 BH |
1821 | writeb(1, csr + 3); |
1822 | } | |
1823 | ||
1824 | iounmap(csr); | |
1825 | } | |
4e68fc97 | 1826 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
a5312e28 | 1827 | |
649426ef AD |
1828 | /* |
1829 | * The 82575 and 82598 may experience data corruption issues when transitioning | |
1830 | * out of L0S. To prevent this we need to disable L0S on the pci-e link | |
1831 | */ | |
1832 | static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) | |
1833 | { | |
1834 | dev_info(&dev->dev, "Disabling L0s\n"); | |
1835 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); | |
1836 | } | |
1837 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | |
1838 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | |
1839 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | |
1840 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | |
1841 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | |
1842 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | |
1843 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | |
1844 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | |
1845 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | |
1846 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | |
1847 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | |
1848 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | |
1849 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | |
1850 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | |
1851 | ||
a5312e28 IK |
1852 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
1853 | { | |
1854 | /* rev 1 ncr53c810 chips don't set the class at all which means | |
1855 | * they don't get their resources remapped. Fix that here. | |
1856 | */ | |
1857 | ||
1858 | if (dev->class == PCI_CLASS_NOT_DEFINED) { | |
f0fda801 | 1859 | dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); |
a5312e28 IK |
1860 | dev->class = PCI_CLASS_STORAGE_SCSI; |
1861 | } | |
1862 | } | |
1863 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
1864 | ||
9d265124 DY |
1865 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
1866 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) | |
1867 | { | |
1868 | u16 en1k; | |
1869 | u8 io_base_lo, io_limit_lo; | |
1870 | unsigned long base, limit; | |
1871 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1872 | ||
1873 | pci_read_config_word(dev, 0x40, &en1k); | |
1874 | ||
1875 | if (en1k & 0x200) { | |
f0fda801 | 1876 | dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); |
9d265124 DY |
1877 | |
1878 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
1879 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
1880 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1881 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1882 | ||
1883 | if (base <= limit) { | |
1884 | res->start = base; | |
1885 | res->end = limit + 0x3ff; | |
1886 | } | |
1887 | } | |
1888 | } | |
1889 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); | |
1890 | ||
15a260d5 DY |
1891 | /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 |
1892 | * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() | |
1893 | * in drivers/pci/setup-bus.c | |
1894 | */ | |
1895 | static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) | |
1896 | { | |
1897 | u16 en1k, iobl_adr, iobl_adr_1k; | |
1898 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1899 | ||
1900 | pci_read_config_word(dev, 0x40, &en1k); | |
1901 | ||
1902 | if (en1k & 0x200) { | |
1903 | pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); | |
1904 | ||
1905 | iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); | |
1906 | ||
1907 | if (iobl_adr != iobl_adr_1k) { | |
f0fda801 | 1908 | dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", |
15a260d5 DY |
1909 | iobl_adr,iobl_adr_1k); |
1910 | pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); | |
1911 | } | |
1912 | } | |
1913 | } | |
1914 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); | |
1915 | ||
cf34a8e0 BG |
1916 | /* Under some circumstances, AER is not linked with extended capabilities. |
1917 | * Force it to be linked by setting the corresponding control bit in the | |
1918 | * config space. | |
1919 | */ | |
1597cacb | 1920 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
1921 | { |
1922 | uint8_t b; | |
1923 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { | |
1924 | if (!(b & 0x20)) { | |
1925 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
f0fda801 | 1926 | dev_info(&dev->dev, |
1927 | "Linking AER extended capability\n"); | |
cf34a8e0 BG |
1928 | } |
1929 | } | |
1930 | } | |
1931 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
1932 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
e1a2a51e | 1933 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacb | 1934 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e0 | 1935 | |
53a9bf42 TY |
1936 | static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
1937 | { | |
1938 | /* | |
1939 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
1940 | * which causes unspecified timing errors with a VT6212L on the PCI | |
1941 | * bus leading to USB2.0 packet loss. The defaults are that these | |
1942 | * features are turned off but some BIOSes turn them on. | |
1943 | */ | |
1944 | ||
1945 | uint8_t b; | |
1946 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { | |
1947 | if (b & 0x40) { | |
1948 | /* Turn off PCI Bus Parking */ | |
1949 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
1950 | ||
bc043274 TY |
1951 | dev_info(&dev->dev, |
1952 | "Disabling VIA CX700 PCI parking\n"); | |
1953 | } | |
1954 | } | |
1955 | ||
1956 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { | |
1957 | if (b != 0) { | |
53a9bf42 TY |
1958 | /* Turn off PCI Master read caching */ |
1959 | pci_write_config_byte(dev, 0x72, 0x0); | |
bc043274 TY |
1960 | |
1961 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ | |
53a9bf42 | 1962 | pci_write_config_byte(dev, 0x75, 0x1); |
bc043274 TY |
1963 | |
1964 | /* Disable "Read FIFO Timer" */ | |
53a9bf42 TY |
1965 | pci_write_config_byte(dev, 0x77, 0x0); |
1966 | ||
d6505a52 | 1967 | dev_info(&dev->dev, |
bc043274 | 1968 | "Disabling VIA CX700 PCI caching\n"); |
53a9bf42 TY |
1969 | } |
1970 | } | |
1971 | } | |
1972 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); | |
1973 | ||
99cb233d BL |
1974 | /* |
1975 | * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the | |
1976 | * VPD end tag will hang the device. This problem was initially | |
1977 | * observed when a vpd entry was created in sysfs | |
1978 | * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry | |
1979 | * will dump 32k of data. Reading a full 32k will cause an access | |
1980 | * beyond the VPD end tag causing the device to hang. Once the device | |
1981 | * is hung, the bnx2 driver will not be able to reset the device. | |
1982 | * We believe that it is legal to read beyond the end tag and | |
1983 | * therefore the solution is to limit the read/write length. | |
1984 | */ | |
1985 | static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) | |
1986 | { | |
9d82d8ea | 1987 | /* |
35405f25 DH |
1988 | * Only disable the VPD capability for 5706, 5706S, 5708, |
1989 | * 5708S and 5709 rev. A | |
9d82d8ea | 1990 | */ |
99cb233d | 1991 | if ((dev->device == PCI_DEVICE_ID_NX2_5706) || |
35405f25 | 1992 | (dev->device == PCI_DEVICE_ID_NX2_5706S) || |
99cb233d | 1993 | (dev->device == PCI_DEVICE_ID_NX2_5708) || |
9d82d8ea | 1994 | (dev->device == PCI_DEVICE_ID_NX2_5708S) || |
99cb233d BL |
1995 | ((dev->device == PCI_DEVICE_ID_NX2_5709) && |
1996 | (dev->revision & 0xf0) == 0x0)) { | |
1997 | if (dev->vpd) | |
1998 | dev->vpd->len = 0x80; | |
1999 | } | |
2000 | } | |
2001 | ||
bffadffd YZ |
2002 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2003 | PCI_DEVICE_ID_NX2_5706, | |
2004 | quirk_brcm_570x_limit_vpd); | |
2005 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2006 | PCI_DEVICE_ID_NX2_5706S, | |
2007 | quirk_brcm_570x_limit_vpd); | |
2008 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2009 | PCI_DEVICE_ID_NX2_5708, | |
2010 | quirk_brcm_570x_limit_vpd); | |
2011 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2012 | PCI_DEVICE_ID_NX2_5708S, | |
2013 | quirk_brcm_570x_limit_vpd); | |
2014 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2015 | PCI_DEVICE_ID_NX2_5709, | |
2016 | quirk_brcm_570x_limit_vpd); | |
2017 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2018 | PCI_DEVICE_ID_NX2_5709S, | |
2019 | quirk_brcm_570x_limit_vpd); | |
99cb233d | 2020 | |
26c56dc0 MM |
2021 | /* Originally in EDAC sources for i82875P: |
2022 | * Intel tells BIOS developers to hide device 6 which | |
2023 | * configures the overflow device access containing | |
2024 | * the DRBs - this is where we expose device 6. | |
2025 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm | |
2026 | */ | |
2027 | static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) | |
2028 | { | |
2029 | u8 reg; | |
2030 | ||
2031 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { | |
2032 | dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); | |
2033 | pci_write_config_byte(dev, 0xF4, reg | 0x02); | |
2034 | } | |
2035 | } | |
2036 | ||
2037 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, | |
2038 | quirk_unhide_mch_dev6); | |
2039 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, | |
2040 | quirk_unhide_mch_dev6); | |
2041 | ||
2042 | ||
3f79e107 | 2043 | #ifdef CONFIG_PCI_MSI |
ebdf7d39 TH |
2044 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
2045 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | |
2046 | * some other busses controlled by the chipset even if Linux is not | |
2047 | * aware of it. Instead of setting the flag on all busses in the | |
2048 | * machine, simply disable MSI globally. | |
3f79e107 | 2049 | */ |
ebdf7d39 | 2050 | static void __init quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 2051 | { |
88187dfa | 2052 | pci_no_msi(); |
f0fda801 | 2053 | dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); |
3f79e107 | 2054 | } |
ebdf7d39 TH |
2055 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2056 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
2057 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
66d715c9 | 2058 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f | 2059 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd3 | 2060 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
3f79e107 BG |
2061 | |
2062 | /* Disable MSI on chipsets that are known to not support it */ | |
2063 | static void __devinit quirk_disable_msi(struct pci_dev *dev) | |
2064 | { | |
2065 | if (dev->subordinate) { | |
f0fda801 | 2066 | dev_warn(&dev->dev, "MSI quirk detected; " |
2067 | "subordinate MSI disabled\n"); | |
3f79e107 BG |
2068 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2069 | } | |
2070 | } | |
2071 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
6397c75c BG |
2072 | |
2073 | /* Go through the list of Hypertransport capabilities and | |
2074 | * return 1 if a HT MSI capability is found and enabled */ | |
2075 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) | |
2076 | { | |
7a380507 ME |
2077 | int pos, ttl = 48; |
2078 | ||
2079 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2080 | while (pos && ttl--) { | |
2081 | u8 flags; | |
2082 | ||
2083 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2084 | &flags) == 0) | |
2085 | { | |
f0fda801 | 2086 | dev_info(&dev->dev, "Found %s HT MSI Mapping\n", |
7a380507 | 2087 | flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801 | 2088 | "enabled" : "disabled"); |
7a380507 | 2089 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75c | 2090 | } |
7a380507 ME |
2091 | |
2092 | pos = pci_find_next_ht_capability(dev, pos, | |
2093 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
2094 | } |
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ | |
2099 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) | |
2100 | { | |
2101 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
f0fda801 | 2102 | dev_warn(&dev->dev, "MSI quirk detected; " |
2103 | "subordinate MSI disabled\n"); | |
6397c75c BG |
2104 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2105 | } | |
2106 | } | |
2107 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
2108 | quirk_msi_ht_cap); | |
6bae1d96 | 2109 | |
6397c75c BG |
2110 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
2111 | * MSI are supported if the MSI capability set in any of these mappings. | |
2112 | */ | |
2113 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) | |
2114 | { | |
2115 | struct pci_dev *pdev; | |
2116 | ||
2117 | if (!dev->subordinate) | |
2118 | return; | |
2119 | ||
2120 | /* check HT MSI cap on this chipset and the root one. | |
2121 | * a single one having MSI is enough to be sure that MSI are supported. | |
2122 | */ | |
11f242f0 | 2123 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
2124 | if (!pdev) |
2125 | return; | |
0c875c28 | 2126 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
f0fda801 | 2127 | dev_warn(&dev->dev, "MSI quirk detected; " |
2128 | "subordinate MSI disabled\n"); | |
6397c75c BG |
2129 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2130 | } | |
11f242f0 | 2131 | pci_dev_put(pdev); |
6397c75c BG |
2132 | } |
2133 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2134 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 | 2135 | |
415b6d0e BH |
2136 | /* Force enable MSI mapping capability on HT bridges */ |
2137 | static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) | |
9dc625e7 PC |
2138 | { |
2139 | int pos, ttl = 48; | |
2140 | ||
2141 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2142 | while (pos && ttl--) { | |
2143 | u8 flags; | |
2144 | ||
2145 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2146 | &flags) == 0) { | |
2147 | dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); | |
2148 | ||
2149 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2150 | flags | HT_MSI_FLAGS_ENABLE); | |
2151 | } | |
2152 | pos = pci_find_next_ht_capability(dev, pos, | |
2153 | HT_CAPTYPE_MSI_MAPPING); | |
2154 | } | |
2155 | } | |
415b6d0e BH |
2156 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2157 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
2158 | ht_enable_msi_mapping); | |
9dc625e7 | 2159 | |
e0ae4f55 YL |
2160 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2161 | ht_enable_msi_mapping); | |
2162 | ||
75e07fc3 AP |
2163 | /* The P5N32-SLI Premium motherboard from Asus has a problem with msi |
2164 | * for the MCP55 NIC. It is not yet determined whether the msi problem | |
2165 | * also affects other devices. As for now, turn off msi for this device. | |
2166 | */ | |
2167 | static void __devinit nvenet_msi_disable(struct pci_dev *dev) | |
2168 | { | |
2169 | if (dmi_name_in_vendors("P5N32-SLI PREMIUM")) { | |
2170 | dev_info(&dev->dev, | |
2171 | "Disabling msi for MCP55 NIC on P5N32-SLI Premium\n"); | |
2172 | dev->no_msi = 1; | |
2173 | } | |
2174 | } | |
2175 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2176 | PCI_DEVICE_ID_NVIDIA_NVENET_15, | |
2177 | nvenet_msi_disable); | |
2178 | ||
de745306 YL |
2179 | static int __devinit ht_check_msi_mapping(struct pci_dev *dev) |
2180 | { | |
2181 | int pos, ttl = 48; | |
2182 | int found = 0; | |
2183 | ||
2184 | /* check if there is HT MSI cap or enabled on this device */ | |
2185 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2186 | while (pos && ttl--) { | |
2187 | u8 flags; | |
2188 | ||
2189 | if (found < 1) | |
2190 | found = 1; | |
2191 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2192 | &flags) == 0) { | |
2193 | if (flags & HT_MSI_FLAGS_ENABLE) { | |
2194 | if (found < 2) { | |
2195 | found = 2; | |
2196 | break; | |
2197 | } | |
2198 | } | |
2199 | } | |
2200 | pos = pci_find_next_ht_capability(dev, pos, | |
2201 | HT_CAPTYPE_MSI_MAPPING); | |
2202 | } | |
2203 | ||
2204 | return found; | |
2205 | } | |
2206 | ||
2207 | static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) | |
2208 | { | |
2209 | struct pci_dev *dev; | |
2210 | int pos; | |
2211 | int i, dev_no; | |
2212 | int found = 0; | |
2213 | ||
2214 | dev_no = host_bridge->devfn >> 3; | |
2215 | for (i = dev_no + 1; i < 0x20; i++) { | |
2216 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); | |
2217 | if (!dev) | |
2218 | continue; | |
2219 | ||
2220 | /* found next host bridge ?*/ | |
2221 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2222 | if (pos != 0) { | |
2223 | pci_dev_put(dev); | |
2224 | break; | |
2225 | } | |
2226 | ||
2227 | if (ht_check_msi_mapping(dev)) { | |
2228 | found = 1; | |
2229 | pci_dev_put(dev); | |
2230 | break; | |
2231 | } | |
2232 | pci_dev_put(dev); | |
2233 | } | |
2234 | ||
2235 | return found; | |
2236 | } | |
2237 | ||
eeafda70 YL |
2238 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2239 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ | |
2240 | ||
2241 | static int __devinit is_end_of_ht_chain(struct pci_dev *dev) | |
2242 | { | |
2243 | int pos, ctrl_off; | |
2244 | int end = 0; | |
2245 | u16 flags, ctrl; | |
2246 | ||
2247 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2248 | ||
2249 | if (!pos) | |
2250 | goto out; | |
2251 | ||
2252 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); | |
2253 | ||
2254 | ctrl_off = ((flags >> 10) & 1) ? | |
2255 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; | |
2256 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); | |
2257 | ||
2258 | if (ctrl & (1 << 6)) | |
2259 | end = 1; | |
2260 | ||
2261 | out: | |
2262 | return end; | |
2263 | } | |
2264 | ||
1dec6b05 | 2265 | static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 PC |
2266 | { |
2267 | struct pci_dev *host_bridge; | |
1dec6b05 YL |
2268 | int pos; |
2269 | int i, dev_no; | |
2270 | int found = 0; | |
2271 | ||
2272 | dev_no = dev->devfn >> 3; | |
2273 | for (i = dev_no; i >= 0; i--) { | |
2274 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); | |
2275 | if (!host_bridge) | |
2276 | continue; | |
2277 | ||
2278 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2279 | if (pos != 0) { | |
2280 | found = 1; | |
2281 | break; | |
2282 | } | |
2283 | pci_dev_put(host_bridge); | |
2284 | } | |
2285 | ||
2286 | if (!found) | |
2287 | return; | |
2288 | ||
eeafda70 YL |
2289 | /* don't enable end_device/host_bridge with leaf directly here */ |
2290 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && | |
2291 | host_bridge_with_leaf(host_bridge)) | |
de745306 YL |
2292 | goto out; |
2293 | ||
1dec6b05 YL |
2294 | /* root did that ! */ |
2295 | if (msi_ht_cap_enabled(host_bridge)) | |
2296 | goto out; | |
2297 | ||
2298 | ht_enable_msi_mapping(dev); | |
2299 | ||
2300 | out: | |
2301 | pci_dev_put(host_bridge); | |
2302 | } | |
2303 | ||
2304 | static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) | |
2305 | { | |
2306 | int pos, ttl = 48; | |
2307 | ||
2308 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2309 | while (pos && ttl--) { | |
2310 | u8 flags; | |
2311 | ||
2312 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2313 | &flags) == 0) { | |
6a958d5b | 2314 | dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); |
1dec6b05 YL |
2315 | |
2316 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2317 | flags & ~HT_MSI_FLAGS_ENABLE); | |
2318 | } | |
2319 | pos = pci_find_next_ht_capability(dev, pos, | |
2320 | HT_CAPTYPE_MSI_MAPPING); | |
2321 | } | |
2322 | } | |
2323 | ||
de745306 | 2324 | static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b05 YL |
2325 | { |
2326 | struct pci_dev *host_bridge; | |
2327 | int pos; | |
2328 | int found; | |
2329 | ||
2330 | /* check if there is HT MSI cap or enabled on this device */ | |
2331 | found = ht_check_msi_mapping(dev); | |
2332 | ||
2333 | /* no HT MSI CAP */ | |
2334 | if (found == 0) | |
2335 | return; | |
9dc625e7 PC |
2336 | |
2337 | /* | |
2338 | * HT MSI mapping should be disabled on devices that are below | |
2339 | * a non-Hypertransport host bridge. Locate the host bridge... | |
2340 | */ | |
2341 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
2342 | if (host_bridge == NULL) { | |
2343 | dev_warn(&dev->dev, | |
2344 | "nv_msi_ht_cap_quirk didn't locate host bridge\n"); | |
2345 | return; | |
2346 | } | |
2347 | ||
2348 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2349 | if (pos != 0) { | |
2350 | /* Host bridge is to HT */ | |
1dec6b05 YL |
2351 | if (found == 1) { |
2352 | /* it is not enabled, try to enable it */ | |
de745306 YL |
2353 | if (all) |
2354 | ht_enable_msi_mapping(dev); | |
2355 | else | |
2356 | nv_ht_enable_msi_mapping(dev); | |
1dec6b05 | 2357 | } |
9dc625e7 PC |
2358 | return; |
2359 | } | |
2360 | ||
1dec6b05 YL |
2361 | /* HT MSI is not enabled */ |
2362 | if (found == 1) | |
2363 | return; | |
9dc625e7 | 2364 | |
1dec6b05 YL |
2365 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
2366 | ht_disable_msi_mapping(dev); | |
9dc625e7 | 2367 | } |
de745306 YL |
2368 | |
2369 | static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) | |
2370 | { | |
2371 | return __nv_msi_ht_cap_quirk(dev, 1); | |
2372 | } | |
2373 | ||
2374 | static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) | |
2375 | { | |
2376 | return __nv_msi_ht_cap_quirk(dev, 0); | |
2377 | } | |
2378 | ||
2379 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); | |
2380 | ||
2381 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); | |
9dc625e7 | 2382 | |
ba698ad4 DM |
2383 | static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) |
2384 | { | |
2385 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2386 | } | |
4600c9d7 SH |
2387 | static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
2388 | { | |
2389 | struct pci_dev *p; | |
2390 | ||
2391 | /* SB700 MSI issue will be fixed at HW level from revision A21, | |
2392 | * we need check PCI REVISION ID of SMBus controller to get SB700 | |
2393 | * revision. | |
2394 | */ | |
2395 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2396 | NULL); | |
2397 | if (!p) | |
2398 | return; | |
2399 | ||
2400 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) | |
2401 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2402 | pci_dev_put(p); | |
2403 | } | |
ba698ad4 DM |
2404 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2405 | PCI_DEVICE_ID_TIGON3_5780, | |
2406 | quirk_msi_intx_disable_bug); | |
2407 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2408 | PCI_DEVICE_ID_TIGON3_5780S, | |
2409 | quirk_msi_intx_disable_bug); | |
2410 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2411 | PCI_DEVICE_ID_TIGON3_5714, | |
2412 | quirk_msi_intx_disable_bug); | |
2413 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2414 | PCI_DEVICE_ID_TIGON3_5714S, | |
2415 | quirk_msi_intx_disable_bug); | |
2416 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2417 | PCI_DEVICE_ID_TIGON3_5715, | |
2418 | quirk_msi_intx_disable_bug); | |
2419 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2420 | PCI_DEVICE_ID_TIGON3_5715S, | |
2421 | quirk_msi_intx_disable_bug); | |
2422 | ||
bc38b411 | 2423 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d7 | 2424 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2425 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d7 | 2426 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2427 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d7 | 2428 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2429 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d7 | 2430 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2431 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d7 | 2432 | quirk_msi_intx_disable_ati_bug); |
bc38b411 DM |
2433 | |
2434 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
2435 | quirk_msi_intx_disable_bug); | |
2436 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
2437 | quirk_msi_intx_disable_bug); | |
2438 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
2439 | quirk_msi_intx_disable_bug); | |
2440 | ||
3f79e107 | 2441 | #endif /* CONFIG_PCI_MSI */ |
3d137310 | 2442 | |
7eb93b17 YZ |
2443 | #ifdef CONFIG_PCI_IOV |
2444 | ||
2445 | /* | |
2446 | * For Intel 82576 SR-IOV NIC, if BIOS doesn't allocate resources for the | |
2447 | * SR-IOV BARs, zero the Flash BAR and program the SR-IOV BARs to use the | |
2448 | * old Flash Memory Space. | |
2449 | */ | |
2450 | static void __devinit quirk_i82576_sriov(struct pci_dev *dev) | |
2451 | { | |
2452 | int pos, flags; | |
2453 | u32 bar, start, size; | |
2454 | ||
2455 | if (PAGE_SIZE > 0x10000) | |
2456 | return; | |
2457 | ||
2458 | flags = pci_resource_flags(dev, 0); | |
2459 | if ((flags & PCI_BASE_ADDRESS_SPACE) != | |
2460 | PCI_BASE_ADDRESS_SPACE_MEMORY || | |
2461 | (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != | |
2462 | PCI_BASE_ADDRESS_MEM_TYPE_32) | |
2463 | return; | |
2464 | ||
2465 | pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV); | |
2466 | if (!pos) | |
2467 | return; | |
2468 | ||
2469 | pci_read_config_dword(dev, pos + PCI_SRIOV_BAR, &bar); | |
2470 | if (bar & PCI_BASE_ADDRESS_MEM_MASK) | |
2471 | return; | |
2472 | ||
2473 | start = pci_resource_start(dev, 1); | |
2474 | size = pci_resource_len(dev, 1); | |
2475 | if (!start || size != 0x400000 || start & (size - 1)) | |
2476 | return; | |
2477 | ||
2478 | pci_resource_flags(dev, 1) = 0; | |
2479 | pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); | |
2480 | pci_write_config_dword(dev, pos + PCI_SRIOV_BAR, start); | |
2481 | pci_write_config_dword(dev, pos + PCI_SRIOV_BAR + 12, start + size / 2); | |
2482 | ||
2483 | dev_info(&dev->dev, "use Flash Memory Space for SR-IOV BARs\n"); | |
2484 | } | |
2485 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c9, quirk_i82576_sriov); | |
2486 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e6, quirk_i82576_sriov); | |
2487 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e7, quirk_i82576_sriov); | |
dcb4ea2e AD |
2488 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e8, quirk_i82576_sriov); |
2489 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x150a, quirk_i82576_sriov); | |
7eb93b17 YZ |
2490 | |
2491 | #endif /* CONFIG_PCI_IOV */ | |
2492 | ||
bfb0f330 JB |
2493 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, |
2494 | struct pci_fixup *end) | |
3d137310 TP |
2495 | { |
2496 | while (f < end) { | |
2497 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && | |
bfb0f330 | 2498 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
c9bbb4ab | 2499 | dev_dbg(&dev->dev, "calling %pF\n", f->hook); |
3d137310 TP |
2500 | f->hook(dev); |
2501 | } | |
2502 | f++; | |
2503 | } | |
2504 | } | |
2505 | ||
2506 | extern struct pci_fixup __start_pci_fixups_early[]; | |
2507 | extern struct pci_fixup __end_pci_fixups_early[]; | |
2508 | extern struct pci_fixup __start_pci_fixups_header[]; | |
2509 | extern struct pci_fixup __end_pci_fixups_header[]; | |
2510 | extern struct pci_fixup __start_pci_fixups_final[]; | |
2511 | extern struct pci_fixup __end_pci_fixups_final[]; | |
2512 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
2513 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
2514 | extern struct pci_fixup __start_pci_fixups_resume[]; | |
2515 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
2516 | extern struct pci_fixup __start_pci_fixups_resume_early[]; | |
2517 | extern struct pci_fixup __end_pci_fixups_resume_early[]; | |
2518 | extern struct pci_fixup __start_pci_fixups_suspend[]; | |
2519 | extern struct pci_fixup __end_pci_fixups_suspend[]; | |
2520 | ||
2521 | ||
2522 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
2523 | { | |
2524 | struct pci_fixup *start, *end; | |
2525 | ||
2526 | switch(pass) { | |
2527 | case pci_fixup_early: | |
2528 | start = __start_pci_fixups_early; | |
2529 | end = __end_pci_fixups_early; | |
2530 | break; | |
2531 | ||
2532 | case pci_fixup_header: | |
2533 | start = __start_pci_fixups_header; | |
2534 | end = __end_pci_fixups_header; | |
2535 | break; | |
2536 | ||
2537 | case pci_fixup_final: | |
2538 | start = __start_pci_fixups_final; | |
2539 | end = __end_pci_fixups_final; | |
2540 | break; | |
2541 | ||
2542 | case pci_fixup_enable: | |
2543 | start = __start_pci_fixups_enable; | |
2544 | end = __end_pci_fixups_enable; | |
2545 | break; | |
2546 | ||
2547 | case pci_fixup_resume: | |
2548 | start = __start_pci_fixups_resume; | |
2549 | end = __end_pci_fixups_resume; | |
2550 | break; | |
2551 | ||
2552 | case pci_fixup_resume_early: | |
2553 | start = __start_pci_fixups_resume_early; | |
2554 | end = __end_pci_fixups_resume_early; | |
2555 | break; | |
2556 | ||
2557 | case pci_fixup_suspend: | |
2558 | start = __start_pci_fixups_suspend; | |
2559 | end = __end_pci_fixups_suspend; | |
2560 | break; | |
2561 | ||
2562 | default: | |
2563 | /* stupid compiler warning, you would think with an enum... */ | |
2564 | return; | |
2565 | } | |
2566 | pci_do_fixups(dev, start, end); | |
2567 | } | |
2568 | #else | |
2569 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) {} | |
2570 | #endif | |
2571 | EXPORT_SYMBOL(pci_fixup_device); |