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PCIe: fix 'symbol not declared' sparse warnings
[deliverable/linux.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
1da177e4
LT		 18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/delay.h>
25be5e6c 23#include <linux/acpi.h>
9f23ed3b 24#include <linux/kallsyms.h>
bc56b9e0 25#include "pci.h"
1da177e4 26
bd8481e1
DT		 27/* The Mellanox Tavor device gives false positive parity errors
28 * Mark this device with a broken_parity_status, to allow
29 * PCI scanning code to "skip" this now blacklisted device.
30 */
31static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
32{
33 dev->broken_parity_status = 1; /* This device gives false positives */
34}
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
36DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
37
1da177e4
LT		 38/* Deal with broken BIOS'es that neglect to enable passive release,
39 which can cause problems in combination with the 82441FX/PPro MTRRs */
1597cacb 40static void quirk_passive_release(struct pci_dev *dev)
1da177e4
LT		 41{
42 struct pci_dev *d = NULL;
43 unsigned char dlc;
44
45 /* We have to make sure a particular bit is set in the PIIX3
46 ISA bridge, so we have to go out and find it. */
47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
48 pci_read_config_byte(d, 0x82, &dlc);
49 if (!(dlc & 1<<1)) {
f0fda801 50 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
1da177e4
LT		 51 dlc |= 1<<1;
52 pci_write_config_byte(d, 0x82, dlc);
53 }
54 }
55}
652c538e
AM		 56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
57DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
1da177e4
LT		 58
59/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
60 but VIA don't answer queries. If you happen to have good contacts at VIA
61 ask them for me please -- Alan
62
63 This appears to be BIOS not version dependent. So presumably there is a
64 chipset level fix */
c30ca1db
AB		 65int isa_dma_bridge_buggy;
66EXPORT_SYMBOL(isa_dma_bridge_buggy);
1da177e4
LT		 67
68static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
69{
70 if (!isa_dma_bridge_buggy) {
71 isa_dma_bridge_buggy=1;
f0fda801 72 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
1da177e4
LT		 73 }
74}
75 /*
76 * Its not totally clear which chipsets are the problematic ones
77 * We know 82C586 and 82C596 variants are affected.
78 */
652c538e
AM		 79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
85DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
1da177e4
LT		 86
87int pci_pci_problems;
c30ca1db 88EXPORT_SYMBOL(pci_pci_problems);
1da177e4
LT		 89
90/*
91 * Chipsets where PCI->PCI transfers vanish or hang
92 */
93static void __devinit quirk_nopcipci(struct pci_dev *dev)
94{
95 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
f0fda801 96 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
1da177e4
LT		 97 pci_pci_problems |= PCIPCI_FAIL;
98 }
99}
652c538e
AM		 100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
236561e5
AC		 102
103static void __devinit quirk_nopciamd(struct pci_dev *dev)
104{
105 u8 rev;
106 pci_read_config_byte(dev, 0x08, &rev);
107 if (rev == 0x13) {
108 /* Erratum 24 */
f0fda801 109 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
236561e5
AC		 110 pci_pci_problems |= PCIAGP_FAIL;
111 }
112}
652c538e 113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
1da177e4
LT		 114
115/*
116 * Triton requires workarounds to be used by the drivers
117 */
118static void __devinit quirk_triton(struct pci_dev *dev)
119{
120 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
f0fda801 121 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 122 pci_pci_problems |= PCIPCI_TRITON;
123 }
124}
652c538e
AM		 125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
1da177e4
LT		 129
130/*
131 * VIA Apollo KT133 needs PCI latency patch
132 * Made according to a windows driver based patch by George E. Breese
133 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
134 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
135 * the info on which Mr Breese based his work.
136 *
137 * Updated based on further information from the site and also on
138 * information provided by VIA
139 */
1597cacb 140static void quirk_vialatency(struct pci_dev *dev)
1da177e4
LT		 141{
142 struct pci_dev *p;
1da177e4
LT		 143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */
146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) {
1da177e4
LT		 149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
150 /* Check for buggy part revisions */
2b1afa87 151 if (p->revision < 0x40 || p->revision > 0x42)
1da177e4
LT		 152 goto exit;
153 } else {
154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
155 if (p==NULL) /* No problem parts */
156 goto exit;
1da177e4 157 /* Check for buggy part revisions */
2b1afa87 158 if (p->revision < 0x10 || p->revision > 0x12)
1da177e4
LT		 159 goto exit;
160 }
161
162 /*
163 * Ok we have the problem. Now set the PCI master grant to
164 * occur every master grant. The apparent bug is that under high
165 * PCI load (quite common in Linux of course) you can get data
166 * loss when the CPU is held off the bus for 3 bus master requests
167 * This happens to include the IDE controllers....
168 *
169 * VIA only apply this fix when an SB Live! is present but under
170 * both Linux and Windows this isnt enough, and we have seen
171 * corruption without SB Live! but with things like 3 UDMA IDE
172 * controllers. So we ignore that bit of the VIA recommendation..
173 */
174
175 pci_read_config_byte(dev, 0x76, &busarb);
176 /* Set bit 4 and bi 5 of byte 76 to 0x01
177 "Master priority rotation on every PCI master grant */
178 busarb &= ~(1<<5);
179 busarb |= (1<<4);
180 pci_write_config_byte(dev, 0x76, busarb);
f0fda801 181 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
1da177e4
LT		 182exit:
183 pci_dev_put(p);
184}
652c538e
AM		 185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1597cacb 188/* Must restore this on a resume from RAM */
652c538e
AM		 189DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
190DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
1da177e4
LT		 192
193/*
194 * VIA Apollo VP3 needs ETBF on BT848/878
195 */
196static void __devinit quirk_viaetbf(struct pci_dev *dev)
197{
198 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
f0fda801 199 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 200 pci_pci_problems |= PCIPCI_VIAETBF;
201 }
202}
652c538e 203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
1da177e4
LT		 204
205static void __devinit quirk_vsfx(struct pci_dev *dev)
206{
207 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
f0fda801 208 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 209 pci_pci_problems |= PCIPCI_VSFX;
210 }
211}
652c538e 212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
1da177e4
LT		 213
214/*
215 * Ali Magik requires workarounds to be used by the drivers
216 * that DMA to AGP space. Latency must be set to 0xA and triton
217 * workaround applied too
218 * [Info kindly provided by ALi]
219 */
220static void __init quirk_alimagik(struct pci_dev *dev)
221{
222 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
f0fda801 223 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 224 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
225 }
226}
652c538e
AM		 227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
1da177e4
LT		 229
230/*
231 * Natoma has some interesting boundary conditions with Zoran stuff
232 * at least
233 */
234static void __devinit quirk_natoma(struct pci_dev *dev)
235{
236 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
f0fda801 237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
1da177e4
LT		 238 pci_pci_problems |= PCIPCI_NATOMA;
239 }
240}
652c538e
AM		 241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
1da177e4
LT		 247
248/*
249 * This chip can cause PCI parity errors if config register 0xA0 is read
250 * while DMAs are occurring.
251 */
252static void __devinit quirk_citrine(struct pci_dev *dev)
253{
254 dev->cfg_size = 0xA0;
255}
652c538e 256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
1da177e4
LT		 257
258/*
259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
260 * If it's needed, re-allocate the region.
261 */
262static void __devinit quirk_s3_64M(struct pci_dev *dev)
263{
264 struct resource *r = &dev->resource[0];
265
266 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
267 r->start = 0;
268 r->end = 0x3ffffff;
269 }
270}
652c538e
AM		 271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
1da177e4 273
6693e74a
LT		 274static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
275 unsigned size, int nr, const char *name)
1da177e4
LT		 276{
277 region &= ~(size-1);
278 if (region) {
085ae41f 279 struct pci_bus_region bus_region;
1da177e4
LT		 280 struct resource *res = dev->resource + nr;
281
282 res->name = pci_name(dev);
283 res->start = region;
284 res->end = region + size - 1;
285 res->flags = IORESOURCE_IO;
085ae41f
DM		 286
287 /* Convert from PCI bus to resource space. */
288 bus_region.start = res->start;
289 bus_region.end = res->end;
290 pcibios_bus_to_resource(dev, res, &bus_region);
291
1da177e4 292 pci_claim_resource(dev, nr);
f0fda801 293 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 294 }
295}
296
297/*
298 * ATI Northbridge setups MCE the processor if you even
299 * read somewhere between 0x3b0->0x3bb or read 0x3d3
300 */
301static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
302{
f0fda801 303 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
1da177e4
LT		 304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
305 request_region(0x3b0, 0x0C, "RadeonIGP");
306 request_region(0x3d3, 0x01, "RadeonIGP");
307}
652c538e 308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
1da177e4
LT		 309
310/*
311 * Let's make the southbridge information explicit instead
312 * of having to worry about people probing the ACPI areas,
313 * for example.. (Yes, it happens, and if you read the wrong
314 * ACPI register it will put the machine to sleep with no
315 * way of waking it up again. Bummer).
316 *
317 * ALI M7101: Two IO regions pointed to by words at
318 * 0xE0 (64 bytes of ACPI registers)
319 * 0xE2 (32 bytes of SMB registers)
320 */
321static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
322{
323 u16 region;
324
325 pci_read_config_word(dev, 0xE0, &region);
6693e74a 326 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 327 pci_read_config_word(dev, 0xE2, &region);
6693e74a 328 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4 329}
652c538e 330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
1da177e4 331
6693e74a
LT		 332static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
333{
334 u32 devres;
335 u32 mask, size, base;
336
337 pci_read_config_dword(dev, port, &devres);
338 if ((devres & enable) != enable)
339 return;
340 mask = (devres >> 16) & 15;
341 base = devres & 0xffff;
342 size = 16;
343 for (;;) {
344 unsigned bit = size >> 1;
345 if ((bit & mask) == bit)
346 break;
347 size = bit;
348 }
349 /*
350 * For now we only print it out. Eventually we'll want to
351 * reserve it (at least if it's in the 0x1000+ range), but
352 * let's get enough confirmation reports first.
353 */
354 base &= -size;
f0fda801 355 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 356}
357
358static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
359{
360 u32 devres;
361 u32 mask, size, base;
362
363 pci_read_config_dword(dev, port, &devres);
364 if ((devres & enable) != enable)
365 return;
366 base = devres & 0xffff0000;
367 mask = (devres & 0x3f) << 16;
368 size = 128 << 16;
369 for (;;) {
370 unsigned bit = size >> 1;
371 if ((bit & mask) == bit)
372 break;
373 size = bit;
374 }
375 /*
376 * For now we only print it out. Eventually we'll want to
377 * reserve it, but let's get enough confirmation reports first.
378 */
379 base &= -size;
f0fda801 380 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
6693e74a
LT		 381}
382
1da177e4
LT		 383/*
384 * PIIX4 ACPI: Two IO regions pointed to by longwords at
385 * 0x40 (64 bytes of ACPI registers)
08db2a70 386 * 0x90 (16 bytes of SMB registers)
6693e74a 387 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 388 */
389static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
390{
6693e74a 391 u32 region, res_a;
1da177e4
LT		 392
393 pci_read_config_dword(dev, 0x40, &region);
6693e74a 394 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 395 pci_read_config_dword(dev, 0x90, &region);
08db2a70 396 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 397
398 /* Device resource A has enables for some of the other ones */
399 pci_read_config_dword(dev, 0x5c, &res_a);
400
401 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
402 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
403
404 /* Device resource D is just bitfields for static resources */
405
406 /* Device 12 enabled? */
407 if (res_a & (1 << 29)) {
408 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
409 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
410 }
411 /* Device 13 enabled? */
412 if (res_a & (1 << 30)) {
413 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
414 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
415 }
416 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
417 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4 418}
652c538e
AM		 419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
1da177e4
LT		 421
422/*
423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
424 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
425 * 0x58 (64 bytes of GPIO I/O space)
426 */
427static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
428{
429 u32 region;
430
431 pci_read_config_dword(dev, 0x40, &region);
6693e74a 432 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 433
434 pci_read_config_dword(dev, 0x58, &region);
6693e74a 435 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4 436}
652c538e
AM		 437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
1da177e4 447
2cea752f
M		 448static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
449{
450 u32 region;
451
452 pci_read_config_dword(dev, 0x40, &region);
453 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
454
455 pci_read_config_dword(dev, 0x48, &region);
456 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
457}
652c538e
AM		 458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
2cea752f 472
1da177e4
LT		 473/*
474 * VIA ACPI: One IO region pointed to by longword at
475 * 0x48 or 0x20 (256 bytes of ACPI registers)
476 */
477static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
478{
1da177e4
LT		 479 u32 region;
480
651472fb 481 if (dev->revision & 0x10) {
1da177e4
LT		 482 pci_read_config_dword(dev, 0x48, &region);
483 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 484 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 485 }
486}
652c538e 487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
1da177e4
LT		 488
489/*
490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
491 * 0x48 (256 bytes of ACPI registers)
492 * 0x70 (128 bytes of hardware monitoring register)
493 * 0x90 (16 bytes of SMB registers)
494 */
495static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
496{
497 u16 hm;
498 u32 smb;
499
500 quirk_vt82c586_acpi(dev);
501
502 pci_read_config_word(dev, 0x70, &hm);
503 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 504 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 505
506 pci_read_config_dword(dev, 0x90, &smb);
507 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 508 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4 509}
652c538e 510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
1da177e4 511
6d85f29b
IK		 512/*
513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
514 * 0x88 (128 bytes of power management registers)
515 * 0xd0 (16 bytes of SMB registers)
516 */
517static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
518{
519 u16 pm, smb;
520
521 pci_read_config_word(dev, 0x88, &pm);
522 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 523 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 524
525 pci_read_config_word(dev, 0xd0, &smb);
526 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 527 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 528}
529DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
530
1da177e4
LT		 531
532#ifdef CONFIG_X86_IO_APIC
533
534#include <asm/io_apic.h>
535
536/*
537 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
538 * devices to the external APIC.
539 *
540 * TODO: When we have device-specific interrupt routers,
541 * this code will go away from quirks.
542 */
1597cacb 543static void quirk_via_ioapic(struct pci_dev *dev)
1da177e4
LT		 544{
545 u8 tmp;
546
547 if (nr_ioapics < 1)
548 tmp = 0; /* nothing routed to external APIC */
549 else
550 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
551
f0fda801 552 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
1da177e4
LT		 553 tmp == 0 ? "Disa" : "Ena");
554
555 /* Offset 0x58: External APIC IRQ output control */
556 pci_write_config_byte (dev, 0x58, tmp);
557}
652c538e 558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
e1a2a51e 559DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
1da177e4 560
a1740913
KW		 561/*
562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
563 * This leads to doubled level interrupt rates.
564 * Set this bit to get rid of cycle wastage.
565 * Otherwise uncritical.
566 */
1597cacb 567static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
a1740913
KW		 568{
569 u8 misc_control2;
570#define BYPASS_APIC_DEASSERT 8
571
572 pci_read_config_byte(dev, 0x5B, &misc_control2);
573 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
f0fda801 574 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
a1740913
KW		 575 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
576 }
577}
578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
e1a2a51e 579DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
a1740913 580
1da177e4
LT		 581/*
582 * The AMD io apic can hang the box when an apic irq is masked.
583 * We check all revs >= B0 (yet not in the pre production!) as the bug
584 * is currently marked NoFix
585 *
586 * We have multiple reports of hangs with this chipset that went away with
236561e5 587 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1da177e4
LT		 588 * of course. However the advice is demonstrably good even if so..
589 */
590static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
591{
44c10138 592 if (dev->revision >= 0x02) {
f0fda801 593 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
594 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
1da177e4
LT		 595 }
596}
652c538e 597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1da177e4
LT		 598
599static void __init quirk_ioapic_rmw(struct pci_dev *dev)
600{
601 if (dev->devfn == 0 && dev->bus->number == 0)
602 sis_apic_bug = 1;
603}
652c538e 604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
1da177e4 605
1da177e4
LT		 606#define AMD8131_revA0 0x01
607#define AMD8131_revB0 0x11
608#define AMD8131_MISC 0x40
609#define AMD8131_NIOAMODE_BIT 0
1597cacb 610static void quirk_amd_8131_ioapic(struct pci_dev *dev)
1da177e4 611{
44c10138 612 unsigned char tmp;
1da177e4 613
1da177e4
LT		 614 if (nr_ioapics == 0)
615 return;
616
44c10138 617 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
f0fda801 618 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
1da177e4
LT		 619 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
620 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
621 pci_write_config_byte( dev, AMD8131_MISC, tmp);
622 }
623}
5da594b1 624DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
e1a2a51e 625DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4
LT		 626#endif /* CONFIG_X86_IO_APIC */
627
d556ad4b
PO		 628/*
629 * Some settings of MMRBC can lead to data corruption so block changes.
630 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
631 */
632static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
633{
aa288d4d 634 if (dev->subordinate && dev->revision <= 0x12) {
f0fda801 635 dev_info(&dev->dev, "AMD8131 rev %x detected; "
636 "disabling PCI-X MMRBC\n", dev->revision);
d556ad4b
PO		 637 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
638 }
639}
640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1da177e4 641
1da177e4
LT		 642/*
643 * FIXME: it is questionable that quirk_via_acpi
644 * is needed. It shows up as an ISA bridge, and does not
645 * support the PCI_INTERRUPT_LINE register at all. Therefore
646 * it seems like setting the pci_dev's 'irq' to the
647 * value of the ACPI SCI interrupt is only done for convenience.
648 * -jgarzik
649 */
650static void __devinit quirk_via_acpi(struct pci_dev *d)
651{
652 /*
653 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
654 */
655 u8 irq;
656 pci_read_config_byte(d, 0x42, &irq);
657 irq &= 0xf;
658 if (irq && (irq != 2))
659 d->irq = irq;
660}
652c538e
AM		 661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
662DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1da177e4 663
09d6029f
DD		 664
665/*
1597cacb 666 * VIA bridges which have VLink
09d6029f 667 */
1597cacb 668
c06bb5d4
JD		 669static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
670
671static void quirk_via_bridge(struct pci_dev *dev)
672{
673 /* See what bridge we have and find the device ranges */
674 switch (dev->device) {
675 case PCI_DEVICE_ID_VIA_82C686:
cb7468ef
JD		 676 /* The VT82C686 is special, it attaches to PCI and can have
677 any device number. All its subdevices are functions of
678 that single device. */
679 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
680 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
c06bb5d4
JD		 681 break;
682 case PCI_DEVICE_ID_VIA_8237:
683 case PCI_DEVICE_ID_VIA_8237A:
684 via_vlink_dev_lo = 15;
685 break;
686 case PCI_DEVICE_ID_VIA_8235:
687 via_vlink_dev_lo = 16;
688 break;
689 case PCI_DEVICE_ID_VIA_8231:
690 case PCI_DEVICE_ID_VIA_8233_0:
691 case PCI_DEVICE_ID_VIA_8233A:
692 case PCI_DEVICE_ID_VIA_8233C_0:
693 via_vlink_dev_lo = 17;
694 break;
695 }
696}
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
09d6029f 705
1597cacb
AC		 706/**
707 * quirk_via_vlink - VIA VLink IRQ number update
708 * @dev: PCI device
709 *
710 * If the device we are dealing with is on a PIC IRQ we need to
711 * ensure that the IRQ line register which usually is not relevant
712 * for PCI cards, is actually written so that interrupts get sent
c06bb5d4
JD		 713 * to the right place.
714 * We only do this on systems where a VIA south bridge was detected,
715 * and only for VIA devices on the motherboard (see quirk_via_bridge
716 * above).
1597cacb
AC		 717 */
718
719static void quirk_via_vlink(struct pci_dev *dev)
25be5e6c
LB		 720{
721 u8 irq, new_irq;
722
c06bb5d4
JD		 723 /* Check if we have VLink at all */
724 if (via_vlink_dev_lo == -1)
09d6029f
DD		 725 return;
726
727 new_irq = dev->irq;
728
729 /* Don't quirk interrupts outside the legacy IRQ range */
730 if (!new_irq || new_irq > 15)
731 return;
732
1597cacb 733 /* Internal device ? */
c06bb5d4
JD		 734 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
735 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1597cacb
AC		 736 return;
737
738 /* This is an internal VLink device on a PIC interrupt. The BIOS
739 ought to have set this but may not have, so we redo it */
740
25be5e6c
LB		 741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
742 if (new_irq != irq) {
f0fda801 743 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
744 irq, new_irq);
25be5e6c
LB		 745 udelay(15); /* unknown if delay really needed */
746 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
747 }
748}
1597cacb 749DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
25be5e6c 750
1da177e4
LT		 751/*
752 * VIA VT82C598 has its device ID settable and many BIOSes
753 * set it to the ID of VT82C597 for backward compatibility.
754 * We need to switch it off to be able to recognize the real
755 * type of the chip.
756 */
757static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
758{
759 pci_write_config_byte(dev, 0xfc, 0);
760 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
761}
652c538e 762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1da177e4
LT		 763
764/*
765 * CardBus controllers have a legacy base address that enables them
766 * to respond as i82365 pcmcia controllers. We don't want them to
767 * do this even if the Linux CardBus driver is not loaded, because
768 * the Linux i82365 driver does not (and should not) handle CardBus.
769 */
1597cacb 770static void quirk_cardbus_legacy(struct pci_dev *dev)
1da177e4
LT		 771{
772 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
773 return;
774 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
775}
776DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
e1a2a51e 777DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
1da177e4
LT		 778
779/*
780 * Following the PCI ordering rules is optional on the AMD762. I'm not
781 * sure what the designers were smoking but let's not inhale...
782 *
783 * To be fair to AMD, it follows the spec by default, its BIOS people
784 * who turn it off!
785 */
1597cacb 786static void quirk_amd_ordering(struct pci_dev *dev)
1da177e4
LT		 787{
788 u32 pcic;
789 pci_read_config_dword(dev, 0x4C, &pcic);
790 if ((pcic&6)!=6) {
791 pcic |= 6;
f0fda801 792 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1da177e4
LT		 793 pci_write_config_dword(dev, 0x4C, pcic);
794 pci_read_config_dword(dev, 0x84, &pcic);
795 pcic |= (1<<23); /* Required in this mode */
796 pci_write_config_dword(dev, 0x84, pcic);
797 }
798}
652c538e 799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
e1a2a51e 800DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1da177e4
LT		 801
802/*
803 * DreamWorks provided workaround for Dunord I-3000 problem
804 *
805 * This card decodes and responds to addresses not apparently
806 * assigned to it. We force a larger allocation to ensure that
807 * nothing gets put too close to it.
808 */
809static void __devinit quirk_dunord ( struct pci_dev * dev )
810{
811 struct resource *r = &dev->resource [1];
812 r->start = 0;
813 r->end = 0xffffff;
814}
652c538e 815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1da177e4
LT		 816
817/*
818 * i82380FB mobile docking controller: its PCI-to-PCI bridge
819 * is subtractive decoding (transparent), and does indicate this
820 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
821 * instead of 0x01.
822 */
823static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
824{
825 dev->transparent = 1;
826}
652c538e
AM		 827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1da177e4
LT		 829
830/*
831 * Common misconfiguration of the MediaGX/Geode PCI master that will
832 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
833 * datasheets found at http://www.national.com/ds/GX for info on what
834 * these bits do. <christer@weinigel.se>
835 */
1597cacb 836static void quirk_mediagx_master(struct pci_dev *dev)
1da177e4
LT		 837{
838 u8 reg;
839 pci_read_config_byte(dev, 0x41, &reg);
840 if (reg & 2) {
841 reg &= ~2;
f0fda801 842 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
1da177e4
LT		 843 pci_write_config_byte(dev, 0x41, reg);
844 }
845}
652c538e
AM		 846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
847DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1da177e4 848
1da177e4
LT		 849/*
850 * Ensure C0 rev restreaming is off. This is normally done by
851 * the BIOS but in the odd case it is not the results are corruption
852 * hence the presence of a Linux check
853 */
1597cacb 854static void quirk_disable_pxb(struct pci_dev *pdev)
1da177e4
LT		 855{
856 u16 config;
1da177e4 857
44c10138 858 if (pdev->revision != 0x04) /* Only C0 requires this */
1da177e4
LT		 859 return;
860 pci_read_config_word(pdev, 0x40, &config);
861 if (config & (1<<6)) {
862 config &= ~(1<<6);
863 pci_write_config_word(pdev, 0x40, config);
f0fda801 864 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1da177e4
LT		 865 }
866}
652c538e 867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
e1a2a51e 868DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1da177e4 869
05a7d22b 870static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
ab17443a 871{
05a7d22b
CC		 872 /* set sb600/sb700/sb800 sata to ahci mode */
873 u8 tmp;
ab17443a 874
05a7d22b
CC		 875 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
876 if (tmp == 0x01) {
ab17443a
CH		 877 pci_read_config_byte(pdev, 0x40, &tmp);
878 pci_write_config_byte(pdev, 0x40, tmp|1);
879 pci_write_config_byte(pdev, 0x9, 1);
880 pci_write_config_byte(pdev, 0xa, 6);
881 pci_write_config_byte(pdev, 0x40, tmp);
882
c9f89475 883 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
05a7d22b 884 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
ab17443a
CH		 885 }
886}
05a7d22b 887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
e1a2a51e 888DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
05a7d22b 889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
e1a2a51e 890DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
ab17443a 891
1da177e4
LT		 892/*
893 * Serverworks CSB5 IDE does not fully support native mode
894 */
895static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
896{
897 u8 prog;
898 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
899 if (prog & 5) {
900 prog &= ~5;
901 pdev->class &= ~5;
902 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
368c73d4 903 /* PCI layer will sort out resources */
1da177e4
LT		 904 }
905}
652c538e 906DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1da177e4
LT		 907
908/*
909 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
910 */
911static void __init quirk_ide_samemode(struct pci_dev *pdev)
912{
913 u8 prog;
914
915 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
916
917 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
f0fda801 918 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1da177e4
LT		 919 prog &= ~5;
920 pdev->class &= ~5;
921 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1da177e4
LT		 922 }
923}
368c73d4 924DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1da177e4
LT		 925
926/* This was originally an Alpha specific thing, but it really fits here.
927 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
928 */
929static void __init quirk_eisa_bridge(struct pci_dev *dev)
930{
931 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
932}
652c538e 933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1da177e4 934
7daa0c4f 935
1da177e4
LT		 936/*
937 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
938 * is not activated. The myth is that Asus said that they do not want the
939 * users to be irritated by just another PCI Device in the Win98 device
940 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
941 * package 2.7.0 for details)
942 *
943 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
944 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
d7698edc 945 * becomes necessary to do this tweak in two steps -- the chosen trigger
946 * is either the Host bridge (preferred) or on-board VGA controller.
9208ee82
JD		 947 *
948 * Note that we used to unhide the SMBus that way on Toshiba laptops
949 * (Satellite A40 and Tecra M2) but then found that the thermal management
950 * was done by SMM code, which could cause unsynchronized concurrent
951 * accesses to the SMBus registers, with potentially bad effects. Thus you
952 * should be very careful when adding new entries: if SMM is accessing the
953 * Intel SMBus, this is a very good reason to leave it hidden.
a99acc83
JD		 954 *
955 * Likewise, many recent laptops use ACPI for thermal management. If the
956 * ACPI DSDT code accesses the SMBus, then Linux should not access it
957 * natively, and keeping the SMBus hidden is the right thing to do. If you
958 * are about to add an entry in the table below, please first disassemble
959 * the DSDT and double-check that there is no code accessing the SMBus.
1da177e4 960 */
9d24a81e 961static int asus_hides_smbus;
1da177e4
LT		 962
963static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
964{
965 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
966 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
967 switch(dev->subsystem_device) {
a00db371 968 case 0x8025: /* P4B-LX */
1da177e4
LT		 969 case 0x8070: /* P4B */
970 case 0x8088: /* P4B533 */
971 case 0x1626: /* L3C notebook */
972 asus_hides_smbus = 1;
973 }
2f2d39d2 974 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1da177e4
LT		 975 switch(dev->subsystem_device) {
976 case 0x80b1: /* P4GE-V */
977 case 0x80b2: /* P4PE */
978 case 0x8093: /* P4B533-V */
979 asus_hides_smbus = 1;
980 }
2f2d39d2 981 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1da177e4
LT		 982 switch(dev->subsystem_device) {
983 case 0x8030: /* P4T533 */
984 asus_hides_smbus = 1;
985 }
2f2d39d2 986 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1da177e4
LT		 987 switch (dev->subsystem_device) {
988 case 0x8070: /* P4G8X Deluxe */
989 asus_hides_smbus = 1;
990 }
2f2d39d2 991 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
321311af
JD		 992 switch (dev->subsystem_device) {
993 case 0x80c9: /* PU-DLS */
994 asus_hides_smbus = 1;
995 }
2f2d39d2 996 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1da177e4
LT		 997 switch (dev->subsystem_device) {
998 case 0x1751: /* M2N notebook */
999 case 0x1821: /* M5N notebook */
1000 asus_hides_smbus = 1;
1001 }
2f2d39d2 1002 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1da177e4
LT		 1003 switch (dev->subsystem_device) {
1004 case 0x184b: /* W1N notebook */
1005 case 0x186a: /* M6Ne notebook */
1006 asus_hides_smbus = 1;
1007 }
2f2d39d2 1008 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
2e45785c
JD		 1009 switch (dev->subsystem_device) {
1010 case 0x80f2: /* P4P800-X */
1011 asus_hides_smbus = 1;
1012 }
2f2d39d2 1013 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
acc06632
M		 1014 switch (dev->subsystem_device) {
1015 case 0x1882: /* M6V notebook */
2d1e1c75 1016 case 0x1977: /* A6VA notebook */
acc06632
M		 1017 asus_hides_smbus = 1;
1018 }
1da177e4
LT		 1019 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1020 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1021 switch(dev->subsystem_device) {
1022 case 0x088C: /* HP Compaq nc8000 */
1023 case 0x0890: /* HP Compaq nc6000 */
1024 asus_hides_smbus = 1;
1025 }
2f2d39d2 1026 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1da177e4
LT		 1027 switch (dev->subsystem_device) {
1028 case 0x12bc: /* HP D330L */
e3b1bd57 1029 case 0x12bd: /* HP D530 */
1da177e4
LT		 1030 asus_hides_smbus = 1;
1031 }
677cc644
JD		 1032 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1033 switch (dev->subsystem_device) {
1034 case 0x12bf: /* HP xw4100 */
1035 asus_hides_smbus = 1;
1036 }
1da177e4
LT		 1037 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1038 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1039 switch(dev->subsystem_device) {
1040 case 0xC00C: /* Samsung P35 notebook */
1041 asus_hides_smbus = 1;
1042 }
c87f883e
RIZ		 1043 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1044 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1045 switch(dev->subsystem_device) {
1046 case 0x0058: /* Compaq Evo N620c */
1047 asus_hides_smbus = 1;
1048 }
d7698edc 1049 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1050 switch(dev->subsystem_device) {
1051 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1052 /* Motherboard doesn't have Host bridge
1053 * subvendor/subdevice IDs, therefore checking
1054 * its on-board VGA controller */
1055 asus_hides_smbus = 1;
1056 }
10260d9a
JD		 1057 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_IG)
1058 switch(dev->subsystem_device) {
1059 case 0x00b8: /* Compaq Evo D510 CMT */
1060 case 0x00b9: /* Compaq Evo D510 SFF */
1061 asus_hides_smbus = 1;
1062 }
1da177e4
LT		 1063 }
1064}
652c538e
AM		 1065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1067DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1068DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
677cc644 1069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
652c538e
AM		 1070DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1071DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1072DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1073DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1075
1076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
10260d9a 1077DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG, asus_hides_smbus_hostbridge);
d7698edc 1078
1597cacb 1079static void asus_hides_smbus_lpc(struct pci_dev *dev)
1da177e4
LT		 1080{
1081 u16 val;
1082
1083 if (likely(!asus_hides_smbus))
1084 return;
1085
1086 pci_read_config_word(dev, 0xF2, &val);
1087 if (val & 0x8) {
1088 pci_write_config_word(dev, 0xF2, val & (~0x8));
1089 pci_read_config_word(dev, 0xF2, &val);
1090 if (val & 0x8)
f0fda801 1091 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1da177e4 1092 else
f0fda801 1093 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1da177e4
LT		 1094 }
1095}
652c538e
AM		 1096DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1097DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1098DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1099DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1100DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1101DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1102DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
e1a2a51e
RW		 1103DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1104DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1105DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1106DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1107DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1108DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1109DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1597cacb 1110
e1a2a51e
RW		 1111/* It appears we just have one such device. If not, we have a warning */
1112static void __iomem *asus_rcba_base;
1113static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
acc06632 1114{
e1a2a51e 1115 u32 rcba;
acc06632
M		 1116
1117 if (likely(!asus_hides_smbus))
1118 return;
e1a2a51e
RW		 1119 WARN_ON(asus_rcba_base);
1120
acc06632 1121 pci_read_config_dword(dev, 0xF0, &rcba);
e1a2a51e
RW		 1122 /* use bits 31:14, 16 kB aligned */
1123 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1124 if (asus_rcba_base == NULL)
1125 return;
1126}
1127
1128static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1129{
1130 u32 val;
1131
1132 if (likely(!asus_hides_smbus || !asus_rcba_base))
1133 return;
1134 /* read the Function Disable register, dword mode only */
1135 val = readl(asus_rcba_base + 0x3418);
1136 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1137}
1138
1139static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1140{
1141 if (likely(!asus_hides_smbus || !asus_rcba_base))
1142 return;
1143 iounmap(asus_rcba_base);
1144 asus_rcba_base = NULL;
f0fda801 1145 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
acc06632 1146}
e1a2a51e
RW		 1147
1148static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1149{
1150 asus_hides_smbus_lpc_ich6_suspend(dev);
1151 asus_hides_smbus_lpc_ich6_resume_early(dev);
1152 asus_hides_smbus_lpc_ich6_resume(dev);
1153}
652c538e 1154DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
e1a2a51e
RW		 1155DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1156DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1157DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
ce007ea5 1158
1da177e4
LT		 1159/*
1160 * SiS 96x south bridge: BIOS typically hides SMBus device...
1161 */
1597cacb 1162static void quirk_sis_96x_smbus(struct pci_dev *dev)
1da177e4
LT		 1163{
1164 u8 val = 0;
1da177e4 1165 pci_read_config_byte(dev, 0x77, &val);
2f5c33b3 1166 if (val & 0x10) {
f0fda801 1167 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
2f5c33b3
MH		 1168 pci_write_config_byte(dev, 0x77, val & ~0x10);
1169 }
1da177e4 1170}
652c538e
AM		 1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1174DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
e1a2a51e
RW		 1175DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1176DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1177DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1178DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1da177e4 1179
1da177e4
LT		 1180/*
1181 * ... This is further complicated by the fact that some SiS96x south
1182 * bridges pretend to be 85C503/5513 instead. In that case see if we
1183 * spotted a compatible north bridge to make sure.
1184 * (pci_find_device doesn't work yet)
1185 *
1186 * We can also enable the sis96x bit in the discovery register..
1187 */
1da177e4
LT		 1188#define SIS_DETECT_REGISTER 0x40
1189
1597cacb 1190static void quirk_sis_503(struct pci_dev *dev)
1da177e4
LT		 1191{
1192 u8 reg;
1193 u16 devid;
1194
1195 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1196 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1197 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1198 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1199 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1200 return;
1201 }
1202
1da177e4 1203 /*
2f5c33b3
MH		 1204 * Ok, it now shows up as a 96x.. run the 96x quirk by
1205 * hand in case it has already been processed.
1206 * (depends on link order, which is apparently not guaranteed)
1da177e4
LT		 1207 */
1208 dev->device = devid;
2f5c33b3 1209 quirk_sis_96x_smbus(dev);
1da177e4 1210}
652c538e 1211DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
e1a2a51e 1212DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1da177e4 1213
1da177e4 1214
e5548e96
BJD		 1215/*
1216 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1217 * and MC97 modem controller are disabled when a second PCI soundcard is
1218 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1219 * -- bjd
1220 */
1597cacb 1221static void asus_hides_ac97_lpc(struct pci_dev *dev)
e5548e96
BJD		 1222{
1223 u8 val;
1224 int asus_hides_ac97 = 0;
1225
1226 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1227 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1228 asus_hides_ac97 = 1;
1229 }
1230
1231 if (!asus_hides_ac97)
1232 return;
1233
1234 pci_read_config_byte(dev, 0x50, &val);
1235 if (val & 0xc0) {
1236 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1237 pci_read_config_byte(dev, 0x50, &val);
1238 if (val & 0xc0)
f0fda801 1239 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
e5548e96 1240 else
f0fda801 1241 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
e5548e96
BJD		 1242 }
1243}
652c538e 1244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
e1a2a51e 1245DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1597cacb 1246
77967052 1247#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
15e0c694
AC		 1248
1249/*
1250 * If we are using libata we can drive this chip properly but must
1251 * do this early on to make the additional device appear during
1252 * the PCI scanning.
1253 */
5ee2ae7f 1254static void quirk_jmicron_ata(struct pci_dev *pdev)
15e0c694 1255{
e34bb370 1256 u32 conf1, conf5, class;
15e0c694
AC		 1257 u8 hdr;
1258
1259 /* Only poke fn 0 */
1260 if (PCI_FUNC(pdev->devfn))
1261 return;
1262
5ee2ae7f
TH		 1263 pci_read_config_dword(pdev, 0x40, &conf1);
1264 pci_read_config_dword(pdev, 0x80, &conf5);
15e0c694 1265
5ee2ae7f
TH		 1266 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1267 conf5 &= ~(1 << 24); /* Clear bit 24 */
1268
1269 switch (pdev->device) {
1270 case PCI_DEVICE_ID_JMICRON_JMB360:
1271 /* The controller should be in single function ahci mode */
1272 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1273 break;
1274
1275 case PCI_DEVICE_ID_JMICRON_JMB365:
1276 case PCI_DEVICE_ID_JMICRON_JMB366:
1277 /* Redirect IDE second PATA port to the right spot */
1278 conf5 |= (1 << 24);
1279 /* Fall through */
1280 case PCI_DEVICE_ID_JMICRON_JMB361:
1281 case PCI_DEVICE_ID_JMICRON_JMB363:
1282 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1283 /* Set the class codes correctly and then direct IDE 0 */
3a9e3a51 1284 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
5ee2ae7f
TH		 1285 break;
1286
1287 case PCI_DEVICE_ID_JMICRON_JMB368:
1288 /* The controller should be in single function IDE mode */
1289 conf1 |= 0x00C00000; /* Set 22, 23 */
1290 break;
15e0c694 1291 }
5ee2ae7f
TH		 1292
1293 pci_write_config_dword(pdev, 0x40, conf1);
1294 pci_write_config_dword(pdev, 0x80, conf5);
1295
1296 /* Update pdev accordingly */
1297 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1298 pdev->hdr_type = hdr & 0x7f;
1299 pdev->multifunction = !!(hdr & 0x80);
e34bb370
TH		 1300
1301 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1302 pdev->class = class >> 8;
15e0c694 1303}
5ee2ae7f
TH		 1304DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1305DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1306DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1307DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1308DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1309DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
e1a2a51e
RW		 1310DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1311DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1312DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1313DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1314DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1315DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
15e0c694
AC		 1316
1317#endif
1318
1da177e4
LT		 1319#ifdef CONFIG_X86_IO_APIC
1320static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1321{
1322 int i;
1323
1324 if ((pdev->class >> 8) != 0xff00)
1325 return;
1326
1327 /* the first BAR is the location of the IO APIC...we must
1328 * not touch this (and it's already covered by the fixmap), so
1329 * forcibly insert it into the resource tree */
1330 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1331 insert_resource(&iomem_resource, &pdev->resource[0]);
1332
1333 /* The next five BARs all seem to be rubbish, so just clean
1334 * them out */
1335 for (i=1; i < 6; i++) {
1336 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1337 }
1338
1339}
652c538e 1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1da177e4
LT		 1341#endif
1342
1da177e4 1343int pcie_mch_quirk;
c30ca1db 1344EXPORT_SYMBOL(pcie_mch_quirk);
1da177e4
LT		 1345
1346static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1347{
1348 pcie_mch_quirk = 1;
1349}
652c538e
AM		 1350DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1351DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1352DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1da177e4 1353
4602b88d
KA		 1354
1355/*
1356 * It's possible for the MSI to get corrupted if shpc and acpi
1357 * are used together on certain PXH-based systems.
1358 */
1359static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1360{
f5f2b131 1361 pci_msi_off(dev);
4602b88d 1362 dev->no_msi = 1;
f0fda801 1363 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
4602b88d
KA		 1364}
1365DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1366DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1367DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1368DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1369DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1370
ffadcc2f
KCA		 1371/*
1372 * Some Intel PCI Express chipsets have trouble with downstream
1373 * device power management.
1374 */
1375static void quirk_intel_pcie_pm(struct pci_dev * dev)
1376{
1377 pci_pm_d3_delay = 120;
1378 dev->no_d1d2 = 1;
1379}
1380
1381DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1382DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1383DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1384DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1385DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1386DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1387DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1388DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1389DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1391DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1392DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1393DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1394DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1395DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1396DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1398DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1399DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1400DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1401DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
4602b88d 1402
33dced2e
SS		 1403/*
1404 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1405 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1406 * Re-allocate the region if needed...
1407 */
1408static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1409{
1410 struct resource *r = &dev->resource[0];
1411
1412 if (r->start & 0x8) {
1413 r->start = 0;
1414 r->end = 0xf;
1415 }
1416}
1417DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1418 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1419 quirk_tc86c001_ide);
1420
1da177e4
LT		 1421static void __devinit quirk_netmos(struct pci_dev *dev)
1422{
1423 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1424 unsigned int num_serial = dev->subsystem_device & 0xf;
1425
1426 /*
1427 * These Netmos parts are multiport serial devices with optional
1428 * parallel ports. Even when parallel ports are present, they
1429 * are identified as class SERIAL, which means the serial driver
1430 * will claim them. To prevent this, mark them as class OTHER.
1431 * These combo devices should be claimed by parport_serial.
1432 *
1433 * The subdevice ID is of the form 0x00PS, where <P> is the number
1434 * of parallel ports and <S> is the number of serial ports.
1435 */
1436 switch (dev->device) {
1437 case PCI_DEVICE_ID_NETMOS_9735:
1438 case PCI_DEVICE_ID_NETMOS_9745:
1439 case PCI_DEVICE_ID_NETMOS_9835:
1440 case PCI_DEVICE_ID_NETMOS_9845:
1441 case PCI_DEVICE_ID_NETMOS_9855:
1442 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1443 num_parallel) {
f0fda801 1444 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1da177e4
LT		 1445 "%u serial); changing class SERIAL to OTHER "
1446 "(use parport_serial)\n",
1447 dev->device, num_parallel, num_serial);
1448 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1449 (dev->class & 0xff);
1450 }
1451 }
1452}
1453DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1454
16a74744
BH		 1455static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1456{
e64aeccb 1457 u16 command, pmcsr;
16a74744
BH		 1458 u8 __iomem *csr;
1459 u8 cmd_hi;
e64aeccb 1460 int pm;
16a74744
BH		 1461
1462 switch (dev->device) {
1463 /* PCI IDs taken from drivers/net/e100.c */
1464 case 0x1029:
1465 case 0x1030 ... 0x1034:
1466 case 0x1038 ... 0x103E:
1467 case 0x1050 ... 0x1057:
1468 case 0x1059:
1469 case 0x1064 ... 0x106B:
1470 case 0x1091 ... 0x1095:
1471 case 0x1209:
1472 case 0x1229:
1473 case 0x2449:
1474 case 0x2459:
1475 case 0x245D:
1476 case 0x27DC:
1477 break;
1478 default:
1479 return;
1480 }
1481
1482 /*
1483 * Some firmware hands off the e100 with interrupts enabled,
1484 * which can cause a flood of interrupts if packets are
1485 * received before the driver attaches to the device. So
1486 * disable all e100 interrupts here. The driver will
1487 * re-enable them when it's ready.
1488 */
1489 pci_read_config_word(dev, PCI_COMMAND, &command);
16a74744 1490
1bef7dc0 1491 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
16a74744
BH		 1492 return;
1493
e64aeccb
IK		 1494 /*
1495 * Check that the device is in the D0 power state. If it's not,
1496 * there is no point to look any further.
1497 */
1498 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1499 if (pm) {
1500 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1501 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1502 return;
1503 }
1504
1bef7dc0
BH		 1505 /* Convert from PCI bus to resource space. */
1506 csr = ioremap(pci_resource_start(dev, 0), 8);
16a74744 1507 if (!csr) {
f0fda801 1508 dev_warn(&dev->dev, "Can't map e100 registers\n");
16a74744
BH		 1509 return;
1510 }
1511
1512 cmd_hi = readb(csr + 3);
1513 if (cmd_hi == 0) {
f0fda801 1514 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1515 "disabling\n");
16a74744
BH		 1516 writeb(1, csr + 3);
1517 }
1518
1519 iounmap(csr);
1520}
4e68fc97 1521DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
a5312e28
IK		 1522
1523static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1524{
1525 /* rev 1 ncr53c810 chips don't set the class at all which means
1526 * they don't get their resources remapped. Fix that here.
1527 */
1528
1529 if (dev->class == PCI_CLASS_NOT_DEFINED) {
f0fda801 1530 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
a5312e28
IK		 1531 dev->class = PCI_CLASS_STORAGE_SCSI;
1532 }
1533}
1534DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1535
1da177e4
LT		 1536static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1537{
1538 while (f < end) {
1539 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1540 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
9f23ed3b 1541#ifdef DEBUG
0255f543 1542 dev_dbg(&dev->dev, "calling ");
a442ac51 1543 print_fn_descriptor_symbol("%s\n", f->hook);
9f23ed3b 1544#endif
1da177e4
LT		 1545 f->hook(dev);
1546 }
1547 f++;
1548 }
1549}
1550
1551extern struct pci_fixup __start_pci_fixups_early[];
1552extern struct pci_fixup __end_pci_fixups_early[];
1553extern struct pci_fixup __start_pci_fixups_header[];
1554extern struct pci_fixup __end_pci_fixups_header[];
1555extern struct pci_fixup __start_pci_fixups_final[];
1556extern struct pci_fixup __end_pci_fixups_final[];
1557extern struct pci_fixup __start_pci_fixups_enable[];
1558extern struct pci_fixup __end_pci_fixups_enable[];
1597cacb
AC		 1559extern struct pci_fixup __start_pci_fixups_resume[];
1560extern struct pci_fixup __end_pci_fixups_resume[];
e1a2a51e
RW		 1561extern struct pci_fixup __start_pci_fixups_resume_early[];
1562extern struct pci_fixup __end_pci_fixups_resume_early[];
1563extern struct pci_fixup __start_pci_fixups_suspend[];
1564extern struct pci_fixup __end_pci_fixups_suspend[];
1da177e4
LT		 1565
1566
1567void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1568{
1569 struct pci_fixup *start, *end;
1570
1571 switch(pass) {
1572 case pci_fixup_early:
1573 start = __start_pci_fixups_early;
1574 end = __end_pci_fixups_early;
1575 break;
1576
1577 case pci_fixup_header:
1578 start = __start_pci_fixups_header;
1579 end = __end_pci_fixups_header;
1580 break;
1581
1582 case pci_fixup_final:
1583 start = __start_pci_fixups_final;
1584 end = __end_pci_fixups_final;
1585 break;
1586
1587 case pci_fixup_enable:
1588 start = __start_pci_fixups_enable;
1589 end = __end_pci_fixups_enable;
1590 break;
1591
1597cacb
AC		 1592 case pci_fixup_resume:
1593 start = __start_pci_fixups_resume;
1594 end = __end_pci_fixups_resume;
1595 break;
1596
e1a2a51e
RW		 1597 case pci_fixup_resume_early:
1598 start = __start_pci_fixups_resume_early;
1599 end = __end_pci_fixups_resume_early;
1600 break;
1601
1602 case pci_fixup_suspend:
1603 start = __start_pci_fixups_suspend;
1604 end = __end_pci_fixups_suspend;
1605 break;
1606
1da177e4
LT		 1607 default:
1608 /* stupid compiler warning, you would think with an enum... */
1609 return;
1610 }
1611 pci_do_fixups(dev, start, end);
1612}
c30ca1db 1613EXPORT_SYMBOL(pci_fixup_device);
1da177e4 1614
9d265124
DY		 1615/* Enable 1k I/O space granularity on the Intel P64H2 */
1616static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1617{
1618 u16 en1k;
1619 u8 io_base_lo, io_limit_lo;
1620 unsigned long base, limit;
1621 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1622
1623 pci_read_config_word(dev, 0x40, &en1k);
1624
1625 if (en1k & 0x200) {
f0fda801 1626 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
9d265124
DY		 1627
1628 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1629 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1630 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1631 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1632
1633 if (base <= limit) {
1634 res->start = base;
1635 res->end = limit + 0x3ff;
1636 }
1637 }
1638}
1639DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1640
15a260d5
DY		 1641/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
1642 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
1643 * in drivers/pci/setup-bus.c
1644 */
1645static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1646{
1647 u16 en1k, iobl_adr, iobl_adr_1k;
1648 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1649
1650 pci_read_config_word(dev, 0x40, &en1k);
1651
1652 if (en1k & 0x200) {
1653 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
1654
1655 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1656
1657 if (iobl_adr != iobl_adr_1k) {
f0fda801 1658 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
15a260d5
DY		 1659 iobl_adr,iobl_adr_1k);
1660 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1661 }
1662 }
1663}
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
1665
cf34a8e0
BG		 1666/* Under some circumstances, AER is not linked with extended capabilities.
1667 * Force it to be linked by setting the corresponding control bit in the
1668 * config space.
1669 */
1597cacb 1670static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
cf34a8e0
BG		 1671{
1672 uint8_t b;
1673 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1674 if (!(b & 0x20)) {
1675 pci_write_config_byte(dev, 0xf41, b | 0x20);
f0fda801 1676 dev_info(&dev->dev,
1677 "Linking AER extended capability\n");
cf34a8e0
BG		 1678 }
1679 }
1680}
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1682 quirk_nvidia_ck804_pcie_aer_ext_cap);
e1a2a51e 1683DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1597cacb 1684 quirk_nvidia_ck804_pcie_aer_ext_cap);
cf34a8e0 1685
53a9bf42
TY		 1686static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1687{
1688 /*
1689 * Disable PCI Bus Parking and PCI Master read caching on CX700
1690 * which causes unspecified timing errors with a VT6212L on the PCI
1691 * bus leading to USB2.0 packet loss. The defaults are that these
1692 * features are turned off but some BIOSes turn them on.
1693 */
1694
1695 uint8_t b;
1696 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1697 if (b & 0x40) {
1698 /* Turn off PCI Bus Parking */
1699 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1700
bc043274
TY		 1701 dev_info(&dev->dev,
1702 "Disabling VIA CX700 PCI parking\n");
1703 }
1704 }
1705
1706 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
1707 if (b != 0) {
53a9bf42
TY		 1708 /* Turn off PCI Master read caching */
1709 pci_write_config_byte(dev, 0x72, 0x0);
bc043274
TY		 1710
1711 /* Set PCI Master Bus time-out to "1x16 PCLK" */
53a9bf42 1712 pci_write_config_byte(dev, 0x75, 0x1);
bc043274
TY		 1713
1714 /* Disable "Read FIFO Timer" */
53a9bf42
TY		 1715 pci_write_config_byte(dev, 0x77, 0x0);
1716
d6505a52 1717 dev_info(&dev->dev,
bc043274 1718 "Disabling VIA CX700 PCI caching\n");
53a9bf42
TY		 1719 }
1720 }
1721}
1722DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1723
3f79e107 1724#ifdef CONFIG_PCI_MSI
ebdf7d39
TH		 1725/* Some chipsets do not support MSI. We cannot easily rely on setting
1726 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
1727 * some other busses controlled by the chipset even if Linux is not
1728 * aware of it. Instead of setting the flag on all busses in the
1729 * machine, simply disable MSI globally.
3f79e107 1730 */
ebdf7d39 1731static void __init quirk_disable_all_msi(struct pci_dev *dev)
3f79e107 1732{
88187dfa 1733 pci_no_msi();
f0fda801 1734 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
3f79e107 1735}
ebdf7d39
TH		 1736DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1737DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
1738DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
184b812f 1739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
3f79e107
BG		 1740
1741/* Disable MSI on chipsets that are known to not support it */
1742static void __devinit quirk_disable_msi(struct pci_dev *dev)
1743{
1744 if (dev->subordinate) {
f0fda801 1745 dev_warn(&dev->dev, "MSI quirk detected; "
1746 "subordinate MSI disabled\n");
3f79e107
BG		 1747 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1748 }
1749}
1750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
6397c75c
BG		 1751
1752/* Go through the list of Hypertransport capabilities and
1753 * return 1 if a HT MSI capability is found and enabled */
1754static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1755{
7a380507
ME		 1756 int pos, ttl = 48;
1757
1758 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1759 while (pos && ttl--) {
1760 u8 flags;
1761
1762 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1763 &flags) == 0)
1764 {
f0fda801 1765 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
7a380507 1766 flags & HT_MSI_FLAGS_ENABLE ?
f0fda801 1767 "enabled" : "disabled");
7a380507 1768 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
6397c75c 1769 }
7a380507
ME		 1770
1771 pos = pci_find_next_ht_capability(dev, pos,
1772 HT_CAPTYPE_MSI_MAPPING);
6397c75c
BG		 1773 }
1774 return 0;
1775}
1776
1777/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
1778static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1779{
1780 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
f0fda801 1781 dev_warn(&dev->dev, "MSI quirk detected; "
1782 "subordinate MSI disabled\n");
6397c75c
BG		 1783 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1784 }
1785}
1786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1787 quirk_msi_ht_cap);
6bae1d96
SD		 1788
1789
6397c75c
BG		 1790/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1791 * MSI are supported if the MSI capability set in any of these mappings.
1792 */
1793static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1794{
1795 struct pci_dev *pdev;
1796
1797 if (!dev->subordinate)
1798 return;
1799
1800 /* check HT MSI cap on this chipset and the root one.
1801 * a single one having MSI is enough to be sure that MSI are supported.
1802 */
11f242f0 1803 pdev = pci_get_slot(dev->bus, 0);
9ac0ce85
JJ		 1804 if (!pdev)
1805 return;
0c875c28 1806 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
f0fda801 1807 dev_warn(&dev->dev, "MSI quirk detected; "
1808 "subordinate MSI disabled\n");
6397c75c
BG		 1809 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1810 }
11f242f0 1811 pci_dev_put(pdev);
6397c75c
BG		 1812}
1813DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1814 quirk_nvidia_ck804_msi_ht_cap);
ba698ad4 1815
415b6d0e
BH		 1816/* Force enable MSI mapping capability on HT bridges */
1817static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
9dc625e7
PC		 1818{
1819 int pos, ttl = 48;
1820
1821 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1822 while (pos && ttl--) {
1823 u8 flags;
1824
1825 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1826 &flags) == 0) {
1827 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
1828
1829 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1830 flags | HT_MSI_FLAGS_ENABLE);
1831 }
1832 pos = pci_find_next_ht_capability(dev, pos,
1833 HT_CAPTYPE_MSI_MAPPING);
1834 }
1835}
415b6d0e
BH		 1836DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1837 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1838 ht_enable_msi_mapping);
9dc625e7
PC		 1839
1840static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev)
1841{
1842 struct pci_dev *host_bridge;
1843 int pos, ttl = 48;
1844
1845 /*
1846 * HT MSI mapping should be disabled on devices that are below
1847 * a non-Hypertransport host bridge. Locate the host bridge...
1848 */
1849 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1850 if (host_bridge == NULL) {
1851 dev_warn(&dev->dev,
1852 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
1853 return;
1854 }
1855
1856 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
1857 if (pos != 0) {
1858 /* Host bridge is to HT */
1859 ht_enable_msi_mapping(dev);
1860 return;
1861 }
1862
1863 /* Host bridge is not to HT, disable HT MSI mapping on this device */
1864 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1865 while (pos && ttl--) {
1866 u8 flags;
1867
1868 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1869 &flags) == 0) {
415b6d0e 1870 dev_info(&dev->dev, "Disabling HT MSI mapping");
9dc625e7
PC		 1871 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1872 flags & ~HT_MSI_FLAGS_ENABLE);
1873 }
1874 pos = pci_find_next_ht_capability(dev, pos,
1875 HT_CAPTYPE_MSI_MAPPING);
1876 }
1877}
1878DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk);
439a7733 1879DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk);
9dc625e7 1880
ba698ad4
DM		 1881static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1882{
1883 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1884}
4600c9d7
SH		 1885static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1886{
1887 struct pci_dev *p;
1888
1889 /* SB700 MSI issue will be fixed at HW level from revision A21,
1890 * we need check PCI REVISION ID of SMBus controller to get SB700
1891 * revision.
1892 */
1893 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1894 NULL);
1895 if (!p)
1896 return;
1897
1898 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1899 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1900 pci_dev_put(p);
1901}
ba698ad4
DM		 1902DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1903 PCI_DEVICE_ID_TIGON3_5780,
1904 quirk_msi_intx_disable_bug);
1905DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1906 PCI_DEVICE_ID_TIGON3_5780S,
1907 quirk_msi_intx_disable_bug);
1908DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1909 PCI_DEVICE_ID_TIGON3_5714,
1910 quirk_msi_intx_disable_bug);
1911DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1912 PCI_DEVICE_ID_TIGON3_5714S,
1913 quirk_msi_intx_disable_bug);
1914DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1915 PCI_DEVICE_ID_TIGON3_5715,
1916 quirk_msi_intx_disable_bug);
1917DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1918 PCI_DEVICE_ID_TIGON3_5715S,
1919 quirk_msi_intx_disable_bug);
1920
bc38b411 1921DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
4600c9d7 1922 quirk_msi_intx_disable_ati_bug);
bc38b411 1923DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
4600c9d7 1924 quirk_msi_intx_disable_ati_bug);
bc38b411 1925DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
4600c9d7 1926 quirk_msi_intx_disable_ati_bug);
bc38b411 1927DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
4600c9d7 1928 quirk_msi_intx_disable_ati_bug);
bc38b411 1929DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
4600c9d7 1930 quirk_msi_intx_disable_ati_bug);
bc38b411
DM		 1931
1932DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1933 quirk_msi_intx_disable_bug);
1934DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
1935 quirk_msi_intx_disable_bug);
1936DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
1937 quirk_msi_intx_disable_bug);
1938
3f79e107 1939#endif /* CONFIG_PCI_MSI */
Linux kernel - Deliverables
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