Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for many known PCI hardware | |
3 | * bugs. Devices present only on certain architectures (host | |
4 | * bridges et cetera) should be handled in arch-specific code. | |
5 | * | |
6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. | |
7 | * | |
8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
9 | * | |
7586269c DB |
10 | * Init/reset quirks for USB host controllers should be in the |
11 | * USB quirks file, where their drivers can access reuse it. | |
12 | * | |
1da177e4 LT |
13 | * The bridge optimization stuff has been removed. If you really |
14 | * have a silly BIOS which is unable to set your host bridge right, | |
15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
25be5e6c | 23 | #include <linux/acpi.h> |
bc56b9e0 | 24 | #include "pci.h" |
1da177e4 | 25 | |
bd8481e1 DT |
26 | /* The Mellanox Tavor device gives false positive parity errors |
27 | * Mark this device with a broken_parity_status, to allow | |
28 | * PCI scanning code to "skip" this now blacklisted device. | |
29 | */ | |
30 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) | |
31 | { | |
32 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
33 | } | |
34 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); | |
35 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); | |
36 | ||
1da177e4 LT |
37 | /* Deal with broken BIOS'es that neglect to enable passive release, |
38 | which can cause problems in combination with the 82441FX/PPro MTRRs */ | |
1597cacb | 39 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
40 | { |
41 | struct pci_dev *d = NULL; | |
42 | unsigned char dlc; | |
43 | ||
44 | /* We have to make sure a particular bit is set in the PIIX3 | |
45 | ISA bridge, so we have to go out and find it. */ | |
46 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { | |
47 | pci_read_config_byte(d, 0x82, &dlc); | |
48 | if (!(dlc & 1<<1)) { | |
49 | printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); | |
50 | dlc |= 1<<1; | |
51 | pci_write_config_byte(d, 0x82, dlc); | |
52 | } | |
53 | } | |
54 | } | |
652c538e AM |
55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
56 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 LT |
57 | |
58 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround | |
59 | but VIA don't answer queries. If you happen to have good contacts at VIA | |
60 | ask them for me please -- Alan | |
61 | ||
62 | This appears to be BIOS not version dependent. So presumably there is a | |
63 | chipset level fix */ | |
c30ca1db AB |
64 | int isa_dma_bridge_buggy; |
65 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
1da177e4 LT |
66 | |
67 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) | |
68 | { | |
69 | if (!isa_dma_bridge_buggy) { | |
70 | isa_dma_bridge_buggy=1; | |
71 | printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); | |
72 | } | |
73 | } | |
74 | /* | |
75 | * Its not totally clear which chipsets are the problematic ones | |
76 | * We know 82C586 and 82C596 variants are affected. | |
77 | */ | |
652c538e AM |
78 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
79 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
80 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
81 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); | |
82 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); | |
83 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
84 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
1da177e4 LT |
85 | |
86 | int pci_pci_problems; | |
c30ca1db | 87 | EXPORT_SYMBOL(pci_pci_problems); |
1da177e4 LT |
88 | |
89 | /* | |
90 | * Chipsets where PCI->PCI transfers vanish or hang | |
91 | */ | |
92 | static void __devinit quirk_nopcipci(struct pci_dev *dev) | |
93 | { | |
94 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { | |
95 | printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); | |
96 | pci_pci_problems |= PCIPCI_FAIL; | |
97 | } | |
98 | } | |
652c538e AM |
99 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
100 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 AC |
101 | |
102 | static void __devinit quirk_nopciamd(struct pci_dev *dev) | |
103 | { | |
104 | u8 rev; | |
105 | pci_read_config_byte(dev, 0x08, &rev); | |
106 | if (rev == 0x13) { | |
107 | /* Erratum 24 */ | |
108 | printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); | |
109 | pci_pci_problems |= PCIAGP_FAIL; | |
110 | } | |
111 | } | |
652c538e | 112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 LT |
113 | |
114 | /* | |
115 | * Triton requires workarounds to be used by the drivers | |
116 | */ | |
117 | static void __devinit quirk_triton(struct pci_dev *dev) | |
118 | { | |
119 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { | |
120 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
121 | pci_pci_problems |= PCIPCI_TRITON; | |
122 | } | |
123 | } | |
652c538e AM |
124 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
125 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
126 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
127 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
128 | |
129 | /* | |
130 | * VIA Apollo KT133 needs PCI latency patch | |
131 | * Made according to a windows driver based patch by George E. Breese | |
132 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
133 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for | |
134 | * the info on which Mr Breese based his work. | |
135 | * | |
136 | * Updated based on further information from the site and also on | |
137 | * information provided by VIA | |
138 | */ | |
1597cacb | 139 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
140 | { |
141 | struct pci_dev *p; | |
1da177e4 LT |
142 | u8 busarb; |
143 | /* Ok we have a potential problem chipset here. Now see if we have | |
144 | a buggy southbridge */ | |
145 | ||
146 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); | |
147 | if (p!=NULL) { | |
1da177e4 LT |
148 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
149 | /* Check for buggy part revisions */ | |
2b1afa87 | 150 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
151 | goto exit; |
152 | } else { | |
153 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
154 | if (p==NULL) /* No problem parts */ | |
155 | goto exit; | |
1da177e4 | 156 | /* Check for buggy part revisions */ |
2b1afa87 | 157 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
158 | goto exit; |
159 | } | |
160 | ||
161 | /* | |
162 | * Ok we have the problem. Now set the PCI master grant to | |
163 | * occur every master grant. The apparent bug is that under high | |
164 | * PCI load (quite common in Linux of course) you can get data | |
165 | * loss when the CPU is held off the bus for 3 bus master requests | |
166 | * This happens to include the IDE controllers.... | |
167 | * | |
168 | * VIA only apply this fix when an SB Live! is present but under | |
169 | * both Linux and Windows this isnt enough, and we have seen | |
170 | * corruption without SB Live! but with things like 3 UDMA IDE | |
171 | * controllers. So we ignore that bit of the VIA recommendation.. | |
172 | */ | |
173 | ||
174 | pci_read_config_byte(dev, 0x76, &busarb); | |
175 | /* Set bit 4 and bi 5 of byte 76 to 0x01 | |
176 | "Master priority rotation on every PCI master grant */ | |
177 | busarb &= ~(1<<5); | |
178 | busarb |= (1<<4); | |
179 | pci_write_config_byte(dev, 0x76, busarb); | |
180 | printk(KERN_INFO "Applying VIA southbridge workaround.\n"); | |
181 | exit: | |
182 | pci_dev_put(p); | |
183 | } | |
652c538e AM |
184 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
185 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
186 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 187 | /* Must restore this on a resume from RAM */ |
652c538e AM |
188 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
189 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
190 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 LT |
191 | |
192 | /* | |
193 | * VIA Apollo VP3 needs ETBF on BT848/878 | |
194 | */ | |
195 | static void __devinit quirk_viaetbf(struct pci_dev *dev) | |
196 | { | |
197 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { | |
198 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
199 | pci_pci_problems |= PCIPCI_VIAETBF; | |
200 | } | |
201 | } | |
652c538e | 202 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 LT |
203 | |
204 | static void __devinit quirk_vsfx(struct pci_dev *dev) | |
205 | { | |
206 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { | |
207 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
208 | pci_pci_problems |= PCIPCI_VSFX; | |
209 | } | |
210 | } | |
652c538e | 211 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
212 | |
213 | /* | |
214 | * Ali Magik requires workarounds to be used by the drivers | |
215 | * that DMA to AGP space. Latency must be set to 0xA and triton | |
216 | * workaround applied too | |
217 | * [Info kindly provided by ALi] | |
218 | */ | |
219 | static void __init quirk_alimagik(struct pci_dev *dev) | |
220 | { | |
221 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { | |
222 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
223 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; | |
224 | } | |
225 | } | |
652c538e AM |
226 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
227 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 LT |
228 | |
229 | /* | |
230 | * Natoma has some interesting boundary conditions with Zoran stuff | |
231 | * at least | |
232 | */ | |
233 | static void __devinit quirk_natoma(struct pci_dev *dev) | |
234 | { | |
235 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { | |
236 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
237 | pci_pci_problems |= PCIPCI_NATOMA; | |
238 | } | |
239 | } | |
652c538e AM |
240 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
241 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
242 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
243 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
244 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
245 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
246 | |
247 | /* | |
248 | * This chip can cause PCI parity errors if config register 0xA0 is read | |
249 | * while DMAs are occurring. | |
250 | */ | |
251 | static void __devinit quirk_citrine(struct pci_dev *dev) | |
252 | { | |
253 | dev->cfg_size = 0xA0; | |
254 | } | |
652c538e | 255 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 LT |
256 | |
257 | /* | |
258 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. | |
259 | * If it's needed, re-allocate the region. | |
260 | */ | |
261 | static void __devinit quirk_s3_64M(struct pci_dev *dev) | |
262 | { | |
263 | struct resource *r = &dev->resource[0]; | |
264 | ||
265 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
266 | r->start = 0; | |
267 | r->end = 0x3ffffff; | |
268 | } | |
269 | } | |
652c538e AM |
270 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
271 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 272 | |
6693e74a LT |
273 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
274 | unsigned size, int nr, const char *name) | |
1da177e4 LT |
275 | { |
276 | region &= ~(size-1); | |
277 | if (region) { | |
085ae41f | 278 | struct pci_bus_region bus_region; |
1da177e4 LT |
279 | struct resource *res = dev->resource + nr; |
280 | ||
281 | res->name = pci_name(dev); | |
282 | res->start = region; | |
283 | res->end = region + size - 1; | |
284 | res->flags = IORESOURCE_IO; | |
085ae41f DM |
285 | |
286 | /* Convert from PCI bus to resource space. */ | |
287 | bus_region.start = res->start; | |
288 | bus_region.end = res->end; | |
289 | pcibios_bus_to_resource(dev, res, &bus_region); | |
290 | ||
1da177e4 | 291 | pci_claim_resource(dev, nr); |
6693e74a | 292 | printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); |
1da177e4 LT |
293 | } |
294 | } | |
295 | ||
296 | /* | |
297 | * ATI Northbridge setups MCE the processor if you even | |
298 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 | |
299 | */ | |
300 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) | |
301 | { | |
302 | printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); | |
303 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ | |
304 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
305 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
306 | } | |
652c538e | 307 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 LT |
308 | |
309 | /* | |
310 | * Let's make the southbridge information explicit instead | |
311 | * of having to worry about people probing the ACPI areas, | |
312 | * for example.. (Yes, it happens, and if you read the wrong | |
313 | * ACPI register it will put the machine to sleep with no | |
314 | * way of waking it up again. Bummer). | |
315 | * | |
316 | * ALI M7101: Two IO regions pointed to by words at | |
317 | * 0xE0 (64 bytes of ACPI registers) | |
318 | * 0xE2 (32 bytes of SMB registers) | |
319 | */ | |
320 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) | |
321 | { | |
322 | u16 region; | |
323 | ||
324 | pci_read_config_word(dev, 0xE0, ®ion); | |
6693e74a | 325 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
1da177e4 | 326 | pci_read_config_word(dev, 0xE2, ®ion); |
6693e74a | 327 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
1da177e4 | 328 | } |
652c538e | 329 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 330 | |
6693e74a LT |
331 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
332 | { | |
333 | u32 devres; | |
334 | u32 mask, size, base; | |
335 | ||
336 | pci_read_config_dword(dev, port, &devres); | |
337 | if ((devres & enable) != enable) | |
338 | return; | |
339 | mask = (devres >> 16) & 15; | |
340 | base = devres & 0xffff; | |
341 | size = 16; | |
342 | for (;;) { | |
343 | unsigned bit = size >> 1; | |
344 | if ((bit & mask) == bit) | |
345 | break; | |
346 | size = bit; | |
347 | } | |
348 | /* | |
349 | * For now we only print it out. Eventually we'll want to | |
350 | * reserve it (at least if it's in the 0x1000+ range), but | |
351 | * let's get enough confirmation reports first. | |
352 | */ | |
353 | base &= -size; | |
354 | printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); | |
355 | } | |
356 | ||
357 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
358 | { | |
359 | u32 devres; | |
360 | u32 mask, size, base; | |
361 | ||
362 | pci_read_config_dword(dev, port, &devres); | |
363 | if ((devres & enable) != enable) | |
364 | return; | |
365 | base = devres & 0xffff0000; | |
366 | mask = (devres & 0x3f) << 16; | |
367 | size = 128 << 16; | |
368 | for (;;) { | |
369 | unsigned bit = size >> 1; | |
370 | if ((bit & mask) == bit) | |
371 | break; | |
372 | size = bit; | |
373 | } | |
374 | /* | |
375 | * For now we only print it out. Eventually we'll want to | |
376 | * reserve it, but let's get enough confirmation reports first. | |
377 | */ | |
378 | base &= -size; | |
379 | printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); | |
380 | } | |
381 | ||
1da177e4 LT |
382 | /* |
383 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
384 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 385 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 386 | * and a few strange programmable PIIX4 device resources. |
1da177e4 LT |
387 | */ |
388 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) | |
389 | { | |
6693e74a | 390 | u32 region, res_a; |
1da177e4 LT |
391 | |
392 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 393 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
1da177e4 | 394 | pci_read_config_dword(dev, 0x90, ®ion); |
08db2a70 | 395 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
6693e74a LT |
396 | |
397 | /* Device resource A has enables for some of the other ones */ | |
398 | pci_read_config_dword(dev, 0x5c, &res_a); | |
399 | ||
400 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
401 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
402 | ||
403 | /* Device resource D is just bitfields for static resources */ | |
404 | ||
405 | /* Device 12 enabled? */ | |
406 | if (res_a & (1 << 29)) { | |
407 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
408 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
409 | } | |
410 | /* Device 13 enabled? */ | |
411 | if (res_a & (1 << 30)) { | |
412 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
413 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
414 | } | |
415 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
416 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 417 | } |
652c538e AM |
418 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
419 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 LT |
420 | |
421 | /* | |
422 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
423 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
424 | * 0x58 (64 bytes of GPIO I/O space) | |
425 | */ | |
426 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) | |
427 | { | |
428 | u32 region; | |
429 | ||
430 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 431 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
1da177e4 LT |
432 | |
433 | pci_read_config_dword(dev, 0x58, ®ion); | |
6693e74a | 434 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
1da177e4 | 435 | } |
652c538e AM |
436 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
437 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
438 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
439 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
440 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
443 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
444 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
445 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 446 | |
2cea752f M |
447 | static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) |
448 | { | |
449 | u32 region; | |
450 | ||
451 | pci_read_config_dword(dev, 0x40, ®ion); | |
452 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); | |
453 | ||
454 | pci_read_config_dword(dev, 0x48, ®ion); | |
455 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); | |
456 | } | |
652c538e AM |
457 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi); |
458 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi); | |
459 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi); | |
460 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi); | |
461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi); | |
462 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi); | |
463 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi); | |
464 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi); | |
465 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi); | |
466 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi); | |
467 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi); | |
468 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi); | |
469 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi); | |
470 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi); | |
2cea752f | 471 | |
1da177e4 LT |
472 | /* |
473 | * VIA ACPI: One IO region pointed to by longword at | |
474 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
475 | */ | |
476 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) | |
477 | { | |
1da177e4 LT |
478 | u32 region; |
479 | ||
651472fb | 480 | if (dev->revision & 0x10) { |
1da177e4 LT |
481 | pci_read_config_dword(dev, 0x48, ®ion); |
482 | region &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 483 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
1da177e4 LT |
484 | } |
485 | } | |
652c538e | 486 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
487 | |
488 | /* | |
489 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
490 | * 0x48 (256 bytes of ACPI registers) | |
491 | * 0x70 (128 bytes of hardware monitoring register) | |
492 | * 0x90 (16 bytes of SMB registers) | |
493 | */ | |
494 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) | |
495 | { | |
496 | u16 hm; | |
497 | u32 smb; | |
498 | ||
499 | quirk_vt82c586_acpi(dev); | |
500 | ||
501 | pci_read_config_word(dev, 0x70, &hm); | |
502 | hm &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 503 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
1da177e4 LT |
504 | |
505 | pci_read_config_dword(dev, 0x90, &smb); | |
506 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 507 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
1da177e4 | 508 | } |
652c538e | 509 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 510 | |
6d85f29b IK |
511 | /* |
512 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
513 | * 0x88 (128 bytes of power management registers) | |
514 | * 0xd0 (16 bytes of SMB registers) | |
515 | */ | |
516 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) | |
517 | { | |
518 | u16 pm, smb; | |
519 | ||
520 | pci_read_config_word(dev, 0x88, &pm); | |
521 | pm &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 522 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
6d85f29b IK |
523 | |
524 | pci_read_config_word(dev, 0xd0, &smb); | |
525 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 526 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
6d85f29b IK |
527 | } |
528 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
529 | ||
1da177e4 LT |
530 | |
531 | #ifdef CONFIG_X86_IO_APIC | |
532 | ||
533 | #include <asm/io_apic.h> | |
534 | ||
535 | /* | |
536 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
537 | * devices to the external APIC. | |
538 | * | |
539 | * TODO: When we have device-specific interrupt routers, | |
540 | * this code will go away from quirks. | |
541 | */ | |
1597cacb | 542 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
543 | { |
544 | u8 tmp; | |
545 | ||
546 | if (nr_ioapics < 1) | |
547 | tmp = 0; /* nothing routed to external APIC */ | |
548 | else | |
549 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
550 | ||
551 | printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", | |
552 | tmp == 0 ? "Disa" : "Ena"); | |
553 | ||
554 | /* Offset 0x58: External APIC IRQ output control */ | |
555 | pci_write_config_byte (dev, 0x58, tmp); | |
556 | } | |
652c538e AM |
557 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
558 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); | |
1da177e4 | 559 | |
a1740913 KW |
560 | /* |
561 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. | |
562 | * This leads to doubled level interrupt rates. | |
563 | * Set this bit to get rid of cycle wastage. | |
564 | * Otherwise uncritical. | |
565 | */ | |
1597cacb | 566 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
567 | { |
568 | u8 misc_control2; | |
569 | #define BYPASS_APIC_DEASSERT 8 | |
570 | ||
571 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
572 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
573 | printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); | |
574 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); | |
575 | } | |
576 | } | |
577 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
1597cacb | 578 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 579 | |
1da177e4 LT |
580 | /* |
581 | * The AMD io apic can hang the box when an apic irq is masked. | |
582 | * We check all revs >= B0 (yet not in the pre production!) as the bug | |
583 | * is currently marked NoFix | |
584 | * | |
585 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 586 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4 LT |
587 | * of course. However the advice is demonstrably good even if so.. |
588 | */ | |
589 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) | |
590 | { | |
44c10138 | 591 | if (dev->revision >= 0x02) { |
236561e5 | 592 | printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
1da177e4 LT |
593 | printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); |
594 | } | |
595 | } | |
652c538e | 596 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
597 | |
598 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) | |
599 | { | |
600 | if (dev->devfn == 0 && dev->bus->number == 0) | |
601 | sis_apic_bug = 1; | |
602 | } | |
652c538e | 603 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); |
1da177e4 | 604 | |
1da177e4 LT |
605 | #define AMD8131_revA0 0x01 |
606 | #define AMD8131_revB0 0x11 | |
607 | #define AMD8131_MISC 0x40 | |
608 | #define AMD8131_NIOAMODE_BIT 0 | |
1597cacb | 609 | static void quirk_amd_8131_ioapic(struct pci_dev *dev) |
1da177e4 | 610 | { |
44c10138 | 611 | unsigned char tmp; |
1da177e4 | 612 | |
1da177e4 LT |
613 | if (nr_ioapics == 0) |
614 | return; | |
615 | ||
44c10138 | 616 | if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) { |
1da177e4 LT |
617 | printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); |
618 | pci_read_config_byte( dev, AMD8131_MISC, &tmp); | |
619 | tmp &= ~(1 << AMD8131_NIOAMODE_BIT); | |
620 | pci_write_config_byte( dev, AMD8131_MISC, tmp); | |
621 | } | |
622 | } | |
5da594b1 | 623 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
1597cacb | 624 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
1da177e4 LT |
625 | #endif /* CONFIG_X86_IO_APIC */ |
626 | ||
d556ad4b PO |
627 | /* |
628 | * Some settings of MMRBC can lead to data corruption so block changes. | |
629 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
630 | */ | |
631 | static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) | |
632 | { | |
aa288d4d | 633 | if (dev->subordinate && dev->revision <= 0x12) { |
b7b095c1 | 634 | printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X " |
aa288d4d | 635 | "MMRBC\n", dev->revision); |
d556ad4b PO |
636 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
637 | } | |
638 | } | |
639 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 640 | |
1da177e4 LT |
641 | /* |
642 | * FIXME: it is questionable that quirk_via_acpi | |
643 | * is needed. It shows up as an ISA bridge, and does not | |
644 | * support the PCI_INTERRUPT_LINE register at all. Therefore | |
645 | * it seems like setting the pci_dev's 'irq' to the | |
646 | * value of the ACPI SCI interrupt is only done for convenience. | |
647 | * -jgarzik | |
648 | */ | |
649 | static void __devinit quirk_via_acpi(struct pci_dev *d) | |
650 | { | |
651 | /* | |
652 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 | |
653 | */ | |
654 | u8 irq; | |
655 | pci_read_config_byte(d, 0x42, &irq); | |
656 | irq &= 0xf; | |
657 | if (irq && (irq != 2)) | |
658 | d->irq = irq; | |
659 | } | |
652c538e AM |
660 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
661 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 662 | |
09d6029f DD |
663 | |
664 | /* | |
1597cacb | 665 | * VIA bridges which have VLink |
09d6029f | 666 | */ |
1597cacb | 667 | |
c06bb5d4 JD |
668 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
669 | ||
670 | static void quirk_via_bridge(struct pci_dev *dev) | |
671 | { | |
672 | /* See what bridge we have and find the device ranges */ | |
673 | switch (dev->device) { | |
674 | case PCI_DEVICE_ID_VIA_82C686: | |
cb7468ef JD |
675 | /* The VT82C686 is special, it attaches to PCI and can have |
676 | any device number. All its subdevices are functions of | |
677 | that single device. */ | |
678 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); | |
679 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
680 | break; |
681 | case PCI_DEVICE_ID_VIA_8237: | |
682 | case PCI_DEVICE_ID_VIA_8237A: | |
683 | via_vlink_dev_lo = 15; | |
684 | break; | |
685 | case PCI_DEVICE_ID_VIA_8235: | |
686 | via_vlink_dev_lo = 16; | |
687 | break; | |
688 | case PCI_DEVICE_ID_VIA_8231: | |
689 | case PCI_DEVICE_ID_VIA_8233_0: | |
690 | case PCI_DEVICE_ID_VIA_8233A: | |
691 | case PCI_DEVICE_ID_VIA_8233C_0: | |
692 | via_vlink_dev_lo = 17; | |
693 | break; | |
694 | } | |
695 | } | |
696 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
697 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
698 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
699 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
700 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
701 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
702 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
703 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 704 | |
1597cacb AC |
705 | /** |
706 | * quirk_via_vlink - VIA VLink IRQ number update | |
707 | * @dev: PCI device | |
708 | * | |
709 | * If the device we are dealing with is on a PIC IRQ we need to | |
710 | * ensure that the IRQ line register which usually is not relevant | |
711 | * for PCI cards, is actually written so that interrupts get sent | |
c06bb5d4 JD |
712 | * to the right place. |
713 | * We only do this on systems where a VIA south bridge was detected, | |
714 | * and only for VIA devices on the motherboard (see quirk_via_bridge | |
715 | * above). | |
1597cacb AC |
716 | */ |
717 | ||
718 | static void quirk_via_vlink(struct pci_dev *dev) | |
25be5e6c LB |
719 | { |
720 | u8 irq, new_irq; | |
721 | ||
c06bb5d4 JD |
722 | /* Check if we have VLink at all */ |
723 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
724 | return; |
725 | ||
726 | new_irq = dev->irq; | |
727 | ||
728 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
729 | if (!new_irq || new_irq > 15) | |
730 | return; | |
731 | ||
1597cacb | 732 | /* Internal device ? */ |
c06bb5d4 JD |
733 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
734 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
735 | return; |
736 | ||
737 | /* This is an internal VLink device on a PIC interrupt. The BIOS | |
738 | ought to have set this but may not have, so we redo it */ | |
739 | ||
25be5e6c LB |
740 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
741 | if (new_irq != irq) { | |
1597cacb | 742 | printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n", |
25be5e6c LB |
743 | pci_name(dev), irq, new_irq); |
744 | udelay(15); /* unknown if delay really needed */ | |
745 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
746 | } | |
747 | } | |
1597cacb | 748 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 749 | |
1da177e4 LT |
750 | /* |
751 | * VIA VT82C598 has its device ID settable and many BIOSes | |
752 | * set it to the ID of VT82C597 for backward compatibility. | |
753 | * We need to switch it off to be able to recognize the real | |
754 | * type of the chip. | |
755 | */ | |
756 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) | |
757 | { | |
758 | pci_write_config_byte(dev, 0xfc, 0); | |
759 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
760 | } | |
652c538e | 761 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
762 | |
763 | /* | |
764 | * CardBus controllers have a legacy base address that enables them | |
765 | * to respond as i82365 pcmcia controllers. We don't want them to | |
766 | * do this even if the Linux CardBus driver is not loaded, because | |
767 | * the Linux i82365 driver does not (and should not) handle CardBus. | |
768 | */ | |
1597cacb | 769 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 LT |
770 | { |
771 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) | |
772 | return; | |
773 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); | |
774 | } | |
775 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); | |
1597cacb | 776 | DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
1da177e4 LT |
777 | |
778 | /* | |
779 | * Following the PCI ordering rules is optional on the AMD762. I'm not | |
780 | * sure what the designers were smoking but let's not inhale... | |
781 | * | |
782 | * To be fair to AMD, it follows the spec by default, its BIOS people | |
783 | * who turn it off! | |
784 | */ | |
1597cacb | 785 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
786 | { |
787 | u32 pcic; | |
788 | pci_read_config_dword(dev, 0x4C, &pcic); | |
789 | if ((pcic&6)!=6) { | |
790 | pcic |= 6; | |
791 | printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); | |
792 | pci_write_config_dword(dev, 0x4C, pcic); | |
793 | pci_read_config_dword(dev, 0x84, &pcic); | |
794 | pcic |= (1<<23); /* Required in this mode */ | |
795 | pci_write_config_dword(dev, 0x84, pcic); | |
796 | } | |
797 | } | |
652c538e AM |
798 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
799 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); | |
1da177e4 LT |
800 | |
801 | /* | |
802 | * DreamWorks provided workaround for Dunord I-3000 problem | |
803 | * | |
804 | * This card decodes and responds to addresses not apparently | |
805 | * assigned to it. We force a larger allocation to ensure that | |
806 | * nothing gets put too close to it. | |
807 | */ | |
808 | static void __devinit quirk_dunord ( struct pci_dev * dev ) | |
809 | { | |
810 | struct resource *r = &dev->resource [1]; | |
811 | r->start = 0; | |
812 | r->end = 0xffffff; | |
813 | } | |
652c538e | 814 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
815 | |
816 | /* | |
817 | * i82380FB mobile docking controller: its PCI-to-PCI bridge | |
818 | * is subtractive decoding (transparent), and does indicate this | |
819 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 | |
820 | * instead of 0x01. | |
821 | */ | |
822 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) | |
823 | { | |
824 | dev->transparent = 1; | |
825 | } | |
652c538e AM |
826 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
827 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
828 | |
829 | /* | |
830 | * Common misconfiguration of the MediaGX/Geode PCI master that will | |
831 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 | |
832 | * datasheets found at http://www.national.com/ds/GX for info on what | |
833 | * these bits do. <christer@weinigel.se> | |
834 | */ | |
1597cacb | 835 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
836 | { |
837 | u8 reg; | |
838 | pci_read_config_byte(dev, 0x41, ®); | |
839 | if (reg & 2) { | |
840 | reg &= ~2; | |
841 | printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); | |
842 | pci_write_config_byte(dev, 0x41, reg); | |
843 | } | |
844 | } | |
652c538e AM |
845 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
846 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 847 | |
1da177e4 LT |
848 | /* |
849 | * Ensure C0 rev restreaming is off. This is normally done by | |
850 | * the BIOS but in the odd case it is not the results are corruption | |
851 | * hence the presence of a Linux check | |
852 | */ | |
1597cacb | 853 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
854 | { |
855 | u16 config; | |
1da177e4 | 856 | |
44c10138 | 857 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
858 | return; |
859 | pci_read_config_word(pdev, 0x40, &config); | |
860 | if (config & (1<<6)) { | |
861 | config &= ~(1<<6); | |
862 | pci_write_config_word(pdev, 0x40, config); | |
863 | printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); | |
864 | } | |
865 | } | |
652c538e AM |
866 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
867 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); | |
1da177e4 | 868 | |
1da177e4 | 869 | |
ab17443a CH |
870 | static void __devinit quirk_sb600_sata(struct pci_dev *pdev) |
871 | { | |
872 | /* set sb600 sata to ahci mode */ | |
873 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
874 | u8 tmp; | |
875 | ||
876 | pci_read_config_byte(pdev, 0x40, &tmp); | |
877 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
878 | pci_write_config_byte(pdev, 0x9, 1); | |
879 | pci_write_config_byte(pdev, 0xa, 6); | |
880 | pci_write_config_byte(pdev, 0x40, tmp); | |
881 | ||
c9f89475 | 882 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
ab17443a CH |
883 | } |
884 | } | |
885 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata); | |
82377718 | 886 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_sb600_sata); |
ab17443a | 887 | |
1da177e4 LT |
888 | /* |
889 | * Serverworks CSB5 IDE does not fully support native mode | |
890 | */ | |
891 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) | |
892 | { | |
893 | u8 prog; | |
894 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
895 | if (prog & 5) { | |
896 | prog &= ~5; | |
897 | pdev->class &= ~5; | |
898 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 899 | /* PCI layer will sort out resources */ |
1da177e4 LT |
900 | } |
901 | } | |
652c538e | 902 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 LT |
903 | |
904 | /* | |
905 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same | |
906 | */ | |
907 | static void __init quirk_ide_samemode(struct pci_dev *pdev) | |
908 | { | |
909 | u8 prog; | |
910 | ||
911 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
912 | ||
913 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
914 | printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); | |
915 | prog &= ~5; | |
916 | pdev->class &= ~5; | |
917 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
918 | } |
919 | } | |
368c73d4 | 920 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 LT |
921 | |
922 | /* This was originally an Alpha specific thing, but it really fits here. | |
923 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. | |
924 | */ | |
925 | static void __init quirk_eisa_bridge(struct pci_dev *dev) | |
926 | { | |
927 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
928 | } | |
652c538e | 929 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 | 930 | |
7daa0c4f | 931 | |
1da177e4 LT |
932 | /* |
933 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
934 | * is not activated. The myth is that Asus said that they do not want the | |
935 | * users to be irritated by just another PCI Device in the Win98 device | |
936 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors | |
937 | * package 2.7.0 for details) | |
938 | * | |
939 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC | |
940 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 941 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
942 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
943 | * |
944 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
945 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
946 | * was done by SMM code, which could cause unsynchronized concurrent | |
947 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
948 | * should be very careful when adding new entries: if SMM is accessing the | |
949 | * Intel SMBus, this is a very good reason to leave it hidden. | |
1da177e4 | 950 | */ |
9d24a81e | 951 | static int asus_hides_smbus; |
1da177e4 LT |
952 | |
953 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) | |
954 | { | |
955 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
956 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
957 | switch(dev->subsystem_device) { | |
a00db371 | 958 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
959 | case 0x8070: /* P4B */ |
960 | case 0x8088: /* P4B533 */ | |
961 | case 0x1626: /* L3C notebook */ | |
962 | asus_hides_smbus = 1; | |
963 | } | |
2f2d39d2 | 964 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1da177e4 LT |
965 | switch(dev->subsystem_device) { |
966 | case 0x80b1: /* P4GE-V */ | |
967 | case 0x80b2: /* P4PE */ | |
968 | case 0x8093: /* P4B533-V */ | |
969 | asus_hides_smbus = 1; | |
970 | } | |
2f2d39d2 | 971 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1da177e4 LT |
972 | switch(dev->subsystem_device) { |
973 | case 0x8030: /* P4T533 */ | |
974 | asus_hides_smbus = 1; | |
975 | } | |
2f2d39d2 | 976 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
977 | switch (dev->subsystem_device) { |
978 | case 0x8070: /* P4G8X Deluxe */ | |
979 | asus_hides_smbus = 1; | |
980 | } | |
2f2d39d2 | 981 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
982 | switch (dev->subsystem_device) { |
983 | case 0x80c9: /* PU-DLS */ | |
984 | asus_hides_smbus = 1; | |
985 | } | |
2f2d39d2 | 986 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
987 | switch (dev->subsystem_device) { |
988 | case 0x1751: /* M2N notebook */ | |
989 | case 0x1821: /* M5N notebook */ | |
990 | asus_hides_smbus = 1; | |
991 | } | |
2f2d39d2 | 992 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
993 | switch (dev->subsystem_device) { |
994 | case 0x184b: /* W1N notebook */ | |
995 | case 0x186a: /* M6Ne notebook */ | |
996 | asus_hides_smbus = 1; | |
997 | } | |
2f2d39d2 | 998 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
999 | switch (dev->subsystem_device) { |
1000 | case 0x80f2: /* P4P800-X */ | |
1001 | asus_hides_smbus = 1; | |
1002 | } | |
2f2d39d2 | 1003 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1004 | switch (dev->subsystem_device) { |
1005 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1006 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1007 | asus_hides_smbus = 1; |
1008 | } | |
1da177e4 LT |
1009 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1010 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1011 | switch(dev->subsystem_device) { | |
1012 | case 0x088C: /* HP Compaq nc8000 */ | |
1013 | case 0x0890: /* HP Compaq nc6000 */ | |
1014 | asus_hides_smbus = 1; | |
1015 | } | |
2f2d39d2 | 1016 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1017 | switch (dev->subsystem_device) { |
1018 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1019 | case 0x12bd: /* HP D530 */ |
1da177e4 LT |
1020 | asus_hides_smbus = 1; |
1021 | } | |
677cc644 JD |
1022 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1023 | switch (dev->subsystem_device) { | |
1024 | case 0x12bf: /* HP xw4100 */ | |
1025 | asus_hides_smbus = 1; | |
1026 | } | |
2f2d39d2 | 1027 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
3c0a654e | 1028 | switch (dev->subsystem_device) { |
1029 | case 0x099c: /* HP Compaq nx6110 */ | |
1030 | asus_hides_smbus = 1; | |
1031 | } | |
1da177e4 LT |
1032 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1033 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1034 | switch(dev->subsystem_device) { | |
1035 | case 0xC00C: /* Samsung P35 notebook */ | |
1036 | asus_hides_smbus = 1; | |
1037 | } | |
c87f883e RIZ |
1038 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1039 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1040 | switch(dev->subsystem_device) { | |
1041 | case 0x0058: /* Compaq Evo N620c */ | |
1042 | asus_hides_smbus = 1; | |
1043 | } | |
d7698edc | 1044 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
1045 | switch(dev->subsystem_device) { | |
1046 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ | |
1047 | /* Motherboard doesn't have Host bridge | |
1048 | * subvendor/subdevice IDs, therefore checking | |
1049 | * its on-board VGA controller */ | |
1050 | asus_hides_smbus = 1; | |
1051 | } | |
1da177e4 LT |
1052 | } |
1053 | } | |
652c538e AM |
1054 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1055 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1056 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1057 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1058 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1059 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1060 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1061 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1062 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1063 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1064 | ||
1065 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
d7698edc | 1066 | |
1597cacb | 1067 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1068 | { |
1069 | u16 val; | |
1070 | ||
1071 | if (likely(!asus_hides_smbus)) | |
1072 | return; | |
1073 | ||
1074 | pci_read_config_word(dev, 0xF2, &val); | |
1075 | if (val & 0x8) { | |
1076 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1077 | pci_read_config_word(dev, 0xF2, &val); | |
1078 | if (val & 0x8) | |
1079 | printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); | |
1080 | else | |
1081 | printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); | |
1082 | } | |
1083 | } | |
652c538e AM |
1084 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1085 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1086 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1087 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1088 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1089 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1090 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1091 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); | |
1092 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1093 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1094 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1095 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1096 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1097 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb AC |
1098 | |
1099 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
acc06632 M |
1100 | { |
1101 | u32 val, rcba; | |
1102 | void __iomem *base; | |
1103 | ||
1104 | if (likely(!asus_hides_smbus)) | |
1105 | return; | |
1106 | pci_read_config_dword(dev, 0xF0, &rcba); | |
1107 | base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ | |
1108 | if (base == NULL) return; | |
1109 | val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ | |
1110 | writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ | |
1111 | iounmap(base); | |
1112 | printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); | |
1113 | } | |
652c538e AM |
1114 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
1115 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); | |
ce007ea5 | 1116 | |
1da177e4 LT |
1117 | /* |
1118 | * SiS 96x south bridge: BIOS typically hides SMBus device... | |
1119 | */ | |
1597cacb | 1120 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1121 | { |
1122 | u8 val = 0; | |
1da177e4 | 1123 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 MH |
1124 | if (val & 0x10) { |
1125 | printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); | |
1126 | pci_write_config_byte(dev, 0x77, val & ~0x10); | |
1127 | } | |
1da177e4 | 1128 | } |
652c538e AM |
1129 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1130 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1131 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1132 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1133 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); | |
1134 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1135 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1136 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1137 | |
1da177e4 LT |
1138 | /* |
1139 | * ... This is further complicated by the fact that some SiS96x south | |
1140 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1141 | * spotted a compatible north bridge to make sure. | |
1142 | * (pci_find_device doesn't work yet) | |
1143 | * | |
1144 | * We can also enable the sis96x bit in the discovery register.. | |
1145 | */ | |
1da177e4 LT |
1146 | #define SIS_DETECT_REGISTER 0x40 |
1147 | ||
1597cacb | 1148 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1149 | { |
1150 | u8 reg; | |
1151 | u16 devid; | |
1152 | ||
1153 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1154 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1155 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1156 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1157 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1158 | return; | |
1159 | } | |
1160 | ||
1da177e4 | 1161 | /* |
2f5c33b3 MH |
1162 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
1163 | * hand in case it has already been processed. | |
1164 | * (depends on link order, which is apparently not guaranteed) | |
1da177e4 LT |
1165 | */ |
1166 | dev->device = devid; | |
2f5c33b3 | 1167 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1168 | } |
652c538e AM |
1169 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1170 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); | |
1da177e4 | 1171 | |
1da177e4 | 1172 | |
e5548e96 BJD |
1173 | /* |
1174 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1175 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1176 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1177 | * -- bjd | |
1178 | */ | |
1597cacb | 1179 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1180 | { |
1181 | u8 val; | |
1182 | int asus_hides_ac97 = 0; | |
1183 | ||
1184 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1185 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1186 | asus_hides_ac97 = 1; | |
1187 | } | |
1188 | ||
1189 | if (!asus_hides_ac97) | |
1190 | return; | |
1191 | ||
1192 | pci_read_config_byte(dev, 0x50, &val); | |
1193 | if (val & 0xc0) { | |
1194 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1195 | pci_read_config_byte(dev, 0x50, &val); | |
1196 | if (val & 0xc0) | |
1197 | printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); | |
1198 | else | |
1199 | printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); | |
1200 | } | |
1201 | } | |
652c538e AM |
1202 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1203 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); | |
1597cacb | 1204 | |
77967052 | 1205 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1206 | |
1207 | /* | |
1208 | * If we are using libata we can drive this chip properly but must | |
1209 | * do this early on to make the additional device appear during | |
1210 | * the PCI scanning. | |
1211 | */ | |
5ee2ae7f | 1212 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1213 | { |
e34bb370 | 1214 | u32 conf1, conf5, class; |
15e0c694 AC |
1215 | u8 hdr; |
1216 | ||
1217 | /* Only poke fn 0 */ | |
1218 | if (PCI_FUNC(pdev->devfn)) | |
1219 | return; | |
1220 | ||
5ee2ae7f TH |
1221 | pci_read_config_dword(pdev, 0x40, &conf1); |
1222 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1223 | |
5ee2ae7f TH |
1224 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1225 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1226 | ||
1227 | switch (pdev->device) { | |
1228 | case PCI_DEVICE_ID_JMICRON_JMB360: | |
1229 | /* The controller should be in single function ahci mode */ | |
1230 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1231 | break; | |
1232 | ||
1233 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1234 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1235 | /* Redirect IDE second PATA port to the right spot */ | |
1236 | conf5 |= (1 << 24); | |
1237 | /* Fall through */ | |
1238 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1239 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
1240 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ | |
1241 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1242 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1243 | break; |
1244 | ||
1245 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1246 | /* The controller should be in single function IDE mode */ | |
1247 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1248 | break; | |
15e0c694 | 1249 | } |
5ee2ae7f TH |
1250 | |
1251 | pci_write_config_dword(pdev, 0x40, conf1); | |
1252 | pci_write_config_dword(pdev, 0x80, conf5); | |
1253 | ||
1254 | /* Update pdev accordingly */ | |
1255 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1256 | pdev->hdr_type = hdr & 0x7f; | |
1257 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1258 | |
1259 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1260 | pdev->class = class >> 8; | |
15e0c694 | 1261 | } |
5ee2ae7f TH |
1262 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1263 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
1264 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); | |
1265 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); | |
1266 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1267 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
1268 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); | |
1269 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
1270 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); | |
1271 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); | |
1272 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1273 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
15e0c694 AC |
1274 | |
1275 | #endif | |
1276 | ||
1da177e4 LT |
1277 | #ifdef CONFIG_X86_IO_APIC |
1278 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) | |
1279 | { | |
1280 | int i; | |
1281 | ||
1282 | if ((pdev->class >> 8) != 0xff00) | |
1283 | return; | |
1284 | ||
1285 | /* the first BAR is the location of the IO APIC...we must | |
1286 | * not touch this (and it's already covered by the fixmap), so | |
1287 | * forcibly insert it into the resource tree */ | |
1288 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) | |
1289 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1290 | ||
1291 | /* The next five BARs all seem to be rubbish, so just clean | |
1292 | * them out */ | |
1293 | for (i=1; i < 6; i++) { | |
1294 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); | |
1295 | } | |
1296 | ||
1297 | } | |
652c538e | 1298 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1299 | #endif |
1300 | ||
1da177e4 | 1301 | int pcie_mch_quirk; |
c30ca1db | 1302 | EXPORT_SYMBOL(pcie_mch_quirk); |
1da177e4 LT |
1303 | |
1304 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) | |
1305 | { | |
1306 | pcie_mch_quirk = 1; | |
1307 | } | |
652c538e AM |
1308 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1309 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1310 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1311 | |
4602b88d KA |
1312 | |
1313 | /* | |
1314 | * It's possible for the MSI to get corrupted if shpc and acpi | |
1315 | * are used together on certain PXH-based systems. | |
1316 | */ | |
1317 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) | |
1318 | { | |
f5f2b131 EB |
1319 | pci_msi_off(dev); |
1320 | ||
4602b88d KA |
1321 | dev->no_msi = 1; |
1322 | ||
1323 | printk(KERN_WARNING "PCI: PXH quirk detected, " | |
1324 | "disabling MSI for SHPC device\n"); | |
1325 | } | |
1326 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1327 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1328 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1329 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1330 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1331 | ||
ffadcc2f KCA |
1332 | /* |
1333 | * Some Intel PCI Express chipsets have trouble with downstream | |
1334 | * device power management. | |
1335 | */ | |
1336 | static void quirk_intel_pcie_pm(struct pci_dev * dev) | |
1337 | { | |
1338 | pci_pm_d3_delay = 120; | |
1339 | dev->no_d1d2 = 1; | |
1340 | } | |
1341 | ||
1342 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); | |
1343 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1344 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1345 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1346 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1347 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1348 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1349 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1350 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1351 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1352 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1353 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1354 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1355 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1356 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1357 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1358 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1359 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1360 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1361 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1362 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1363 | |
33dced2e SS |
1364 | /* |
1365 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
1366 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
1367 | * Re-allocate the region if needed... | |
1368 | */ | |
1369 | static void __init quirk_tc86c001_ide(struct pci_dev *dev) | |
1370 | { | |
1371 | struct resource *r = &dev->resource[0]; | |
1372 | ||
1373 | if (r->start & 0x8) { | |
1374 | r->start = 0; | |
1375 | r->end = 0xf; | |
1376 | } | |
1377 | } | |
1378 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
1379 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
1380 | quirk_tc86c001_ide); | |
1381 | ||
1da177e4 LT |
1382 | static void __devinit quirk_netmos(struct pci_dev *dev) |
1383 | { | |
1384 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
1385 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
1386 | ||
1387 | /* | |
1388 | * These Netmos parts are multiport serial devices with optional | |
1389 | * parallel ports. Even when parallel ports are present, they | |
1390 | * are identified as class SERIAL, which means the serial driver | |
1391 | * will claim them. To prevent this, mark them as class OTHER. | |
1392 | * These combo devices should be claimed by parport_serial. | |
1393 | * | |
1394 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
1395 | * of parallel ports and <S> is the number of serial ports. | |
1396 | */ | |
1397 | switch (dev->device) { | |
1398 | case PCI_DEVICE_ID_NETMOS_9735: | |
1399 | case PCI_DEVICE_ID_NETMOS_9745: | |
1400 | case PCI_DEVICE_ID_NETMOS_9835: | |
1401 | case PCI_DEVICE_ID_NETMOS_9845: | |
1402 | case PCI_DEVICE_ID_NETMOS_9855: | |
1403 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && | |
1404 | num_parallel) { | |
1405 | printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " | |
1406 | "%u serial); changing class SERIAL to OTHER " | |
1407 | "(use parport_serial)\n", | |
1408 | dev->device, num_parallel, num_serial); | |
1409 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
1410 | (dev->class & 0xff); | |
1411 | } | |
1412 | } | |
1413 | } | |
1414 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); | |
1415 | ||
16a74744 BH |
1416 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
1417 | { | |
1418 | u16 command; | |
16a74744 BH |
1419 | u8 __iomem *csr; |
1420 | u8 cmd_hi; | |
1421 | ||
1422 | switch (dev->device) { | |
1423 | /* PCI IDs taken from drivers/net/e100.c */ | |
1424 | case 0x1029: | |
1425 | case 0x1030 ... 0x1034: | |
1426 | case 0x1038 ... 0x103E: | |
1427 | case 0x1050 ... 0x1057: | |
1428 | case 0x1059: | |
1429 | case 0x1064 ... 0x106B: | |
1430 | case 0x1091 ... 0x1095: | |
1431 | case 0x1209: | |
1432 | case 0x1229: | |
1433 | case 0x2449: | |
1434 | case 0x2459: | |
1435 | case 0x245D: | |
1436 | case 0x27DC: | |
1437 | break; | |
1438 | default: | |
1439 | return; | |
1440 | } | |
1441 | ||
1442 | /* | |
1443 | * Some firmware hands off the e100 with interrupts enabled, | |
1444 | * which can cause a flood of interrupts if packets are | |
1445 | * received before the driver attaches to the device. So | |
1446 | * disable all e100 interrupts here. The driver will | |
1447 | * re-enable them when it's ready. | |
1448 | */ | |
1449 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 1450 | |
1bef7dc0 | 1451 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
1452 | return; |
1453 | ||
1bef7dc0 BH |
1454 | /* Convert from PCI bus to resource space. */ |
1455 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 BH |
1456 | if (!csr) { |
1457 | printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", | |
1458 | pci_name(dev)); | |
1459 | return; | |
1460 | } | |
1461 | ||
1462 | cmd_hi = readb(csr + 3); | |
1463 | if (cmd_hi == 0) { | |
1464 | printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " | |
1465 | "enabled, disabling\n", pci_name(dev)); | |
1466 | writeb(1, csr + 3); | |
1467 | } | |
1468 | ||
1469 | iounmap(csr); | |
1470 | } | |
4e68fc97 | 1471 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
a5312e28 IK |
1472 | |
1473 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) | |
1474 | { | |
1475 | /* rev 1 ncr53c810 chips don't set the class at all which means | |
1476 | * they don't get their resources remapped. Fix that here. | |
1477 | */ | |
1478 | ||
1479 | if (dev->class == PCI_CLASS_NOT_DEFINED) { | |
1480 | printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); | |
1481 | dev->class = PCI_CLASS_STORAGE_SCSI; | |
1482 | } | |
1483 | } | |
1484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
1485 | ||
1da177e4 LT |
1486 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) |
1487 | { | |
1488 | while (f < end) { | |
1489 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && | |
1490 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { | |
1491 | pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); | |
1492 | f->hook(dev); | |
1493 | } | |
1494 | f++; | |
1495 | } | |
1496 | } | |
1497 | ||
1498 | extern struct pci_fixup __start_pci_fixups_early[]; | |
1499 | extern struct pci_fixup __end_pci_fixups_early[]; | |
1500 | extern struct pci_fixup __start_pci_fixups_header[]; | |
1501 | extern struct pci_fixup __end_pci_fixups_header[]; | |
1502 | extern struct pci_fixup __start_pci_fixups_final[]; | |
1503 | extern struct pci_fixup __end_pci_fixups_final[]; | |
1504 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
1505 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
1597cacb AC |
1506 | extern struct pci_fixup __start_pci_fixups_resume[]; |
1507 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
1da177e4 LT |
1508 | |
1509 | ||
1510 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
1511 | { | |
1512 | struct pci_fixup *start, *end; | |
1513 | ||
1514 | switch(pass) { | |
1515 | case pci_fixup_early: | |
1516 | start = __start_pci_fixups_early; | |
1517 | end = __end_pci_fixups_early; | |
1518 | break; | |
1519 | ||
1520 | case pci_fixup_header: | |
1521 | start = __start_pci_fixups_header; | |
1522 | end = __end_pci_fixups_header; | |
1523 | break; | |
1524 | ||
1525 | case pci_fixup_final: | |
1526 | start = __start_pci_fixups_final; | |
1527 | end = __end_pci_fixups_final; | |
1528 | break; | |
1529 | ||
1530 | case pci_fixup_enable: | |
1531 | start = __start_pci_fixups_enable; | |
1532 | end = __end_pci_fixups_enable; | |
1533 | break; | |
1534 | ||
1597cacb AC |
1535 | case pci_fixup_resume: |
1536 | start = __start_pci_fixups_resume; | |
1537 | end = __end_pci_fixups_resume; | |
1538 | break; | |
1539 | ||
1da177e4 LT |
1540 | default: |
1541 | /* stupid compiler warning, you would think with an enum... */ | |
1542 | return; | |
1543 | } | |
1544 | pci_do_fixups(dev, start, end); | |
1545 | } | |
c30ca1db | 1546 | EXPORT_SYMBOL(pci_fixup_device); |
1da177e4 | 1547 | |
9d265124 DY |
1548 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
1549 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) | |
1550 | { | |
1551 | u16 en1k; | |
1552 | u8 io_base_lo, io_limit_lo; | |
1553 | unsigned long base, limit; | |
1554 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1555 | ||
1556 | pci_read_config_word(dev, 0x40, &en1k); | |
1557 | ||
1558 | if (en1k & 0x200) { | |
1559 | printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); | |
1560 | ||
1561 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
1562 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
1563 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1564 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1565 | ||
1566 | if (base <= limit) { | |
1567 | res->start = base; | |
1568 | res->end = limit + 0x3ff; | |
1569 | } | |
1570 | } | |
1571 | } | |
1572 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); | |
1573 | ||
15a260d5 DY |
1574 | /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 |
1575 | * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() | |
1576 | * in drivers/pci/setup-bus.c | |
1577 | */ | |
1578 | static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) | |
1579 | { | |
1580 | u16 en1k, iobl_adr, iobl_adr_1k; | |
1581 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1582 | ||
1583 | pci_read_config_word(dev, 0x40, &en1k); | |
1584 | ||
1585 | if (en1k & 0x200) { | |
1586 | pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); | |
1587 | ||
1588 | iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); | |
1589 | ||
1590 | if (iobl_adr != iobl_adr_1k) { | |
1591 | printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n", | |
1592 | iobl_adr,iobl_adr_1k); | |
1593 | pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); | |
1594 | } | |
1595 | } | |
1596 | } | |
1597 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); | |
1598 | ||
cf34a8e0 BG |
1599 | /* Under some circumstances, AER is not linked with extended capabilities. |
1600 | * Force it to be linked by setting the corresponding control bit in the | |
1601 | * config space. | |
1602 | */ | |
1597cacb | 1603 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
1604 | { |
1605 | uint8_t b; | |
1606 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { | |
1607 | if (!(b & 0x20)) { | |
1608 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
1609 | printk(KERN_INFO | |
1610 | "PCI: Linking AER extended capability on %s\n", | |
1611 | pci_name(dev)); | |
1612 | } | |
1613 | } | |
1614 | } | |
1615 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
1616 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
1597cacb AC |
1617 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1618 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
cf34a8e0 | 1619 | |
53a9bf42 TY |
1620 | static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
1621 | { | |
1622 | /* | |
1623 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
1624 | * which causes unspecified timing errors with a VT6212L on the PCI | |
1625 | * bus leading to USB2.0 packet loss. The defaults are that these | |
1626 | * features are turned off but some BIOSes turn them on. | |
1627 | */ | |
1628 | ||
1629 | uint8_t b; | |
1630 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { | |
1631 | if (b & 0x40) { | |
1632 | /* Turn off PCI Bus Parking */ | |
1633 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
1634 | ||
1635 | /* Turn off PCI Master read caching */ | |
1636 | pci_write_config_byte(dev, 0x72, 0x0); | |
1637 | pci_write_config_byte(dev, 0x75, 0x1); | |
1638 | pci_write_config_byte(dev, 0x77, 0x0); | |
1639 | ||
1640 | printk(KERN_INFO | |
1641 | "PCI: VIA CX700 PCI parking/caching fixup on %s\n", | |
1642 | pci_name(dev)); | |
1643 | } | |
1644 | } | |
1645 | } | |
1646 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); | |
1647 | ||
3f79e107 | 1648 | #ifdef CONFIG_PCI_MSI |
ebdf7d39 TH |
1649 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
1650 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | |
1651 | * some other busses controlled by the chipset even if Linux is not | |
1652 | * aware of it. Instead of setting the flag on all busses in the | |
1653 | * machine, simply disable MSI globally. | |
3f79e107 | 1654 | */ |
ebdf7d39 | 1655 | static void __init quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 1656 | { |
88187dfa ME |
1657 | pci_no_msi(); |
1658 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n"); | |
3f79e107 | 1659 | } |
ebdf7d39 TH |
1660 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
1661 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
1662 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
184b812f | 1663 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
3f79e107 BG |
1664 | |
1665 | /* Disable MSI on chipsets that are known to not support it */ | |
1666 | static void __devinit quirk_disable_msi(struct pci_dev *dev) | |
1667 | { | |
1668 | if (dev->subordinate) { | |
1669 | printk(KERN_WARNING "PCI: MSI quirk detected. " | |
1670 | "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", | |
1671 | pci_name(dev)); | |
1672 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; | |
1673 | } | |
1674 | } | |
1675 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
6397c75c BG |
1676 | |
1677 | /* Go through the list of Hypertransport capabilities and | |
1678 | * return 1 if a HT MSI capability is found and enabled */ | |
1679 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) | |
1680 | { | |
7a380507 ME |
1681 | int pos, ttl = 48; |
1682 | ||
1683 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
1684 | while (pos && ttl--) { | |
1685 | u8 flags; | |
1686 | ||
1687 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
1688 | &flags) == 0) | |
1689 | { | |
1690 | printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n", | |
1691 | flags & HT_MSI_FLAGS_ENABLE ? | |
1692 | "enabled" : "disabled", pci_name(dev)); | |
1693 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; | |
6397c75c | 1694 | } |
7a380507 ME |
1695 | |
1696 | pos = pci_find_next_ht_capability(dev, pos, | |
1697 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
1698 | } |
1699 | return 0; | |
1700 | } | |
1701 | ||
1702 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ | |
1703 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) | |
1704 | { | |
1705 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
1706 | printk(KERN_WARNING "PCI: MSI quirk detected. " | |
1707 | "MSI disabled on chipset %s.\n", | |
1708 | pci_name(dev)); | |
1709 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; | |
1710 | } | |
1711 | } | |
1712 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
1713 | quirk_msi_ht_cap); | |
1d84b542 DM |
1714 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, |
1715 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
1716 | quirk_msi_ht_cap); | |
6397c75c BG |
1717 | |
1718 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. | |
1719 | * MSI are supported if the MSI capability set in any of these mappings. | |
1720 | */ | |
1721 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) | |
1722 | { | |
1723 | struct pci_dev *pdev; | |
1724 | ||
1725 | if (!dev->subordinate) | |
1726 | return; | |
1727 | ||
1728 | /* check HT MSI cap on this chipset and the root one. | |
1729 | * a single one having MSI is enough to be sure that MSI are supported. | |
1730 | */ | |
11f242f0 | 1731 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
1732 | if (!pdev) |
1733 | return; | |
0c875c28 | 1734 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
6397c75c BG |
1735 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
1736 | "MSI disabled on chipset %s.\n", | |
1737 | pci_name(dev)); | |
1738 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; | |
1739 | } | |
11f242f0 | 1740 | pci_dev_put(pdev); |
6397c75c BG |
1741 | } |
1742 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
1743 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 DM |
1744 | |
1745 | static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) | |
1746 | { | |
1747 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
1748 | } | |
1749 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
1750 | PCI_DEVICE_ID_TIGON3_5780, | |
1751 | quirk_msi_intx_disable_bug); | |
1752 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
1753 | PCI_DEVICE_ID_TIGON3_5780S, | |
1754 | quirk_msi_intx_disable_bug); | |
1755 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
1756 | PCI_DEVICE_ID_TIGON3_5714, | |
1757 | quirk_msi_intx_disable_bug); | |
1758 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
1759 | PCI_DEVICE_ID_TIGON3_5714S, | |
1760 | quirk_msi_intx_disable_bug); | |
1761 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
1762 | PCI_DEVICE_ID_TIGON3_5715, | |
1763 | quirk_msi_intx_disable_bug); | |
1764 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
1765 | PCI_DEVICE_ID_TIGON3_5715S, | |
1766 | quirk_msi_intx_disable_bug); | |
1767 | ||
bc38b411 DM |
1768 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
1769 | quirk_msi_intx_disable_bug); | |
1770 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, | |
1771 | quirk_msi_intx_disable_bug); | |
1772 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, | |
1773 | quirk_msi_intx_disable_bug); | |
1774 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, | |
1775 | quirk_msi_intx_disable_bug); | |
1776 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, | |
1777 | quirk_msi_intx_disable_bug); | |
1778 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4395, | |
1779 | quirk_msi_intx_disable_bug); | |
1780 | ||
1781 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
1782 | quirk_msi_intx_disable_bug); | |
1783 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
1784 | quirk_msi_intx_disable_bug); | |
1785 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
1786 | quirk_msi_intx_disable_bug); | |
1787 | ||
3f79e107 | 1788 | #endif /* CONFIG_PCI_MSI */ |