Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for many known PCI hardware | |
3 | * bugs. Devices present only on certain architectures (host | |
4 | * bridges et cetera) should be handled in arch-specific code. | |
5 | * | |
6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. | |
7 | * | |
8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
9 | * | |
7586269c DB |
10 | * Init/reset quirks for USB host controllers should be in the |
11 | * USB quirks file, where their drivers can access reuse it. | |
12 | * | |
1da177e4 LT |
13 | * The bridge optimization stuff has been removed. If you really |
14 | * have a silly BIOS which is unable to set your host bridge right, | |
15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
25be5e6c | 23 | #include <linux/acpi.h> |
bc56b9e0 | 24 | #include "pci.h" |
1da177e4 | 25 | |
bd8481e1 DT |
26 | /* The Mellanox Tavor device gives false positive parity errors |
27 | * Mark this device with a broken_parity_status, to allow | |
28 | * PCI scanning code to "skip" this now blacklisted device. | |
29 | */ | |
30 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) | |
31 | { | |
32 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
33 | } | |
34 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); | |
35 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); | |
36 | ||
1da177e4 LT |
37 | /* Deal with broken BIOS'es that neglect to enable passive release, |
38 | which can cause problems in combination with the 82441FX/PPro MTRRs */ | |
1597cacb | 39 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
40 | { |
41 | struct pci_dev *d = NULL; | |
42 | unsigned char dlc; | |
43 | ||
44 | /* We have to make sure a particular bit is set in the PIIX3 | |
45 | ISA bridge, so we have to go out and find it. */ | |
46 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { | |
47 | pci_read_config_byte(d, 0x82, &dlc); | |
48 | if (!(dlc & 1<<1)) { | |
49 | printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); | |
50 | dlc |= 1<<1; | |
51 | pci_write_config_byte(d, 0x82, dlc); | |
52 | } | |
53 | } | |
54 | } | |
55 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); | |
1597cacb | 56 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); |
1da177e4 LT |
57 | |
58 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround | |
59 | but VIA don't answer queries. If you happen to have good contacts at VIA | |
60 | ask them for me please -- Alan | |
61 | ||
62 | This appears to be BIOS not version dependent. So presumably there is a | |
63 | chipset level fix */ | |
c30ca1db AB |
64 | int isa_dma_bridge_buggy; |
65 | EXPORT_SYMBOL(isa_dma_bridge_buggy); | |
1da177e4 LT |
66 | |
67 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) | |
68 | { | |
69 | if (!isa_dma_bridge_buggy) { | |
70 | isa_dma_bridge_buggy=1; | |
71 | printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); | |
72 | } | |
73 | } | |
74 | /* | |
75 | * Its not totally clear which chipsets are the problematic ones | |
76 | * We know 82C586 and 82C596 variants are affected. | |
77 | */ | |
78 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); | |
79 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); | |
80 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); | |
81 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); | |
82 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); | |
83 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); | |
84 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); | |
85 | ||
86 | int pci_pci_problems; | |
c30ca1db | 87 | EXPORT_SYMBOL(pci_pci_problems); |
1da177e4 LT |
88 | |
89 | /* | |
90 | * Chipsets where PCI->PCI transfers vanish or hang | |
91 | */ | |
92 | static void __devinit quirk_nopcipci(struct pci_dev *dev) | |
93 | { | |
94 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { | |
95 | printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); | |
96 | pci_pci_problems |= PCIPCI_FAIL; | |
97 | } | |
98 | } | |
c30ca1db AB |
99 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); |
100 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); | |
236561e5 AC |
101 | |
102 | static void __devinit quirk_nopciamd(struct pci_dev *dev) | |
103 | { | |
104 | u8 rev; | |
105 | pci_read_config_byte(dev, 0x08, &rev); | |
106 | if (rev == 0x13) { | |
107 | /* Erratum 24 */ | |
108 | printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); | |
109 | pci_pci_problems |= PCIAGP_FAIL; | |
110 | } | |
111 | } | |
236561e5 | 112 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd ); |
1da177e4 LT |
113 | |
114 | /* | |
115 | * Triton requires workarounds to be used by the drivers | |
116 | */ | |
117 | static void __devinit quirk_triton(struct pci_dev *dev) | |
118 | { | |
119 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { | |
120 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
121 | pci_pci_problems |= PCIPCI_TRITON; | |
122 | } | |
123 | } | |
124 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); | |
125 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); | |
126 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); | |
127 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); | |
128 | ||
129 | /* | |
130 | * VIA Apollo KT133 needs PCI latency patch | |
131 | * Made according to a windows driver based patch by George E. Breese | |
132 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
133 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for | |
134 | * the info on which Mr Breese based his work. | |
135 | * | |
136 | * Updated based on further information from the site and also on | |
137 | * information provided by VIA | |
138 | */ | |
1597cacb | 139 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
140 | { |
141 | struct pci_dev *p; | |
142 | u8 rev; | |
143 | u8 busarb; | |
144 | /* Ok we have a potential problem chipset here. Now see if we have | |
145 | a buggy southbridge */ | |
146 | ||
147 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); | |
148 | if (p!=NULL) { | |
149 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); | |
150 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ | |
151 | /* Check for buggy part revisions */ | |
152 | if (rev < 0x40 || rev > 0x42) | |
153 | goto exit; | |
154 | } else { | |
155 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
156 | if (p==NULL) /* No problem parts */ | |
157 | goto exit; | |
158 | pci_read_config_byte(p, PCI_CLASS_REVISION, &rev); | |
159 | /* Check for buggy part revisions */ | |
160 | if (rev < 0x10 || rev > 0x12) | |
161 | goto exit; | |
162 | } | |
163 | ||
164 | /* | |
165 | * Ok we have the problem. Now set the PCI master grant to | |
166 | * occur every master grant. The apparent bug is that under high | |
167 | * PCI load (quite common in Linux of course) you can get data | |
168 | * loss when the CPU is held off the bus for 3 bus master requests | |
169 | * This happens to include the IDE controllers.... | |
170 | * | |
171 | * VIA only apply this fix when an SB Live! is present but under | |
172 | * both Linux and Windows this isnt enough, and we have seen | |
173 | * corruption without SB Live! but with things like 3 UDMA IDE | |
174 | * controllers. So we ignore that bit of the VIA recommendation.. | |
175 | */ | |
176 | ||
177 | pci_read_config_byte(dev, 0x76, &busarb); | |
178 | /* Set bit 4 and bi 5 of byte 76 to 0x01 | |
179 | "Master priority rotation on every PCI master grant */ | |
180 | busarb &= ~(1<<5); | |
181 | busarb |= (1<<4); | |
182 | pci_write_config_byte(dev, 0x76, busarb); | |
183 | printk(KERN_INFO "Applying VIA southbridge workaround.\n"); | |
184 | exit: | |
185 | pci_dev_put(p); | |
186 | } | |
187 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); | |
188 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); | |
189 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); | |
1597cacb AC |
190 | /* Must restore this on a resume from RAM */ |
191 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); | |
192 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); | |
193 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); | |
1da177e4 LT |
194 | |
195 | /* | |
196 | * VIA Apollo VP3 needs ETBF on BT848/878 | |
197 | */ | |
198 | static void __devinit quirk_viaetbf(struct pci_dev *dev) | |
199 | { | |
200 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { | |
201 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
202 | pci_pci_problems |= PCIPCI_VIAETBF; | |
203 | } | |
204 | } | |
205 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); | |
206 | ||
207 | static void __devinit quirk_vsfx(struct pci_dev *dev) | |
208 | { | |
209 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { | |
210 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
211 | pci_pci_problems |= PCIPCI_VSFX; | |
212 | } | |
213 | } | |
214 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); | |
215 | ||
216 | /* | |
217 | * Ali Magik requires workarounds to be used by the drivers | |
218 | * that DMA to AGP space. Latency must be set to 0xA and triton | |
219 | * workaround applied too | |
220 | * [Info kindly provided by ALi] | |
221 | */ | |
222 | static void __init quirk_alimagik(struct pci_dev *dev) | |
223 | { | |
224 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { | |
225 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
226 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; | |
227 | } | |
228 | } | |
229 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); | |
230 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); | |
231 | ||
232 | /* | |
233 | * Natoma has some interesting boundary conditions with Zoran stuff | |
234 | * at least | |
235 | */ | |
236 | static void __devinit quirk_natoma(struct pci_dev *dev) | |
237 | { | |
238 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { | |
239 | printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); | |
240 | pci_pci_problems |= PCIPCI_NATOMA; | |
241 | } | |
242 | } | |
243 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); | |
244 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); | |
245 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); | |
246 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); | |
247 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); | |
248 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); | |
249 | ||
250 | /* | |
251 | * This chip can cause PCI parity errors if config register 0xA0 is read | |
252 | * while DMAs are occurring. | |
253 | */ | |
254 | static void __devinit quirk_citrine(struct pci_dev *dev) | |
255 | { | |
256 | dev->cfg_size = 0xA0; | |
257 | } | |
258 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); | |
259 | ||
260 | /* | |
261 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. | |
262 | * If it's needed, re-allocate the region. | |
263 | */ | |
264 | static void __devinit quirk_s3_64M(struct pci_dev *dev) | |
265 | { | |
266 | struct resource *r = &dev->resource[0]; | |
267 | ||
268 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
269 | r->start = 0; | |
270 | r->end = 0x3ffffff; | |
271 | } | |
272 | } | |
273 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); | |
274 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); | |
275 | ||
6693e74a LT |
276 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
277 | unsigned size, int nr, const char *name) | |
1da177e4 LT |
278 | { |
279 | region &= ~(size-1); | |
280 | if (region) { | |
085ae41f | 281 | struct pci_bus_region bus_region; |
1da177e4 LT |
282 | struct resource *res = dev->resource + nr; |
283 | ||
284 | res->name = pci_name(dev); | |
285 | res->start = region; | |
286 | res->end = region + size - 1; | |
287 | res->flags = IORESOURCE_IO; | |
085ae41f DM |
288 | |
289 | /* Convert from PCI bus to resource space. */ | |
290 | bus_region.start = res->start; | |
291 | bus_region.end = res->end; | |
292 | pcibios_bus_to_resource(dev, res, &bus_region); | |
293 | ||
1da177e4 | 294 | pci_claim_resource(dev, nr); |
6693e74a | 295 | printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); |
1da177e4 LT |
296 | } |
297 | } | |
298 | ||
299 | /* | |
300 | * ATI Northbridge setups MCE the processor if you even | |
301 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 | |
302 | */ | |
303 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) | |
304 | { | |
305 | printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); | |
306 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ | |
307 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
308 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
309 | } | |
310 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); | |
311 | ||
312 | /* | |
313 | * Let's make the southbridge information explicit instead | |
314 | * of having to worry about people probing the ACPI areas, | |
315 | * for example.. (Yes, it happens, and if you read the wrong | |
316 | * ACPI register it will put the machine to sleep with no | |
317 | * way of waking it up again. Bummer). | |
318 | * | |
319 | * ALI M7101: Two IO regions pointed to by words at | |
320 | * 0xE0 (64 bytes of ACPI registers) | |
321 | * 0xE2 (32 bytes of SMB registers) | |
322 | */ | |
323 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) | |
324 | { | |
325 | u16 region; | |
326 | ||
327 | pci_read_config_word(dev, 0xE0, ®ion); | |
6693e74a | 328 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
1da177e4 | 329 | pci_read_config_word(dev, 0xE2, ®ion); |
6693e74a | 330 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
1da177e4 LT |
331 | } |
332 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); | |
333 | ||
6693e74a LT |
334 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
335 | { | |
336 | u32 devres; | |
337 | u32 mask, size, base; | |
338 | ||
339 | pci_read_config_dword(dev, port, &devres); | |
340 | if ((devres & enable) != enable) | |
341 | return; | |
342 | mask = (devres >> 16) & 15; | |
343 | base = devres & 0xffff; | |
344 | size = 16; | |
345 | for (;;) { | |
346 | unsigned bit = size >> 1; | |
347 | if ((bit & mask) == bit) | |
348 | break; | |
349 | size = bit; | |
350 | } | |
351 | /* | |
352 | * For now we only print it out. Eventually we'll want to | |
353 | * reserve it (at least if it's in the 0x1000+ range), but | |
354 | * let's get enough confirmation reports first. | |
355 | */ | |
356 | base &= -size; | |
357 | printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); | |
358 | } | |
359 | ||
360 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
361 | { | |
362 | u32 devres; | |
363 | u32 mask, size, base; | |
364 | ||
365 | pci_read_config_dword(dev, port, &devres); | |
366 | if ((devres & enable) != enable) | |
367 | return; | |
368 | base = devres & 0xffff0000; | |
369 | mask = (devres & 0x3f) << 16; | |
370 | size = 128 << 16; | |
371 | for (;;) { | |
372 | unsigned bit = size >> 1; | |
373 | if ((bit & mask) == bit) | |
374 | break; | |
375 | size = bit; | |
376 | } | |
377 | /* | |
378 | * For now we only print it out. Eventually we'll want to | |
379 | * reserve it, but let's get enough confirmation reports first. | |
380 | */ | |
381 | base &= -size; | |
382 | printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); | |
383 | } | |
384 | ||
1da177e4 LT |
385 | /* |
386 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
387 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 388 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 389 | * and a few strange programmable PIIX4 device resources. |
1da177e4 LT |
390 | */ |
391 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) | |
392 | { | |
6693e74a | 393 | u32 region, res_a; |
1da177e4 LT |
394 | |
395 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 396 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
1da177e4 | 397 | pci_read_config_dword(dev, 0x90, ®ion); |
08db2a70 | 398 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
6693e74a LT |
399 | |
400 | /* Device resource A has enables for some of the other ones */ | |
401 | pci_read_config_dword(dev, 0x5c, &res_a); | |
402 | ||
403 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
404 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
405 | ||
406 | /* Device resource D is just bitfields for static resources */ | |
407 | ||
408 | /* Device 12 enabled? */ | |
409 | if (res_a & (1 << 29)) { | |
410 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
411 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
412 | } | |
413 | /* Device 13 enabled? */ | |
414 | if (res_a & (1 << 30)) { | |
415 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
416 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
417 | } | |
418 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
419 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 LT |
420 | } |
421 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); | |
c6764664 | 422 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); |
1da177e4 LT |
423 | |
424 | /* | |
425 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
426 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
427 | * 0x58 (64 bytes of GPIO I/O space) | |
428 | */ | |
429 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) | |
430 | { | |
431 | u32 region; | |
432 | ||
433 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 434 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO"); |
1da177e4 LT |
435 | |
436 | pci_read_config_dword(dev, 0x58, ®ion); | |
6693e74a | 437 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); |
1da177e4 LT |
438 | } |
439 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); | |
440 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); | |
441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); | |
442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); | |
443 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); | |
444 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); | |
445 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); | |
446 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); | |
447 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); | |
3aa8c4fe | 448 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); |
1da177e4 | 449 | |
2cea752f M |
450 | static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) |
451 | { | |
452 | u32 region; | |
453 | ||
454 | pci_read_config_dword(dev, 0x40, ®ion); | |
455 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO"); | |
456 | ||
457 | pci_read_config_dword(dev, 0x48, ®ion); | |
458 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); | |
459 | } | |
65ae4ddd | 460 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); |
2cea752f | 461 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); |
bacedce3 DR |
462 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi ); |
463 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi ); | |
464 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi ); | |
465 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi ); | |
466 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi ); | |
467 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi ); | |
2cea752f | 468 | |
1da177e4 LT |
469 | /* |
470 | * VIA ACPI: One IO region pointed to by longword at | |
471 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
472 | */ | |
473 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) | |
474 | { | |
475 | u8 rev; | |
476 | u32 region; | |
477 | ||
478 | pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev); | |
479 | if (rev & 0x10) { | |
480 | pci_read_config_dword(dev, 0x48, ®ion); | |
481 | region &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 482 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
1da177e4 LT |
483 | } |
484 | } | |
485 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); | |
486 | ||
487 | /* | |
488 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
489 | * 0x48 (256 bytes of ACPI registers) | |
490 | * 0x70 (128 bytes of hardware monitoring register) | |
491 | * 0x90 (16 bytes of SMB registers) | |
492 | */ | |
493 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) | |
494 | { | |
495 | u16 hm; | |
496 | u32 smb; | |
497 | ||
498 | quirk_vt82c586_acpi(dev); | |
499 | ||
500 | pci_read_config_word(dev, 0x70, &hm); | |
501 | hm &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 502 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
1da177e4 LT |
503 | |
504 | pci_read_config_dword(dev, 0x90, &smb); | |
505 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 506 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
1da177e4 LT |
507 | } |
508 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); | |
509 | ||
6d85f29b IK |
510 | /* |
511 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
512 | * 0x88 (128 bytes of power management registers) | |
513 | * 0xd0 (16 bytes of SMB registers) | |
514 | */ | |
515 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) | |
516 | { | |
517 | u16 pm, smb; | |
518 | ||
519 | pci_read_config_word(dev, 0x88, &pm); | |
520 | pm &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 521 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
6d85f29b IK |
522 | |
523 | pci_read_config_word(dev, 0xd0, &smb); | |
524 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 525 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
6d85f29b IK |
526 | } |
527 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
528 | ||
1da177e4 LT |
529 | |
530 | #ifdef CONFIG_X86_IO_APIC | |
531 | ||
532 | #include <asm/io_apic.h> | |
533 | ||
534 | /* | |
535 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
536 | * devices to the external APIC. | |
537 | * | |
538 | * TODO: When we have device-specific interrupt routers, | |
539 | * this code will go away from quirks. | |
540 | */ | |
1597cacb | 541 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
542 | { |
543 | u8 tmp; | |
544 | ||
545 | if (nr_ioapics < 1) | |
546 | tmp = 0; /* nothing routed to external APIC */ | |
547 | else | |
548 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
549 | ||
550 | printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", | |
551 | tmp == 0 ? "Disa" : "Ena"); | |
552 | ||
553 | /* Offset 0x58: External APIC IRQ output control */ | |
554 | pci_write_config_byte (dev, 0x58, tmp); | |
555 | } | |
556 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); | |
1597cacb | 557 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); |
1da177e4 | 558 | |
a1740913 KW |
559 | /* |
560 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. | |
561 | * This leads to doubled level interrupt rates. | |
562 | * Set this bit to get rid of cycle wastage. | |
563 | * Otherwise uncritical. | |
564 | */ | |
1597cacb | 565 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
566 | { |
567 | u8 misc_control2; | |
568 | #define BYPASS_APIC_DEASSERT 8 | |
569 | ||
570 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
571 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
572 | printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); | |
573 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); | |
574 | } | |
575 | } | |
576 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
1597cacb | 577 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 578 | |
1da177e4 LT |
579 | /* |
580 | * The AMD io apic can hang the box when an apic irq is masked. | |
581 | * We check all revs >= B0 (yet not in the pre production!) as the bug | |
582 | * is currently marked NoFix | |
583 | * | |
584 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 585 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4 LT |
586 | * of course. However the advice is demonstrably good even if so.. |
587 | */ | |
588 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) | |
589 | { | |
590 | u8 rev; | |
591 | ||
592 | pci_read_config_byte(dev, PCI_REVISION_ID, &rev); | |
593 | if (rev >= 0x02) { | |
236561e5 | 594 | printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
1da177e4 LT |
595 | printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); |
596 | } | |
597 | } | |
598 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); | |
599 | ||
600 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) | |
601 | { | |
602 | if (dev->devfn == 0 && dev->bus->number == 0) | |
603 | sis_apic_bug = 1; | |
604 | } | |
605 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); | |
606 | ||
1da177e4 LT |
607 | #define AMD8131_revA0 0x01 |
608 | #define AMD8131_revB0 0x11 | |
609 | #define AMD8131_MISC 0x40 | |
610 | #define AMD8131_NIOAMODE_BIT 0 | |
1597cacb | 611 | static void quirk_amd_8131_ioapic(struct pci_dev *dev) |
1da177e4 LT |
612 | { |
613 | unsigned char revid, tmp; | |
614 | ||
1da177e4 LT |
615 | if (nr_ioapics == 0) |
616 | return; | |
617 | ||
618 | pci_read_config_byte(dev, PCI_REVISION_ID, &revid); | |
619 | if (revid == AMD8131_revA0 || revid == AMD8131_revB0) { | |
620 | printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); | |
621 | pci_read_config_byte( dev, AMD8131_MISC, &tmp); | |
622 | tmp &= ~(1 << AMD8131_NIOAMODE_BIT); | |
623 | pci_write_config_byte( dev, AMD8131_MISC, tmp); | |
624 | } | |
625 | } | |
5da594b1 | 626 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
1597cacb | 627 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic); |
1da177e4 LT |
628 | #endif /* CONFIG_X86_IO_APIC */ |
629 | ||
630 | ||
1da177e4 LT |
631 | /* |
632 | * FIXME: it is questionable that quirk_via_acpi | |
633 | * is needed. It shows up as an ISA bridge, and does not | |
634 | * support the PCI_INTERRUPT_LINE register at all. Therefore | |
635 | * it seems like setting the pci_dev's 'irq' to the | |
636 | * value of the ACPI SCI interrupt is only done for convenience. | |
637 | * -jgarzik | |
638 | */ | |
639 | static void __devinit quirk_via_acpi(struct pci_dev *d) | |
640 | { | |
641 | /* | |
642 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 | |
643 | */ | |
644 | u8 irq; | |
645 | pci_read_config_byte(d, 0x42, &irq); | |
646 | irq &= 0xf; | |
647 | if (irq && (irq != 2)) | |
648 | d->irq = irq; | |
649 | } | |
650 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); | |
651 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); | |
652 | ||
09d6029f DD |
653 | |
654 | /* | |
1597cacb | 655 | * VIA bridges which have VLink |
09d6029f | 656 | */ |
1597cacb | 657 | |
c06bb5d4 JD |
658 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
659 | ||
660 | static void quirk_via_bridge(struct pci_dev *dev) | |
661 | { | |
662 | /* See what bridge we have and find the device ranges */ | |
663 | switch (dev->device) { | |
664 | case PCI_DEVICE_ID_VIA_82C686: | |
cb7468ef JD |
665 | /* The VT82C686 is special, it attaches to PCI and can have |
666 | any device number. All its subdevices are functions of | |
667 | that single device. */ | |
668 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); | |
669 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
670 | break; |
671 | case PCI_DEVICE_ID_VIA_8237: | |
672 | case PCI_DEVICE_ID_VIA_8237A: | |
673 | via_vlink_dev_lo = 15; | |
674 | break; | |
675 | case PCI_DEVICE_ID_VIA_8235: | |
676 | via_vlink_dev_lo = 16; | |
677 | break; | |
678 | case PCI_DEVICE_ID_VIA_8231: | |
679 | case PCI_DEVICE_ID_VIA_8233_0: | |
680 | case PCI_DEVICE_ID_VIA_8233A: | |
681 | case PCI_DEVICE_ID_VIA_8233C_0: | |
682 | via_vlink_dev_lo = 17; | |
683 | break; | |
684 | } | |
685 | } | |
686 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
687 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
688 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
689 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
690 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
691 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
692 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
693 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 694 | |
1597cacb AC |
695 | /** |
696 | * quirk_via_vlink - VIA VLink IRQ number update | |
697 | * @dev: PCI device | |
698 | * | |
699 | * If the device we are dealing with is on a PIC IRQ we need to | |
700 | * ensure that the IRQ line register which usually is not relevant | |
701 | * for PCI cards, is actually written so that interrupts get sent | |
c06bb5d4 JD |
702 | * to the right place. |
703 | * We only do this on systems where a VIA south bridge was detected, | |
704 | * and only for VIA devices on the motherboard (see quirk_via_bridge | |
705 | * above). | |
1597cacb AC |
706 | */ |
707 | ||
708 | static void quirk_via_vlink(struct pci_dev *dev) | |
25be5e6c LB |
709 | { |
710 | u8 irq, new_irq; | |
711 | ||
c06bb5d4 JD |
712 | /* Check if we have VLink at all */ |
713 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
714 | return; |
715 | ||
716 | new_irq = dev->irq; | |
717 | ||
718 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
719 | if (!new_irq || new_irq > 15) | |
720 | return; | |
721 | ||
1597cacb | 722 | /* Internal device ? */ |
c06bb5d4 JD |
723 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
724 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
725 | return; |
726 | ||
727 | /* This is an internal VLink device on a PIC interrupt. The BIOS | |
728 | ought to have set this but may not have, so we redo it */ | |
729 | ||
25be5e6c LB |
730 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
731 | if (new_irq != irq) { | |
1597cacb | 732 | printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n", |
25be5e6c LB |
733 | pci_name(dev), irq, new_irq); |
734 | udelay(15); /* unknown if delay really needed */ | |
735 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
736 | } | |
737 | } | |
1597cacb | 738 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 739 | |
1da177e4 LT |
740 | /* |
741 | * VIA VT82C598 has its device ID settable and many BIOSes | |
742 | * set it to the ID of VT82C597 for backward compatibility. | |
743 | * We need to switch it off to be able to recognize the real | |
744 | * type of the chip. | |
745 | */ | |
746 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) | |
747 | { | |
748 | pci_write_config_byte(dev, 0xfc, 0); | |
749 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
750 | } | |
751 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); | |
752 | ||
753 | /* | |
754 | * CardBus controllers have a legacy base address that enables them | |
755 | * to respond as i82365 pcmcia controllers. We don't want them to | |
756 | * do this even if the Linux CardBus driver is not loaded, because | |
757 | * the Linux i82365 driver does not (and should not) handle CardBus. | |
758 | */ | |
1597cacb | 759 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 LT |
760 | { |
761 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) | |
762 | return; | |
763 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); | |
764 | } | |
765 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); | |
1597cacb | 766 | DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
1da177e4 LT |
767 | |
768 | /* | |
769 | * Following the PCI ordering rules is optional on the AMD762. I'm not | |
770 | * sure what the designers were smoking but let's not inhale... | |
771 | * | |
772 | * To be fair to AMD, it follows the spec by default, its BIOS people | |
773 | * who turn it off! | |
774 | */ | |
1597cacb | 775 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
776 | { |
777 | u32 pcic; | |
778 | pci_read_config_dword(dev, 0x4C, &pcic); | |
779 | if ((pcic&6)!=6) { | |
780 | pcic |= 6; | |
781 | printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); | |
782 | pci_write_config_dword(dev, 0x4C, pcic); | |
783 | pci_read_config_dword(dev, 0x84, &pcic); | |
784 | pcic |= (1<<23); /* Required in this mode */ | |
785 | pci_write_config_dword(dev, 0x84, pcic); | |
786 | } | |
787 | } | |
788 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); | |
1597cacb | 789 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); |
1da177e4 LT |
790 | |
791 | /* | |
792 | * DreamWorks provided workaround for Dunord I-3000 problem | |
793 | * | |
794 | * This card decodes and responds to addresses not apparently | |
795 | * assigned to it. We force a larger allocation to ensure that | |
796 | * nothing gets put too close to it. | |
797 | */ | |
798 | static void __devinit quirk_dunord ( struct pci_dev * dev ) | |
799 | { | |
800 | struct resource *r = &dev->resource [1]; | |
801 | r->start = 0; | |
802 | r->end = 0xffffff; | |
803 | } | |
804 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); | |
805 | ||
806 | /* | |
807 | * i82380FB mobile docking controller: its PCI-to-PCI bridge | |
808 | * is subtractive decoding (transparent), and does indicate this | |
809 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 | |
810 | * instead of 0x01. | |
811 | */ | |
812 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) | |
813 | { | |
814 | dev->transparent = 1; | |
815 | } | |
816 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); | |
817 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); | |
818 | ||
819 | /* | |
820 | * Common misconfiguration of the MediaGX/Geode PCI master that will | |
821 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 | |
822 | * datasheets found at http://www.national.com/ds/GX for info on what | |
823 | * these bits do. <christer@weinigel.se> | |
824 | */ | |
1597cacb | 825 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
826 | { |
827 | u8 reg; | |
828 | pci_read_config_byte(dev, 0x41, ®); | |
829 | if (reg & 2) { | |
830 | reg &= ~2; | |
831 | printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); | |
832 | pci_write_config_byte(dev, 0x41, reg); | |
833 | } | |
834 | } | |
835 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); | |
1597cacb | 836 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); |
1da177e4 | 837 | |
1da177e4 LT |
838 | /* |
839 | * Ensure C0 rev restreaming is off. This is normally done by | |
840 | * the BIOS but in the odd case it is not the results are corruption | |
841 | * hence the presence of a Linux check | |
842 | */ | |
1597cacb | 843 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
844 | { |
845 | u16 config; | |
846 | u8 rev; | |
847 | ||
848 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); | |
849 | if (rev != 0x04) /* Only C0 requires this */ | |
850 | return; | |
851 | pci_read_config_word(pdev, 0x40, &config); | |
852 | if (config & (1<<6)) { | |
853 | config &= ~(1<<6); | |
854 | pci_write_config_word(pdev, 0x40, config); | |
855 | printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); | |
856 | } | |
857 | } | |
858 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); | |
1597cacb | 859 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); |
1da177e4 | 860 | |
1da177e4 | 861 | |
ab17443a CH |
862 | static void __devinit quirk_sb600_sata(struct pci_dev *pdev) |
863 | { | |
864 | /* set sb600 sata to ahci mode */ | |
865 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) { | |
866 | u8 tmp; | |
867 | ||
868 | pci_read_config_byte(pdev, 0x40, &tmp); | |
869 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
870 | pci_write_config_byte(pdev, 0x9, 1); | |
871 | pci_write_config_byte(pdev, 0xa, 6); | |
872 | pci_write_config_byte(pdev, 0x40, tmp); | |
873 | ||
874 | pdev->class = 0x010601; | |
875 | } | |
876 | } | |
877 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_sb600_sata); | |
878 | ||
1da177e4 LT |
879 | /* |
880 | * Serverworks CSB5 IDE does not fully support native mode | |
881 | */ | |
882 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) | |
883 | { | |
884 | u8 prog; | |
885 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
886 | if (prog & 5) { | |
887 | prog &= ~5; | |
888 | pdev->class &= ~5; | |
889 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 890 | /* PCI layer will sort out resources */ |
1da177e4 LT |
891 | } |
892 | } | |
368c73d4 | 893 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); |
1da177e4 LT |
894 | |
895 | /* | |
896 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same | |
897 | */ | |
898 | static void __init quirk_ide_samemode(struct pci_dev *pdev) | |
899 | { | |
900 | u8 prog; | |
901 | ||
902 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
903 | ||
904 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
905 | printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); | |
906 | prog &= ~5; | |
907 | pdev->class &= ~5; | |
908 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
909 | } |
910 | } | |
368c73d4 | 911 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 LT |
912 | |
913 | /* This was originally an Alpha specific thing, but it really fits here. | |
914 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. | |
915 | */ | |
916 | static void __init quirk_eisa_bridge(struct pci_dev *dev) | |
917 | { | |
918 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
919 | } | |
920 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); | |
921 | ||
7daa0c4f JG |
922 | /* |
923 | * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled | |
924 | * when a PCI-Soundcard is added. The BIOS only gives Options | |
925 | * "Disabled" and "AUTO". This Quirk Sets the corresponding | |
926 | * Register-Value to enable the Soundcard. | |
bd91fde9 CW |
927 | * |
928 | * FIXME: Presently this quirk will run on anything that has an 8237 | |
929 | * which isn't correct, we need to check DMI tables or something in | |
930 | * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it | |
931 | * runs everywhere at present we suppress the printk output in most | |
932 | * irrelevant cases. | |
7daa0c4f | 933 | */ |
1597cacb | 934 | static void k8t_sound_hostbridge(struct pci_dev *dev) |
7daa0c4f JG |
935 | { |
936 | unsigned char val; | |
937 | ||
7daa0c4f JG |
938 | pci_read_config_byte(dev, 0x50, &val); |
939 | if (val == 0x88 || val == 0xc8) { | |
bd91fde9 CW |
940 | /* Assume it's probably a MSI-K8T-Neo2Fir */ |
941 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n"); | |
7daa0c4f JG |
942 | pci_write_config_byte(dev, 0x50, val & (~0x40)); |
943 | ||
944 | /* Verify the Change for Status output */ | |
945 | pci_read_config_byte(dev, 0x50, &val); | |
946 | if (val & 0x40) | |
bd91fde9 | 947 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard still off\n"); |
7daa0c4f | 948 | else |
bd91fde9 | 949 | printk(KERN_INFO "PCI: MSI-K8T-Neo2Fir, soundcard on\n"); |
7daa0c4f | 950 | } |
7daa0c4f JG |
951 | } |
952 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); | |
1597cacb | 953 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge); |
7daa0c4f | 954 | |
1da177e4 LT |
955 | /* |
956 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
957 | * is not activated. The myth is that Asus said that they do not want the | |
958 | * users to be irritated by just another PCI Device in the Win98 device | |
959 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors | |
960 | * package 2.7.0 for details) | |
961 | * | |
962 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC | |
963 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
964 | * becomes necessary to do this tweak in two steps -- I've chosen the Host | |
965 | * bridge as trigger. | |
966 | */ | |
9d24a81e | 967 | static int asus_hides_smbus; |
1da177e4 LT |
968 | |
969 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) | |
970 | { | |
971 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
972 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
973 | switch(dev->subsystem_device) { | |
a00db371 | 974 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
975 | case 0x8070: /* P4B */ |
976 | case 0x8088: /* P4B533 */ | |
977 | case 0x1626: /* L3C notebook */ | |
978 | asus_hides_smbus = 1; | |
979 | } | |
2f2d39d2 | 980 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1da177e4 LT |
981 | switch(dev->subsystem_device) { |
982 | case 0x80b1: /* P4GE-V */ | |
983 | case 0x80b2: /* P4PE */ | |
984 | case 0x8093: /* P4B533-V */ | |
985 | asus_hides_smbus = 1; | |
986 | } | |
2f2d39d2 | 987 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1da177e4 LT |
988 | switch(dev->subsystem_device) { |
989 | case 0x8030: /* P4T533 */ | |
990 | asus_hides_smbus = 1; | |
991 | } | |
2f2d39d2 | 992 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
993 | switch (dev->subsystem_device) { |
994 | case 0x8070: /* P4G8X Deluxe */ | |
995 | asus_hides_smbus = 1; | |
996 | } | |
2f2d39d2 | 997 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
998 | switch (dev->subsystem_device) { |
999 | case 0x80c9: /* PU-DLS */ | |
1000 | asus_hides_smbus = 1; | |
1001 | } | |
2f2d39d2 | 1002 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1003 | switch (dev->subsystem_device) { |
1004 | case 0x1751: /* M2N notebook */ | |
1005 | case 0x1821: /* M5N notebook */ | |
1006 | asus_hides_smbus = 1; | |
1007 | } | |
2f2d39d2 | 1008 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1009 | switch (dev->subsystem_device) { |
1010 | case 0x184b: /* W1N notebook */ | |
1011 | case 0x186a: /* M6Ne notebook */ | |
1012 | asus_hides_smbus = 1; | |
1013 | } | |
2f2d39d2 | 1014 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1015 | switch (dev->subsystem_device) { |
1016 | case 0x80f2: /* P4P800-X */ | |
1017 | asus_hides_smbus = 1; | |
1018 | } | |
2f2d39d2 | 1019 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1020 | switch (dev->subsystem_device) { |
1021 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1022 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1023 | asus_hides_smbus = 1; |
1024 | } | |
1da177e4 LT |
1025 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1026 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1027 | switch(dev->subsystem_device) { | |
1028 | case 0x088C: /* HP Compaq nc8000 */ | |
1029 | case 0x0890: /* HP Compaq nc6000 */ | |
1030 | asus_hides_smbus = 1; | |
1031 | } | |
2f2d39d2 | 1032 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1033 | switch (dev->subsystem_device) { |
1034 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1035 | case 0x12bd: /* HP D530 */ |
1da177e4 LT |
1036 | asus_hides_smbus = 1; |
1037 | } | |
2f2d39d2 | 1038 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
3c0a654e | 1039 | switch (dev->subsystem_device) { |
1040 | case 0x099c: /* HP Compaq nx6110 */ | |
1041 | asus_hides_smbus = 1; | |
1042 | } | |
1da177e4 LT |
1043 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) { |
1044 | if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) | |
1045 | switch(dev->subsystem_device) { | |
1046 | case 0x0001: /* Toshiba Satellite A40 */ | |
1047 | asus_hides_smbus = 1; | |
1048 | } | |
2f2d39d2 | 1049 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
e96e2f14 DG |
1050 | switch(dev->subsystem_device) { |
1051 | case 0x0001: /* Toshiba Tecra M2 */ | |
1052 | asus_hides_smbus = 1; | |
1053 | } | |
1da177e4 LT |
1054 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1055 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1056 | switch(dev->subsystem_device) { | |
1057 | case 0xC00C: /* Samsung P35 notebook */ | |
1058 | asus_hides_smbus = 1; | |
1059 | } | |
c87f883e RIZ |
1060 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1061 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1062 | switch(dev->subsystem_device) { | |
1063 | case 0x0058: /* Compaq Evo N620c */ | |
1064 | asus_hides_smbus = 1; | |
1065 | } | |
1da177e4 LT |
1066 | } |
1067 | } | |
1068 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); | |
1069 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); | |
1070 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); | |
1071 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); | |
1072 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); | |
321311af | 1073 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); |
1da177e4 LT |
1074 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); |
1075 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); | |
acc06632 | 1076 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); |
1da177e4 | 1077 | |
1597cacb | 1078 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1079 | { |
1080 | u16 val; | |
1081 | ||
1082 | if (likely(!asus_hides_smbus)) | |
1083 | return; | |
1084 | ||
1085 | pci_read_config_word(dev, 0xF2, &val); | |
1086 | if (val & 0x8) { | |
1087 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1088 | pci_read_config_word(dev, 0xF2, &val); | |
1089 | if (val & 0x8) | |
1090 | printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); | |
1091 | else | |
1092 | printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); | |
1093 | } | |
1094 | } | |
1095 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); | |
1096 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); | |
321311af | 1097 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); |
1da177e4 LT |
1098 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); |
1099 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); | |
1100 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); | |
1597cacb AC |
1101 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); |
1102 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); | |
1103 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); | |
1104 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); | |
1105 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); | |
1106 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); | |
1107 | ||
1108 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
acc06632 M |
1109 | { |
1110 | u32 val, rcba; | |
1111 | void __iomem *base; | |
1112 | ||
1113 | if (likely(!asus_hides_smbus)) | |
1114 | return; | |
1115 | pci_read_config_dword(dev, 0xF0, &rcba); | |
1116 | base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */ | |
1117 | if (base == NULL) return; | |
1118 | val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ | |
1119 | writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ | |
1120 | iounmap(base); | |
1121 | printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); | |
1122 | } | |
1123 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); | |
1597cacb | 1124 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); |
ce007ea5 | 1125 | |
1da177e4 LT |
1126 | /* |
1127 | * SiS 96x south bridge: BIOS typically hides SMBus device... | |
1128 | */ | |
1597cacb | 1129 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1130 | { |
1131 | u8 val = 0; | |
1da177e4 | 1132 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 MH |
1133 | if (val & 0x10) { |
1134 | printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); | |
1135 | pci_write_config_byte(dev, 0x77, val & ~0x10); | |
1136 | } | |
1da177e4 | 1137 | } |
c30ca1db AB |
1138 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); |
1139 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); | |
1140 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); | |
1141 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); | |
1142 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); | |
1143 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); | |
1144 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); | |
1145 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); | |
1da177e4 | 1146 | |
1da177e4 LT |
1147 | /* |
1148 | * ... This is further complicated by the fact that some SiS96x south | |
1149 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1150 | * spotted a compatible north bridge to make sure. | |
1151 | * (pci_find_device doesn't work yet) | |
1152 | * | |
1153 | * We can also enable the sis96x bit in the discovery register.. | |
1154 | */ | |
1da177e4 LT |
1155 | #define SIS_DETECT_REGISTER 0x40 |
1156 | ||
1597cacb | 1157 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1158 | { |
1159 | u8 reg; | |
1160 | u16 devid; | |
1161 | ||
1162 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1163 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1164 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1165 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1166 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1167 | return; | |
1168 | } | |
1169 | ||
1da177e4 | 1170 | /* |
2f5c33b3 MH |
1171 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
1172 | * hand in case it has already been processed. | |
1173 | * (depends on link order, which is apparently not guaranteed) | |
1da177e4 LT |
1174 | */ |
1175 | dev->device = devid; | |
2f5c33b3 | 1176 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1177 | } |
c30ca1db AB |
1178 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); |
1179 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); | |
1da177e4 | 1180 | |
1da177e4 | 1181 | |
e5548e96 BJD |
1182 | /* |
1183 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1184 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1185 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1186 | * -- bjd | |
1187 | */ | |
1597cacb | 1188 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1189 | { |
1190 | u8 val; | |
1191 | int asus_hides_ac97 = 0; | |
1192 | ||
1193 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1194 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1195 | asus_hides_ac97 = 1; | |
1196 | } | |
1197 | ||
1198 | if (!asus_hides_ac97) | |
1199 | return; | |
1200 | ||
1201 | pci_read_config_byte(dev, 0x50, &val); | |
1202 | if (val & 0xc0) { | |
1203 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1204 | pci_read_config_byte(dev, 0x50, &val); | |
1205 | if (val & 0xc0) | |
1206 | printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); | |
1207 | else | |
1208 | printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); | |
1209 | } | |
1210 | } | |
1211 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); | |
1597cacb AC |
1212 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); |
1213 | ||
77967052 | 1214 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1215 | |
1216 | /* | |
1217 | * If we are using libata we can drive this chip properly but must | |
1218 | * do this early on to make the additional device appear during | |
1219 | * the PCI scanning. | |
1220 | */ | |
1221 | ||
1597cacb | 1222 | static void quirk_jmicron_dualfn(struct pci_dev *pdev) |
15e0c694 AC |
1223 | { |
1224 | u32 conf; | |
1225 | u8 hdr; | |
1226 | ||
1227 | /* Only poke fn 0 */ | |
1228 | if (PCI_FUNC(pdev->devfn)) | |
1229 | return; | |
1230 | ||
1231 | switch(pdev->device) { | |
1232 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1233 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1234 | /* Redirect IDE second PATA port to the right spot */ | |
1235 | pci_read_config_dword(pdev, 0x80, &conf); | |
1236 | conf |= (1 << 24); | |
1237 | /* Fall through */ | |
1238 | pci_write_config_dword(pdev, 0x80, conf); | |
1239 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1240 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
1241 | pci_read_config_dword(pdev, 0x40, &conf); | |
1242 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ | |
1243 | /* Set the class codes correctly and then direct IDE 0 */ | |
77280989 TH |
1244 | conf &= ~0x000FF200; /* Clear bit 9 and 12-19 */ |
1245 | conf |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */ | |
15e0c694 AC |
1246 | pci_write_config_dword(pdev, 0x40, conf); |
1247 | ||
1248 | /* Reconfigure so that the PCI scanner discovers the | |
1249 | device is now multifunction */ | |
1250 | ||
1251 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1252 | pdev->hdr_type = hdr & 0x7f; | |
1253 | pdev->multifunction = !!(hdr & 0x80); | |
1254 | ||
1255 | break; | |
1256 | } | |
1257 | } | |
15e0c694 | 1258 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn); |
1597cacb | 1259 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn); |
15e0c694 AC |
1260 | |
1261 | #endif | |
1262 | ||
1da177e4 LT |
1263 | #ifdef CONFIG_X86_IO_APIC |
1264 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) | |
1265 | { | |
1266 | int i; | |
1267 | ||
1268 | if ((pdev->class >> 8) != 0xff00) | |
1269 | return; | |
1270 | ||
1271 | /* the first BAR is the location of the IO APIC...we must | |
1272 | * not touch this (and it's already covered by the fixmap), so | |
1273 | * forcibly insert it into the resource tree */ | |
1274 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) | |
1275 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1276 | ||
1277 | /* The next five BARs all seem to be rubbish, so just clean | |
1278 | * them out */ | |
1279 | for (i=1; i < 6; i++) { | |
1280 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); | |
1281 | } | |
1282 | ||
1283 | } | |
1284 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); | |
1285 | #endif | |
1286 | ||
2bd0fa3b JB |
1287 | enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 }; |
1288 | /* Defaults to combined */ | |
1289 | static enum ide_combined_type combined_mode; | |
1290 | ||
1291 | static int __init combined_setup(char *str) | |
1292 | { | |
1293 | if (!strncmp(str, "ide", 3)) | |
1294 | combined_mode = IDE; | |
1295 | else if (!strncmp(str, "libata", 6)) | |
1296 | combined_mode = LIBATA; | |
1297 | else /* "combined" or anything else defaults to old behavior */ | |
1298 | combined_mode = COMBINED; | |
1299 | ||
1300 | return 1; | |
1301 | } | |
1302 | __setup("combined_mode=", combined_setup); | |
1303 | ||
77967052 | 1304 | #ifdef CONFIG_SATA_INTEL_COMBINED |
1da177e4 LT |
1305 | static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev) |
1306 | { | |
1307 | u8 prog, comb, tmp; | |
1308 | int ich = 0; | |
1309 | ||
1310 | /* | |
1311 | * Narrow down to Intel SATA PCI devices. | |
1312 | */ | |
1313 | switch (pdev->device) { | |
1314 | /* PCI ids taken from drivers/scsi/ata_piix.c */ | |
1315 | case 0x24d1: | |
1316 | case 0x24df: | |
1317 | case 0x25a3: | |
1318 | case 0x25b0: | |
1319 | ich = 5; | |
1320 | break; | |
1321 | case 0x2651: | |
1322 | case 0x2652: | |
1323 | case 0x2653: | |
c368ca4e | 1324 | case 0x2680: /* ESB2 */ |
1da177e4 LT |
1325 | ich = 6; |
1326 | break; | |
1327 | case 0x27c0: | |
1328 | case 0x27c4: | |
1329 | ich = 7; | |
1330 | break; | |
012b265f JG |
1331 | case 0x2828: /* ICH8M */ |
1332 | ich = 8; | |
1333 | break; | |
1da177e4 LT |
1334 | default: |
1335 | /* we do not handle this PCI device */ | |
1336 | return; | |
1337 | } | |
1338 | ||
1339 | /* | |
1340 | * Read combined mode register. | |
1341 | */ | |
1342 | pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */ | |
1343 | ||
1344 | if (ich == 5) { | |
1345 | tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */ | |
1346 | if (tmp == 0x4) /* bits 10x */ | |
1347 | comb = (1 << 0); /* SATA port 0, PATA port 1 */ | |
1348 | else if (tmp == 0x6) /* bits 11x */ | |
1349 | comb = (1 << 2); /* PATA port 0, SATA port 1 */ | |
1350 | else | |
1351 | return; /* not in combined mode */ | |
1352 | } else { | |
012b265f | 1353 | WARN_ON((ich != 6) && (ich != 7) && (ich != 8)); |
1da177e4 LT |
1354 | tmp &= 0x3; /* interesting bits 1:0 */ |
1355 | if (tmp & (1 << 0)) | |
1356 | comb = (1 << 2); /* PATA port 0, SATA port 1 */ | |
1357 | else if (tmp & (1 << 1)) | |
1358 | comb = (1 << 0); /* SATA port 0, PATA port 1 */ | |
1359 | else | |
1360 | return; /* not in combined mode */ | |
1361 | } | |
1362 | ||
1363 | /* | |
1364 | * Read programming interface register. | |
1365 | * (Tells us if it's legacy or native mode) | |
1366 | */ | |
1367 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1368 | ||
1369 | /* if SATA port is in native mode, we're ok. */ | |
1370 | if (prog & comb) | |
1371 | return; | |
1372 | ||
2bd0fa3b JB |
1373 | /* Don't reserve any so the IDE driver can get them (but only if |
1374 | * combined_mode=ide). | |
1375 | */ | |
1376 | if (combined_mode == IDE) | |
1377 | return; | |
1378 | ||
1379 | /* Grab them both for libata if combined_mode=libata. */ | |
1380 | if (combined_mode == LIBATA) { | |
1381 | request_region(0x1f0, 8, "libata"); /* port 0 */ | |
1382 | request_region(0x170, 8, "libata"); /* port 1 */ | |
1383 | return; | |
1384 | } | |
1385 | ||
1da177e4 LT |
1386 | /* SATA port is in legacy mode. Reserve port so that |
1387 | * IDE driver does not attempt to use it. If request_region | |
1388 | * fails, it will be obvious at boot time, so we don't bother | |
1389 | * checking return values. | |
1390 | */ | |
1391 | if (comb == (1 << 0)) | |
1392 | request_region(0x1f0, 8, "libata"); /* port 0 */ | |
1393 | else | |
1394 | request_region(0x170, 8, "libata"); /* port 1 */ | |
1395 | } | |
1396 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined ); | |
77967052 | 1397 | #endif /* CONFIG_SATA_INTEL_COMBINED */ |
1da177e4 LT |
1398 | |
1399 | ||
1400 | int pcie_mch_quirk; | |
c30ca1db | 1401 | EXPORT_SYMBOL(pcie_mch_quirk); |
1da177e4 LT |
1402 | |
1403 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) | |
1404 | { | |
1405 | pcie_mch_quirk = 1; | |
1406 | } | |
1407 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); | |
1408 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); | |
1409 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); | |
1410 | ||
4602b88d KA |
1411 | |
1412 | /* | |
1413 | * It's possible for the MSI to get corrupted if shpc and acpi | |
1414 | * are used together on certain PXH-based systems. | |
1415 | */ | |
1416 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) | |
1417 | { | |
1418 | disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI), | |
1419 | PCI_CAP_ID_MSI); | |
1420 | dev->no_msi = 1; | |
1421 | ||
1422 | printk(KERN_WARNING "PCI: PXH quirk detected, " | |
1423 | "disabling MSI for SHPC device\n"); | |
1424 | } | |
1425 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1426 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1427 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1428 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1429 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1430 | ||
ffadcc2f KCA |
1431 | /* |
1432 | * Some Intel PCI Express chipsets have trouble with downstream | |
1433 | * device power management. | |
1434 | */ | |
1435 | static void quirk_intel_pcie_pm(struct pci_dev * dev) | |
1436 | { | |
1437 | pci_pm_d3_delay = 120; | |
1438 | dev->no_d1d2 = 1; | |
1439 | } | |
1440 | ||
1441 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); | |
1442 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1443 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1444 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1445 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1446 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1447 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1448 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1449 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1450 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1451 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1452 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1453 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1454 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1455 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1456 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1457 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1458 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1459 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1460 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1461 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1462 | |
33dced2e SS |
1463 | /* |
1464 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
1465 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
1466 | * Re-allocate the region if needed... | |
1467 | */ | |
1468 | static void __init quirk_tc86c001_ide(struct pci_dev *dev) | |
1469 | { | |
1470 | struct resource *r = &dev->resource[0]; | |
1471 | ||
1472 | if (r->start & 0x8) { | |
1473 | r->start = 0; | |
1474 | r->end = 0xf; | |
1475 | } | |
1476 | } | |
1477 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
1478 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
1479 | quirk_tc86c001_ide); | |
1480 | ||
1da177e4 LT |
1481 | static void __devinit quirk_netmos(struct pci_dev *dev) |
1482 | { | |
1483 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
1484 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
1485 | ||
1486 | /* | |
1487 | * These Netmos parts are multiport serial devices with optional | |
1488 | * parallel ports. Even when parallel ports are present, they | |
1489 | * are identified as class SERIAL, which means the serial driver | |
1490 | * will claim them. To prevent this, mark them as class OTHER. | |
1491 | * These combo devices should be claimed by parport_serial. | |
1492 | * | |
1493 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
1494 | * of parallel ports and <S> is the number of serial ports. | |
1495 | */ | |
1496 | switch (dev->device) { | |
1497 | case PCI_DEVICE_ID_NETMOS_9735: | |
1498 | case PCI_DEVICE_ID_NETMOS_9745: | |
1499 | case PCI_DEVICE_ID_NETMOS_9835: | |
1500 | case PCI_DEVICE_ID_NETMOS_9845: | |
1501 | case PCI_DEVICE_ID_NETMOS_9855: | |
1502 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && | |
1503 | num_parallel) { | |
1504 | printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " | |
1505 | "%u serial); changing class SERIAL to OTHER " | |
1506 | "(use parport_serial)\n", | |
1507 | dev->device, num_parallel, num_serial); | |
1508 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
1509 | (dev->class & 0xff); | |
1510 | } | |
1511 | } | |
1512 | } | |
1513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); | |
1514 | ||
16a74744 BH |
1515 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
1516 | { | |
1517 | u16 command; | |
1518 | u32 bar; | |
1519 | u8 __iomem *csr; | |
1520 | u8 cmd_hi; | |
1521 | ||
1522 | switch (dev->device) { | |
1523 | /* PCI IDs taken from drivers/net/e100.c */ | |
1524 | case 0x1029: | |
1525 | case 0x1030 ... 0x1034: | |
1526 | case 0x1038 ... 0x103E: | |
1527 | case 0x1050 ... 0x1057: | |
1528 | case 0x1059: | |
1529 | case 0x1064 ... 0x106B: | |
1530 | case 0x1091 ... 0x1095: | |
1531 | case 0x1209: | |
1532 | case 0x1229: | |
1533 | case 0x2449: | |
1534 | case 0x2459: | |
1535 | case 0x245D: | |
1536 | case 0x27DC: | |
1537 | break; | |
1538 | default: | |
1539 | return; | |
1540 | } | |
1541 | ||
1542 | /* | |
1543 | * Some firmware hands off the e100 with interrupts enabled, | |
1544 | * which can cause a flood of interrupts if packets are | |
1545 | * received before the driver attaches to the device. So | |
1546 | * disable all e100 interrupts here. The driver will | |
1547 | * re-enable them when it's ready. | |
1548 | */ | |
1549 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
1550 | pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar); | |
1551 | ||
1552 | if (!(command & PCI_COMMAND_MEMORY) || !bar) | |
1553 | return; | |
1554 | ||
1555 | csr = ioremap(bar, 8); | |
1556 | if (!csr) { | |
1557 | printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", | |
1558 | pci_name(dev)); | |
1559 | return; | |
1560 | } | |
1561 | ||
1562 | cmd_hi = readb(csr + 3); | |
1563 | if (cmd_hi == 0) { | |
1564 | printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " | |
1565 | "enabled, disabling\n", pci_name(dev)); | |
1566 | writeb(1, csr + 3); | |
1567 | } | |
1568 | ||
1569 | iounmap(csr); | |
1570 | } | |
1571 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); | |
a5312e28 IK |
1572 | |
1573 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) | |
1574 | { | |
1575 | /* rev 1 ncr53c810 chips don't set the class at all which means | |
1576 | * they don't get their resources remapped. Fix that here. | |
1577 | */ | |
1578 | ||
1579 | if (dev->class == PCI_CLASS_NOT_DEFINED) { | |
1580 | printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); | |
1581 | dev->class = PCI_CLASS_STORAGE_SCSI; | |
1582 | } | |
1583 | } | |
1584 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
1585 | ||
1da177e4 LT |
1586 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end) |
1587 | { | |
1588 | while (f < end) { | |
1589 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && | |
1590 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { | |
1591 | pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); | |
1592 | f->hook(dev); | |
1593 | } | |
1594 | f++; | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | extern struct pci_fixup __start_pci_fixups_early[]; | |
1599 | extern struct pci_fixup __end_pci_fixups_early[]; | |
1600 | extern struct pci_fixup __start_pci_fixups_header[]; | |
1601 | extern struct pci_fixup __end_pci_fixups_header[]; | |
1602 | extern struct pci_fixup __start_pci_fixups_final[]; | |
1603 | extern struct pci_fixup __end_pci_fixups_final[]; | |
1604 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
1605 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
1597cacb AC |
1606 | extern struct pci_fixup __start_pci_fixups_resume[]; |
1607 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
1da177e4 LT |
1608 | |
1609 | ||
1610 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
1611 | { | |
1612 | struct pci_fixup *start, *end; | |
1613 | ||
1614 | switch(pass) { | |
1615 | case pci_fixup_early: | |
1616 | start = __start_pci_fixups_early; | |
1617 | end = __end_pci_fixups_early; | |
1618 | break; | |
1619 | ||
1620 | case pci_fixup_header: | |
1621 | start = __start_pci_fixups_header; | |
1622 | end = __end_pci_fixups_header; | |
1623 | break; | |
1624 | ||
1625 | case pci_fixup_final: | |
1626 | start = __start_pci_fixups_final; | |
1627 | end = __end_pci_fixups_final; | |
1628 | break; | |
1629 | ||
1630 | case pci_fixup_enable: | |
1631 | start = __start_pci_fixups_enable; | |
1632 | end = __end_pci_fixups_enable; | |
1633 | break; | |
1634 | ||
1597cacb AC |
1635 | case pci_fixup_resume: |
1636 | start = __start_pci_fixups_resume; | |
1637 | end = __end_pci_fixups_resume; | |
1638 | break; | |
1639 | ||
1da177e4 LT |
1640 | default: |
1641 | /* stupid compiler warning, you would think with an enum... */ | |
1642 | return; | |
1643 | } | |
1644 | pci_do_fixups(dev, start, end); | |
1645 | } | |
c30ca1db | 1646 | EXPORT_SYMBOL(pci_fixup_device); |
1da177e4 | 1647 | |
9d265124 DY |
1648 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
1649 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) | |
1650 | { | |
1651 | u16 en1k; | |
1652 | u8 io_base_lo, io_limit_lo; | |
1653 | unsigned long base, limit; | |
1654 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1655 | ||
1656 | pci_read_config_word(dev, 0x40, &en1k); | |
1657 | ||
1658 | if (en1k & 0x200) { | |
1659 | printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); | |
1660 | ||
1661 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
1662 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
1663 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1664 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
1665 | ||
1666 | if (base <= limit) { | |
1667 | res->start = base; | |
1668 | res->end = limit + 0x3ff; | |
1669 | } | |
1670 | } | |
1671 | } | |
1672 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); | |
1673 | ||
15a260d5 DY |
1674 | /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 |
1675 | * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() | |
1676 | * in drivers/pci/setup-bus.c | |
1677 | */ | |
1678 | static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) | |
1679 | { | |
1680 | u16 en1k, iobl_adr, iobl_adr_1k; | |
1681 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
1682 | ||
1683 | pci_read_config_word(dev, 0x40, &en1k); | |
1684 | ||
1685 | if (en1k & 0x200) { | |
1686 | pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); | |
1687 | ||
1688 | iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); | |
1689 | ||
1690 | if (iobl_adr != iobl_adr_1k) { | |
1691 | printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n", | |
1692 | iobl_adr,iobl_adr_1k); | |
1693 | pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); | |
1694 | } | |
1695 | } | |
1696 | } | |
1697 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); | |
1698 | ||
cf34a8e0 BG |
1699 | /* Under some circumstances, AER is not linked with extended capabilities. |
1700 | * Force it to be linked by setting the corresponding control bit in the | |
1701 | * config space. | |
1702 | */ | |
1597cacb | 1703 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
1704 | { |
1705 | uint8_t b; | |
1706 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { | |
1707 | if (!(b & 0x20)) { | |
1708 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
1709 | printk(KERN_INFO | |
1710 | "PCI: Linking AER extended capability on %s\n", | |
1711 | pci_name(dev)); | |
1712 | } | |
1713 | } | |
1714 | } | |
1715 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
1716 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
1597cacb AC |
1717 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1718 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
cf34a8e0 | 1719 | |
3f79e107 | 1720 | #ifdef CONFIG_PCI_MSI |
3f79e107 BG |
1721 | /* The Serverworks PCI-X chipset does not support MSI. We cannot easily rely |
1722 | * on setting PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | |
1723 | * some other busses controlled by the chipset even if Linux is not aware of it. | |
1724 | * Instead of setting the flag on all busses in the machine, simply disable MSI | |
1725 | * globally. | |
1726 | */ | |
1727 | static void __init quirk_svw_msi(struct pci_dev *dev) | |
1728 | { | |
88187dfa ME |
1729 | pci_no_msi(); |
1730 | printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n"); | |
3f79e107 BG |
1731 | } |
1732 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi); | |
1733 | ||
1734 | /* Disable MSI on chipsets that are known to not support it */ | |
1735 | static void __devinit quirk_disable_msi(struct pci_dev *dev) | |
1736 | { | |
1737 | if (dev->subordinate) { | |
1738 | printk(KERN_WARNING "PCI: MSI quirk detected. " | |
1739 | "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", | |
1740 | pci_name(dev)); | |
1741 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; | |
1742 | } | |
1743 | } | |
1744 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
6397c75c BG |
1745 | |
1746 | /* Go through the list of Hypertransport capabilities and | |
1747 | * return 1 if a HT MSI capability is found and enabled */ | |
1748 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) | |
1749 | { | |
7a380507 ME |
1750 | int pos, ttl = 48; |
1751 | ||
1752 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
1753 | while (pos && ttl--) { | |
1754 | u8 flags; | |
1755 | ||
1756 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
1757 | &flags) == 0) | |
1758 | { | |
1759 | printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n", | |
1760 | flags & HT_MSI_FLAGS_ENABLE ? | |
1761 | "enabled" : "disabled", pci_name(dev)); | |
1762 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; | |
6397c75c | 1763 | } |
7a380507 ME |
1764 | |
1765 | pos = pci_find_next_ht_capability(dev, pos, | |
1766 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
1767 | } |
1768 | return 0; | |
1769 | } | |
1770 | ||
1771 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ | |
1772 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) | |
1773 | { | |
1774 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
1775 | printk(KERN_WARNING "PCI: MSI quirk detected. " | |
1776 | "MSI disabled on chipset %s.\n", | |
1777 | pci_name(dev)); | |
1778 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; | |
1779 | } | |
1780 | } | |
1781 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
1782 | quirk_msi_ht_cap); | |
1783 | ||
1784 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. | |
1785 | * MSI are supported if the MSI capability set in any of these mappings. | |
1786 | */ | |
1787 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) | |
1788 | { | |
1789 | struct pci_dev *pdev; | |
1790 | ||
1791 | if (!dev->subordinate) | |
1792 | return; | |
1793 | ||
1794 | /* check HT MSI cap on this chipset and the root one. | |
1795 | * a single one having MSI is enough to be sure that MSI are supported. | |
1796 | */ | |
11f242f0 | 1797 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
1798 | if (!pdev) |
1799 | return; | |
0c875c28 | 1800 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
6397c75c BG |
1801 | printk(KERN_WARNING "PCI: MSI quirk detected. " |
1802 | "MSI disabled on chipset %s.\n", | |
1803 | pci_name(dev)); | |
1804 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; | |
1805 | } | |
11f242f0 | 1806 | pci_dev_put(pdev); |
6397c75c BG |
1807 | } |
1808 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
1809 | quirk_nvidia_ck804_msi_ht_cap); | |
3f79e107 | 1810 | #endif /* CONFIG_PCI_MSI */ |