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[PATCH] PCI: fix race with pci_walk_bus and pci_destroy_dev
[deliverable/linux.git] / drivers / pci / quirks.c
CommitLineData
1da177e4
LT		 1/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
7586269c
DB		 10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
1da177e4
LT		 13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
25be5e6c 24#include <linux/acpi.h>
bc56b9e0 25#include "pci.h"
1da177e4 26
bd8481e1
DT		 27/* The Mellanox Tavor device gives false positive parity errors
28 * Mark this device with a broken_parity_status, to allow
29 * PCI scanning code to "skip" this now blacklisted device.
30 */
31static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
32{
33 dev->broken_parity_status = 1; /* This device gives false positives */
34}
35DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
36DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
37
1da177e4
LT		 38/* Deal with broken BIOS'es that neglect to enable passive release,
39 which can cause problems in combination with the 82441FX/PPro MTRRs */
40static void __devinit quirk_passive_release(struct pci_dev *dev)
41{
42 struct pci_dev *d = NULL;
43 unsigned char dlc;
44
45 /* We have to make sure a particular bit is set in the PIIX3
46 ISA bridge, so we have to go out and find it. */
47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
48 pci_read_config_byte(d, 0x82, &dlc);
49 if (!(dlc & 1<<1)) {
50 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
51 dlc |= 1<<1;
52 pci_write_config_byte(d, 0x82, dlc);
53 }
54 }
55}
56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
57
58/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA
60 ask them for me please -- Alan
61
62 This appears to be BIOS not version dependent. So presumably there is a
63 chipset level fix */
64int isa_dma_bridge_buggy; /* Exported */
65
66static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
67{
68 if (!isa_dma_bridge_buggy) {
69 isa_dma_bridge_buggy=1;
70 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
71 }
72}
73 /*
74 * Its not totally clear which chipsets are the problematic ones
75 * We know 82C586 and 82C596 variants are affected.
76 */
77DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
84
85int pci_pci_problems;
86
87/*
88 * Chipsets where PCI->PCI transfers vanish or hang
89 */
90static void __devinit quirk_nopcipci(struct pci_dev *dev)
91{
92 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
93 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
94 pci_pci_problems |= PCIPCI_FAIL;
95 }
96}
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
99
100/*
101 * Triton requires workarounds to be used by the drivers
102 */
103static void __devinit quirk_triton(struct pci_dev *dev)
104{
105 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
106 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
107 pci_pci_problems |= PCIPCI_TRITON;
108 }
109}
110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
111DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
114
115/*
116 * VIA Apollo KT133 needs PCI latency patch
117 * Made according to a windows driver based patch by George E. Breese
118 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
119 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
120 * the info on which Mr Breese based his work.
121 *
122 * Updated based on further information from the site and also on
123 * information provided by VIA
124 */
125static void __devinit quirk_vialatency(struct pci_dev *dev)
126{
127 struct pci_dev *p;
128 u8 rev;
129 u8 busarb;
130 /* Ok we have a potential problem chipset here. Now see if we have
131 a buggy southbridge */
132
133 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
134 if (p!=NULL) {
135 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
136 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
137 /* Check for buggy part revisions */
138 if (rev < 0x40 || rev > 0x42)
139 goto exit;
140 } else {
141 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
142 if (p==NULL) /* No problem parts */
143 goto exit;
144 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
145 /* Check for buggy part revisions */
146 if (rev < 0x10 || rev > 0x12)
147 goto exit;
148 }
149
150 /*
151 * Ok we have the problem. Now set the PCI master grant to
152 * occur every master grant. The apparent bug is that under high
153 * PCI load (quite common in Linux of course) you can get data
154 * loss when the CPU is held off the bus for 3 bus master requests
155 * This happens to include the IDE controllers....
156 *
157 * VIA only apply this fix when an SB Live! is present but under
158 * both Linux and Windows this isnt enough, and we have seen
159 * corruption without SB Live! but with things like 3 UDMA IDE
160 * controllers. So we ignore that bit of the VIA recommendation..
161 */
162
163 pci_read_config_byte(dev, 0x76, &busarb);
164 /* Set bit 4 and bi 5 of byte 76 to 0x01
165 "Master priority rotation on every PCI master grant */
166 busarb &= ~(1<<5);
167 busarb |= (1<<4);
168 pci_write_config_byte(dev, 0x76, busarb);
169 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
170exit:
171 pci_dev_put(p);
172}
173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
176
177/*
178 * VIA Apollo VP3 needs ETBF on BT848/878
179 */
180static void __devinit quirk_viaetbf(struct pci_dev *dev)
181{
182 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
183 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
184 pci_pci_problems |= PCIPCI_VIAETBF;
185 }
186}
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
188
189static void __devinit quirk_vsfx(struct pci_dev *dev)
190{
191 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
192 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
193 pci_pci_problems |= PCIPCI_VSFX;
194 }
195}
196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
197
198/*
199 * Ali Magik requires workarounds to be used by the drivers
200 * that DMA to AGP space. Latency must be set to 0xA and triton
201 * workaround applied too
202 * [Info kindly provided by ALi]
203 */
204static void __init quirk_alimagik(struct pci_dev *dev)
205{
206 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
209 }
210}
211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
213
214/*
215 * Natoma has some interesting boundary conditions with Zoran stuff
216 * at least
217 */
218static void __devinit quirk_natoma(struct pci_dev *dev)
219{
220 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
221 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
222 pci_pci_problems |= PCIPCI_NATOMA;
223 }
224}
225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
226DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
231
232/*
233 * This chip can cause PCI parity errors if config register 0xA0 is read
234 * while DMAs are occurring.
235 */
236static void __devinit quirk_citrine(struct pci_dev *dev)
237{
238 dev->cfg_size = 0xA0;
239}
240DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
241
242/*
243 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
244 * If it's needed, re-allocate the region.
245 */
246static void __devinit quirk_s3_64M(struct pci_dev *dev)
247{
248 struct resource *r = &dev->resource[0];
249
250 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
251 r->start = 0;
252 r->end = 0x3ffffff;
253 }
254}
255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
257
6693e74a
LT		 258static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
259 unsigned size, int nr, const char *name)
1da177e4
LT		 260{
261 region &= ~(size-1);
262 if (region) {
085ae41f 263 struct pci_bus_region bus_region;
1da177e4
LT		 264 struct resource *res = dev->resource + nr;
265
266 res->name = pci_name(dev);
267 res->start = region;
268 res->end = region + size - 1;
269 res->flags = IORESOURCE_IO;
085ae41f
DM		 270
271 /* Convert from PCI bus to resource space. */
272 bus_region.start = res->start;
273 bus_region.end = res->end;
274 pcibios_bus_to_resource(dev, res, &bus_region);
275
1da177e4 276 pci_claim_resource(dev, nr);
6693e74a 277 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
1da177e4
LT		 278 }
279}
280
281/*
282 * ATI Northbridge setups MCE the processor if you even
283 * read somewhere between 0x3b0->0x3bb or read 0x3d3
284 */
285static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
286{
287 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
288 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
289 request_region(0x3b0, 0x0C, "RadeonIGP");
290 request_region(0x3d3, 0x01, "RadeonIGP");
291}
292DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
293
294/*
295 * Let's make the southbridge information explicit instead
296 * of having to worry about people probing the ACPI areas,
297 * for example.. (Yes, it happens, and if you read the wrong
298 * ACPI register it will put the machine to sleep with no
299 * way of waking it up again. Bummer).
300 *
301 * ALI M7101: Two IO regions pointed to by words at
302 * 0xE0 (64 bytes of ACPI registers)
303 * 0xE2 (32 bytes of SMB registers)
304 */
305static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
306{
307 u16 region;
308
309 pci_read_config_word(dev, 0xE0, &region);
6693e74a 310 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
1da177e4 311 pci_read_config_word(dev, 0xE2, &region);
6693e74a 312 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
1da177e4
LT		 313}
314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
315
6693e74a
LT		 316static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
317{
318 u32 devres;
319 u32 mask, size, base;
320
321 pci_read_config_dword(dev, port, &devres);
322 if ((devres & enable) != enable)
323 return;
324 mask = (devres >> 16) & 15;
325 base = devres & 0xffff;
326 size = 16;
327 for (;;) {
328 unsigned bit = size >> 1;
329 if ((bit & mask) == bit)
330 break;
331 size = bit;
332 }
333 /*
334 * For now we only print it out. Eventually we'll want to
335 * reserve it (at least if it's in the 0x1000+ range), but
336 * let's get enough confirmation reports first.
337 */
338 base &= -size;
339 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1);
340}
341
342static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
343{
344 u32 devres;
345 u32 mask, size, base;
346
347 pci_read_config_dword(dev, port, &devres);
348 if ((devres & enable) != enable)
349 return;
350 base = devres & 0xffff0000;
351 mask = (devres & 0x3f) << 16;
352 size = 128 << 16;
353 for (;;) {
354 unsigned bit = size >> 1;
355 if ((bit & mask) == bit)
356 break;
357 size = bit;
358 }
359 /*
360 * For now we only print it out. Eventually we'll want to
361 * reserve it, but let's get enough confirmation reports first.
362 */
363 base &= -size;
364 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1);
365}
366
1da177e4
LT		 367/*
368 * PIIX4 ACPI: Two IO regions pointed to by longwords at
369 * 0x40 (64 bytes of ACPI registers)
08db2a70 370 * 0x90 (16 bytes of SMB registers)
6693e74a 371 * and a few strange programmable PIIX4 device resources.
1da177e4
LT		 372 */
373static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
374{
6693e74a 375 u32 region, res_a;
1da177e4
LT		 376
377 pci_read_config_dword(dev, 0x40, &region);
6693e74a 378 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
1da177e4 379 pci_read_config_dword(dev, 0x90, &region);
08db2a70 380 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
6693e74a
LT		 381
382 /* Device resource A has enables for some of the other ones */
383 pci_read_config_dword(dev, 0x5c, &res_a);
384
385 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
386 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
387
388 /* Device resource D is just bitfields for static resources */
389
390 /* Device 12 enabled? */
391 if (res_a & (1 << 29)) {
392 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
393 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
394 }
395 /* Device 13 enabled? */
396 if (res_a & (1 << 30)) {
397 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
398 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
399 }
400 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
401 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
1da177e4
LT		 402}
403DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
404
405/*
406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
408 * 0x58 (64 bytes of GPIO I/O space)
409 */
410static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
411{
412 u32 region;
413
414 pci_read_config_dword(dev, 0x40, &region);
6693e74a 415 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH4 ACPI/GPIO/TCO");
1da177e4
LT		 416
417 pci_read_config_dword(dev, 0x58, &region);
6693e74a 418 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
1da177e4
LT		 419}
420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
426DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
428DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
3aa8c4fe 429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
1da177e4 430
2cea752f
M		 431static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
432{
433 u32 region;
434
435 pci_read_config_dword(dev, 0x40, &region);
436 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, "ICH6 ACPI/GPIO/TCO");
437
438 pci_read_config_dword(dev, 0x48, &region);
439 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
440}
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi );
442
1da177e4
LT		 443/*
444 * VIA ACPI: One IO region pointed to by longword at
445 * 0x48 or 0x20 (256 bytes of ACPI registers)
446 */
447static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
448{
449 u8 rev;
450 u32 region;
451
452 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
453 if (rev & 0x10) {
454 pci_read_config_dword(dev, 0x48, &region);
455 region &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 456 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
1da177e4
LT		 457 }
458}
459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
460
461/*
462 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
463 * 0x48 (256 bytes of ACPI registers)
464 * 0x70 (128 bytes of hardware monitoring register)
465 * 0x90 (16 bytes of SMB registers)
466 */
467static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
468{
469 u16 hm;
470 u32 smb;
471
472 quirk_vt82c586_acpi(dev);
473
474 pci_read_config_word(dev, 0x70, &hm);
475 hm &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 476 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
1da177e4
LT		 477
478 pci_read_config_dword(dev, 0x90, &smb);
479 smb &= PCI_BASE_ADDRESS_IO_MASK;
02f313b2 480 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
1da177e4
LT		 481}
482DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
483
6d85f29b
IK		 484/*
485 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
486 * 0x88 (128 bytes of power management registers)
487 * 0xd0 (16 bytes of SMB registers)
488 */
489static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
490{
491 u16 pm, smb;
492
493 pci_read_config_word(dev, 0x88, &pm);
494 pm &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 495 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
6d85f29b
IK		 496
497 pci_read_config_word(dev, 0xd0, &smb);
498 smb &= PCI_BASE_ADDRESS_IO_MASK;
6693e74a 499 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
6d85f29b
IK		 500}
501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
502
1da177e4
LT		 503
504#ifdef CONFIG_X86_IO_APIC
505
506#include <asm/io_apic.h>
507
508/*
509 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
510 * devices to the external APIC.
511 *
512 * TODO: When we have device-specific interrupt routers,
513 * this code will go away from quirks.
514 */
515static void __devinit quirk_via_ioapic(struct pci_dev *dev)
516{
517 u8 tmp;
518
519 if (nr_ioapics < 1)
520 tmp = 0; /* nothing routed to external APIC */
521 else
522 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
523
524 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
525 tmp == 0 ? "Disa" : "Ena");
526
527 /* Offset 0x58: External APIC IRQ output control */
528 pci_write_config_byte (dev, 0x58, tmp);
529}
530DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
531
a1740913
KW		 532/*
533 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
534 * This leads to doubled level interrupt rates.
535 * Set this bit to get rid of cycle wastage.
536 * Otherwise uncritical.
537 */
538static void __devinit quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
539{
540 u8 misc_control2;
541#define BYPASS_APIC_DEASSERT 8
542
543 pci_read_config_byte(dev, 0x5B, &misc_control2);
544 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
545 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
546 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
547 }
548}
549DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
550
1da177e4
LT		 551/*
552 * The AMD io apic can hang the box when an apic irq is masked.
553 * We check all revs >= B0 (yet not in the pre production!) as the bug
554 * is currently marked NoFix
555 *
556 * We have multiple reports of hangs with this chipset that went away with
557 * noapic specified. For the moment we assume its the errata. We may be wrong
558 * of course. However the advice is demonstrably good even if so..
559 */
560static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
561{
562 u8 rev;
563
564 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
565 if (rev >= 0x02) {
566 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
567 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
568 }
569}
570DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
571
572static void __init quirk_ioapic_rmw(struct pci_dev *dev)
573{
574 if (dev->devfn == 0 && dev->bus->number == 0)
575 sis_apic_bug = 1;
576}
577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
578
579int pci_msi_quirk;
580
581#define AMD8131_revA0 0x01
582#define AMD8131_revB0 0x11
583#define AMD8131_MISC 0x40
584#define AMD8131_NIOAMODE_BIT 0
585static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
586{
587 unsigned char revid, tmp;
588
6e325a62
MT		 589 if (dev->subordinate) {
590 printk(KERN_WARNING "PCI: MSI quirk detected. "
591 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
592 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
593 }
1da177e4
LT		 594
595 if (nr_ioapics == 0)
596 return;
597
598 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
599 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
600 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
601 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
602 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
603 pci_write_config_byte( dev, AMD8131_MISC, tmp);
604 }
605}
5da594b1 606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);
1da177e4 607
1e062767
NS		 608static void __init quirk_svw_msi(struct pci_dev *dev)
609{
610 pci_msi_quirk = 1;
611 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
612}
613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_svw_msi );
1da177e4
LT		 614#endif /* CONFIG_X86_IO_APIC */
615
616
1da177e4
LT		 617/*
618 * FIXME: it is questionable that quirk_via_acpi
619 * is needed. It shows up as an ISA bridge, and does not
620 * support the PCI_INTERRUPT_LINE register at all. Therefore
621 * it seems like setting the pci_dev's 'irq' to the
622 * value of the ACPI SCI interrupt is only done for convenience.
623 * -jgarzik
624 */
625static void __devinit quirk_via_acpi(struct pci_dev *d)
626{
627 /*
628 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
629 */
630 u8 irq;
631 pci_read_config_byte(d, 0x42, &irq);
632 irq &= 0xf;
633 if (irq && (irq != 2))
634 d->irq = irq;
635}
636DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
637DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
638
93cffffa
BH		 639/*
640 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
641 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
642 * when written, it makes an internal connection to the PIC.
643 * For these devices, this register is defined to be 4 bits wide.
644 * Normally this is fine. However for IO-APIC motherboards, or
645 * non-x86 architectures (yes Via exists on PPC among other places),
646 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
647 * interrupts delivered properly.
a7b862f6
CW		 648 *
649 * Some of the on-chip devices are actually '586 devices' so they are
650 * listed here.
93cffffa
BH		 651 */
652static void quirk_via_irq(struct pci_dev *dev)
25be5e6c
LB		 653{
654 u8 irq, new_irq;
655
25be5e6c
LB		 656 new_irq = dev->irq & 0xf;
657 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
658 if (new_irq != irq) {
75cf7456 659 printk(KERN_INFO "PCI: VIA IRQ fixup for %s, from %d to %d\n",
25be5e6c
LB		 660 pci_name(dev), irq, new_irq);
661 udelay(15); /* unknown if delay really needed */
662 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
663 }
664}
a7b862f6
CW		 665DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_via_irq);
666DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, quirk_via_irq);
667DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irq);
668DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_irq);
75cf7456
CW		 669DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_irq);
670DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_irq);
671DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irq);
25be5e6c 672
1da177e4
LT		 673/*
674 * VIA VT82C598 has its device ID settable and many BIOSes
675 * set it to the ID of VT82C597 for backward compatibility.
676 * We need to switch it off to be able to recognize the real
677 * type of the chip.
678 */
679static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
680{
681 pci_write_config_byte(dev, 0xfc, 0);
682 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
683}
684DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
685
686/*
687 * CardBus controllers have a legacy base address that enables them
688 * to respond as i82365 pcmcia controllers. We don't want them to
689 * do this even if the Linux CardBus driver is not loaded, because
690 * the Linux i82365 driver does not (and should not) handle CardBus.
691 */
692static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
693{
694 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
695 return;
696 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
697}
698DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
699
700/*
701 * Following the PCI ordering rules is optional on the AMD762. I'm not
702 * sure what the designers were smoking but let's not inhale...
703 *
704 * To be fair to AMD, it follows the spec by default, its BIOS people
705 * who turn it off!
706 */
707static void __devinit quirk_amd_ordering(struct pci_dev *dev)
708{
709 u32 pcic;
710 pci_read_config_dword(dev, 0x4C, &pcic);
711 if ((pcic&6)!=6) {
712 pcic |= 6;
713 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
714 pci_write_config_dword(dev, 0x4C, pcic);
715 pci_read_config_dword(dev, 0x84, &pcic);
716 pcic |= (1<<23); /* Required in this mode */
717 pci_write_config_dword(dev, 0x84, pcic);
718 }
719}
720DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
721
722/*
723 * DreamWorks provided workaround for Dunord I-3000 problem
724 *
725 * This card decodes and responds to addresses not apparently
726 * assigned to it. We force a larger allocation to ensure that
727 * nothing gets put too close to it.
728 */
729static void __devinit quirk_dunord ( struct pci_dev * dev )
730{
731 struct resource *r = &dev->resource [1];
732 r->start = 0;
733 r->end = 0xffffff;
734}
735DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
736
737/*
738 * i82380FB mobile docking controller: its PCI-to-PCI bridge
739 * is subtractive decoding (transparent), and does indicate this
740 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
741 * instead of 0x01.
742 */
743static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
744{
745 dev->transparent = 1;
746}
747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
749
750/*
751 * Common misconfiguration of the MediaGX/Geode PCI master that will
752 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
753 * datasheets found at http://www.national.com/ds/GX for info on what
754 * these bits do. <christer@weinigel.se>
755 */
756static void __init quirk_mediagx_master(struct pci_dev *dev)
757{
758 u8 reg;
759 pci_read_config_byte(dev, 0x41, &reg);
760 if (reg & 2) {
761 reg &= ~2;
762 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
763 pci_write_config_byte(dev, 0x41, reg);
764 }
765}
766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
767
768/*
769 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
770 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
771 * secondary channels respectively). If the device reports Compatible mode
772 * but does use BAR0-3 for address decoding, we assume that firmware has
773 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
774 * Exceptions (if they exist) must be handled in chip/architecture specific
775 * fixups.
776 *
777 * Note: for non x86 people. You may need an arch specific quirk to handle
778 * moving IDE devices to native mode as well. Some plug in card devices power
779 * up in compatible mode and assume the BIOS will adjust them.
780 *
781 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
782 * we do now ? We don't want is pci_enable_device to come along
783 * and assign new resources. Both approaches work for that.
784 */
785static void __devinit quirk_ide_bases(struct pci_dev *dev)
786{
787 struct resource *res;
788 int first_bar = 2, last_bar = 0;
789
790 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
791 return;
792
793 res = &dev->resource[0];
794
795 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
796 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
797 res[0].start = res[0].end = res[0].flags = 0;
798 res[1].start = res[1].end = res[1].flags = 0;
799 first_bar = 0;
800 last_bar = 1;
801 }
802
803 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
804 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
805 res[2].start = res[2].end = res[2].flags = 0;
806 res[3].start = res[3].end = res[3].flags = 0;
807 last_bar = 3;
808 }
809
810 if (!last_bar)
811 return;
812
813 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
814 first_bar, last_bar, pci_name(dev));
815}
816DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
817
818/*
819 * Ensure C0 rev restreaming is off. This is normally done by
820 * the BIOS but in the odd case it is not the results are corruption
821 * hence the presence of a Linux check
822 */
823static void __init quirk_disable_pxb(struct pci_dev *pdev)
824{
825 u16 config;
826 u8 rev;
827
828 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
829 if (rev != 0x04) /* Only C0 requires this */
830 return;
831 pci_read_config_word(pdev, 0x40, &config);
832 if (config & (1<<6)) {
833 config &= ~(1<<6);
834 pci_write_config_word(pdev, 0x40, config);
835 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
836 }
837}
838DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
839
1da177e4
LT		 840
841/*
842 * Serverworks CSB5 IDE does not fully support native mode
843 */
844static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
845{
846 u8 prog;
847 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
848 if (prog & 5) {
849 prog &= ~5;
850 pdev->class &= ~5;
851 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
852 /* need to re-assign BARs for compat mode */
853 quirk_ide_bases(pdev);
854 }
855}
856DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
857
858/*
859 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
860 */
861static void __init quirk_ide_samemode(struct pci_dev *pdev)
862{
863 u8 prog;
864
865 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
866
867 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
868 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
869 prog &= ~5;
870 pdev->class &= ~5;
871 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
872 /* need to re-assign BARs for compat mode */
873 quirk_ide_bases(pdev);
874 }
875}
876DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
877
878/* This was originally an Alpha specific thing, but it really fits here.
879 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
880 */
881static void __init quirk_eisa_bridge(struct pci_dev *dev)
882{
883 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
884}
885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
886
7daa0c4f
JG		 887/*
888 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
889 * when a PCI-Soundcard is added. The BIOS only gives Options
890 * "Disabled" and "AUTO". This Quirk Sets the corresponding
891 * Register-Value to enable the Soundcard.
892 */
893static void __init k8t_sound_hostbridge(struct pci_dev *dev)
894{
895 unsigned char val;
896
897 printk(KERN_INFO "PCI: Quirk-MSI-K8T Soundcard On\n");
898 pci_read_config_byte(dev, 0x50, &val);
899 if (val == 0x88 || val == 0xc8) {
900 pci_write_config_byte(dev, 0x50, val & (~0x40));
901
902 /* Verify the Change for Status output */
903 pci_read_config_byte(dev, 0x50, &val);
904 if (val & 0x40)
905 printk(KERN_INFO "PCI: MSI-K8T soundcard still off\n");
906 else
907 printk(KERN_INFO "PCI: MSI-K8T soundcard on\n");
908 } else {
909 printk(KERN_INFO "PCI: Unexpected Value in PCI-Register: "
910 "no Change!\n");
911 }
912
913}
914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, k8t_sound_hostbridge);
915
ce007ea5 916#ifndef CONFIG_ACPI_SLEEP
1da177e4
LT		 917/*
918 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
919 * is not activated. The myth is that Asus said that they do not want the
920 * users to be irritated by just another PCI Device in the Win98 device
921 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
922 * package 2.7.0 for details)
923 *
924 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
925 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
926 * becomes necessary to do this tweak in two steps -- I've chosen the Host
927 * bridge as trigger.
ce007ea5
CDH		 928 *
929 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
930 * will cause thermal management to break down, and causing machine to
931 * overheat.
1da177e4 932 */
ce007ea5 933static int __initdata asus_hides_smbus;
1da177e4
LT		 934
935static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
936{
937 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
938 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
939 switch(dev->subsystem_device) {
a00db371 940 case 0x8025: /* P4B-LX */
1da177e4
LT		 941 case 0x8070: /* P4B */
942 case 0x8088: /* P4B533 */
943 case 0x1626: /* L3C notebook */
944 asus_hides_smbus = 1;
945 }
946 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
947 switch(dev->subsystem_device) {
948 case 0x80b1: /* P4GE-V */
949 case 0x80b2: /* P4PE */
950 case 0x8093: /* P4B533-V */
951 asus_hides_smbus = 1;
952 }
953 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
954 switch(dev->subsystem_device) {
955 case 0x8030: /* P4T533 */
956 asus_hides_smbus = 1;
957 }
958 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
959 switch (dev->subsystem_device) {
960 case 0x8070: /* P4G8X Deluxe */
961 asus_hides_smbus = 1;
962 }
963 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
964 switch (dev->subsystem_device) {
965 case 0x1751: /* M2N notebook */
966 case 0x1821: /* M5N notebook */
967 asus_hides_smbus = 1;
968 }
969 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
970 switch (dev->subsystem_device) {
971 case 0x184b: /* W1N notebook */
972 case 0x186a: /* M6Ne notebook */
973 asus_hides_smbus = 1;
974 }
acc06632
M		 975 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
976 switch (dev->subsystem_device) {
977 case 0x1882: /* M6V notebook */
2d1e1c75 978 case 0x1977: /* A6VA notebook */
acc06632
M		 979 asus_hides_smbus = 1;
980 }
981 }
1da177e4
LT		 982 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
983 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
984 switch(dev->subsystem_device) {
985 case 0x088C: /* HP Compaq nc8000 */
986 case 0x0890: /* HP Compaq nc6000 */
987 asus_hides_smbus = 1;
988 }
989 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
990 switch (dev->subsystem_device) {
991 case 0x12bc: /* HP D330L */
e3b1bd57 992 case 0x12bd: /* HP D530 */
1da177e4
LT		 993 asus_hides_smbus = 1;
994 }
3c0a654e 995 if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) {
996 switch (dev->subsystem_device) {
997 case 0x099c: /* HP Compaq nx6110 */
998 asus_hides_smbus = 1;
999 }
1000 }
1da177e4
LT		 1001 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
1002 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1003 switch(dev->subsystem_device) {
1004 case 0x0001: /* Toshiba Satellite A40 */
1005 asus_hides_smbus = 1;
1006 }
e96e2f14
DG		 1007 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1008 switch(dev->subsystem_device) {
1009 case 0x0001: /* Toshiba Tecra M2 */
1010 asus_hides_smbus = 1;
1011 }
1da177e4
LT		 1012 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1013 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1014 switch(dev->subsystem_device) {
1015 case 0xC00C: /* Samsung P35 notebook */
1016 asus_hides_smbus = 1;
1017 }
c87f883e
RIZ		 1018 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1019 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1020 switch(dev->subsystem_device) {
1021 case 0x0058: /* Compaq Evo N620c */
1022 asus_hides_smbus = 1;
1023 }
1da177e4
LT		 1024 }
1025}
1026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
1027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
1028DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
1029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
1030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
1031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
1032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
acc06632 1033DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge );
1da177e4
LT		 1034
1035static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
1036{
1037 u16 val;
1038
1039 if (likely(!asus_hides_smbus))
1040 return;
1041
1042 pci_read_config_word(dev, 0xF2, &val);
1043 if (val & 0x8) {
1044 pci_write_config_word(dev, 0xF2, val & (~0x8));
1045 pci_read_config_word(dev, 0xF2, &val);
1046 if (val & 0x8)
1047 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1048 else
1049 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
1050 }
1051}
1052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
1053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
2d1e1c75 1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc );
1da177e4 1058
acc06632
M		 1059static void __init asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1060{
1061 u32 val, rcba;
1062 void __iomem *base;
1063
1064 if (likely(!asus_hides_smbus))
1065 return;
1066 pci_read_config_dword(dev, 0xF0, &rcba);
1067 base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1068 if (base == NULL) return;
1069 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1070 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1071 iounmap(base);
1072 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n");
1073}
1074DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 );
1075
ce007ea5
CDH		 1076#endif
1077
1da177e4
LT		 1078/*
1079 * SiS 96x south bridge: BIOS typically hides SMBus device...
1080 */
1081static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
1082{
1083 u8 val = 0;
1084 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
1085 pci_read_config_byte(dev, 0x77, &val);
1086 pci_write_config_byte(dev, 0x77, val & ~0x10);
1087 pci_read_config_byte(dev, 0x77, &val);
1088}
1089
1da177e4
LT		 1090/*
1091 * ... This is further complicated by the fact that some SiS96x south
1092 * bridges pretend to be 85C503/5513 instead. In that case see if we
1093 * spotted a compatible north bridge to make sure.
1094 * (pci_find_device doesn't work yet)
1095 *
1096 * We can also enable the sis96x bit in the discovery register..
1097 */
1098static int __devinitdata sis_96x_compatible = 0;
1099
1100#define SIS_DETECT_REGISTER 0x40
1101
1102static void __init quirk_sis_503(struct pci_dev *dev)
1103{
1104 u8 reg;
1105 u16 devid;
1106
1107 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1108 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1109 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1110 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1111 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1112 return;
1113 }
1114
1115 /* Make people aware that we changed the config.. */
1116 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1117
1118 /*
1119 * Ok, it now shows up as a 96x.. The 96x quirks are after
1120 * the 503 quirk in the quirk table, so they'll automatically
1121 * run and enable things like the SMBus device
1122 */
1123 dev->device = devid;
1124}
1125
1126static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1127{
1128 sis_96x_compatible = 1;
1129}
1130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1133DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1134DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1135DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1136
1137DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
e5548e96
BJD		 1138/*
1139 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1140 * and MC97 modem controller are disabled when a second PCI soundcard is
1141 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1142 * -- bjd
1143 */
1144static void __init asus_hides_ac97_lpc(struct pci_dev *dev)
1145{
1146 u8 val;
1147 int asus_hides_ac97 = 0;
1148
1149 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1150 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1151 asus_hides_ac97 = 1;
1152 }
1153
1154 if (!asus_hides_ac97)
1155 return;
1156
1157 pci_read_config_byte(dev, 0x50, &val);
1158 if (val & 0xc0) {
1159 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1160 pci_read_config_byte(dev, 0x50, &val);
1161 if (val & 0xc0)
1162 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1163 else
1164 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n");
1165 }
1166}
1167DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc );
1168
1da177e4
LT		 1169
1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1171DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1173DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1174
1175#ifdef CONFIG_X86_IO_APIC
1176static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1177{
1178 int i;
1179
1180 if ((pdev->class >> 8) != 0xff00)
1181 return;
1182
1183 /* the first BAR is the location of the IO APIC...we must
1184 * not touch this (and it's already covered by the fixmap), so
1185 * forcibly insert it into the resource tree */
1186 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1187 insert_resource(&iomem_resource, &pdev->resource[0]);
1188
1189 /* The next five BARs all seem to be rubbish, so just clean
1190 * them out */
1191 for (i=1; i < 6; i++) {
1192 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1193 }
1194
1195}
1196DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1197#endif
1198
2bd0fa3b
JB		 1199enum ide_combined_type { COMBINED = 0, IDE = 1, LIBATA = 2 };
1200/* Defaults to combined */
1201static enum ide_combined_type combined_mode;
1202
1203static int __init combined_setup(char *str)
1204{
1205 if (!strncmp(str, "ide", 3))
1206 combined_mode = IDE;
1207 else if (!strncmp(str, "libata", 6))
1208 combined_mode = LIBATA;
1209 else /* "combined" or anything else defaults to old behavior */
1210 combined_mode = COMBINED;
1211
1212 return 1;
1213}
1214__setup("combined_mode=", combined_setup);
1215
cc675230 1216#ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1da177e4
LT		 1217static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1218{
1219 u8 prog, comb, tmp;
1220 int ich = 0;
1221
1222 /*
1223 * Narrow down to Intel SATA PCI devices.
1224 */
1225 switch (pdev->device) {
1226 /* PCI ids taken from drivers/scsi/ata_piix.c */
1227 case 0x24d1:
1228 case 0x24df:
1229 case 0x25a3:
1230 case 0x25b0:
1231 ich = 5;
1232 break;
1233 case 0x2651:
1234 case 0x2652:
1235 case 0x2653:
c368ca4e 1236 case 0x2680: /* ESB2 */
1da177e4
LT		 1237 ich = 6;
1238 break;
1239 case 0x27c0:
1240 case 0x27c4:
1241 ich = 7;
1242 break;
012b265f
JG		 1243 case 0x2828: /* ICH8M */
1244 ich = 8;
1245 break;
1da177e4
LT		 1246 default:
1247 /* we do not handle this PCI device */
1248 return;
1249 }
1250
1251 /*
1252 * Read combined mode register.
1253 */
1254 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1255
1256 if (ich == 5) {
1257 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1258 if (tmp == 0x4) /* bits 10x */
1259 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1260 else if (tmp == 0x6) /* bits 11x */
1261 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1262 else
1263 return; /* not in combined mode */
1264 } else {
012b265f 1265 WARN_ON((ich != 6) && (ich != 7) && (ich != 8));
1da177e4
LT		 1266 tmp &= 0x3; /* interesting bits 1:0 */
1267 if (tmp & (1 << 0))
1268 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1269 else if (tmp & (1 << 1))
1270 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1271 else
1272 return; /* not in combined mode */
1273 }
1274
1275 /*
1276 * Read programming interface register.
1277 * (Tells us if it's legacy or native mode)
1278 */
1279 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1280
1281 /* if SATA port is in native mode, we're ok. */
1282 if (prog & comb)
1283 return;
1284
2bd0fa3b
JB		 1285 /* Don't reserve any so the IDE driver can get them (but only if
1286 * combined_mode=ide).
1287 */
1288 if (combined_mode == IDE)
1289 return;
1290
1291 /* Grab them both for libata if combined_mode=libata. */
1292 if (combined_mode == LIBATA) {
1293 request_region(0x1f0, 8, "libata"); /* port 0 */
1294 request_region(0x170, 8, "libata"); /* port 1 */
1295 return;
1296 }
1297
1da177e4
LT		 1298 /* SATA port is in legacy mode. Reserve port so that
1299 * IDE driver does not attempt to use it. If request_region
1300 * fails, it will be obvious at boot time, so we don't bother
1301 * checking return values.
1302 */
1303 if (comb == (1 << 0))
1304 request_region(0x1f0, 8, "libata"); /* port 0 */
1305 else
1306 request_region(0x170, 8, "libata"); /* port 1 */
1307}
1308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
cc675230 1309#endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1da177e4
LT		 1310
1311
1312int pcie_mch_quirk;
1313
1314static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1315{
1316 pcie_mch_quirk = 1;
1317}
1318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1321
4602b88d
KA		 1322
1323/*
1324 * It's possible for the MSI to get corrupted if shpc and acpi
1325 * are used together on certain PXH-based systems.
1326 */
1327static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1328{
1329 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
1330 PCI_CAP_ID_MSI);
1331 dev->no_msi = 1;
1332
1333 printk(KERN_WARNING "PCI: PXH quirk detected, "
1334 "disabling MSI for SHPC device\n");
1335}
1336DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1337DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1338DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1339DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1340DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1341
1342
c408a379
KA		 1343/*
1344 * Fixup the cardbus bridges on the IBM Dock II docking station
1345 */
1346static void __devinit quirk_ibm_dock2_cardbus(struct pci_dev *dev)
1347{
1348 u32 val;
1349
1350 /*
1351 * tie the 2 interrupt pins to INTA, and configure the
1352 * multifunction routing register to handle this.
1353 */
1354 if ((dev->subsystem_vendor == PCI_VENDOR_ID_IBM) &&
1355 (dev->subsystem_device == 0x0148)) {
1356 printk(KERN_INFO "PCI: Found IBM Dock II Cardbus Bridge "
1357 "applying quirk\n");
1358 pci_read_config_dword(dev, 0x8c, &val);
1359 val = ((val & 0xffffff00) | 0x1002);
1360 pci_write_config_dword(dev, 0x8c, val);
1361 pci_read_config_dword(dev, 0x80, &val);
1362 val = ((val & 0x00ffff00) | 0x2864c077);
1363 pci_write_config_dword(dev, 0x80, val);
1364 }
1365}
1366
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420,
1368 quirk_ibm_dock2_cardbus);
1369
1da177e4
LT		 1370static void __devinit quirk_netmos(struct pci_dev *dev)
1371{
1372 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1373 unsigned int num_serial = dev->subsystem_device & 0xf;
1374
1375 /*
1376 * These Netmos parts are multiport serial devices with optional
1377 * parallel ports. Even when parallel ports are present, they
1378 * are identified as class SERIAL, which means the serial driver
1379 * will claim them. To prevent this, mark them as class OTHER.
1380 * These combo devices should be claimed by parport_serial.
1381 *
1382 * The subdevice ID is of the form 0x00PS, where <P> is the number
1383 * of parallel ports and <S> is the number of serial ports.
1384 */
1385 switch (dev->device) {
1386 case PCI_DEVICE_ID_NETMOS_9735:
1387 case PCI_DEVICE_ID_NETMOS_9745:
1388 case PCI_DEVICE_ID_NETMOS_9835:
1389 case PCI_DEVICE_ID_NETMOS_9845:
1390 case PCI_DEVICE_ID_NETMOS_9855:
1391 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1392 num_parallel) {
1393 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1394 "%u serial); changing class SERIAL to OTHER "
1395 "(use parport_serial)\n",
1396 dev->device, num_parallel, num_serial);
1397 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1398 (dev->class & 0xff);
1399 }
1400 }
1401}
1402DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1403
a5312e28
IK		 1404
1405static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1406{
1407 /* rev 1 ncr53c810 chips don't set the class at all which means
1408 * they don't get their resources remapped. Fix that here.
1409 */
1410
1411 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1412 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n");
1413 dev->class = PCI_CLASS_STORAGE_SCSI;
1414 }
1415}
1416DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1417
1418
1da177e4
LT		 1419static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1420{
1421 while (f < end) {
1422 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1423 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1424 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1425 f->hook(dev);
1426 }
1427 f++;
1428 }
1429}
1430
1431extern struct pci_fixup __start_pci_fixups_early[];
1432extern struct pci_fixup __end_pci_fixups_early[];
1433extern struct pci_fixup __start_pci_fixups_header[];
1434extern struct pci_fixup __end_pci_fixups_header[];
1435extern struct pci_fixup __start_pci_fixups_final[];
1436extern struct pci_fixup __end_pci_fixups_final[];
1437extern struct pci_fixup __start_pci_fixups_enable[];
1438extern struct pci_fixup __end_pci_fixups_enable[];
1439
1440
1441void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1442{
1443 struct pci_fixup *start, *end;
1444
1445 switch(pass) {
1446 case pci_fixup_early:
1447 start = __start_pci_fixups_early;
1448 end = __end_pci_fixups_early;
1449 break;
1450
1451 case pci_fixup_header:
1452 start = __start_pci_fixups_header;
1453 end = __end_pci_fixups_header;
1454 break;
1455
1456 case pci_fixup_final:
1457 start = __start_pci_fixups_final;
1458 end = __end_pci_fixups_final;
1459 break;
1460
1461 case pci_fixup_enable:
1462 start = __start_pci_fixups_enable;
1463 end = __end_pci_fixups_enable;
1464 break;
1465
1466 default:
1467 /* stupid compiler warning, you would think with an enum... */
1468 return;
1469 }
1470 pci_do_fixups(dev, start, end);
1471}
1472
9d265124
DY		 1473/* Enable 1k I/O space granularity on the Intel P64H2 */
1474static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1475{
1476 u16 en1k;
1477 u8 io_base_lo, io_limit_lo;
1478 unsigned long base, limit;
1479 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
1480
1481 pci_read_config_word(dev, 0x40, &en1k);
1482
1483 if (en1k & 0x200) {
1484 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n");
1485
1486 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1487 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1488 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1489 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
1490
1491 if (base <= limit) {
1492 res->start = base;
1493 res->end = limit + 0x3ff;
1494 }
1495 }
1496}
1497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
1498
1da177e4
LT		 1499EXPORT_SYMBOL(pcie_mch_quirk);
1500#ifdef CONFIG_HOTPLUG
1501EXPORT_SYMBOL(pci_fixup_device);
1502#endif
Linux kernel - Deliverables
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