Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file contains work-arounds for many known PCI hardware | |
3 | * bugs. Devices present only on certain architectures (host | |
4 | * bridges et cetera) should be handled in arch-specific code. | |
5 | * | |
6 | * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. | |
7 | * | |
8 | * Copyright (c) 1999 Martin Mares <mj@ucw.cz> | |
9 | * | |
7586269c DB |
10 | * Init/reset quirks for USB host controllers should be in the |
11 | * USB quirks file, where their drivers can access reuse it. | |
12 | * | |
1da177e4 LT |
13 | * The bridge optimization stuff has been removed. If you really |
14 | * have a silly BIOS which is unable to set your host bridge right, | |
15 | * use the PowerTweak utility (see http://powertweak.sourceforge.net). | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <linux/types.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/delay.h> | |
25be5e6c | 23 | #include <linux/acpi.h> |
9f23ed3b | 24 | #include <linux/kallsyms.h> |
75e07fc3 | 25 | #include <linux/dmi.h> |
649426ef | 26 | #include <linux/pci-aspm.h> |
32a9a682 | 27 | #include <linux/ioport.h> |
93177a74 | 28 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
bc56b9e0 | 29 | #include "pci.h" |
1da177e4 | 30 | |
32a9a682 | 31 | /* |
0cdbe30f YS |
32 | * This quirk function disables memory decoding and releases memory resources |
33 | * of the device specified by kernel's boot parameter 'pci=resource_alignment='. | |
32a9a682 YS |
34 | * It also rounds up size to specified alignment. |
35 | * Later on, the kernel will assign page-aligned memory resource back | |
0cdbe30f | 36 | * to the device. |
32a9a682 YS |
37 | */ |
38 | static void __devinit quirk_resource_alignment(struct pci_dev *dev) | |
39 | { | |
40 | int i; | |
41 | struct resource *r; | |
42 | resource_size_t align, size; | |
0cdbe30f | 43 | u16 command; |
32a9a682 YS |
44 | |
45 | if (!pci_is_reassigndev(dev)) | |
46 | return; | |
47 | ||
48 | if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
49 | (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { | |
50 | dev_warn(&dev->dev, | |
51 | "Can't reassign resources to host bridge.\n"); | |
52 | return; | |
53 | } | |
54 | ||
0cdbe30f YS |
55 | dev_info(&dev->dev, |
56 | "Disabling memory decoding and releasing memory resources.\n"); | |
57 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
58 | command &= ~PCI_COMMAND_MEMORY; | |
59 | pci_write_config_word(dev, PCI_COMMAND, command); | |
32a9a682 YS |
60 | |
61 | align = pci_specified_resource_alignment(dev); | |
62 | for (i=0; i < PCI_BRIDGE_RESOURCES; i++) { | |
63 | r = &dev->resource[i]; | |
64 | if (!(r->flags & IORESOURCE_MEM)) | |
65 | continue; | |
66 | size = resource_size(r); | |
67 | if (size < align) { | |
68 | size = align; | |
69 | dev_info(&dev->dev, | |
70 | "Rounding up size of resource #%d to %#llx.\n", | |
71 | i, (unsigned long long)size); | |
72 | } | |
73 | r->end = size - 1; | |
74 | r->start = 0; | |
75 | } | |
76 | /* Need to disable bridge's resource window, | |
77 | * to enable the kernel to reassign new resource | |
78 | * window later on. | |
79 | */ | |
80 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && | |
81 | (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { | |
82 | for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) { | |
83 | r = &dev->resource[i]; | |
84 | if (!(r->flags & IORESOURCE_MEM)) | |
85 | continue; | |
86 | r->end = resource_size(r) - 1; | |
87 | r->start = 0; | |
88 | } | |
89 | pci_disable_bridge_window(dev); | |
90 | } | |
91 | } | |
92 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment); | |
93 | ||
253d2e54 JP |
94 | /* |
95 | * Decoding should be disabled for a PCI device during BAR sizing to avoid | |
96 | * conflict. But doing so may cause problems on host bridge and perhaps other | |
97 | * key system devices. For devices that need to have mmio decoding always-on, | |
98 | * we need to set the dev->mmio_always_on bit. | |
99 | */ | |
100 | static void __devinit quirk_mmio_always_on(struct pci_dev *dev) | |
101 | { | |
102 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
103 | dev->mmio_always_on = 1; | |
104 | } | |
105 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on); | |
106 | ||
bd8481e1 DT |
107 | /* The Mellanox Tavor device gives false positive parity errors |
108 | * Mark this device with a broken_parity_status, to allow | |
109 | * PCI scanning code to "skip" this now blacklisted device. | |
110 | */ | |
111 | static void __devinit quirk_mellanox_tavor(struct pci_dev *dev) | |
112 | { | |
113 | dev->broken_parity_status = 1; /* This device gives false positives */ | |
114 | } | |
115 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor); | |
116 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor); | |
117 | ||
1da177e4 LT |
118 | /* Deal with broken BIOS'es that neglect to enable passive release, |
119 | which can cause problems in combination with the 82441FX/PPro MTRRs */ | |
1597cacb | 120 | static void quirk_passive_release(struct pci_dev *dev) |
1da177e4 LT |
121 | { |
122 | struct pci_dev *d = NULL; | |
123 | unsigned char dlc; | |
124 | ||
125 | /* We have to make sure a particular bit is set in the PIIX3 | |
126 | ISA bridge, so we have to go out and find it. */ | |
127 | while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { | |
128 | pci_read_config_byte(d, 0x82, &dlc); | |
129 | if (!(dlc & 1<<1)) { | |
999da9fd | 130 | dev_info(&d->dev, "PIIX3: Enabling Passive Release\n"); |
1da177e4 LT |
131 | dlc |= 1<<1; |
132 | pci_write_config_byte(d, 0x82, dlc); | |
133 | } | |
134 | } | |
135 | } | |
652c538e AM |
136 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); |
137 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); | |
1da177e4 LT |
138 | |
139 | /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround | |
140 | but VIA don't answer queries. If you happen to have good contacts at VIA | |
141 | ask them for me please -- Alan | |
142 | ||
143 | This appears to be BIOS not version dependent. So presumably there is a | |
144 | chipset level fix */ | |
1da177e4 LT |
145 | |
146 | static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev) | |
147 | { | |
148 | if (!isa_dma_bridge_buggy) { | |
149 | isa_dma_bridge_buggy=1; | |
f0fda801 | 150 | dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n"); |
1da177e4 LT |
151 | } |
152 | } | |
153 | /* | |
154 | * Its not totally clear which chipsets are the problematic ones | |
155 | * We know 82C586 and 82C596 variants are affected. | |
156 | */ | |
652c538e AM |
157 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); |
158 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); | |
159 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); | |
160 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); | |
161 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); | |
162 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); | |
163 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); | |
1da177e4 | 164 | |
4731fdcf LB |
165 | /* |
166 | * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear | |
167 | * for some HT machines to use C4 w/o hanging. | |
168 | */ | |
169 | static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev) | |
170 | { | |
171 | u32 pmbase; | |
172 | u16 pm1a; | |
173 | ||
174 | pci_read_config_dword(dev, 0x40, &pmbase); | |
175 | pmbase = pmbase & 0xff80; | |
176 | pm1a = inw(pmbase); | |
177 | ||
178 | if (pm1a & 0x10) { | |
179 | dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n"); | |
180 | outw(0x10, pmbase); | |
181 | } | |
182 | } | |
183 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); | |
184 | ||
1da177e4 LT |
185 | /* |
186 | * Chipsets where PCI->PCI transfers vanish or hang | |
187 | */ | |
188 | static void __devinit quirk_nopcipci(struct pci_dev *dev) | |
189 | { | |
190 | if ((pci_pci_problems & PCIPCI_FAIL)==0) { | |
f0fda801 | 191 | dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n"); |
1da177e4 LT |
192 | pci_pci_problems |= PCIPCI_FAIL; |
193 | } | |
194 | } | |
652c538e AM |
195 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); |
196 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); | |
236561e5 AC |
197 | |
198 | static void __devinit quirk_nopciamd(struct pci_dev *dev) | |
199 | { | |
200 | u8 rev; | |
201 | pci_read_config_byte(dev, 0x08, &rev); | |
202 | if (rev == 0x13) { | |
203 | /* Erratum 24 */ | |
f0fda801 | 204 | dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); |
236561e5 AC |
205 | pci_pci_problems |= PCIAGP_FAIL; |
206 | } | |
207 | } | |
652c538e | 208 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); |
1da177e4 LT |
209 | |
210 | /* | |
211 | * Triton requires workarounds to be used by the drivers | |
212 | */ | |
213 | static void __devinit quirk_triton(struct pci_dev *dev) | |
214 | { | |
215 | if ((pci_pci_problems&PCIPCI_TRITON)==0) { | |
f0fda801 | 216 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
217 | pci_pci_problems |= PCIPCI_TRITON; |
218 | } | |
219 | } | |
652c538e AM |
220 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); |
221 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); | |
222 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); | |
223 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); | |
1da177e4 LT |
224 | |
225 | /* | |
226 | * VIA Apollo KT133 needs PCI latency patch | |
227 | * Made according to a windows driver based patch by George E. Breese | |
228 | * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm | |
631dd1a8 | 229 | * and http://www.georgebreese.com/net/software/#PCI |
1da177e4 LT |
230 | * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for |
231 | * the info on which Mr Breese based his work. | |
232 | * | |
233 | * Updated based on further information from the site and also on | |
234 | * information provided by VIA | |
235 | */ | |
1597cacb | 236 | static void quirk_vialatency(struct pci_dev *dev) |
1da177e4 LT |
237 | { |
238 | struct pci_dev *p; | |
1da177e4 LT |
239 | u8 busarb; |
240 | /* Ok we have a potential problem chipset here. Now see if we have | |
241 | a buggy southbridge */ | |
242 | ||
243 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); | |
244 | if (p!=NULL) { | |
1da177e4 LT |
245 | /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ |
246 | /* Check for buggy part revisions */ | |
2b1afa87 | 247 | if (p->revision < 0x40 || p->revision > 0x42) |
1da177e4 LT |
248 | goto exit; |
249 | } else { | |
250 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); | |
251 | if (p==NULL) /* No problem parts */ | |
252 | goto exit; | |
1da177e4 | 253 | /* Check for buggy part revisions */ |
2b1afa87 | 254 | if (p->revision < 0x10 || p->revision > 0x12) |
1da177e4 LT |
255 | goto exit; |
256 | } | |
257 | ||
258 | /* | |
259 | * Ok we have the problem. Now set the PCI master grant to | |
260 | * occur every master grant. The apparent bug is that under high | |
261 | * PCI load (quite common in Linux of course) you can get data | |
262 | * loss when the CPU is held off the bus for 3 bus master requests | |
263 | * This happens to include the IDE controllers.... | |
264 | * | |
265 | * VIA only apply this fix when an SB Live! is present but under | |
25985edc | 266 | * both Linux and Windows this isn't enough, and we have seen |
1da177e4 LT |
267 | * corruption without SB Live! but with things like 3 UDMA IDE |
268 | * controllers. So we ignore that bit of the VIA recommendation.. | |
269 | */ | |
270 | ||
271 | pci_read_config_byte(dev, 0x76, &busarb); | |
272 | /* Set bit 4 and bi 5 of byte 76 to 0x01 | |
273 | "Master priority rotation on every PCI master grant */ | |
274 | busarb &= ~(1<<5); | |
275 | busarb |= (1<<4); | |
276 | pci_write_config_byte(dev, 0x76, busarb); | |
f0fda801 | 277 | dev_info(&dev->dev, "Applying VIA southbridge workaround\n"); |
1da177e4 LT |
278 | exit: |
279 | pci_dev_put(p); | |
280 | } | |
652c538e AM |
281 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
282 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
283 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1597cacb | 284 | /* Must restore this on a resume from RAM */ |
652c538e AM |
285 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); |
286 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); | |
287 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); | |
1da177e4 LT |
288 | |
289 | /* | |
290 | * VIA Apollo VP3 needs ETBF on BT848/878 | |
291 | */ | |
292 | static void __devinit quirk_viaetbf(struct pci_dev *dev) | |
293 | { | |
294 | if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { | |
f0fda801 | 295 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
296 | pci_pci_problems |= PCIPCI_VIAETBF; |
297 | } | |
298 | } | |
652c538e | 299 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); |
1da177e4 LT |
300 | |
301 | static void __devinit quirk_vsfx(struct pci_dev *dev) | |
302 | { | |
303 | if ((pci_pci_problems&PCIPCI_VSFX)==0) { | |
f0fda801 | 304 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
305 | pci_pci_problems |= PCIPCI_VSFX; |
306 | } | |
307 | } | |
652c538e | 308 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); |
1da177e4 LT |
309 | |
310 | /* | |
311 | * Ali Magik requires workarounds to be used by the drivers | |
312 | * that DMA to AGP space. Latency must be set to 0xA and triton | |
313 | * workaround applied too | |
314 | * [Info kindly provided by ALi] | |
315 | */ | |
316 | static void __init quirk_alimagik(struct pci_dev *dev) | |
317 | { | |
318 | if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { | |
f0fda801 | 319 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
320 | pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; |
321 | } | |
322 | } | |
652c538e AM |
323 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); |
324 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); | |
1da177e4 LT |
325 | |
326 | /* | |
327 | * Natoma has some interesting boundary conditions with Zoran stuff | |
328 | * at least | |
329 | */ | |
330 | static void __devinit quirk_natoma(struct pci_dev *dev) | |
331 | { | |
332 | if ((pci_pci_problems&PCIPCI_NATOMA)==0) { | |
f0fda801 | 333 | dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n"); |
1da177e4 LT |
334 | pci_pci_problems |= PCIPCI_NATOMA; |
335 | } | |
336 | } | |
652c538e AM |
337 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); |
338 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); | |
339 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); | |
340 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); | |
341 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); | |
342 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); | |
1da177e4 LT |
343 | |
344 | /* | |
345 | * This chip can cause PCI parity errors if config register 0xA0 is read | |
346 | * while DMAs are occurring. | |
347 | */ | |
348 | static void __devinit quirk_citrine(struct pci_dev *dev) | |
349 | { | |
350 | dev->cfg_size = 0xA0; | |
351 | } | |
652c538e | 352 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); |
1da177e4 LT |
353 | |
354 | /* | |
355 | * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. | |
356 | * If it's needed, re-allocate the region. | |
357 | */ | |
358 | static void __devinit quirk_s3_64M(struct pci_dev *dev) | |
359 | { | |
360 | struct resource *r = &dev->resource[0]; | |
361 | ||
362 | if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { | |
363 | r->start = 0; | |
364 | r->end = 0x3ffffff; | |
365 | } | |
366 | } | |
652c538e AM |
367 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); |
368 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); | |
1da177e4 | 369 | |
73d2eaac AS |
370 | /* |
371 | * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS | |
372 | * ver. 1.33 20070103) don't set the correct ISA PCI region header info. | |
373 | * BAR0 should be 8 bytes; instead, it may be set to something like 8k | |
374 | * (which conflicts w/ BAR1's memory range). | |
375 | */ | |
376 | static void __devinit quirk_cs5536_vsa(struct pci_dev *dev) | |
377 | { | |
378 | if (pci_resource_len(dev, 0) != 8) { | |
379 | struct resource *res = &dev->resource[0]; | |
380 | res->end = res->start + 8 - 1; | |
381 | dev_info(&dev->dev, "CS5536 ISA bridge bug detected " | |
382 | "(incorrect header); workaround applied.\n"); | |
383 | } | |
384 | } | |
385 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); | |
386 | ||
6693e74a LT |
387 | static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, |
388 | unsigned size, int nr, const char *name) | |
1da177e4 LT |
389 | { |
390 | region &= ~(size-1); | |
391 | if (region) { | |
085ae41f | 392 | struct pci_bus_region bus_region; |
1da177e4 LT |
393 | struct resource *res = dev->resource + nr; |
394 | ||
395 | res->name = pci_name(dev); | |
396 | res->start = region; | |
397 | res->end = region + size - 1; | |
398 | res->flags = IORESOURCE_IO; | |
085ae41f DM |
399 | |
400 | /* Convert from PCI bus to resource space. */ | |
401 | bus_region.start = res->start; | |
402 | bus_region.end = res->end; | |
403 | pcibios_bus_to_resource(dev, res, &bus_region); | |
404 | ||
f967a443 BH |
405 | if (pci_claim_resource(dev, nr) == 0) |
406 | dev_info(&dev->dev, "quirk: %pR claimed by %s\n", | |
407 | res, name); | |
1da177e4 LT |
408 | } |
409 | } | |
410 | ||
411 | /* | |
412 | * ATI Northbridge setups MCE the processor if you even | |
413 | * read somewhere between 0x3b0->0x3bb or read 0x3d3 | |
414 | */ | |
415 | static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) | |
416 | { | |
f0fda801 | 417 | dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); |
1da177e4 LT |
418 | /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ |
419 | request_region(0x3b0, 0x0C, "RadeonIGP"); | |
420 | request_region(0x3d3, 0x01, "RadeonIGP"); | |
421 | } | |
652c538e | 422 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); |
1da177e4 LT |
423 | |
424 | /* | |
425 | * Let's make the southbridge information explicit instead | |
426 | * of having to worry about people probing the ACPI areas, | |
427 | * for example.. (Yes, it happens, and if you read the wrong | |
428 | * ACPI register it will put the machine to sleep with no | |
429 | * way of waking it up again. Bummer). | |
430 | * | |
431 | * ALI M7101: Two IO regions pointed to by words at | |
432 | * 0xE0 (64 bytes of ACPI registers) | |
433 | * 0xE2 (32 bytes of SMB registers) | |
434 | */ | |
435 | static void __devinit quirk_ali7101_acpi(struct pci_dev *dev) | |
436 | { | |
437 | u16 region; | |
438 | ||
439 | pci_read_config_word(dev, 0xE0, ®ion); | |
6693e74a | 440 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); |
1da177e4 | 441 | pci_read_config_word(dev, 0xE2, ®ion); |
6693e74a | 442 | quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); |
1da177e4 | 443 | } |
652c538e | 444 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); |
1da177e4 | 445 | |
6693e74a LT |
446 | static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) |
447 | { | |
448 | u32 devres; | |
449 | u32 mask, size, base; | |
450 | ||
451 | pci_read_config_dword(dev, port, &devres); | |
452 | if ((devres & enable) != enable) | |
453 | return; | |
454 | mask = (devres >> 16) & 15; | |
455 | base = devres & 0xffff; | |
456 | size = 16; | |
457 | for (;;) { | |
458 | unsigned bit = size >> 1; | |
459 | if ((bit & mask) == bit) | |
460 | break; | |
461 | size = bit; | |
462 | } | |
463 | /* | |
464 | * For now we only print it out. Eventually we'll want to | |
465 | * reserve it (at least if it's in the 0x1000+ range), but | |
466 | * let's get enough confirmation reports first. | |
467 | */ | |
468 | base &= -size; | |
f0fda801 | 469 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
470 | } |
471 | ||
472 | static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) | |
473 | { | |
474 | u32 devres; | |
475 | u32 mask, size, base; | |
476 | ||
477 | pci_read_config_dword(dev, port, &devres); | |
478 | if ((devres & enable) != enable) | |
479 | return; | |
480 | base = devres & 0xffff0000; | |
481 | mask = (devres & 0x3f) << 16; | |
482 | size = 128 << 16; | |
483 | for (;;) { | |
484 | unsigned bit = size >> 1; | |
485 | if ((bit & mask) == bit) | |
486 | break; | |
487 | size = bit; | |
488 | } | |
489 | /* | |
490 | * For now we only print it out. Eventually we'll want to | |
491 | * reserve it, but let's get enough confirmation reports first. | |
492 | */ | |
493 | base &= -size; | |
f0fda801 | 494 | dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); |
6693e74a LT |
495 | } |
496 | ||
1da177e4 LT |
497 | /* |
498 | * PIIX4 ACPI: Two IO regions pointed to by longwords at | |
499 | * 0x40 (64 bytes of ACPI registers) | |
08db2a70 | 500 | * 0x90 (16 bytes of SMB registers) |
6693e74a | 501 | * and a few strange programmable PIIX4 device resources. |
1da177e4 LT |
502 | */ |
503 | static void __devinit quirk_piix4_acpi(struct pci_dev *dev) | |
504 | { | |
6693e74a | 505 | u32 region, res_a; |
1da177e4 LT |
506 | |
507 | pci_read_config_dword(dev, 0x40, ®ion); | |
6693e74a | 508 | quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); |
1da177e4 | 509 | pci_read_config_dword(dev, 0x90, ®ion); |
08db2a70 | 510 | quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); |
6693e74a LT |
511 | |
512 | /* Device resource A has enables for some of the other ones */ | |
513 | pci_read_config_dword(dev, 0x5c, &res_a); | |
514 | ||
515 | piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); | |
516 | piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); | |
517 | ||
518 | /* Device resource D is just bitfields for static resources */ | |
519 | ||
520 | /* Device 12 enabled? */ | |
521 | if (res_a & (1 << 29)) { | |
522 | piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); | |
523 | piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); | |
524 | } | |
525 | /* Device 13 enabled? */ | |
526 | if (res_a & (1 << 30)) { | |
527 | piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); | |
528 | piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); | |
529 | } | |
530 | piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); | |
531 | piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); | |
1da177e4 | 532 | } |
652c538e AM |
533 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); |
534 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); | |
1da177e4 | 535 | |
cdb97558 JS |
536 | #define ICH_PMBASE 0x40 |
537 | #define ICH_ACPI_CNTL 0x44 | |
538 | #define ICH4_ACPI_EN 0x10 | |
539 | #define ICH6_ACPI_EN 0x80 | |
540 | #define ICH4_GPIOBASE 0x58 | |
541 | #define ICH4_GPIO_CNTL 0x5c | |
542 | #define ICH4_GPIO_EN 0x10 | |
543 | #define ICH6_GPIOBASE 0x48 | |
544 | #define ICH6_GPIO_CNTL 0x4c | |
545 | #define ICH6_GPIO_EN 0x10 | |
546 | ||
1da177e4 LT |
547 | /* |
548 | * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at | |
549 | * 0x40 (128 bytes of ACPI, GPIO & TCO registers) | |
550 | * 0x58 (64 bytes of GPIO I/O space) | |
551 | */ | |
552 | static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev) | |
553 | { | |
554 | u32 region; | |
cdb97558 | 555 | u8 enable; |
1da177e4 | 556 | |
87e3dc38 JS |
557 | /* |
558 | * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict | |
559 | * with low legacy (and fixed) ports. We don't know the decoding | |
560 | * priority and can't tell whether the legacy device or the one created | |
561 | * here is really at that address. This happens on boards with broken | |
562 | * BIOSes. | |
563 | */ | |
564 | ||
cdb97558 JS |
565 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
566 | if (enable & ICH4_ACPI_EN) { | |
567 | pci_read_config_dword(dev, ICH_PMBASE, ®ion); | |
87e3dc38 JS |
568 | region &= PCI_BASE_ADDRESS_IO_MASK; |
569 | if (region >= PCIBIOS_MIN_IO) | |
570 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, | |
571 | "ICH4 ACPI/GPIO/TCO"); | |
cdb97558 | 572 | } |
1da177e4 | 573 | |
cdb97558 JS |
574 | pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); |
575 | if (enable & ICH4_GPIO_EN) { | |
576 | pci_read_config_dword(dev, ICH4_GPIOBASE, ®ion); | |
87e3dc38 JS |
577 | region &= PCI_BASE_ADDRESS_IO_MASK; |
578 | if (region >= PCIBIOS_MIN_IO) | |
579 | quirk_io_region(dev, region, 64, | |
580 | PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO"); | |
cdb97558 | 581 | } |
1da177e4 | 582 | } |
652c538e AM |
583 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); |
584 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); | |
585 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); | |
586 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); | |
587 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); | |
588 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); | |
589 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); | |
590 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); | |
591 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); | |
592 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); | |
1da177e4 | 593 | |
894886e5 | 594 | static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev) |
2cea752f M |
595 | { |
596 | u32 region; | |
cdb97558 | 597 | u8 enable; |
2cea752f | 598 | |
cdb97558 JS |
599 | pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); |
600 | if (enable & ICH6_ACPI_EN) { | |
601 | pci_read_config_dword(dev, ICH_PMBASE, ®ion); | |
87e3dc38 JS |
602 | region &= PCI_BASE_ADDRESS_IO_MASK; |
603 | if (region >= PCIBIOS_MIN_IO) | |
604 | quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES, | |
605 | "ICH6 ACPI/GPIO/TCO"); | |
cdb97558 | 606 | } |
2cea752f | 607 | |
cdb97558 | 608 | pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); |
b6d95bb6 | 609 | if (enable & ICH6_GPIO_EN) { |
cdb97558 | 610 | pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion); |
87e3dc38 JS |
611 | region &= PCI_BASE_ADDRESS_IO_MASK; |
612 | if (region >= PCIBIOS_MIN_IO) | |
613 | quirk_io_region(dev, region, 64, | |
614 | PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO"); | |
cdb97558 | 615 | } |
2cea752f | 616 | } |
894886e5 LT |
617 | |
618 | static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize) | |
619 | { | |
620 | u32 val; | |
621 | u32 size, base; | |
622 | ||
623 | pci_read_config_dword(dev, reg, &val); | |
624 | ||
625 | /* Enabled? */ | |
626 | if (!(val & 1)) | |
627 | return; | |
628 | base = val & 0xfffc; | |
629 | if (dynsize) { | |
630 | /* | |
631 | * This is not correct. It is 16, 32 or 64 bytes depending on | |
632 | * register D31:F0:ADh bits 5:4. | |
633 | * | |
634 | * But this gets us at least _part_ of it. | |
635 | */ | |
636 | size = 16; | |
637 | } else { | |
638 | size = 128; | |
639 | } | |
640 | base &= ~(size-1); | |
641 | ||
642 | /* Just print it out for now. We should reserve it after more debugging */ | |
643 | dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); | |
644 | } | |
645 | ||
646 | static void __devinit quirk_ich6_lpc(struct pci_dev *dev) | |
647 | { | |
648 | /* Shared ACPI/GPIO decode with all ICH6+ */ | |
649 | ich6_lpc_acpi_gpio(dev); | |
650 | ||
651 | /* ICH6-specific generic IO decode */ | |
652 | ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); | |
653 | ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); | |
654 | } | |
655 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); | |
656 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); | |
657 | ||
658 | static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name) | |
659 | { | |
660 | u32 val; | |
661 | u32 mask, base; | |
662 | ||
663 | pci_read_config_dword(dev, reg, &val); | |
664 | ||
665 | /* Enabled? */ | |
666 | if (!(val & 1)) | |
667 | return; | |
668 | ||
669 | /* | |
670 | * IO base in bits 15:2, mask in bits 23:18, both | |
671 | * are dword-based | |
672 | */ | |
673 | base = val & 0xfffc; | |
674 | mask = (val >> 16) & 0xfc; | |
675 | mask |= 3; | |
676 | ||
677 | /* Just print it out for now. We should reserve it after more debugging */ | |
678 | dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); | |
679 | } | |
680 | ||
681 | /* ICH7-10 has the same common LPC generic IO decode registers */ | |
682 | static void __devinit quirk_ich7_lpc(struct pci_dev *dev) | |
683 | { | |
5d9c0a79 | 684 | /* We share the common ACPI/GPIO decode with ICH6 */ |
894886e5 LT |
685 | ich6_lpc_acpi_gpio(dev); |
686 | ||
687 | /* And have 4 ICH7+ generic decodes */ | |
688 | ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); | |
689 | ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); | |
690 | ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); | |
691 | ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); | |
692 | } | |
693 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); | |
694 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); | |
695 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); | |
696 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); | |
697 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); | |
698 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); | |
699 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); | |
700 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); | |
701 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); | |
702 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); | |
703 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); | |
704 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); | |
705 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); | |
2cea752f | 706 | |
1da177e4 LT |
707 | /* |
708 | * VIA ACPI: One IO region pointed to by longword at | |
709 | * 0x48 or 0x20 (256 bytes of ACPI registers) | |
710 | */ | |
711 | static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev) | |
712 | { | |
1da177e4 LT |
713 | u32 region; |
714 | ||
651472fb | 715 | if (dev->revision & 0x10) { |
1da177e4 LT |
716 | pci_read_config_dword(dev, 0x48, ®ion); |
717 | region &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 718 | quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); |
1da177e4 LT |
719 | } |
720 | } | |
652c538e | 721 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); |
1da177e4 LT |
722 | |
723 | /* | |
724 | * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at | |
725 | * 0x48 (256 bytes of ACPI registers) | |
726 | * 0x70 (128 bytes of hardware monitoring register) | |
727 | * 0x90 (16 bytes of SMB registers) | |
728 | */ | |
729 | static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev) | |
730 | { | |
731 | u16 hm; | |
732 | u32 smb; | |
733 | ||
734 | quirk_vt82c586_acpi(dev); | |
735 | ||
736 | pci_read_config_word(dev, 0x70, &hm); | |
737 | hm &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 738 | quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon"); |
1da177e4 LT |
739 | |
740 | pci_read_config_dword(dev, 0x90, &smb); | |
741 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
02f313b2 | 742 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); |
1da177e4 | 743 | } |
652c538e | 744 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); |
1da177e4 | 745 | |
6d85f29b IK |
746 | /* |
747 | * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at | |
748 | * 0x88 (128 bytes of power management registers) | |
749 | * 0xd0 (16 bytes of SMB registers) | |
750 | */ | |
751 | static void __devinit quirk_vt8235_acpi(struct pci_dev *dev) | |
752 | { | |
753 | u16 pm, smb; | |
754 | ||
755 | pci_read_config_word(dev, 0x88, &pm); | |
756 | pm &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 757 | quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); |
6d85f29b IK |
758 | |
759 | pci_read_config_word(dev, 0xd0, &smb); | |
760 | smb &= PCI_BASE_ADDRESS_IO_MASK; | |
6693e74a | 761 | quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB"); |
6d85f29b IK |
762 | } |
763 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); | |
764 | ||
1f56f4a2 GB |
765 | /* |
766 | * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back: | |
767 | * Disable fast back-to-back on the secondary bus segment | |
768 | */ | |
769 | static void __devinit quirk_xio2000a(struct pci_dev *dev) | |
770 | { | |
771 | struct pci_dev *pdev; | |
772 | u16 command; | |
773 | ||
774 | dev_warn(&dev->dev, "TI XIO2000a quirk detected; " | |
775 | "secondary bus fast back-to-back transfers disabled\n"); | |
776 | list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { | |
777 | pci_read_config_word(pdev, PCI_COMMAND, &command); | |
778 | if (command & PCI_COMMAND_FAST_BACK) | |
779 | pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); | |
780 | } | |
781 | } | |
782 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, | |
783 | quirk_xio2000a); | |
1da177e4 LT |
784 | |
785 | #ifdef CONFIG_X86_IO_APIC | |
786 | ||
787 | #include <asm/io_apic.h> | |
788 | ||
789 | /* | |
790 | * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip | |
791 | * devices to the external APIC. | |
792 | * | |
793 | * TODO: When we have device-specific interrupt routers, | |
794 | * this code will go away from quirks. | |
795 | */ | |
1597cacb | 796 | static void quirk_via_ioapic(struct pci_dev *dev) |
1da177e4 LT |
797 | { |
798 | u8 tmp; | |
799 | ||
800 | if (nr_ioapics < 1) | |
801 | tmp = 0; /* nothing routed to external APIC */ | |
802 | else | |
803 | tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ | |
804 | ||
f0fda801 | 805 | dev_info(&dev->dev, "%sbling VIA external APIC routing\n", |
1da177e4 LT |
806 | tmp == 0 ? "Disa" : "Ena"); |
807 | ||
808 | /* Offset 0x58: External APIC IRQ output control */ | |
809 | pci_write_config_byte (dev, 0x58, tmp); | |
810 | } | |
652c538e | 811 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
e1a2a51e | 812 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); |
1da177e4 | 813 | |
a1740913 KW |
814 | /* |
815 | * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. | |
816 | * This leads to doubled level interrupt rates. | |
817 | * Set this bit to get rid of cycle wastage. | |
818 | * Otherwise uncritical. | |
819 | */ | |
1597cacb | 820 | static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) |
a1740913 KW |
821 | { |
822 | u8 misc_control2; | |
823 | #define BYPASS_APIC_DEASSERT 8 | |
824 | ||
825 | pci_read_config_byte(dev, 0x5B, &misc_control2); | |
826 | if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { | |
f0fda801 | 827 | dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); |
a1740913 KW |
828 | pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); |
829 | } | |
830 | } | |
831 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); | |
e1a2a51e | 832 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); |
a1740913 | 833 | |
1da177e4 LT |
834 | /* |
835 | * The AMD io apic can hang the box when an apic irq is masked. | |
836 | * We check all revs >= B0 (yet not in the pre production!) as the bug | |
837 | * is currently marked NoFix | |
838 | * | |
839 | * We have multiple reports of hangs with this chipset that went away with | |
236561e5 | 840 | * noapic specified. For the moment we assume it's the erratum. We may be wrong |
1da177e4 LT |
841 | * of course. However the advice is demonstrably good even if so.. |
842 | */ | |
843 | static void __devinit quirk_amd_ioapic(struct pci_dev *dev) | |
844 | { | |
44c10138 | 845 | if (dev->revision >= 0x02) { |
f0fda801 | 846 | dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); |
847 | dev_warn(&dev->dev, " : booting with the \"noapic\" option\n"); | |
1da177e4 LT |
848 | } |
849 | } | |
652c538e | 850 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); |
1da177e4 LT |
851 | |
852 | static void __init quirk_ioapic_rmw(struct pci_dev *dev) | |
853 | { | |
854 | if (dev->devfn == 0 && dev->bus->number == 0) | |
855 | sis_apic_bug = 1; | |
856 | } | |
652c538e | 857 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw); |
1da177e4 LT |
858 | #endif /* CONFIG_X86_IO_APIC */ |
859 | ||
d556ad4b PO |
860 | /* |
861 | * Some settings of MMRBC can lead to data corruption so block changes. | |
862 | * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide | |
863 | */ | |
864 | static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) | |
865 | { | |
aa288d4d | 866 | if (dev->subordinate && dev->revision <= 0x12) { |
f0fda801 | 867 | dev_info(&dev->dev, "AMD8131 rev %x detected; " |
868 | "disabling PCI-X MMRBC\n", dev->revision); | |
d556ad4b PO |
869 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; |
870 | } | |
871 | } | |
872 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); | |
1da177e4 | 873 | |
1da177e4 LT |
874 | /* |
875 | * FIXME: it is questionable that quirk_via_acpi | |
876 | * is needed. It shows up as an ISA bridge, and does not | |
877 | * support the PCI_INTERRUPT_LINE register at all. Therefore | |
878 | * it seems like setting the pci_dev's 'irq' to the | |
879 | * value of the ACPI SCI interrupt is only done for convenience. | |
880 | * -jgarzik | |
881 | */ | |
882 | static void __devinit quirk_via_acpi(struct pci_dev *d) | |
883 | { | |
884 | /* | |
885 | * VIA ACPI device: SCI IRQ line in PCI config byte 0x42 | |
886 | */ | |
887 | u8 irq; | |
888 | pci_read_config_byte(d, 0x42, &irq); | |
889 | irq &= 0xf; | |
890 | if (irq && (irq != 2)) | |
891 | d->irq = irq; | |
892 | } | |
652c538e AM |
893 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); |
894 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); | |
1da177e4 | 895 | |
09d6029f DD |
896 | |
897 | /* | |
1597cacb | 898 | * VIA bridges which have VLink |
09d6029f | 899 | */ |
1597cacb | 900 | |
c06bb5d4 JD |
901 | static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; |
902 | ||
903 | static void quirk_via_bridge(struct pci_dev *dev) | |
904 | { | |
905 | /* See what bridge we have and find the device ranges */ | |
906 | switch (dev->device) { | |
907 | case PCI_DEVICE_ID_VIA_82C686: | |
cb7468ef JD |
908 | /* The VT82C686 is special, it attaches to PCI and can have |
909 | any device number. All its subdevices are functions of | |
910 | that single device. */ | |
911 | via_vlink_dev_lo = PCI_SLOT(dev->devfn); | |
912 | via_vlink_dev_hi = PCI_SLOT(dev->devfn); | |
c06bb5d4 JD |
913 | break; |
914 | case PCI_DEVICE_ID_VIA_8237: | |
915 | case PCI_DEVICE_ID_VIA_8237A: | |
916 | via_vlink_dev_lo = 15; | |
917 | break; | |
918 | case PCI_DEVICE_ID_VIA_8235: | |
919 | via_vlink_dev_lo = 16; | |
920 | break; | |
921 | case PCI_DEVICE_ID_VIA_8231: | |
922 | case PCI_DEVICE_ID_VIA_8233_0: | |
923 | case PCI_DEVICE_ID_VIA_8233A: | |
924 | case PCI_DEVICE_ID_VIA_8233C_0: | |
925 | via_vlink_dev_lo = 17; | |
926 | break; | |
927 | } | |
928 | } | |
929 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); | |
930 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); | |
931 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); | |
932 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); | |
933 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); | |
934 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); | |
935 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); | |
936 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); | |
09d6029f | 937 | |
1597cacb AC |
938 | /** |
939 | * quirk_via_vlink - VIA VLink IRQ number update | |
940 | * @dev: PCI device | |
941 | * | |
942 | * If the device we are dealing with is on a PIC IRQ we need to | |
943 | * ensure that the IRQ line register which usually is not relevant | |
944 | * for PCI cards, is actually written so that interrupts get sent | |
c06bb5d4 JD |
945 | * to the right place. |
946 | * We only do this on systems where a VIA south bridge was detected, | |
947 | * and only for VIA devices on the motherboard (see quirk_via_bridge | |
948 | * above). | |
1597cacb AC |
949 | */ |
950 | ||
951 | static void quirk_via_vlink(struct pci_dev *dev) | |
25be5e6c LB |
952 | { |
953 | u8 irq, new_irq; | |
954 | ||
c06bb5d4 JD |
955 | /* Check if we have VLink at all */ |
956 | if (via_vlink_dev_lo == -1) | |
09d6029f DD |
957 | return; |
958 | ||
959 | new_irq = dev->irq; | |
960 | ||
961 | /* Don't quirk interrupts outside the legacy IRQ range */ | |
962 | if (!new_irq || new_irq > 15) | |
963 | return; | |
964 | ||
1597cacb | 965 | /* Internal device ? */ |
c06bb5d4 JD |
966 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || |
967 | PCI_SLOT(dev->devfn) < via_vlink_dev_lo) | |
1597cacb AC |
968 | return; |
969 | ||
970 | /* This is an internal VLink device on a PIC interrupt. The BIOS | |
971 | ought to have set this but may not have, so we redo it */ | |
972 | ||
25be5e6c LB |
973 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
974 | if (new_irq != irq) { | |
f0fda801 | 975 | dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n", |
976 | irq, new_irq); | |
25be5e6c LB |
977 | udelay(15); /* unknown if delay really needed */ |
978 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); | |
979 | } | |
980 | } | |
1597cacb | 981 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); |
25be5e6c | 982 | |
1da177e4 LT |
983 | /* |
984 | * VIA VT82C598 has its device ID settable and many BIOSes | |
985 | * set it to the ID of VT82C597 for backward compatibility. | |
986 | * We need to switch it off to be able to recognize the real | |
987 | * type of the chip. | |
988 | */ | |
989 | static void __devinit quirk_vt82c598_id(struct pci_dev *dev) | |
990 | { | |
991 | pci_write_config_byte(dev, 0xfc, 0); | |
992 | pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); | |
993 | } | |
652c538e | 994 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); |
1da177e4 LT |
995 | |
996 | /* | |
997 | * CardBus controllers have a legacy base address that enables them | |
998 | * to respond as i82365 pcmcia controllers. We don't want them to | |
999 | * do this even if the Linux CardBus driver is not loaded, because | |
1000 | * the Linux i82365 driver does not (and should not) handle CardBus. | |
1001 | */ | |
1597cacb | 1002 | static void quirk_cardbus_legacy(struct pci_dev *dev) |
1da177e4 LT |
1003 | { |
1004 | if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class) | |
1005 | return; | |
1006 | pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); | |
1007 | } | |
1008 | DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); | |
e1a2a51e | 1009 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); |
1da177e4 LT |
1010 | |
1011 | /* | |
1012 | * Following the PCI ordering rules is optional on the AMD762. I'm not | |
1013 | * sure what the designers were smoking but let's not inhale... | |
1014 | * | |
1015 | * To be fair to AMD, it follows the spec by default, its BIOS people | |
1016 | * who turn it off! | |
1017 | */ | |
1597cacb | 1018 | static void quirk_amd_ordering(struct pci_dev *dev) |
1da177e4 LT |
1019 | { |
1020 | u32 pcic; | |
1021 | pci_read_config_dword(dev, 0x4C, &pcic); | |
1022 | if ((pcic&6)!=6) { | |
1023 | pcic |= 6; | |
f0fda801 | 1024 | dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); |
1da177e4 LT |
1025 | pci_write_config_dword(dev, 0x4C, pcic); |
1026 | pci_read_config_dword(dev, 0x84, &pcic); | |
1027 | pcic |= (1<<23); /* Required in this mode */ | |
1028 | pci_write_config_dword(dev, 0x84, pcic); | |
1029 | } | |
1030 | } | |
652c538e | 1031 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
e1a2a51e | 1032 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); |
1da177e4 LT |
1033 | |
1034 | /* | |
1035 | * DreamWorks provided workaround for Dunord I-3000 problem | |
1036 | * | |
1037 | * This card decodes and responds to addresses not apparently | |
1038 | * assigned to it. We force a larger allocation to ensure that | |
1039 | * nothing gets put too close to it. | |
1040 | */ | |
1041 | static void __devinit quirk_dunord ( struct pci_dev * dev ) | |
1042 | { | |
1043 | struct resource *r = &dev->resource [1]; | |
1044 | r->start = 0; | |
1045 | r->end = 0xffffff; | |
1046 | } | |
652c538e | 1047 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); |
1da177e4 LT |
1048 | |
1049 | /* | |
1050 | * i82380FB mobile docking controller: its PCI-to-PCI bridge | |
1051 | * is subtractive decoding (transparent), and does indicate this | |
1052 | * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80 | |
1053 | * instead of 0x01. | |
1054 | */ | |
1055 | static void __devinit quirk_transparent_bridge(struct pci_dev *dev) | |
1056 | { | |
1057 | dev->transparent = 1; | |
1058 | } | |
652c538e AM |
1059 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); |
1060 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); | |
1da177e4 LT |
1061 | |
1062 | /* | |
1063 | * Common misconfiguration of the MediaGX/Geode PCI master that will | |
1064 | * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 | |
631dd1a8 | 1065 | * datasheets found at http://www.national.com/analog for info on what |
1da177e4 LT |
1066 | * these bits do. <christer@weinigel.se> |
1067 | */ | |
1597cacb | 1068 | static void quirk_mediagx_master(struct pci_dev *dev) |
1da177e4 LT |
1069 | { |
1070 | u8 reg; | |
1071 | pci_read_config_byte(dev, 0x41, ®); | |
1072 | if (reg & 2) { | |
1073 | reg &= ~2; | |
f0fda801 | 1074 | dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); |
1da177e4 LT |
1075 | pci_write_config_byte(dev, 0x41, reg); |
1076 | } | |
1077 | } | |
652c538e AM |
1078 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); |
1079 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); | |
1da177e4 | 1080 | |
1da177e4 LT |
1081 | /* |
1082 | * Ensure C0 rev restreaming is off. This is normally done by | |
1083 | * the BIOS but in the odd case it is not the results are corruption | |
1084 | * hence the presence of a Linux check | |
1085 | */ | |
1597cacb | 1086 | static void quirk_disable_pxb(struct pci_dev *pdev) |
1da177e4 LT |
1087 | { |
1088 | u16 config; | |
1da177e4 | 1089 | |
44c10138 | 1090 | if (pdev->revision != 0x04) /* Only C0 requires this */ |
1da177e4 LT |
1091 | return; |
1092 | pci_read_config_word(pdev, 0x40, &config); | |
1093 | if (config & (1<<6)) { | |
1094 | config &= ~(1<<6); | |
1095 | pci_write_config_word(pdev, 0x40, config); | |
f0fda801 | 1096 | dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n"); |
1da177e4 LT |
1097 | } |
1098 | } | |
652c538e | 1099 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
e1a2a51e | 1100 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); |
1da177e4 | 1101 | |
05a7d22b | 1102 | static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev) |
ab17443a | 1103 | { |
5deab536 | 1104 | /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ |
05a7d22b | 1105 | u8 tmp; |
ab17443a | 1106 | |
05a7d22b CC |
1107 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); |
1108 | if (tmp == 0x01) { | |
ab17443a CH |
1109 | pci_read_config_byte(pdev, 0x40, &tmp); |
1110 | pci_write_config_byte(pdev, 0x40, tmp|1); | |
1111 | pci_write_config_byte(pdev, 0x9, 1); | |
1112 | pci_write_config_byte(pdev, 0xa, 6); | |
1113 | pci_write_config_byte(pdev, 0x40, tmp); | |
1114 | ||
c9f89475 | 1115 | pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; |
05a7d22b | 1116 | dev_info(&pdev->dev, "set SATA to AHCI mode\n"); |
ab17443a CH |
1117 | } |
1118 | } | |
05a7d22b | 1119 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1120 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); |
05a7d22b | 1121 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
e1a2a51e | 1122 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); |
5deab536 SH |
1123 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); |
1124 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); | |
ab17443a | 1125 | |
1da177e4 LT |
1126 | /* |
1127 | * Serverworks CSB5 IDE does not fully support native mode | |
1128 | */ | |
1129 | static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) | |
1130 | { | |
1131 | u8 prog; | |
1132 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1133 | if (prog & 5) { | |
1134 | prog &= ~5; | |
1135 | pdev->class &= ~5; | |
1136 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
368c73d4 | 1137 | /* PCI layer will sort out resources */ |
1da177e4 LT |
1138 | } |
1139 | } | |
652c538e | 1140 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); |
1da177e4 LT |
1141 | |
1142 | /* | |
1143 | * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same | |
1144 | */ | |
1145 | static void __init quirk_ide_samemode(struct pci_dev *pdev) | |
1146 | { | |
1147 | u8 prog; | |
1148 | ||
1149 | pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); | |
1150 | ||
1151 | if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { | |
f0fda801 | 1152 | dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n"); |
1da177e4 LT |
1153 | prog &= ~5; |
1154 | pdev->class &= ~5; | |
1155 | pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); | |
1da177e4 LT |
1156 | } |
1157 | } | |
368c73d4 | 1158 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); |
1da177e4 | 1159 | |
979b1791 AC |
1160 | /* |
1161 | * Some ATA devices break if put into D3 | |
1162 | */ | |
1163 | ||
1164 | static void __devinit quirk_no_ata_d3(struct pci_dev *pdev) | |
1165 | { | |
1166 | /* Quirk the legacy ATA devices only. The AHCI ones are ok */ | |
1167 | if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
1168 | pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; | |
1169 | } | |
1170 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3); | |
1171 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3); | |
7a661c6f AC |
1172 | /* ALi loses some register settings that we cannot then restore */ |
1173 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3); | |
1174 | /* VIA comes back fine but we need to keep it alive or ACPI GTM failures | |
1175 | occur when mode detecting */ | |
1176 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3); | |
979b1791 | 1177 | |
1da177e4 LT |
1178 | /* This was originally an Alpha specific thing, but it really fits here. |
1179 | * The i82375 PCI/EISA bridge appears as non-classified. Fix that. | |
1180 | */ | |
1181 | static void __init quirk_eisa_bridge(struct pci_dev *dev) | |
1182 | { | |
1183 | dev->class = PCI_CLASS_BRIDGE_EISA << 8; | |
1184 | } | |
652c538e | 1185 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); |
1da177e4 | 1186 | |
7daa0c4f | 1187 | |
1da177e4 LT |
1188 | /* |
1189 | * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge | |
1190 | * is not activated. The myth is that Asus said that they do not want the | |
1191 | * users to be irritated by just another PCI Device in the Win98 device | |
1192 | * manager. (see the file prog/hotplug/README.p4b in the lm_sensors | |
1193 | * package 2.7.0 for details) | |
1194 | * | |
1195 | * The SMBus PCI Device can be activated by setting a bit in the ICH LPC | |
1196 | * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it | |
d7698edc | 1197 | * becomes necessary to do this tweak in two steps -- the chosen trigger |
1198 | * is either the Host bridge (preferred) or on-board VGA controller. | |
9208ee82 JD |
1199 | * |
1200 | * Note that we used to unhide the SMBus that way on Toshiba laptops | |
1201 | * (Satellite A40 and Tecra M2) but then found that the thermal management | |
1202 | * was done by SMM code, which could cause unsynchronized concurrent | |
1203 | * accesses to the SMBus registers, with potentially bad effects. Thus you | |
1204 | * should be very careful when adding new entries: if SMM is accessing the | |
1205 | * Intel SMBus, this is a very good reason to leave it hidden. | |
a99acc83 JD |
1206 | * |
1207 | * Likewise, many recent laptops use ACPI for thermal management. If the | |
1208 | * ACPI DSDT code accesses the SMBus, then Linux should not access it | |
1209 | * natively, and keeping the SMBus hidden is the right thing to do. If you | |
1210 | * are about to add an entry in the table below, please first disassemble | |
1211 | * the DSDT and double-check that there is no code accessing the SMBus. | |
1da177e4 | 1212 | */ |
9d24a81e | 1213 | static int asus_hides_smbus; |
1da177e4 LT |
1214 | |
1215 | static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) | |
1216 | { | |
1217 | if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1218 | if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) | |
1219 | switch(dev->subsystem_device) { | |
a00db371 | 1220 | case 0x8025: /* P4B-LX */ |
1da177e4 LT |
1221 | case 0x8070: /* P4B */ |
1222 | case 0x8088: /* P4B533 */ | |
1223 | case 0x1626: /* L3C notebook */ | |
1224 | asus_hides_smbus = 1; | |
1225 | } | |
2f2d39d2 | 1226 | else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) |
1da177e4 LT |
1227 | switch(dev->subsystem_device) { |
1228 | case 0x80b1: /* P4GE-V */ | |
1229 | case 0x80b2: /* P4PE */ | |
1230 | case 0x8093: /* P4B533-V */ | |
1231 | asus_hides_smbus = 1; | |
1232 | } | |
2f2d39d2 | 1233 | else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) |
1da177e4 LT |
1234 | switch(dev->subsystem_device) { |
1235 | case 0x8030: /* P4T533 */ | |
1236 | asus_hides_smbus = 1; | |
1237 | } | |
2f2d39d2 | 1238 | else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) |
1da177e4 LT |
1239 | switch (dev->subsystem_device) { |
1240 | case 0x8070: /* P4G8X Deluxe */ | |
1241 | asus_hides_smbus = 1; | |
1242 | } | |
2f2d39d2 | 1243 | else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) |
321311af JD |
1244 | switch (dev->subsystem_device) { |
1245 | case 0x80c9: /* PU-DLS */ | |
1246 | asus_hides_smbus = 1; | |
1247 | } | |
2f2d39d2 | 1248 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) |
1da177e4 LT |
1249 | switch (dev->subsystem_device) { |
1250 | case 0x1751: /* M2N notebook */ | |
1251 | case 0x1821: /* M5N notebook */ | |
4096ed0f | 1252 | case 0x1897: /* A6L notebook */ |
1da177e4 LT |
1253 | asus_hides_smbus = 1; |
1254 | } | |
2f2d39d2 | 1255 | else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) |
1da177e4 LT |
1256 | switch (dev->subsystem_device) { |
1257 | case 0x184b: /* W1N notebook */ | |
1258 | case 0x186a: /* M6Ne notebook */ | |
1259 | asus_hides_smbus = 1; | |
1260 | } | |
2f2d39d2 | 1261 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
2e45785c JD |
1262 | switch (dev->subsystem_device) { |
1263 | case 0x80f2: /* P4P800-X */ | |
1264 | asus_hides_smbus = 1; | |
1265 | } | |
2f2d39d2 | 1266 | else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) |
acc06632 M |
1267 | switch (dev->subsystem_device) { |
1268 | case 0x1882: /* M6V notebook */ | |
2d1e1c75 | 1269 | case 0x1977: /* A6VA notebook */ |
acc06632 M |
1270 | asus_hides_smbus = 1; |
1271 | } | |
1da177e4 LT |
1272 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { |
1273 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1274 | switch(dev->subsystem_device) { | |
1275 | case 0x088C: /* HP Compaq nc8000 */ | |
1276 | case 0x0890: /* HP Compaq nc6000 */ | |
1277 | asus_hides_smbus = 1; | |
1278 | } | |
2f2d39d2 | 1279 | else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) |
1da177e4 LT |
1280 | switch (dev->subsystem_device) { |
1281 | case 0x12bc: /* HP D330L */ | |
e3b1bd57 | 1282 | case 0x12bd: /* HP D530 */ |
74c57428 | 1283 | case 0x006a: /* HP Compaq nx9500 */ |
1da177e4 LT |
1284 | asus_hides_smbus = 1; |
1285 | } | |
677cc644 JD |
1286 | else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) |
1287 | switch (dev->subsystem_device) { | |
1288 | case 0x12bf: /* HP xw4100 */ | |
1289 | asus_hides_smbus = 1; | |
1290 | } | |
1da177e4 LT |
1291 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { |
1292 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1293 | switch(dev->subsystem_device) { | |
1294 | case 0xC00C: /* Samsung P35 notebook */ | |
1295 | asus_hides_smbus = 1; | |
1296 | } | |
c87f883e RIZ |
1297 | } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { |
1298 | if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) | |
1299 | switch(dev->subsystem_device) { | |
1300 | case 0x0058: /* Compaq Evo N620c */ | |
1301 | asus_hides_smbus = 1; | |
1302 | } | |
d7698edc | 1303 | else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) |
1304 | switch(dev->subsystem_device) { | |
1305 | case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ | |
1306 | /* Motherboard doesn't have Host bridge | |
1307 | * subvendor/subdevice IDs, therefore checking | |
1308 | * its on-board VGA controller */ | |
1309 | asus_hides_smbus = 1; | |
1310 | } | |
8293b0f6 | 1311 | else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) |
10260d9a JD |
1312 | switch(dev->subsystem_device) { |
1313 | case 0x00b8: /* Compaq Evo D510 CMT */ | |
1314 | case 0x00b9: /* Compaq Evo D510 SFF */ | |
6b5096e4 | 1315 | case 0x00ba: /* Compaq Evo D510 USDT */ |
8293b0f6 DS |
1316 | /* Motherboard doesn't have Host bridge |
1317 | * subvendor/subdevice IDs and on-board VGA | |
1318 | * controller is disabled if an AGP card is | |
1319 | * inserted, therefore checking USB UHCI | |
1320 | * Controller #1 */ | |
10260d9a JD |
1321 | asus_hides_smbus = 1; |
1322 | } | |
27e46859 KH |
1323 | else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) |
1324 | switch (dev->subsystem_device) { | |
1325 | case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ | |
1326 | /* Motherboard doesn't have host bridge | |
1327 | * subvendor/subdevice IDs, therefore checking | |
1328 | * its on-board VGA controller */ | |
1329 | asus_hides_smbus = 1; | |
1330 | } | |
1da177e4 LT |
1331 | } |
1332 | } | |
652c538e AM |
1333 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); |
1334 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); | |
1335 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); | |
1336 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); | |
677cc644 | 1337 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); |
652c538e AM |
1338 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); |
1339 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); | |
1340 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); | |
1341 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); | |
1342 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); | |
1343 | ||
1344 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); | |
8293b0f6 | 1345 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); |
27e46859 | 1346 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); |
d7698edc | 1347 | |
1597cacb | 1348 | static void asus_hides_smbus_lpc(struct pci_dev *dev) |
1da177e4 LT |
1349 | { |
1350 | u16 val; | |
1351 | ||
1352 | if (likely(!asus_hides_smbus)) | |
1353 | return; | |
1354 | ||
1355 | pci_read_config_word(dev, 0xF2, &val); | |
1356 | if (val & 0x8) { | |
1357 | pci_write_config_word(dev, 0xF2, val & (~0x8)); | |
1358 | pci_read_config_word(dev, 0xF2, &val); | |
1359 | if (val & 0x8) | |
f0fda801 | 1360 | dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); |
1da177e4 | 1361 | else |
f0fda801 | 1362 | dev_info(&dev->dev, "Enabled i801 SMBus device\n"); |
1da177e4 LT |
1363 | } |
1364 | } | |
652c538e AM |
1365 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1366 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1367 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1368 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1369 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1370 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1371 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
e1a2a51e RW |
1372 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); |
1373 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); | |
1374 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); | |
1375 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); | |
1376 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); | |
1377 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); | |
1378 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); | |
1597cacb | 1379 | |
e1a2a51e RW |
1380 | /* It appears we just have one such device. If not, we have a warning */ |
1381 | static void __iomem *asus_rcba_base; | |
1382 | static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) | |
acc06632 | 1383 | { |
e1a2a51e | 1384 | u32 rcba; |
acc06632 M |
1385 | |
1386 | if (likely(!asus_hides_smbus)) | |
1387 | return; | |
e1a2a51e RW |
1388 | WARN_ON(asus_rcba_base); |
1389 | ||
acc06632 | 1390 | pci_read_config_dword(dev, 0xF0, &rcba); |
e1a2a51e RW |
1391 | /* use bits 31:14, 16 kB aligned */ |
1392 | asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000); | |
1393 | if (asus_rcba_base == NULL) | |
1394 | return; | |
1395 | } | |
1396 | ||
1397 | static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) | |
1398 | { | |
1399 | u32 val; | |
1400 | ||
1401 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1402 | return; | |
1403 | /* read the Function Disable register, dword mode only */ | |
1404 | val = readl(asus_rcba_base + 0x3418); | |
1405 | writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */ | |
1406 | } | |
1407 | ||
1408 | static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) | |
1409 | { | |
1410 | if (likely(!asus_hides_smbus || !asus_rcba_base)) | |
1411 | return; | |
1412 | iounmap(asus_rcba_base); | |
1413 | asus_rcba_base = NULL; | |
f0fda801 | 1414 | dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n"); |
acc06632 | 1415 | } |
e1a2a51e RW |
1416 | |
1417 | static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) | |
1418 | { | |
1419 | asus_hides_smbus_lpc_ich6_suspend(dev); | |
1420 | asus_hides_smbus_lpc_ich6_resume_early(dev); | |
1421 | asus_hides_smbus_lpc_ich6_resume(dev); | |
1422 | } | |
652c538e | 1423 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); |
e1a2a51e RW |
1424 | DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); |
1425 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); | |
1426 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); | |
ce007ea5 | 1427 | |
1da177e4 LT |
1428 | /* |
1429 | * SiS 96x south bridge: BIOS typically hides SMBus device... | |
1430 | */ | |
1597cacb | 1431 | static void quirk_sis_96x_smbus(struct pci_dev *dev) |
1da177e4 LT |
1432 | { |
1433 | u8 val = 0; | |
1da177e4 | 1434 | pci_read_config_byte(dev, 0x77, &val); |
2f5c33b3 | 1435 | if (val & 0x10) { |
f0fda801 | 1436 | dev_info(&dev->dev, "Enabling SiS 96x SMBus\n"); |
2f5c33b3 MH |
1437 | pci_write_config_byte(dev, 0x77, val & ~0x10); |
1438 | } | |
1da177e4 | 1439 | } |
652c538e AM |
1440 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1443 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
e1a2a51e RW |
1444 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); |
1445 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); | |
1446 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); | |
1447 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); | |
1da177e4 | 1448 | |
1da177e4 LT |
1449 | /* |
1450 | * ... This is further complicated by the fact that some SiS96x south | |
1451 | * bridges pretend to be 85C503/5513 instead. In that case see if we | |
1452 | * spotted a compatible north bridge to make sure. | |
1453 | * (pci_find_device doesn't work yet) | |
1454 | * | |
1455 | * We can also enable the sis96x bit in the discovery register.. | |
1456 | */ | |
1da177e4 LT |
1457 | #define SIS_DETECT_REGISTER 0x40 |
1458 | ||
1597cacb | 1459 | static void quirk_sis_503(struct pci_dev *dev) |
1da177e4 LT |
1460 | { |
1461 | u8 reg; | |
1462 | u16 devid; | |
1463 | ||
1464 | pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); | |
1465 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); | |
1466 | pci_read_config_word(dev, PCI_DEVICE_ID, &devid); | |
1467 | if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { | |
1468 | pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); | |
1469 | return; | |
1470 | } | |
1471 | ||
1da177e4 | 1472 | /* |
2f5c33b3 MH |
1473 | * Ok, it now shows up as a 96x.. run the 96x quirk by |
1474 | * hand in case it has already been processed. | |
1475 | * (depends on link order, which is apparently not guaranteed) | |
1da177e4 LT |
1476 | */ |
1477 | dev->device = devid; | |
2f5c33b3 | 1478 | quirk_sis_96x_smbus(dev); |
1da177e4 | 1479 | } |
652c538e | 1480 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
e1a2a51e | 1481 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); |
1da177e4 | 1482 | |
1da177e4 | 1483 | |
e5548e96 BJD |
1484 | /* |
1485 | * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller | |
1486 | * and MC97 modem controller are disabled when a second PCI soundcard is | |
1487 | * present. This patch, tweaking the VT8237 ISA bridge, enables them. | |
1488 | * -- bjd | |
1489 | */ | |
1597cacb | 1490 | static void asus_hides_ac97_lpc(struct pci_dev *dev) |
e5548e96 BJD |
1491 | { |
1492 | u8 val; | |
1493 | int asus_hides_ac97 = 0; | |
1494 | ||
1495 | if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { | |
1496 | if (dev->device == PCI_DEVICE_ID_VIA_8237) | |
1497 | asus_hides_ac97 = 1; | |
1498 | } | |
1499 | ||
1500 | if (!asus_hides_ac97) | |
1501 | return; | |
1502 | ||
1503 | pci_read_config_byte(dev, 0x50, &val); | |
1504 | if (val & 0xc0) { | |
1505 | pci_write_config_byte(dev, 0x50, val & (~0xc0)); | |
1506 | pci_read_config_byte(dev, 0x50, &val); | |
1507 | if (val & 0xc0) | |
f0fda801 | 1508 | dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); |
e5548e96 | 1509 | else |
f0fda801 | 1510 | dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n"); |
e5548e96 BJD |
1511 | } |
1512 | } | |
652c538e | 1513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
e1a2a51e | 1514 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); |
1597cacb | 1515 | |
77967052 | 1516 | #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) |
15e0c694 AC |
1517 | |
1518 | /* | |
1519 | * If we are using libata we can drive this chip properly but must | |
1520 | * do this early on to make the additional device appear during | |
1521 | * the PCI scanning. | |
1522 | */ | |
5ee2ae7f | 1523 | static void quirk_jmicron_ata(struct pci_dev *pdev) |
15e0c694 | 1524 | { |
e34bb370 | 1525 | u32 conf1, conf5, class; |
15e0c694 AC |
1526 | u8 hdr; |
1527 | ||
1528 | /* Only poke fn 0 */ | |
1529 | if (PCI_FUNC(pdev->devfn)) | |
1530 | return; | |
1531 | ||
5ee2ae7f TH |
1532 | pci_read_config_dword(pdev, 0x40, &conf1); |
1533 | pci_read_config_dword(pdev, 0x80, &conf5); | |
15e0c694 | 1534 | |
5ee2ae7f TH |
1535 | conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ |
1536 | conf5 &= ~(1 << 24); /* Clear bit 24 */ | |
1537 | ||
1538 | switch (pdev->device) { | |
4daedcfe TH |
1539 | case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ |
1540 | case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ | |
5b6ae5ba | 1541 | case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ |
5ee2ae7f TH |
1542 | /* The controller should be in single function ahci mode */ |
1543 | conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ | |
1544 | break; | |
1545 | ||
1546 | case PCI_DEVICE_ID_JMICRON_JMB365: | |
1547 | case PCI_DEVICE_ID_JMICRON_JMB366: | |
1548 | /* Redirect IDE second PATA port to the right spot */ | |
1549 | conf5 |= (1 << 24); | |
1550 | /* Fall through */ | |
1551 | case PCI_DEVICE_ID_JMICRON_JMB361: | |
1552 | case PCI_DEVICE_ID_JMICRON_JMB363: | |
5b6ae5ba | 1553 | case PCI_DEVICE_ID_JMICRON_JMB369: |
5ee2ae7f TH |
1554 | /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ |
1555 | /* Set the class codes correctly and then direct IDE 0 */ | |
3a9e3a51 | 1556 | conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ |
5ee2ae7f TH |
1557 | break; |
1558 | ||
1559 | case PCI_DEVICE_ID_JMICRON_JMB368: | |
1560 | /* The controller should be in single function IDE mode */ | |
1561 | conf1 |= 0x00C00000; /* Set 22, 23 */ | |
1562 | break; | |
15e0c694 | 1563 | } |
5ee2ae7f TH |
1564 | |
1565 | pci_write_config_dword(pdev, 0x40, conf1); | |
1566 | pci_write_config_dword(pdev, 0x80, conf5); | |
1567 | ||
1568 | /* Update pdev accordingly */ | |
1569 | pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); | |
1570 | pdev->hdr_type = hdr & 0x7f; | |
1571 | pdev->multifunction = !!(hdr & 0x80); | |
e34bb370 TH |
1572 | |
1573 | pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); | |
1574 | pdev->class = class >> 8; | |
15e0c694 | 1575 | } |
5ee2ae7f TH |
1576 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1577 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1578 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
5ee2ae7f | 1579 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1580 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
5ee2ae7f TH |
1581 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1582 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1583 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1584 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
e1a2a51e RW |
1585 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); |
1586 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); | |
4daedcfe | 1587 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); |
e1a2a51e | 1588 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); |
5b6ae5ba | 1589 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); |
e1a2a51e RW |
1590 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); |
1591 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); | |
1592 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); | |
5b6ae5ba | 1593 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); |
15e0c694 AC |
1594 | |
1595 | #endif | |
1596 | ||
1da177e4 LT |
1597 | #ifdef CONFIG_X86_IO_APIC |
1598 | static void __init quirk_alder_ioapic(struct pci_dev *pdev) | |
1599 | { | |
1600 | int i; | |
1601 | ||
1602 | if ((pdev->class >> 8) != 0xff00) | |
1603 | return; | |
1604 | ||
1605 | /* the first BAR is the location of the IO APIC...we must | |
1606 | * not touch this (and it's already covered by the fixmap), so | |
1607 | * forcibly insert it into the resource tree */ | |
1608 | if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) | |
1609 | insert_resource(&iomem_resource, &pdev->resource[0]); | |
1610 | ||
1611 | /* The next five BARs all seem to be rubbish, so just clean | |
1612 | * them out */ | |
1613 | for (i=1; i < 6; i++) { | |
1614 | memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); | |
1615 | } | |
1616 | ||
1617 | } | |
652c538e | 1618 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); |
1da177e4 LT |
1619 | #endif |
1620 | ||
1da177e4 LT |
1621 | static void __devinit quirk_pcie_mch(struct pci_dev *pdev) |
1622 | { | |
0ba379ec EB |
1623 | pci_msi_off(pdev); |
1624 | pdev->no_msi = 1; | |
1da177e4 | 1625 | } |
652c538e AM |
1626 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); |
1627 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); | |
1628 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); | |
1da177e4 | 1629 | |
4602b88d KA |
1630 | |
1631 | /* | |
1632 | * It's possible for the MSI to get corrupted if shpc and acpi | |
1633 | * are used together on certain PXH-based systems. | |
1634 | */ | |
1635 | static void __devinit quirk_pcie_pxh(struct pci_dev *dev) | |
1636 | { | |
f5f2b131 | 1637 | pci_msi_off(dev); |
4602b88d | 1638 | dev->no_msi = 1; |
f0fda801 | 1639 | dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n"); |
4602b88d KA |
1640 | } |
1641 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); | |
1642 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); | |
1643 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); | |
1644 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); | |
1645 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); | |
1646 | ||
ffadcc2f KCA |
1647 | /* |
1648 | * Some Intel PCI Express chipsets have trouble with downstream | |
1649 | * device power management. | |
1650 | */ | |
1651 | static void quirk_intel_pcie_pm(struct pci_dev * dev) | |
1652 | { | |
1653 | pci_pm_d3_delay = 120; | |
1654 | dev->no_d1d2 = 1; | |
1655 | } | |
1656 | ||
1657 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); | |
1658 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); | |
1659 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); | |
1660 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); | |
1661 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); | |
1662 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); | |
1663 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); | |
1664 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); | |
1665 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); | |
1666 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); | |
1667 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); | |
1668 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); | |
1669 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); | |
1670 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); | |
1671 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); | |
1672 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); | |
1673 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); | |
1674 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); | |
1675 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); | |
1676 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); | |
1677 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); | |
4602b88d | 1678 | |
426b3b8d | 1679 | #ifdef CONFIG_X86_IO_APIC |
e1d3a908 SA |
1680 | /* |
1681 | * Boot interrupts on some chipsets cannot be turned off. For these chipsets, | |
1682 | * remap the original interrupt in the linux kernel to the boot interrupt, so | |
1683 | * that a PCI device's interrupt handler is installed on the boot interrupt | |
1684 | * line instead. | |
1685 | */ | |
1686 | static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) | |
1687 | { | |
41b9eb26 | 1688 | if (noioapicquirk || noioapicreroute) |
e1d3a908 SA |
1689 | return; |
1690 | ||
1691 | dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; | |
fdcdaf6c BH |
1692 | dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n", |
1693 | dev->vendor, dev->device); | |
e1d3a908 | 1694 | } |
88d1dce3 OD |
1695 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); |
1696 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1697 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1698 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1699 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1700 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1701 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1702 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
1703 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); | |
1704 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); | |
1705 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); | |
1706 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); | |
1707 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); | |
1708 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); | |
1709 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); | |
1710 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); | |
e1d3a908 | 1711 | |
426b3b8d SA |
1712 | /* |
1713 | * On some chipsets we can disable the generation of legacy INTx boot | |
1714 | * interrupts. | |
1715 | */ | |
1716 | ||
1717 | /* | |
1718 | * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no | |
1719 | * 300641-004US, section 5.7.3. | |
1720 | */ | |
1721 | #define INTEL_6300_IOAPIC_ABAR 0x40 | |
1722 | #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) | |
1723 | ||
1724 | static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) | |
1725 | { | |
1726 | u16 pci_config_word; | |
1727 | ||
1728 | if (noioapicquirk) | |
1729 | return; | |
1730 | ||
1731 | pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word); | |
1732 | pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; | |
1733 | pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word); | |
1734 | ||
fdcdaf6c BH |
1735 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1736 | dev->vendor, dev->device); | |
426b3b8d | 1737 | } |
88d1dce3 OD |
1738 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); |
1739 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt); | |
77251188 OD |
1740 | |
1741 | /* | |
1742 | * disable boot interrupts on HT-1000 | |
1743 | */ | |
1744 | #define BC_HT1000_FEATURE_REG 0x64 | |
1745 | #define BC_HT1000_PIC_REGS_ENABLE (1<<0) | |
1746 | #define BC_HT1000_MAP_IDX 0xC00 | |
1747 | #define BC_HT1000_MAP_DATA 0xC01 | |
1748 | ||
1749 | static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) | |
1750 | { | |
1751 | u32 pci_config_dword; | |
1752 | u8 irq; | |
1753 | ||
1754 | if (noioapicquirk) | |
1755 | return; | |
1756 | ||
1757 | pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); | |
1758 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | | |
1759 | BC_HT1000_PIC_REGS_ENABLE); | |
1760 | ||
1761 | for (irq = 0x10; irq < 0x10 + 32; irq++) { | |
1762 | outb(irq, BC_HT1000_MAP_IDX); | |
1763 | outb(0x00, BC_HT1000_MAP_DATA); | |
1764 | } | |
1765 | ||
1766 | pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); | |
1767 | ||
fdcdaf6c BH |
1768 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1769 | dev->vendor, dev->device); | |
77251188 | 1770 | } |
88d1dce3 OD |
1771 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); |
1772 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); | |
542622da OD |
1773 | |
1774 | /* | |
1775 | * disable boot interrupts on AMD and ATI chipsets | |
1776 | */ | |
1777 | /* | |
1778 | * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 | |
1779 | * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode | |
1780 | * (due to an erratum). | |
1781 | */ | |
1782 | #define AMD_813X_MISC 0x40 | |
1783 | #define AMD_813X_NOIOAMODE (1<<0) | |
4fd8bdc5 | 1784 | #define AMD_813X_REV_B1 0x12 |
bbe19443 | 1785 | #define AMD_813X_REV_B2 0x13 |
542622da OD |
1786 | |
1787 | static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) | |
1788 | { | |
1789 | u32 pci_config_dword; | |
1790 | ||
1791 | if (noioapicquirk) | |
1792 | return; | |
4fd8bdc5 SA |
1793 | if ((dev->revision == AMD_813X_REV_B1) || |
1794 | (dev->revision == AMD_813X_REV_B2)) | |
bbe19443 | 1795 | return; |
542622da OD |
1796 | |
1797 | pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); | |
1798 | pci_config_dword &= ~AMD_813X_NOIOAMODE; | |
1799 | pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); | |
1800 | ||
fdcdaf6c BH |
1801 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1802 | dev->vendor, dev->device); | |
542622da | 1803 | } |
4fd8bdc5 SA |
1804 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); |
1805 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
1806 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
1807 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); | |
542622da OD |
1808 | |
1809 | #define AMD_8111_PCI_IRQ_ROUTING 0x56 | |
1810 | ||
1811 | static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) | |
1812 | { | |
1813 | u16 pci_config_word; | |
1814 | ||
1815 | if (noioapicquirk) | |
1816 | return; | |
1817 | ||
1818 | pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); | |
1819 | if (!pci_config_word) { | |
fdcdaf6c BH |
1820 | dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] " |
1821 | "already disabled\n", dev->vendor, dev->device); | |
542622da OD |
1822 | return; |
1823 | } | |
1824 | pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); | |
fdcdaf6c BH |
1825 | dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n", |
1826 | dev->vendor, dev->device); | |
542622da | 1827 | } |
88d1dce3 OD |
1828 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); |
1829 | DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); | |
426b3b8d SA |
1830 | #endif /* CONFIG_X86_IO_APIC */ |
1831 | ||
33dced2e SS |
1832 | /* |
1833 | * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size | |
1834 | * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. | |
1835 | * Re-allocate the region if needed... | |
1836 | */ | |
1837 | static void __init quirk_tc86c001_ide(struct pci_dev *dev) | |
1838 | { | |
1839 | struct resource *r = &dev->resource[0]; | |
1840 | ||
1841 | if (r->start & 0x8) { | |
1842 | r->start = 0; | |
1843 | r->end = 0xf; | |
1844 | } | |
1845 | } | |
1846 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, | |
1847 | PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, | |
1848 | quirk_tc86c001_ide); | |
1849 | ||
1da177e4 LT |
1850 | static void __devinit quirk_netmos(struct pci_dev *dev) |
1851 | { | |
1852 | unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; | |
1853 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
1854 | ||
1855 | /* | |
1856 | * These Netmos parts are multiport serial devices with optional | |
1857 | * parallel ports. Even when parallel ports are present, they | |
1858 | * are identified as class SERIAL, which means the serial driver | |
1859 | * will claim them. To prevent this, mark them as class OTHER. | |
1860 | * These combo devices should be claimed by parport_serial. | |
1861 | * | |
1862 | * The subdevice ID is of the form 0x00PS, where <P> is the number | |
1863 | * of parallel ports and <S> is the number of serial ports. | |
1864 | */ | |
1865 | switch (dev->device) { | |
4c9c1686 JS |
1866 | case PCI_DEVICE_ID_NETMOS_9835: |
1867 | /* Well, this rule doesn't hold for the following 9835 device */ | |
1868 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && | |
1869 | dev->subsystem_device == 0x0299) | |
1870 | return; | |
1da177e4 LT |
1871 | case PCI_DEVICE_ID_NETMOS_9735: |
1872 | case PCI_DEVICE_ID_NETMOS_9745: | |
1da177e4 LT |
1873 | case PCI_DEVICE_ID_NETMOS_9845: |
1874 | case PCI_DEVICE_ID_NETMOS_9855: | |
1875 | if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && | |
1876 | num_parallel) { | |
f0fda801 | 1877 | dev_info(&dev->dev, "Netmos %04x (%u parallel, " |
1da177e4 LT |
1878 | "%u serial); changing class SERIAL to OTHER " |
1879 | "(use parport_serial)\n", | |
1880 | dev->device, num_parallel, num_serial); | |
1881 | dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | | |
1882 | (dev->class & 0xff); | |
1883 | } | |
1884 | } | |
1885 | } | |
1886 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos); | |
1887 | ||
16a74744 BH |
1888 | static void __devinit quirk_e100_interrupt(struct pci_dev *dev) |
1889 | { | |
e64aeccb | 1890 | u16 command, pmcsr; |
16a74744 BH |
1891 | u8 __iomem *csr; |
1892 | u8 cmd_hi; | |
e64aeccb | 1893 | int pm; |
16a74744 BH |
1894 | |
1895 | switch (dev->device) { | |
1896 | /* PCI IDs taken from drivers/net/e100.c */ | |
1897 | case 0x1029: | |
1898 | case 0x1030 ... 0x1034: | |
1899 | case 0x1038 ... 0x103E: | |
1900 | case 0x1050 ... 0x1057: | |
1901 | case 0x1059: | |
1902 | case 0x1064 ... 0x106B: | |
1903 | case 0x1091 ... 0x1095: | |
1904 | case 0x1209: | |
1905 | case 0x1229: | |
1906 | case 0x2449: | |
1907 | case 0x2459: | |
1908 | case 0x245D: | |
1909 | case 0x27DC: | |
1910 | break; | |
1911 | default: | |
1912 | return; | |
1913 | } | |
1914 | ||
1915 | /* | |
1916 | * Some firmware hands off the e100 with interrupts enabled, | |
1917 | * which can cause a flood of interrupts if packets are | |
1918 | * received before the driver attaches to the device. So | |
1919 | * disable all e100 interrupts here. The driver will | |
1920 | * re-enable them when it's ready. | |
1921 | */ | |
1922 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
16a74744 | 1923 | |
1bef7dc0 | 1924 | if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) |
16a74744 BH |
1925 | return; |
1926 | ||
e64aeccb IK |
1927 | /* |
1928 | * Check that the device is in the D0 power state. If it's not, | |
1929 | * there is no point to look any further. | |
1930 | */ | |
1931 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); | |
1932 | if (pm) { | |
1933 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); | |
1934 | if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) | |
1935 | return; | |
1936 | } | |
1937 | ||
1bef7dc0 BH |
1938 | /* Convert from PCI bus to resource space. */ |
1939 | csr = ioremap(pci_resource_start(dev, 0), 8); | |
16a74744 | 1940 | if (!csr) { |
f0fda801 | 1941 | dev_warn(&dev->dev, "Can't map e100 registers\n"); |
16a74744 BH |
1942 | return; |
1943 | } | |
1944 | ||
1945 | cmd_hi = readb(csr + 3); | |
1946 | if (cmd_hi == 0) { | |
f0fda801 | 1947 | dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; " |
1948 | "disabling\n"); | |
16a74744 BH |
1949 | writeb(1, csr + 3); |
1950 | } | |
1951 | ||
1952 | iounmap(csr); | |
1953 | } | |
4e68fc97 | 1954 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
a5312e28 | 1955 | |
649426ef AD |
1956 | /* |
1957 | * The 82575 and 82598 may experience data corruption issues when transitioning | |
1958 | * out of L0S. To prevent this we need to disable L0S on the pci-e link | |
1959 | */ | |
1960 | static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) | |
1961 | { | |
1962 | dev_info(&dev->dev, "Disabling L0s\n"); | |
1963 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); | |
1964 | } | |
1965 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | |
1966 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | |
1967 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | |
1968 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | |
1969 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | |
1970 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | |
1971 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | |
1972 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | |
1973 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | |
1974 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | |
1975 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | |
1976 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | |
1977 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | |
1978 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | |
1979 | ||
a5312e28 IK |
1980 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
1981 | { | |
1982 | /* rev 1 ncr53c810 chips don't set the class at all which means | |
1983 | * they don't get their resources remapped. Fix that here. | |
1984 | */ | |
1985 | ||
1986 | if (dev->class == PCI_CLASS_NOT_DEFINED) { | |
f0fda801 | 1987 | dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n"); |
a5312e28 IK |
1988 | dev->class = PCI_CLASS_STORAGE_SCSI; |
1989 | } | |
1990 | } | |
1991 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); | |
1992 | ||
9d265124 DY |
1993 | /* Enable 1k I/O space granularity on the Intel P64H2 */ |
1994 | static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev) | |
1995 | { | |
1996 | u16 en1k; | |
1997 | u8 io_base_lo, io_limit_lo; | |
1998 | unsigned long base, limit; | |
1999 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
2000 | ||
2001 | pci_read_config_word(dev, 0x40, &en1k); | |
2002 | ||
2003 | if (en1k & 0x200) { | |
f0fda801 | 2004 | dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n"); |
9d265124 DY |
2005 | |
2006 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
2007 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
2008 | base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
2009 | limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8; | |
2010 | ||
2011 | if (base <= limit) { | |
2012 | res->start = base; | |
2013 | res->end = limit + 0x3ff; | |
2014 | } | |
2015 | } | |
2016 | } | |
2017 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); | |
2018 | ||
15a260d5 DY |
2019 | /* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2 |
2020 | * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge() | |
2021 | * in drivers/pci/setup-bus.c | |
2022 | */ | |
2023 | static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev) | |
2024 | { | |
2025 | u16 en1k, iobl_adr, iobl_adr_1k; | |
2026 | struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES; | |
2027 | ||
2028 | pci_read_config_word(dev, 0x40, &en1k); | |
2029 | ||
2030 | if (en1k & 0x200) { | |
2031 | pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr); | |
2032 | ||
2033 | iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); | |
2034 | ||
2035 | if (iobl_adr != iobl_adr_1k) { | |
f0fda801 | 2036 | dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n", |
15a260d5 DY |
2037 | iobl_adr,iobl_adr_1k); |
2038 | pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); | |
2039 | } | |
2040 | } | |
2041 | } | |
2042 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl); | |
2043 | ||
cf34a8e0 BG |
2044 | /* Under some circumstances, AER is not linked with extended capabilities. |
2045 | * Force it to be linked by setting the corresponding control bit in the | |
2046 | * config space. | |
2047 | */ | |
1597cacb | 2048 | static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) |
cf34a8e0 BG |
2049 | { |
2050 | uint8_t b; | |
2051 | if (pci_read_config_byte(dev, 0xf41, &b) == 0) { | |
2052 | if (!(b & 0x20)) { | |
2053 | pci_write_config_byte(dev, 0xf41, b | 0x20); | |
f0fda801 | 2054 | dev_info(&dev->dev, |
2055 | "Linking AER extended capability\n"); | |
cf34a8e0 BG |
2056 | } |
2057 | } | |
2058 | } | |
2059 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2060 | quirk_nvidia_ck804_pcie_aer_ext_cap); | |
e1a2a51e | 2061 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, |
1597cacb | 2062 | quirk_nvidia_ck804_pcie_aer_ext_cap); |
cf34a8e0 | 2063 | |
53a9bf42 TY |
2064 | static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) |
2065 | { | |
2066 | /* | |
2067 | * Disable PCI Bus Parking and PCI Master read caching on CX700 | |
2068 | * which causes unspecified timing errors with a VT6212L on the PCI | |
ca846392 TY |
2069 | * bus leading to USB2.0 packet loss. |
2070 | * | |
2071 | * This quirk is only enabled if a second (on the external PCI bus) | |
2072 | * VT6212L is found -- the CX700 core itself also contains a USB | |
2073 | * host controller with the same PCI ID as the VT6212L. | |
53a9bf42 TY |
2074 | */ |
2075 | ||
ca846392 TY |
2076 | /* Count VT6212L instances */ |
2077 | struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, | |
2078 | PCI_DEVICE_ID_VIA_8235_USB_2, NULL); | |
53a9bf42 | 2079 | uint8_t b; |
ca846392 TY |
2080 | |
2081 | /* p should contain the first (internal) VT6212L -- see if we have | |
2082 | an external one by searching again */ | |
2083 | p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); | |
2084 | if (!p) | |
2085 | return; | |
2086 | pci_dev_put(p); | |
2087 | ||
53a9bf42 TY |
2088 | if (pci_read_config_byte(dev, 0x76, &b) == 0) { |
2089 | if (b & 0x40) { | |
2090 | /* Turn off PCI Bus Parking */ | |
2091 | pci_write_config_byte(dev, 0x76, b ^ 0x40); | |
2092 | ||
bc043274 TY |
2093 | dev_info(&dev->dev, |
2094 | "Disabling VIA CX700 PCI parking\n"); | |
2095 | } | |
2096 | } | |
2097 | ||
2098 | if (pci_read_config_byte(dev, 0x72, &b) == 0) { | |
2099 | if (b != 0) { | |
53a9bf42 TY |
2100 | /* Turn off PCI Master read caching */ |
2101 | pci_write_config_byte(dev, 0x72, 0x0); | |
bc043274 TY |
2102 | |
2103 | /* Set PCI Master Bus time-out to "1x16 PCLK" */ | |
53a9bf42 | 2104 | pci_write_config_byte(dev, 0x75, 0x1); |
bc043274 TY |
2105 | |
2106 | /* Disable "Read FIFO Timer" */ | |
53a9bf42 TY |
2107 | pci_write_config_byte(dev, 0x77, 0x0); |
2108 | ||
d6505a52 | 2109 | dev_info(&dev->dev, |
bc043274 | 2110 | "Disabling VIA CX700 PCI caching\n"); |
53a9bf42 TY |
2111 | } |
2112 | } | |
2113 | } | |
ca846392 | 2114 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
53a9bf42 | 2115 | |
99cb233d BL |
2116 | /* |
2117 | * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the | |
2118 | * VPD end tag will hang the device. This problem was initially | |
2119 | * observed when a vpd entry was created in sysfs | |
2120 | * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry | |
2121 | * will dump 32k of data. Reading a full 32k will cause an access | |
2122 | * beyond the VPD end tag causing the device to hang. Once the device | |
2123 | * is hung, the bnx2 driver will not be able to reset the device. | |
2124 | * We believe that it is legal to read beyond the end tag and | |
2125 | * therefore the solution is to limit the read/write length. | |
2126 | */ | |
2127 | static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) | |
2128 | { | |
9d82d8ea | 2129 | /* |
35405f25 DH |
2130 | * Only disable the VPD capability for 5706, 5706S, 5708, |
2131 | * 5708S and 5709 rev. A | |
9d82d8ea | 2132 | */ |
99cb233d | 2133 | if ((dev->device == PCI_DEVICE_ID_NX2_5706) || |
35405f25 | 2134 | (dev->device == PCI_DEVICE_ID_NX2_5706S) || |
99cb233d | 2135 | (dev->device == PCI_DEVICE_ID_NX2_5708) || |
9d82d8ea | 2136 | (dev->device == PCI_DEVICE_ID_NX2_5708S) || |
99cb233d BL |
2137 | ((dev->device == PCI_DEVICE_ID_NX2_5709) && |
2138 | (dev->revision & 0xf0) == 0x0)) { | |
2139 | if (dev->vpd) | |
2140 | dev->vpd->len = 0x80; | |
2141 | } | |
2142 | } | |
2143 | ||
bffadffd YZ |
2144 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2145 | PCI_DEVICE_ID_NX2_5706, | |
2146 | quirk_brcm_570x_limit_vpd); | |
2147 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2148 | PCI_DEVICE_ID_NX2_5706S, | |
2149 | quirk_brcm_570x_limit_vpd); | |
2150 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2151 | PCI_DEVICE_ID_NX2_5708, | |
2152 | quirk_brcm_570x_limit_vpd); | |
2153 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2154 | PCI_DEVICE_ID_NX2_5708S, | |
2155 | quirk_brcm_570x_limit_vpd); | |
2156 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2157 | PCI_DEVICE_ID_NX2_5709, | |
2158 | quirk_brcm_570x_limit_vpd); | |
2159 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2160 | PCI_DEVICE_ID_NX2_5709S, | |
2161 | quirk_brcm_570x_limit_vpd); | |
99cb233d | 2162 | |
26c56dc0 MM |
2163 | /* Originally in EDAC sources for i82875P: |
2164 | * Intel tells BIOS developers to hide device 6 which | |
2165 | * configures the overflow device access containing | |
2166 | * the DRBs - this is where we expose device 6. | |
2167 | * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm | |
2168 | */ | |
2169 | static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev) | |
2170 | { | |
2171 | u8 reg; | |
2172 | ||
2173 | if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { | |
2174 | dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n"); | |
2175 | pci_write_config_byte(dev, 0xF4, reg | 0x02); | |
2176 | } | |
2177 | } | |
2178 | ||
2179 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, | |
2180 | quirk_unhide_mch_dev6); | |
2181 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, | |
2182 | quirk_unhide_mch_dev6); | |
2183 | ||
f02cbbe6 CM |
2184 | #ifdef CONFIG_TILE |
2185 | /* | |
2186 | * The Tilera TILEmpower platform needs to set the link speed | |
2187 | * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed | |
2188 | * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe | |
2189 | * capability register of the PEX8624 PCIe switch. The switch | |
2190 | * supports link speed auto negotiation, but falsely sets | |
2191 | * the link speed to 5GT/s. | |
2192 | */ | |
2193 | static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev) | |
2194 | { | |
2195 | if (tile_plx_gen1) { | |
2196 | pci_write_config_dword(dev, 0x98, 0x1); | |
2197 | mdelay(50); | |
2198 | } | |
2199 | } | |
2200 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); | |
2201 | #endif /* CONFIG_TILE */ | |
26c56dc0 | 2202 | |
3f79e107 | 2203 | #ifdef CONFIG_PCI_MSI |
ebdf7d39 TH |
2204 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
2205 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | |
2206 | * some other busses controlled by the chipset even if Linux is not | |
2207 | * aware of it. Instead of setting the flag on all busses in the | |
2208 | * machine, simply disable MSI globally. | |
3f79e107 | 2209 | */ |
ebdf7d39 | 2210 | static void __init quirk_disable_all_msi(struct pci_dev *dev) |
3f79e107 | 2211 | { |
88187dfa | 2212 | pci_no_msi(); |
f0fda801 | 2213 | dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n"); |
3f79e107 | 2214 | } |
ebdf7d39 TH |
2215 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); |
2216 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); | |
2217 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); | |
66d715c9 | 2218 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); |
184b812f | 2219 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); |
162dedd3 | 2220 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); |
549e1561 | 2221 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); |
3f79e107 BG |
2222 | |
2223 | /* Disable MSI on chipsets that are known to not support it */ | |
2224 | static void __devinit quirk_disable_msi(struct pci_dev *dev) | |
2225 | { | |
2226 | if (dev->subordinate) { | |
f0fda801 | 2227 | dev_warn(&dev->dev, "MSI quirk detected; " |
2228 | "subordinate MSI disabled\n"); | |
3f79e107 BG |
2229 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2230 | } | |
2231 | } | |
2232 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); | |
134b3450 | 2233 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); |
9313ff45 | 2234 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); |
6397c75c | 2235 | |
aff61369 CL |
2236 | /* |
2237 | * The APC bridge device in AMD 780 family northbridges has some random | |
2238 | * OEM subsystem ID in its vendor ID register (erratum 18), so instead | |
2239 | * we use the possible vendor/device IDs of the host bridge for the | |
2240 | * declared quirk, and search for the APC bridge by slot number. | |
2241 | */ | |
2242 | static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge) | |
2243 | { | |
2244 | struct pci_dev *apc_bridge; | |
2245 | ||
2246 | apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); | |
2247 | if (apc_bridge) { | |
2248 | if (apc_bridge->device == 0x9602) | |
2249 | quirk_disable_msi(apc_bridge); | |
2250 | pci_dev_put(apc_bridge); | |
2251 | } | |
2252 | } | |
2253 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); | |
2254 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); | |
2255 | ||
6397c75c BG |
2256 | /* Go through the list of Hypertransport capabilities and |
2257 | * return 1 if a HT MSI capability is found and enabled */ | |
2258 | static int __devinit msi_ht_cap_enabled(struct pci_dev *dev) | |
2259 | { | |
7a380507 ME |
2260 | int pos, ttl = 48; |
2261 | ||
2262 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2263 | while (pos && ttl--) { | |
2264 | u8 flags; | |
2265 | ||
2266 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2267 | &flags) == 0) | |
2268 | { | |
f0fda801 | 2269 | dev_info(&dev->dev, "Found %s HT MSI Mapping\n", |
7a380507 | 2270 | flags & HT_MSI_FLAGS_ENABLE ? |
f0fda801 | 2271 | "enabled" : "disabled"); |
7a380507 | 2272 | return (flags & HT_MSI_FLAGS_ENABLE) != 0; |
6397c75c | 2273 | } |
7a380507 ME |
2274 | |
2275 | pos = pci_find_next_ht_capability(dev, pos, | |
2276 | HT_CAPTYPE_MSI_MAPPING); | |
6397c75c BG |
2277 | } |
2278 | return 0; | |
2279 | } | |
2280 | ||
2281 | /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */ | |
2282 | static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) | |
2283 | { | |
2284 | if (dev->subordinate && !msi_ht_cap_enabled(dev)) { | |
f0fda801 | 2285 | dev_warn(&dev->dev, "MSI quirk detected; " |
2286 | "subordinate MSI disabled\n"); | |
6397c75c BG |
2287 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2288 | } | |
2289 | } | |
2290 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, | |
2291 | quirk_msi_ht_cap); | |
6bae1d96 | 2292 | |
6397c75c BG |
2293 | /* The nVidia CK804 chipset may have 2 HT MSI mappings. |
2294 | * MSI are supported if the MSI capability set in any of these mappings. | |
2295 | */ | |
2296 | static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) | |
2297 | { | |
2298 | struct pci_dev *pdev; | |
2299 | ||
2300 | if (!dev->subordinate) | |
2301 | return; | |
2302 | ||
2303 | /* check HT MSI cap on this chipset and the root one. | |
2304 | * a single one having MSI is enough to be sure that MSI are supported. | |
2305 | */ | |
11f242f0 | 2306 | pdev = pci_get_slot(dev->bus, 0); |
9ac0ce85 JJ |
2307 | if (!pdev) |
2308 | return; | |
0c875c28 | 2309 | if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { |
f0fda801 | 2310 | dev_warn(&dev->dev, "MSI quirk detected; " |
2311 | "subordinate MSI disabled\n"); | |
6397c75c BG |
2312 | dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; |
2313 | } | |
11f242f0 | 2314 | pci_dev_put(pdev); |
6397c75c BG |
2315 | } |
2316 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, | |
2317 | quirk_nvidia_ck804_msi_ht_cap); | |
ba698ad4 | 2318 | |
415b6d0e BH |
2319 | /* Force enable MSI mapping capability on HT bridges */ |
2320 | static void __devinit ht_enable_msi_mapping(struct pci_dev *dev) | |
9dc625e7 PC |
2321 | { |
2322 | int pos, ttl = 48; | |
2323 | ||
2324 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2325 | while (pos && ttl--) { | |
2326 | u8 flags; | |
2327 | ||
2328 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2329 | &flags) == 0) { | |
2330 | dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); | |
2331 | ||
2332 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2333 | flags | HT_MSI_FLAGS_ENABLE); | |
2334 | } | |
2335 | pos = pci_find_next_ht_capability(dev, pos, | |
2336 | HT_CAPTYPE_MSI_MAPPING); | |
2337 | } | |
2338 | } | |
415b6d0e BH |
2339 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, |
2340 | PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, | |
2341 | ht_enable_msi_mapping); | |
9dc625e7 | 2342 | |
e0ae4f55 YL |
2343 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, |
2344 | ht_enable_msi_mapping); | |
2345 | ||
e4146bb9 | 2346 | /* The P5N32-SLI motherboards from Asus have a problem with msi |
75e07fc3 AP |
2347 | * for the MCP55 NIC. It is not yet determined whether the msi problem |
2348 | * also affects other devices. As for now, turn off msi for this device. | |
2349 | */ | |
2350 | static void __devinit nvenet_msi_disable(struct pci_dev *dev) | |
2351 | { | |
9251bac9 JD |
2352 | const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); |
2353 | ||
2354 | if (board_name && | |
2355 | (strstr(board_name, "P5N32-SLI PREMIUM") || | |
2356 | strstr(board_name, "P5N32-E SLI"))) { | |
75e07fc3 | 2357 | dev_info(&dev->dev, |
e4146bb9 | 2358 | "Disabling msi for MCP55 NIC on P5N32-SLI\n"); |
75e07fc3 AP |
2359 | dev->no_msi = 1; |
2360 | } | |
2361 | } | |
2362 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2363 | PCI_DEVICE_ID_NVIDIA_NVENET_15, | |
2364 | nvenet_msi_disable); | |
2365 | ||
66db60ea NH |
2366 | /* |
2367 | * Some versions of the MCP55 bridge from nvidia have a legacy irq routing | |
2368 | * config register. This register controls the routing of legacy interrupts | |
2369 | * from devices that route through the MCP55. If this register is misprogramed | |
2370 | * interrupts are only sent to the bsp, unlike conventional systems where the | |
2371 | * irq is broadxast to all online cpus. Not having this register set | |
2372 | * properly prevents kdump from booting up properly, so lets make sure that | |
2373 | * we have it set correctly. | |
2374 | * Note this is an undocumented register. | |
2375 | */ | |
2376 | static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev) | |
2377 | { | |
2378 | u32 cfg; | |
2379 | ||
49c2fa08 NH |
2380 | if (!pci_find_capability(dev, PCI_CAP_ID_HT)) |
2381 | return; | |
2382 | ||
66db60ea NH |
2383 | pci_read_config_dword(dev, 0x74, &cfg); |
2384 | ||
2385 | if (cfg & ((1 << 2) | (1 << 15))) { | |
2386 | printk(KERN_INFO "Rewriting irq routing register on MCP55\n"); | |
2387 | cfg &= ~((1 << 2) | (1 << 15)); | |
2388 | pci_write_config_dword(dev, 0x74, cfg); | |
2389 | } | |
2390 | } | |
2391 | ||
2392 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2393 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, | |
2394 | nvbridge_check_legacy_irq_routing); | |
2395 | ||
2396 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, | |
2397 | PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, | |
2398 | nvbridge_check_legacy_irq_routing); | |
2399 | ||
de745306 YL |
2400 | static int __devinit ht_check_msi_mapping(struct pci_dev *dev) |
2401 | { | |
2402 | int pos, ttl = 48; | |
2403 | int found = 0; | |
2404 | ||
2405 | /* check if there is HT MSI cap or enabled on this device */ | |
2406 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2407 | while (pos && ttl--) { | |
2408 | u8 flags; | |
2409 | ||
2410 | if (found < 1) | |
2411 | found = 1; | |
2412 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2413 | &flags) == 0) { | |
2414 | if (flags & HT_MSI_FLAGS_ENABLE) { | |
2415 | if (found < 2) { | |
2416 | found = 2; | |
2417 | break; | |
2418 | } | |
2419 | } | |
2420 | } | |
2421 | pos = pci_find_next_ht_capability(dev, pos, | |
2422 | HT_CAPTYPE_MSI_MAPPING); | |
2423 | } | |
2424 | ||
2425 | return found; | |
2426 | } | |
2427 | ||
2428 | static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge) | |
2429 | { | |
2430 | struct pci_dev *dev; | |
2431 | int pos; | |
2432 | int i, dev_no; | |
2433 | int found = 0; | |
2434 | ||
2435 | dev_no = host_bridge->devfn >> 3; | |
2436 | for (i = dev_no + 1; i < 0x20; i++) { | |
2437 | dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); | |
2438 | if (!dev) | |
2439 | continue; | |
2440 | ||
2441 | /* found next host bridge ?*/ | |
2442 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2443 | if (pos != 0) { | |
2444 | pci_dev_put(dev); | |
2445 | break; | |
2446 | } | |
2447 | ||
2448 | if (ht_check_msi_mapping(dev)) { | |
2449 | found = 1; | |
2450 | pci_dev_put(dev); | |
2451 | break; | |
2452 | } | |
2453 | pci_dev_put(dev); | |
2454 | } | |
2455 | ||
2456 | return found; | |
2457 | } | |
2458 | ||
eeafda70 YL |
2459 | #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ |
2460 | #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ | |
2461 | ||
2462 | static int __devinit is_end_of_ht_chain(struct pci_dev *dev) | |
2463 | { | |
2464 | int pos, ctrl_off; | |
2465 | int end = 0; | |
2466 | u16 flags, ctrl; | |
2467 | ||
2468 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); | |
2469 | ||
2470 | if (!pos) | |
2471 | goto out; | |
2472 | ||
2473 | pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); | |
2474 | ||
2475 | ctrl_off = ((flags >> 10) & 1) ? | |
2476 | PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; | |
2477 | pci_read_config_word(dev, pos + ctrl_off, &ctrl); | |
2478 | ||
2479 | if (ctrl & (1 << 6)) | |
2480 | end = 1; | |
2481 | ||
2482 | out: | |
2483 | return end; | |
2484 | } | |
2485 | ||
1dec6b05 | 2486 | static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev) |
9dc625e7 PC |
2487 | { |
2488 | struct pci_dev *host_bridge; | |
1dec6b05 YL |
2489 | int pos; |
2490 | int i, dev_no; | |
2491 | int found = 0; | |
2492 | ||
2493 | dev_no = dev->devfn >> 3; | |
2494 | for (i = dev_no; i >= 0; i--) { | |
2495 | host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); | |
2496 | if (!host_bridge) | |
2497 | continue; | |
2498 | ||
2499 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2500 | if (pos != 0) { | |
2501 | found = 1; | |
2502 | break; | |
2503 | } | |
2504 | pci_dev_put(host_bridge); | |
2505 | } | |
2506 | ||
2507 | if (!found) | |
2508 | return; | |
2509 | ||
eeafda70 YL |
2510 | /* don't enable end_device/host_bridge with leaf directly here */ |
2511 | if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && | |
2512 | host_bridge_with_leaf(host_bridge)) | |
de745306 YL |
2513 | goto out; |
2514 | ||
1dec6b05 YL |
2515 | /* root did that ! */ |
2516 | if (msi_ht_cap_enabled(host_bridge)) | |
2517 | goto out; | |
2518 | ||
2519 | ht_enable_msi_mapping(dev); | |
2520 | ||
2521 | out: | |
2522 | pci_dev_put(host_bridge); | |
2523 | } | |
2524 | ||
2525 | static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) | |
2526 | { | |
2527 | int pos, ttl = 48; | |
2528 | ||
2529 | pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); | |
2530 | while (pos && ttl--) { | |
2531 | u8 flags; | |
2532 | ||
2533 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | |
2534 | &flags) == 0) { | |
6a958d5b | 2535 | dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); |
1dec6b05 YL |
2536 | |
2537 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | |
2538 | flags & ~HT_MSI_FLAGS_ENABLE); | |
2539 | } | |
2540 | pos = pci_find_next_ht_capability(dev, pos, | |
2541 | HT_CAPTYPE_MSI_MAPPING); | |
2542 | } | |
2543 | } | |
2544 | ||
de745306 | 2545 | static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) |
1dec6b05 YL |
2546 | { |
2547 | struct pci_dev *host_bridge; | |
2548 | int pos; | |
2549 | int found; | |
2550 | ||
3d2a5318 RW |
2551 | if (!pci_msi_enabled()) |
2552 | return; | |
2553 | ||
1dec6b05 YL |
2554 | /* check if there is HT MSI cap or enabled on this device */ |
2555 | found = ht_check_msi_mapping(dev); | |
2556 | ||
2557 | /* no HT MSI CAP */ | |
2558 | if (found == 0) | |
2559 | return; | |
9dc625e7 PC |
2560 | |
2561 | /* | |
2562 | * HT MSI mapping should be disabled on devices that are below | |
2563 | * a non-Hypertransport host bridge. Locate the host bridge... | |
2564 | */ | |
2565 | host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); | |
2566 | if (host_bridge == NULL) { | |
2567 | dev_warn(&dev->dev, | |
2568 | "nv_msi_ht_cap_quirk didn't locate host bridge\n"); | |
2569 | return; | |
2570 | } | |
2571 | ||
2572 | pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); | |
2573 | if (pos != 0) { | |
2574 | /* Host bridge is to HT */ | |
1dec6b05 YL |
2575 | if (found == 1) { |
2576 | /* it is not enabled, try to enable it */ | |
de745306 YL |
2577 | if (all) |
2578 | ht_enable_msi_mapping(dev); | |
2579 | else | |
2580 | nv_ht_enable_msi_mapping(dev); | |
1dec6b05 | 2581 | } |
9dc625e7 PC |
2582 | return; |
2583 | } | |
2584 | ||
1dec6b05 YL |
2585 | /* HT MSI is not enabled */ |
2586 | if (found == 1) | |
2587 | return; | |
9dc625e7 | 2588 | |
1dec6b05 YL |
2589 | /* Host bridge is not to HT, disable HT MSI mapping on this device */ |
2590 | ht_disable_msi_mapping(dev); | |
9dc625e7 | 2591 | } |
de745306 YL |
2592 | |
2593 | static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev) | |
2594 | { | |
2595 | return __nv_msi_ht_cap_quirk(dev, 1); | |
2596 | } | |
2597 | ||
2598 | static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) | |
2599 | { | |
2600 | return __nv_msi_ht_cap_quirk(dev, 0); | |
2601 | } | |
2602 | ||
2603 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); | |
6dab62ee | 2604 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); |
de745306 YL |
2605 | |
2606 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); | |
6dab62ee | 2607 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); |
9dc625e7 | 2608 | |
ba698ad4 DM |
2609 | static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev) |
2610 | { | |
2611 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2612 | } | |
4600c9d7 SH |
2613 | static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) |
2614 | { | |
2615 | struct pci_dev *p; | |
2616 | ||
2617 | /* SB700 MSI issue will be fixed at HW level from revision A21, | |
2618 | * we need check PCI REVISION ID of SMBus controller to get SB700 | |
2619 | * revision. | |
2620 | */ | |
2621 | p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, | |
2622 | NULL); | |
2623 | if (!p) | |
2624 | return; | |
2625 | ||
2626 | if ((p->revision < 0x3B) && (p->revision >= 0x30)) | |
2627 | dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; | |
2628 | pci_dev_put(p); | |
2629 | } | |
ba698ad4 DM |
2630 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, |
2631 | PCI_DEVICE_ID_TIGON3_5780, | |
2632 | quirk_msi_intx_disable_bug); | |
2633 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2634 | PCI_DEVICE_ID_TIGON3_5780S, | |
2635 | quirk_msi_intx_disable_bug); | |
2636 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2637 | PCI_DEVICE_ID_TIGON3_5714, | |
2638 | quirk_msi_intx_disable_bug); | |
2639 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2640 | PCI_DEVICE_ID_TIGON3_5714S, | |
2641 | quirk_msi_intx_disable_bug); | |
2642 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2643 | PCI_DEVICE_ID_TIGON3_5715, | |
2644 | quirk_msi_intx_disable_bug); | |
2645 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, | |
2646 | PCI_DEVICE_ID_TIGON3_5715S, | |
2647 | quirk_msi_intx_disable_bug); | |
2648 | ||
bc38b411 | 2649 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, |
4600c9d7 | 2650 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2651 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, |
4600c9d7 | 2652 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2653 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, |
4600c9d7 | 2654 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2655 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, |
4600c9d7 | 2656 | quirk_msi_intx_disable_ati_bug); |
bc38b411 | 2657 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, |
4600c9d7 | 2658 | quirk_msi_intx_disable_ati_bug); |
bc38b411 DM |
2659 | |
2660 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, | |
2661 | quirk_msi_intx_disable_bug); | |
2662 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, | |
2663 | quirk_msi_intx_disable_bug); | |
2664 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, | |
2665 | quirk_msi_intx_disable_bug); | |
2666 | ||
3f79e107 | 2667 | #endif /* CONFIG_PCI_MSI */ |
3d137310 | 2668 | |
3322340a FR |
2669 | /* Allow manual resource allocation for PCI hotplug bridges |
2670 | * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For | |
2671 | * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6), | |
2672 | * kernel fails to allocate resources when hotplug device is | |
2673 | * inserted and PCI bus is rescanned. | |
2674 | */ | |
2675 | static void __devinit quirk_hotplug_bridge(struct pci_dev *dev) | |
2676 | { | |
2677 | dev->is_hotplug_bridge = 1; | |
2678 | } | |
2679 | ||
2680 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); | |
2681 | ||
03cd8f7e ML |
2682 | /* |
2683 | * This is a quirk for the Ricoh MMC controller found as a part of | |
2684 | * some mulifunction chips. | |
2685 | ||
25985edc | 2686 | * This is very similar and based on the ricoh_mmc driver written by |
03cd8f7e ML |
2687 | * Philip Langdale. Thank you for these magic sequences. |
2688 | * | |
2689 | * These chips implement the four main memory card controllers (SD, MMC, MS, xD) | |
2690 | * and one or both of cardbus or firewire. | |
2691 | * | |
2692 | * It happens that they implement SD and MMC | |
2693 | * support as separate controllers (and PCI functions). The linux SDHCI | |
2694 | * driver supports MMC cards but the chip detects MMC cards in hardware | |
2695 | * and directs them to the MMC controller - so the SDHCI driver never sees | |
2696 | * them. | |
2697 | * | |
2698 | * To get around this, we must disable the useless MMC controller. | |
2699 | * At that point, the SDHCI controller will start seeing them | |
2700 | * It seems to be the case that the relevant PCI registers to deactivate the | |
2701 | * MMC controller live on PCI function 0, which might be the cardbus controller | |
2702 | * or the firewire controller, depending on the particular chip in question | |
2703 | * | |
2704 | * This has to be done early, because as soon as we disable the MMC controller | |
2705 | * other pci functions shift up one level, e.g. function #2 becomes function | |
2706 | * #1, and this will confuse the pci core. | |
2707 | */ | |
2708 | ||
2709 | #ifdef CONFIG_MMC_RICOH_MMC | |
2710 | static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) | |
2711 | { | |
2712 | /* disable via cardbus interface */ | |
2713 | u8 write_enable; | |
2714 | u8 write_target; | |
2715 | u8 disable; | |
2716 | ||
2717 | /* disable must be done via function #0 */ | |
2718 | if (PCI_FUNC(dev->devfn)) | |
2719 | return; | |
2720 | ||
2721 | pci_read_config_byte(dev, 0xB7, &disable); | |
2722 | if (disable & 0x02) | |
2723 | return; | |
2724 | ||
2725 | pci_read_config_byte(dev, 0x8E, &write_enable); | |
2726 | pci_write_config_byte(dev, 0x8E, 0xAA); | |
2727 | pci_read_config_byte(dev, 0x8D, &write_target); | |
2728 | pci_write_config_byte(dev, 0x8D, 0xB7); | |
2729 | pci_write_config_byte(dev, 0xB7, disable | 0x02); | |
2730 | pci_write_config_byte(dev, 0x8E, write_enable); | |
2731 | pci_write_config_byte(dev, 0x8D, write_target); | |
2732 | ||
2733 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n"); | |
2734 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); | |
2735 | } | |
2736 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2737 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); | |
2738 | ||
2739 | static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) | |
2740 | { | |
2741 | /* disable via firewire interface */ | |
2742 | u8 write_enable; | |
2743 | u8 disable; | |
2744 | ||
2745 | /* disable must be done via function #0 */ | |
2746 | if (PCI_FUNC(dev->devfn)) | |
2747 | return; | |
15bed0f2 MI |
2748 | /* |
2749 | * RICOH 0xe823 SD/MMC card reader fails to recognize | |
2750 | * certain types of SD/MMC cards. Lowering the SD base | |
2751 | * clock frequency from 200Mhz to 50Mhz fixes this issue. | |
2752 | * | |
2753 | * 0x150 - SD2.0 mode enable for changing base clock | |
2754 | * frequency to 50Mhz | |
2755 | * 0xe1 - Base clock frequency | |
2756 | * 0x32 - 50Mhz new clock frequency | |
2757 | * 0xf9 - Key register for 0x150 | |
2758 | * 0xfc - key register for 0xe1 | |
2759 | */ | |
2760 | if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { | |
2761 | pci_write_config_byte(dev, 0xf9, 0xfc); | |
2762 | pci_write_config_byte(dev, 0x150, 0x10); | |
2763 | pci_write_config_byte(dev, 0xf9, 0x00); | |
2764 | pci_write_config_byte(dev, 0xfc, 0x01); | |
2765 | pci_write_config_byte(dev, 0xe1, 0x32); | |
2766 | pci_write_config_byte(dev, 0xfc, 0x00); | |
2767 | ||
2768 | dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n"); | |
2769 | } | |
3e309cdf JB |
2770 | |
2771 | pci_read_config_byte(dev, 0xCB, &disable); | |
2772 | ||
2773 | if (disable & 0x02) | |
2774 | return; | |
2775 | ||
2776 | pci_read_config_byte(dev, 0xCA, &write_enable); | |
2777 | pci_write_config_byte(dev, 0xCA, 0x57); | |
2778 | pci_write_config_byte(dev, 0xCB, disable | 0x02); | |
2779 | pci_write_config_byte(dev, 0xCA, write_enable); | |
2780 | ||
2781 | dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n"); | |
2782 | dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n"); | |
2783 | ||
03cd8f7e ML |
2784 | } |
2785 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
2786 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); | |
be98ca65 MI |
2787 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); |
2788 | DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); | |
03cd8f7e ML |
2789 | #endif /*CONFIG_MMC_RICOH_MMC*/ |
2790 | ||
d3f13810 | 2791 | #ifdef CONFIG_DMAR_TABLE |
254e4200 SS |
2792 | #define VTUNCERRMSK_REG 0x1ac |
2793 | #define VTD_MSK_SPEC_ERRORS (1 << 31) | |
2794 | /* | |
2795 | * This is a quirk for masking vt-d spec defined errors to platform error | |
2796 | * handling logic. With out this, platforms using Intel 7500, 5500 chipsets | |
2797 | * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based | |
2798 | * on the RAS config settings of the platform) when a vt-d fault happens. | |
2799 | * The resulting SMI caused the system to hang. | |
2800 | * | |
2801 | * VT-d spec related errors are already handled by the VT-d OS code, so no | |
2802 | * need to report the same error through other channels. | |
2803 | */ | |
2804 | static void vtd_mask_spec_errors(struct pci_dev *dev) | |
2805 | { | |
2806 | u32 word; | |
2807 | ||
2808 | pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); | |
2809 | pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); | |
2810 | } | |
2811 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); | |
2812 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); | |
2813 | #endif | |
03cd8f7e | 2814 | |
63c44080 HP |
2815 | static void __devinit fixup_ti816x_class(struct pci_dev* dev) |
2816 | { | |
2817 | /* TI 816x devices do not have class code set when in PCIe boot mode */ | |
2818 | if (dev->class == PCI_CLASS_NOT_DEFINED) { | |
2819 | dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n"); | |
2820 | dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; | |
2821 | } | |
2822 | } | |
2823 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class); | |
2824 | ||
a94d072b BH |
2825 | /* Some PCIe devices do not work reliably with the claimed maximum |
2826 | * payload size supported. | |
2827 | */ | |
2828 | static void __devinit fixup_mpss_256(struct pci_dev *dev) | |
2829 | { | |
2830 | dev->pcie_mpss = 1; /* 256 bytes */ | |
2831 | } | |
2832 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
2833 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); | |
2834 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
2835 | PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); | |
2836 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE, | |
2837 | PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); | |
2838 | ||
d387a8d6 JM |
2839 | /* Intel 5000 and 5100 Memory controllers have an errata with read completion |
2840 | * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. | |
2841 | * Since there is no way of knowing what the PCIE MPS on each fabric will be | |
2842 | * until all of the devices are discovered and buses walked, read completion | |
2843 | * coalescing must be disabled. Unfortunately, it cannot be re-enabled because | |
2844 | * it is possible to hotplug a device with MPS of 256B. | |
2845 | */ | |
2846 | static void __devinit quirk_intel_mc_errata(struct pci_dev *dev) | |
2847 | { | |
2848 | int err; | |
2849 | u16 rcc; | |
2850 | ||
2851 | if (pcie_bus_config == PCIE_BUS_TUNE_OFF) | |
2852 | return; | |
2853 | ||
2854 | /* Intel errata specifies bits to change but does not say what they are. | |
2855 | * Keeping them magical until such time as the registers and values can | |
2856 | * be explained. | |
2857 | */ | |
2858 | err = pci_read_config_word(dev, 0x48, &rcc); | |
2859 | if (err) { | |
2860 | dev_err(&dev->dev, "Error attempting to read the read " | |
2861 | "completion coalescing register.\n"); | |
2862 | return; | |
2863 | } | |
2864 | ||
2865 | if (!(rcc & (1 << 10))) | |
2866 | return; | |
2867 | ||
2868 | rcc &= ~(1 << 10); | |
2869 | ||
2870 | err = pci_write_config_word(dev, 0x48, rcc); | |
2871 | if (err) { | |
2872 | dev_err(&dev->dev, "Error attempting to write the read " | |
2873 | "completion coalescing register.\n"); | |
2874 | return; | |
2875 | } | |
2876 | ||
2877 | pr_info_once("Read completion coalescing disabled due to hardware " | |
2878 | "errata relating to 256B MPS.\n"); | |
2879 | } | |
2880 | /* Intel 5000 series memory controllers and ports 2-7 */ | |
2881 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); | |
2882 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); | |
2883 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); | |
2884 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); | |
2885 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); | |
2886 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); | |
2887 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); | |
2888 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); | |
2889 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); | |
2890 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); | |
2891 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); | |
2892 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); | |
2893 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); | |
2894 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); | |
2895 | /* Intel 5100 series memory controllers and ports 2-7 */ | |
2896 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); | |
2897 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); | |
2898 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); | |
2899 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); | |
2900 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); | |
2901 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); | |
2902 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); | |
2903 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); | |
2904 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); | |
2905 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); | |
2906 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); | |
2907 | ||
bfb0f330 JB |
2908 | static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, |
2909 | struct pci_fixup *end) | |
3d137310 TP |
2910 | { |
2911 | while (f < end) { | |
2912 | if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && | |
bfb0f330 | 2913 | (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { |
c9bbb4ab | 2914 | dev_dbg(&dev->dev, "calling %pF\n", f->hook); |
3d137310 TP |
2915 | f->hook(dev); |
2916 | } | |
2917 | f++; | |
2918 | } | |
2919 | } | |
2920 | ||
2921 | extern struct pci_fixup __start_pci_fixups_early[]; | |
2922 | extern struct pci_fixup __end_pci_fixups_early[]; | |
2923 | extern struct pci_fixup __start_pci_fixups_header[]; | |
2924 | extern struct pci_fixup __end_pci_fixups_header[]; | |
2925 | extern struct pci_fixup __start_pci_fixups_final[]; | |
2926 | extern struct pci_fixup __end_pci_fixups_final[]; | |
2927 | extern struct pci_fixup __start_pci_fixups_enable[]; | |
2928 | extern struct pci_fixup __end_pci_fixups_enable[]; | |
2929 | extern struct pci_fixup __start_pci_fixups_resume[]; | |
2930 | extern struct pci_fixup __end_pci_fixups_resume[]; | |
2931 | extern struct pci_fixup __start_pci_fixups_resume_early[]; | |
2932 | extern struct pci_fixup __end_pci_fixups_resume_early[]; | |
2933 | extern struct pci_fixup __start_pci_fixups_suspend[]; | |
2934 | extern struct pci_fixup __end_pci_fixups_suspend[]; | |
2935 | ||
2936 | ||
2937 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) | |
2938 | { | |
2939 | struct pci_fixup *start, *end; | |
2940 | ||
2941 | switch(pass) { | |
2942 | case pci_fixup_early: | |
2943 | start = __start_pci_fixups_early; | |
2944 | end = __end_pci_fixups_early; | |
2945 | break; | |
2946 | ||
2947 | case pci_fixup_header: | |
2948 | start = __start_pci_fixups_header; | |
2949 | end = __end_pci_fixups_header; | |
2950 | break; | |
2951 | ||
2952 | case pci_fixup_final: | |
2953 | start = __start_pci_fixups_final; | |
2954 | end = __end_pci_fixups_final; | |
2955 | break; | |
2956 | ||
2957 | case pci_fixup_enable: | |
2958 | start = __start_pci_fixups_enable; | |
2959 | end = __end_pci_fixups_enable; | |
2960 | break; | |
2961 | ||
2962 | case pci_fixup_resume: | |
2963 | start = __start_pci_fixups_resume; | |
2964 | end = __end_pci_fixups_resume; | |
2965 | break; | |
2966 | ||
2967 | case pci_fixup_resume_early: | |
2968 | start = __start_pci_fixups_resume_early; | |
2969 | end = __end_pci_fixups_resume_early; | |
2970 | break; | |
2971 | ||
2972 | case pci_fixup_suspend: | |
2973 | start = __start_pci_fixups_suspend; | |
2974 | end = __end_pci_fixups_suspend; | |
2975 | break; | |
2976 | ||
2977 | default: | |
2978 | /* stupid compiler warning, you would think with an enum... */ | |
2979 | return; | |
2980 | } | |
2981 | pci_do_fixups(dev, start, end); | |
2982 | } | |
93177a74 | 2983 | EXPORT_SYMBOL(pci_fixup_device); |
8d86fb2c | 2984 | |
00010268 | 2985 | static int __init pci_apply_final_quirks(void) |
8d86fb2c DW |
2986 | { |
2987 | struct pci_dev *dev = NULL; | |
ac1aa47b JB |
2988 | u8 cls = 0; |
2989 | u8 tmp; | |
2990 | ||
2991 | if (pci_cache_line_size) | |
2992 | printk(KERN_DEBUG "PCI: CLS %u bytes\n", | |
2993 | pci_cache_line_size << 2); | |
8d86fb2c | 2994 | |
4e344b1c | 2995 | for_each_pci_dev(dev) { |
8d86fb2c | 2996 | pci_fixup_device(pci_fixup_final, dev); |
ac1aa47b JB |
2997 | /* |
2998 | * If arch hasn't set it explicitly yet, use the CLS | |
2999 | * value shared by all PCI devices. If there's a | |
3000 | * mismatch, fall back to the default value. | |
3001 | */ | |
3002 | if (!pci_cache_line_size) { | |
3003 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); | |
3004 | if (!cls) | |
3005 | cls = tmp; | |
3006 | if (!tmp || cls == tmp) | |
3007 | continue; | |
3008 | ||
3009 | printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), " | |
3010 | "using %u bytes\n", cls << 2, tmp << 2, | |
3011 | pci_dfl_cache_line_size << 2); | |
3012 | pci_cache_line_size = pci_dfl_cache_line_size; | |
3013 | } | |
3014 | } | |
3015 | if (!pci_cache_line_size) { | |
3016 | printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n", | |
3017 | cls << 2, pci_dfl_cache_line_size << 2); | |
2820f333 | 3018 | pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; |
8d86fb2c DW |
3019 | } |
3020 | ||
3021 | return 0; | |
3022 | } | |
3023 | ||
cf6f3bf7 | 3024 | fs_initcall_sync(pci_apply_final_quirks); |
b9c3b266 DC |
3025 | |
3026 | /* | |
3027 | * Followings are device-specific reset methods which can be used to | |
3028 | * reset a single function if other methods (e.g. FLR, PM D0->D3) are | |
3029 | * not available. | |
3030 | */ | |
aeb30016 DC |
3031 | static int reset_intel_generic_dev(struct pci_dev *dev, int probe) |
3032 | { | |
3033 | int pos; | |
3034 | ||
3035 | /* only implement PCI_CLASS_SERIAL_USB at present */ | |
3036 | if (dev->class == PCI_CLASS_SERIAL_USB) { | |
3037 | pos = pci_find_capability(dev, PCI_CAP_ID_VNDR); | |
3038 | if (!pos) | |
3039 | return -ENOTTY; | |
3040 | ||
3041 | if (probe) | |
3042 | return 0; | |
3043 | ||
3044 | pci_write_config_byte(dev, pos + 0x4, 1); | |
3045 | msleep(100); | |
3046 | ||
3047 | return 0; | |
3048 | } else { | |
3049 | return -ENOTTY; | |
3050 | } | |
3051 | } | |
3052 | ||
c763e7b5 DC |
3053 | static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) |
3054 | { | |
3055 | int pos; | |
3056 | ||
3057 | pos = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
3058 | if (!pos) | |
3059 | return -ENOTTY; | |
3060 | ||
3061 | if (probe) | |
3062 | return 0; | |
3063 | ||
3064 | pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, | |
3065 | PCI_EXP_DEVCTL_BCR_FLR); | |
3066 | msleep(100); | |
3067 | ||
3068 | return 0; | |
3069 | } | |
3070 | ||
3071 | #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed | |
3072 | ||
5b889bf2 | 3073 | static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { |
c763e7b5 DC |
3074 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, |
3075 | reset_intel_82599_sfp_virtfn }, | |
aeb30016 DC |
3076 | { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
3077 | reset_intel_generic_dev }, | |
b9c3b266 DC |
3078 | { 0 } |
3079 | }; | |
5b889bf2 RW |
3080 | |
3081 | int pci_dev_specific_reset(struct pci_dev *dev, int probe) | |
3082 | { | |
df9d1e8a | 3083 | const struct pci_dev_reset_methods *i; |
5b889bf2 RW |
3084 | |
3085 | for (i = pci_dev_reset_methods; i->reset; i++) { | |
3086 | if ((i->vendor == dev->vendor || | |
3087 | i->vendor == (u16)PCI_ANY_ID) && | |
3088 | (i->device == dev->device || | |
3089 | i->device == (u16)PCI_ANY_ID)) | |
3090 | return i->reset(dev, probe); | |
3091 | } | |
3092 | ||
3093 | return -ENOTTY; | |
3094 | } |