Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
28 | ||
29 | ||
30 | #define DEBUG_CONFIG 1 | |
31 | #if DEBUG_CONFIG | |
32 | #define DBG(x...) printk(x) | |
33 | #else | |
34 | #define DBG(x...) | |
35 | #endif | |
36 | ||
96bde06a | 37 | static void pbus_assign_resources_sorted(struct pci_bus *bus) |
1da177e4 LT |
38 | { |
39 | struct pci_dev *dev; | |
40 | struct resource *res; | |
41 | struct resource_list head, *list, *tmp; | |
42 | int idx; | |
43 | ||
1da177e4 LT |
44 | head.next = NULL; |
45 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
46 | u16 class = dev->class >> 8; | |
47 | ||
9bded00b | 48 | /* Don't touch classless devices or host bridges or ioapics. */ |
1da177e4 | 49 | if (class == PCI_CLASS_NOT_DEFINED || |
23186279 | 50 | class == PCI_CLASS_BRIDGE_HOST) |
1da177e4 LT |
51 | continue; |
52 | ||
9bded00b | 53 | /* Don't touch ioapic devices already enabled by firmware */ |
23186279 | 54 | if (class == PCI_CLASS_SYSTEM_PIC) { |
9bded00b KK |
55 | u16 command; |
56 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
57 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
23186279 ST |
58 | continue; |
59 | } | |
60 | ||
1da177e4 LT |
61 | pdev_sort_resources(dev, &head); |
62 | } | |
63 | ||
64 | for (list = head.next; list;) { | |
65 | res = list->res; | |
66 | idx = res - &list->dev->resource[0]; | |
542df5de | 67 | if (pci_assign_resource(list->dev, idx)) { |
88452565 | 68 | /* FIXME: get rid of this */ |
542df5de | 69 | res->start = 0; |
960b8466 | 70 | res->end = 0; |
542df5de RS |
71 | res->flags = 0; |
72 | } | |
1da177e4 LT |
73 | tmp = list; |
74 | list = list->next; | |
75 | kfree(tmp); | |
76 | } | |
77 | } | |
78 | ||
b3743fa4 | 79 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
80 | { |
81 | struct pci_dev *bridge = bus->self; | |
82 | struct pci_bus_region region; | |
83 | ||
84 | printk("PCI: Bus %d, cardbus bridge: %s\n", | |
85 | bus->number, pci_name(bridge)); | |
86 | ||
87 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); | |
88 | if (bus->resource[0]->flags & IORESOURCE_IO) { | |
89 | /* | |
90 | * The IO resource is allocated a range twice as large as it | |
91 | * would normally need. This allows us to set both IO regs. | |
92 | */ | |
c40a22e0 BH |
93 | printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", |
94 | (unsigned long)region.start, | |
95 | (unsigned long)region.end); | |
1da177e4 LT |
96 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
97 | region.start); | |
98 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
99 | region.end); | |
100 | } | |
101 | ||
102 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); | |
103 | if (bus->resource[1]->flags & IORESOURCE_IO) { | |
c40a22e0 BH |
104 | printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", |
105 | (unsigned long)region.start, | |
106 | (unsigned long)region.end); | |
1da177e4 LT |
107 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
108 | region.start); | |
109 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
110 | region.end); | |
111 | } | |
112 | ||
113 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); | |
114 | if (bus->resource[2]->flags & IORESOURCE_MEM) { | |
c40a22e0 BH |
115 | printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n", |
116 | (unsigned long)region.start, | |
117 | (unsigned long)region.end); | |
1da177e4 LT |
118 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
119 | region.start); | |
120 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
121 | region.end); | |
122 | } | |
123 | ||
124 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); | |
125 | if (bus->resource[3]->flags & IORESOURCE_MEM) { | |
c40a22e0 BH |
126 | printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", |
127 | (unsigned long)region.start, | |
128 | (unsigned long)region.end); | |
1da177e4 LT |
129 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
130 | region.start); | |
131 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
132 | region.end); | |
133 | } | |
134 | } | |
b3743fa4 | 135 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
136 | |
137 | /* Initialize bridges with base/limit values we have collected. | |
138 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
139 | requires that if there is no I/O ports or memory behind the | |
140 | bridge, corresponding range must be turned off by writing base | |
141 | value greater than limit to the bridge's base/limit registers. | |
142 | ||
143 | Note: care must be taken when updating I/O base/limit registers | |
144 | of bridges which support 32-bit I/O. This update requires two | |
145 | config space writes, so it's quite possible that an I/O window of | |
146 | the bridge will have some undesirable address (e.g. 0) after the | |
147 | first write. Ditto 64-bit prefetchable MMIO. */ | |
a391f197 | 148 | static void pci_setup_bridge(struct pci_bus *bus) |
1da177e4 LT |
149 | { |
150 | struct pci_dev *bridge = bus->self; | |
151 | struct pci_bus_region region; | |
c40a22e0 | 152 | u32 l, bu, lu, io_upper16; |
1da177e4 LT |
153 | |
154 | DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); | |
155 | ||
156 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
157 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); | |
158 | if (bus->resource[0]->flags & IORESOURCE_IO) { | |
159 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); | |
160 | l &= 0xffff0000; | |
161 | l |= (region.start >> 8) & 0x00f0; | |
162 | l |= region.end & 0xf000; | |
163 | /* Set up upper 16 bits of I/O base/limit. */ | |
164 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
165 | DBG(KERN_INFO " IO window: %04lx-%04lx\n", | |
c40a22e0 BH |
166 | (unsigned long)region.start, |
167 | (unsigned long)region.end); | |
1da177e4 LT |
168 | } |
169 | else { | |
170 | /* Clear upper 16 bits of I/O base/limit. */ | |
171 | io_upper16 = 0; | |
172 | l = 0x00f0; | |
173 | DBG(KERN_INFO " IO window: disabled.\n"); | |
174 | } | |
175 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
176 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
177 | /* Update lower 16 bits of I/O base/limit. */ | |
178 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
179 | /* Update upper 16 bits of I/O base/limit. */ | |
180 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
181 | ||
182 | /* Set up the top and bottom of the PCI Memory segment | |
183 | for this bus. */ | |
184 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); | |
185 | if (bus->resource[1]->flags & IORESOURCE_MEM) { | |
186 | l = (region.start >> 16) & 0xfff0; | |
187 | l |= region.end & 0xfff00000; | |
c40a22e0 BH |
188 | DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", |
189 | (unsigned long)region.start, | |
190 | (unsigned long)region.end); | |
1da177e4 LT |
191 | } |
192 | else { | |
193 | l = 0x0000fff0; | |
194 | DBG(KERN_INFO " MEM window: disabled.\n"); | |
195 | } | |
196 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
197 | ||
198 | /* Clear out the upper 32 bits of PREF limit. | |
199 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
200 | disables PREF range, which is ok. */ | |
201 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
202 | ||
203 | /* Set up PREF base/limit. */ | |
c40a22e0 | 204 | bu = lu = 0; |
1da177e4 LT |
205 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); |
206 | if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { | |
207 | l = (region.start >> 16) & 0xfff0; | |
208 | l |= region.end & 0xfff00000; | |
13d36c24 AM |
209 | bu = upper_32_bits(region.start); |
210 | lu = upper_32_bits(region.end); | |
c40a22e0 BH |
211 | DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n", |
212 | (unsigned long long)region.start, | |
213 | (unsigned long long)region.end); | |
1da177e4 LT |
214 | } |
215 | else { | |
216 | l = 0x0000fff0; | |
217 | DBG(KERN_INFO " PREFETCH window: disabled.\n"); | |
218 | } | |
219 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
220 | ||
c40a22e0 BH |
221 | /* Set the upper 32 bits of PREF base & limit. */ |
222 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
223 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
1da177e4 LT |
224 | |
225 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
226 | } | |
227 | ||
228 | /* Check whether the bridge supports optional I/O and | |
229 | prefetchable memory ranges. If not, the respective | |
230 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 231 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
232 | { |
233 | u16 io; | |
234 | u32 pmem; | |
235 | struct pci_dev *bridge = bus->self; | |
236 | struct resource *b_res; | |
237 | ||
238 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
239 | b_res[1].flags |= IORESOURCE_MEM; | |
240 | ||
241 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
242 | if (!io) { | |
243 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
244 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
245 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
246 | } | |
247 | if (io) | |
248 | b_res[0].flags |= IORESOURCE_IO; | |
249 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
250 | disconnect boundary by one PCI data phase. | |
251 | Workaround: do not use prefetching on this device. */ | |
252 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
253 | return; | |
254 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
255 | if (!pmem) { | |
256 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
257 | 0xfff0fff0); | |
258 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
259 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
260 | } | |
261 | if (pmem) | |
262 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
263 | } | |
264 | ||
265 | /* Helper function for sizing routines: find first available | |
266 | bus resource of a given type. Note: we intentionally skip | |
267 | the bus resources which have already been assigned (that is, | |
268 | have non-NULL parent resource). */ | |
96bde06a | 269 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
270 | { |
271 | int i; | |
272 | struct resource *r; | |
273 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
274 | IORESOURCE_PREFETCH; | |
275 | ||
276 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { | |
277 | r = bus->resource[i]; | |
299de034 IK |
278 | if (r == &ioport_resource || r == &iomem_resource) |
279 | continue; | |
1da177e4 LT |
280 | if (r && (r->flags & type_mask) == type && !r->parent) |
281 | return r; | |
282 | } | |
283 | return NULL; | |
284 | } | |
285 | ||
286 | /* Sizing the IO windows of the PCI-PCI bridge is trivial, | |
287 | since these windows have 4K granularity and the IO ranges | |
288 | of non-bridge PCI devices are limited to 256 bytes. | |
289 | We must be careful with the ISA aliasing though. */ | |
96bde06a | 290 | static void pbus_size_io(struct pci_bus *bus) |
1da177e4 LT |
291 | { |
292 | struct pci_dev *dev; | |
293 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
294 | unsigned long size = 0, size1 = 0; | |
295 | ||
296 | if (!b_res) | |
297 | return; | |
298 | ||
299 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
300 | int i; | |
301 | ||
302 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
303 | struct resource *r = &dev->resource[i]; | |
304 | unsigned long r_size; | |
305 | ||
306 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
307 | continue; | |
308 | r_size = r->end - r->start + 1; | |
309 | ||
310 | if (r_size < 0x400) | |
311 | /* Might be re-aligned for ISA */ | |
312 | size += r_size; | |
313 | else | |
314 | size1 += r_size; | |
315 | } | |
316 | } | |
317 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
318 | flag in the struct pci_bus. */ | |
319 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
320 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
321 | #endif | |
6f6f8c2f | 322 | size = ALIGN(size + size1, 4096); |
1da177e4 LT |
323 | if (!size) { |
324 | b_res->flags = 0; | |
325 | return; | |
326 | } | |
327 | /* Alignment of the IO window is always 4K */ | |
328 | b_res->start = 4096; | |
329 | b_res->end = b_res->start + size - 1; | |
88452565 | 330 | b_res->flags |= IORESOURCE_STARTALIGN; |
1da177e4 LT |
331 | } |
332 | ||
333 | /* Calculate the size of the bus and minimal alignment which | |
334 | guarantees that all child resources fit in this size. */ | |
96bde06a | 335 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) |
1da177e4 LT |
336 | { |
337 | struct pci_dev *dev; | |
c40a22e0 BH |
338 | resource_size_t min_align, align, size; |
339 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ | |
1da177e4 LT |
340 | int order, max_order; |
341 | struct resource *b_res = find_free_bus_resource(bus, type); | |
342 | ||
343 | if (!b_res) | |
344 | return 0; | |
345 | ||
346 | memset(aligns, 0, sizeof(aligns)); | |
347 | max_order = 0; | |
348 | size = 0; | |
349 | ||
350 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
351 | int i; | |
352 | ||
353 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
354 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 355 | resource_size_t r_size; |
1da177e4 LT |
356 | |
357 | if (r->parent || (r->flags & mask) != type) | |
358 | continue; | |
359 | r_size = r->end - r->start + 1; | |
360 | /* For bridges size != alignment */ | |
361 | align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; | |
362 | order = __ffs(align) - 20; | |
363 | if (order > 11) { | |
364 | printk(KERN_WARNING "PCI: region %s/%d " | |
c40a22e0 | 365 | "too large: 0x%016llx-0x%016llx\n", |
1396a8c3 | 366 | pci_name(dev), i, |
c40a22e0 BH |
367 | (unsigned long long)r->start, |
368 | (unsigned long long)r->end); | |
1da177e4 LT |
369 | r->flags = 0; |
370 | continue; | |
371 | } | |
372 | size += r_size; | |
373 | if (order < 0) | |
374 | order = 0; | |
375 | /* Exclude ranges with size > align from | |
376 | calculation of the alignment. */ | |
377 | if (r_size == align) | |
378 | aligns[order] += align; | |
379 | if (order > max_order) | |
380 | max_order = order; | |
381 | } | |
382 | } | |
383 | ||
384 | align = 0; | |
385 | min_align = 0; | |
386 | for (order = 0; order <= max_order; order++) { | |
c40a22e0 BH |
387 | #ifdef CONFIG_RESOURCES_64BIT |
388 | resource_size_t align1 = 1ULL << (order + 20); | |
389 | #else | |
390 | resource_size_t align1 = 1U << (order + 20); | |
391 | #endif | |
1da177e4 LT |
392 | if (!align) |
393 | min_align = align1; | |
6f6f8c2f | 394 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
395 | min_align = align1 >> 1; |
396 | align += aligns[order]; | |
397 | } | |
6f6f8c2f | 398 | size = ALIGN(size, min_align); |
1da177e4 LT |
399 | if (!size) { |
400 | b_res->flags = 0; | |
401 | return 1; | |
402 | } | |
403 | b_res->start = min_align; | |
404 | b_res->end = size + min_align - 1; | |
88452565 | 405 | b_res->flags |= IORESOURCE_STARTALIGN; |
1da177e4 LT |
406 | return 1; |
407 | } | |
408 | ||
5468ae61 | 409 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
1da177e4 LT |
410 | { |
411 | struct pci_dev *bridge = bus->self; | |
412 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
413 | u16 ctrl; | |
414 | ||
415 | /* | |
416 | * Reserve some resources for CardBus. We reserve | |
417 | * a fixed amount of bus space for CardBus bridges. | |
418 | */ | |
934b7024 LT |
419 | b_res[0].start = 0; |
420 | b_res[0].end = pci_cardbus_io_size - 1; | |
421 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 | 422 | |
934b7024 LT |
423 | b_res[1].start = 0; |
424 | b_res[1].end = pci_cardbus_io_size - 1; | |
425 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
426 | |
427 | /* | |
428 | * Check whether prefetchable memory is supported | |
429 | * by this bridge. | |
430 | */ | |
431 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
432 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
433 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
434 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
435 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
436 | } | |
437 | ||
438 | /* | |
439 | * If we have prefetchable memory support, allocate | |
440 | * two regions. Otherwise, allocate one region of | |
441 | * twice the size. | |
442 | */ | |
443 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 LT |
444 | b_res[2].start = 0; |
445 | b_res[2].end = pci_cardbus_mem_size - 1; | |
446 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; | |
1da177e4 | 447 | |
934b7024 LT |
448 | b_res[3].start = 0; |
449 | b_res[3].end = pci_cardbus_mem_size - 1; | |
450 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 | 451 | } else { |
934b7024 LT |
452 | b_res[3].start = 0; |
453 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; | |
454 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
455 | } |
456 | } | |
457 | ||
451124a7 | 458 | void __ref pci_bus_size_bridges(struct pci_bus *bus) |
1da177e4 LT |
459 | { |
460 | struct pci_dev *dev; | |
461 | unsigned long mask, prefmask; | |
462 | ||
463 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
464 | struct pci_bus *b = dev->subordinate; | |
465 | if (!b) | |
466 | continue; | |
467 | ||
468 | switch (dev->class >> 8) { | |
469 | case PCI_CLASS_BRIDGE_CARDBUS: | |
470 | pci_bus_size_cardbus(b); | |
471 | break; | |
472 | ||
473 | case PCI_CLASS_BRIDGE_PCI: | |
474 | default: | |
475 | pci_bus_size_bridges(b); | |
476 | break; | |
477 | } | |
478 | } | |
479 | ||
480 | /* The root bus? */ | |
481 | if (!bus->self) | |
482 | return; | |
483 | ||
484 | switch (bus->self->class >> 8) { | |
485 | case PCI_CLASS_BRIDGE_CARDBUS: | |
486 | /* don't size cardbuses yet. */ | |
487 | break; | |
488 | ||
489 | case PCI_CLASS_BRIDGE_PCI: | |
490 | pci_bridge_check_ranges(bus); | |
491 | default: | |
492 | pbus_size_io(bus); | |
493 | /* If the bridge supports prefetchable range, size it | |
494 | separately. If it doesn't, or its prefetchable window | |
495 | has already been allocated by arch code, try | |
496 | non-prefetchable range for both types of PCI memory | |
497 | resources. */ | |
498 | mask = IORESOURCE_MEM; | |
499 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
500 | if (pbus_size_mem(bus, prefmask, prefmask)) | |
501 | mask = prefmask; /* Success, size non-prefetch only. */ | |
502 | pbus_size_mem(bus, mask, IORESOURCE_MEM); | |
503 | break; | |
504 | } | |
505 | } | |
506 | EXPORT_SYMBOL(pci_bus_size_bridges); | |
507 | ||
451124a7 | 508 | void __ref pci_bus_assign_resources(struct pci_bus *bus) |
1da177e4 LT |
509 | { |
510 | struct pci_bus *b; | |
511 | struct pci_dev *dev; | |
512 | ||
513 | pbus_assign_resources_sorted(bus); | |
514 | ||
1da177e4 LT |
515 | list_for_each_entry(dev, &bus->devices, bus_list) { |
516 | b = dev->subordinate; | |
517 | if (!b) | |
518 | continue; | |
519 | ||
520 | pci_bus_assign_resources(b); | |
521 | ||
522 | switch (dev->class >> 8) { | |
523 | case PCI_CLASS_BRIDGE_PCI: | |
524 | pci_setup_bridge(b); | |
525 | break; | |
526 | ||
527 | case PCI_CLASS_BRIDGE_CARDBUS: | |
528 | pci_setup_cardbus(b); | |
529 | break; | |
530 | ||
531 | default: | |
532 | printk(KERN_INFO "PCI: not setting up bridge %s " | |
533 | "for bus %d\n", pci_name(dev), b->number); | |
534 | break; | |
535 | } | |
536 | } | |
537 | } | |
538 | EXPORT_SYMBOL(pci_bus_assign_resources); | |
539 | ||
540 | void __init | |
541 | pci_assign_unassigned_resources(void) | |
542 | { | |
543 | struct pci_bus *bus; | |
544 | ||
545 | /* Depth first, calculate sizes and alignments of all | |
546 | subordinate buses. */ | |
547 | list_for_each_entry(bus, &pci_root_buses, node) { | |
548 | pci_bus_size_bridges(bus); | |
549 | } | |
550 | /* Depth last, allocate resources and update the hardware. */ | |
551 | list_for_each_entry(bus, &pci_root_buses, node) { | |
552 | pci_bus_assign_resources(bus); | |
553 | pci_enable_bridges(bus); | |
554 | } | |
555 | } |