Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
568ddef8 YL |
30 | struct resource_list_x { |
31 | struct resource_list_x *next; | |
32 | struct resource *res; | |
33 | struct pci_dev *dev; | |
34 | resource_size_t start; | |
35 | resource_size_t end; | |
36 | unsigned long flags; | |
37 | }; | |
38 | ||
094732a5 RP |
39 | #define free_list(type, head) do { \ |
40 | struct type *list, *tmp; \ | |
41 | for (list = (head)->next; list;) { \ | |
42 | tmp = list; \ | |
43 | list = list->next; \ | |
44 | kfree(tmp); \ | |
45 | } \ | |
46 | (head)->next = NULL; \ | |
47 | } while (0) | |
48 | ||
568ddef8 YL |
49 | static void add_to_failed_list(struct resource_list_x *head, |
50 | struct pci_dev *dev, struct resource *res) | |
51 | { | |
52 | struct resource_list_x *list = head; | |
53 | struct resource_list_x *ln = list->next; | |
54 | struct resource_list_x *tmp; | |
55 | ||
56 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
57 | if (!tmp) { | |
58 | pr_warning("add_to_failed_list: kmalloc() failed!\n"); | |
59 | return; | |
60 | } | |
61 | ||
62 | tmp->next = ln; | |
63 | tmp->res = res; | |
64 | tmp->dev = dev; | |
65 | tmp->start = res->start; | |
66 | tmp->end = res->end; | |
67 | tmp->flags = res->flags; | |
68 | list->next = tmp; | |
69 | } | |
70 | ||
6841ec68 YL |
71 | static void __dev_sort_resources(struct pci_dev *dev, |
72 | struct resource_list *head) | |
1da177e4 | 73 | { |
6841ec68 | 74 | u16 class = dev->class >> 8; |
1da177e4 | 75 | |
6841ec68 YL |
76 | /* Don't touch classless devices or host bridges or ioapics. */ |
77 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
78 | return; | |
1da177e4 | 79 | |
6841ec68 YL |
80 | /* Don't touch ioapic devices already enabled by firmware */ |
81 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
82 | u16 command; | |
83 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
84 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
85 | return; | |
86 | } | |
1da177e4 | 87 | |
6841ec68 YL |
88 | pdev_sort_resources(dev, head); |
89 | } | |
23186279 | 90 | |
6841ec68 YL |
91 | static void __assign_resources_sorted(struct resource_list *head, |
92 | struct resource_list_x *fail_head) | |
93 | { | |
94 | struct resource *res; | |
95 | struct resource_list *list, *tmp; | |
96 | int idx; | |
1da177e4 | 97 | |
6841ec68 | 98 | for (list = head->next; list;) { |
1da177e4 LT |
99 | res = list->res; |
100 | idx = res - &list->dev->resource[0]; | |
9a928660 | 101 | |
542df5de | 102 | if (pci_assign_resource(list->dev, idx)) { |
9a928660 YL |
103 | if (fail_head && !pci_is_root_bus(list->dev->bus)) { |
104 | /* | |
105 | * if the failed res is for ROM BAR, and it will | |
106 | * be enabled later, don't add it to the list | |
107 | */ | |
108 | if (!((idx == PCI_ROM_RESOURCE) && | |
109 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
110 | add_to_failed_list(fail_head, list->dev, res); | |
111 | } | |
542df5de | 112 | res->start = 0; |
960b8466 | 113 | res->end = 0; |
542df5de RS |
114 | res->flags = 0; |
115 | } | |
1da177e4 LT |
116 | tmp = list; |
117 | list = list->next; | |
118 | kfree(tmp); | |
119 | } | |
120 | } | |
121 | ||
6841ec68 YL |
122 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
123 | struct resource_list_x *fail_head) | |
124 | { | |
125 | struct resource_list head; | |
126 | ||
127 | head.next = NULL; | |
128 | __dev_sort_resources(dev, &head); | |
129 | __assign_resources_sorted(&head, fail_head); | |
130 | ||
131 | } | |
132 | ||
133 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
134 | struct resource_list_x *fail_head) | |
135 | { | |
136 | struct pci_dev *dev; | |
137 | struct resource_list head; | |
138 | ||
139 | head.next = NULL; | |
140 | list_for_each_entry(dev, &bus->devices, bus_list) | |
141 | __dev_sort_resources(dev, &head); | |
142 | ||
143 | __assign_resources_sorted(&head, fail_head); | |
144 | } | |
145 | ||
b3743fa4 | 146 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
147 | { |
148 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 149 | struct resource *res; |
1da177e4 LT |
150 | struct pci_bus_region region; |
151 | ||
865df576 BH |
152 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
153 | bus->secondary, bus->subordinate); | |
1da177e4 | 154 | |
c7dabef8 BH |
155 | res = bus->resource[0]; |
156 | pcibios_resource_to_bus(bridge, ®ion, res); | |
157 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
158 | /* |
159 | * The IO resource is allocated a range twice as large as it | |
160 | * would normally need. This allows us to set both IO regs. | |
161 | */ | |
c7dabef8 | 162 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
163 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
164 | region.start); | |
165 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
166 | region.end); | |
167 | } | |
168 | ||
c7dabef8 BH |
169 | res = bus->resource[1]; |
170 | pcibios_resource_to_bus(bridge, ®ion, res); | |
171 | if (res->flags & IORESOURCE_IO) { | |
172 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
173 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
174 | region.start); | |
175 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
176 | region.end); | |
177 | } | |
178 | ||
c7dabef8 BH |
179 | res = bus->resource[2]; |
180 | pcibios_resource_to_bus(bridge, ®ion, res); | |
181 | if (res->flags & IORESOURCE_MEM) { | |
182 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
183 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
184 | region.start); | |
185 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
186 | region.end); | |
187 | } | |
188 | ||
c7dabef8 BH |
189 | res = bus->resource[3]; |
190 | pcibios_resource_to_bus(bridge, ®ion, res); | |
191 | if (res->flags & IORESOURCE_MEM) { | |
192 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
193 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
194 | region.start); | |
195 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
196 | region.end); | |
197 | } | |
198 | } | |
b3743fa4 | 199 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
200 | |
201 | /* Initialize bridges with base/limit values we have collected. | |
202 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
203 | requires that if there is no I/O ports or memory behind the | |
204 | bridge, corresponding range must be turned off by writing base | |
205 | value greater than limit to the bridge's base/limit registers. | |
206 | ||
207 | Note: care must be taken when updating I/O base/limit registers | |
208 | of bridges which support 32-bit I/O. This update requires two | |
209 | config space writes, so it's quite possible that an I/O window of | |
210 | the bridge will have some undesirable address (e.g. 0) after the | |
211 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 212 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
213 | { |
214 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 215 | struct resource *res; |
1da177e4 | 216 | struct pci_bus_region region; |
7cc5997d | 217 | u32 l, io_upper16; |
1da177e4 LT |
218 | |
219 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
220 | res = bus->resource[0]; |
221 | pcibios_resource_to_bus(bridge, ®ion, res); | |
222 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
223 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
224 | l &= 0xffff0000; | |
225 | l |= (region.start >> 8) & 0x00f0; | |
226 | l |= region.end & 0xf000; | |
227 | /* Set up upper 16 bits of I/O base/limit. */ | |
228 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 229 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 230 | } else { |
1da177e4 LT |
231 | /* Clear upper 16 bits of I/O base/limit. */ |
232 | io_upper16 = 0; | |
233 | l = 0x00f0; | |
c7dabef8 | 234 | dev_info(&bridge->dev, " bridge window [io disabled]\n"); |
1da177e4 LT |
235 | } |
236 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
237 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
238 | /* Update lower 16 bits of I/O base/limit. */ | |
239 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
240 | /* Update upper 16 bits of I/O base/limit. */ | |
241 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
242 | } |
243 | ||
244 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
245 | { | |
246 | struct pci_dev *bridge = bus->self; | |
247 | struct resource *res; | |
248 | struct pci_bus_region region; | |
249 | u32 l; | |
1da177e4 | 250 | |
7cc5997d | 251 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
252 | res = bus->resource[1]; |
253 | pcibios_resource_to_bus(bridge, ®ion, res); | |
254 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
255 | l = (region.start >> 16) & 0xfff0; |
256 | l |= region.end & 0xfff00000; | |
c7dabef8 | 257 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 258 | } else { |
1da177e4 | 259 | l = 0x0000fff0; |
c7dabef8 | 260 | dev_info(&bridge->dev, " bridge window [mem disabled]\n"); |
1da177e4 LT |
261 | } |
262 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
263 | } |
264 | ||
265 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
266 | { | |
267 | struct pci_dev *bridge = bus->self; | |
268 | struct resource *res; | |
269 | struct pci_bus_region region; | |
270 | u32 l, bu, lu; | |
1da177e4 LT |
271 | |
272 | /* Clear out the upper 32 bits of PREF limit. | |
273 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
274 | disables PREF range, which is ok. */ | |
275 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
276 | ||
277 | /* Set up PREF base/limit. */ | |
c40a22e0 | 278 | bu = lu = 0; |
c7dabef8 BH |
279 | res = bus->resource[2]; |
280 | pcibios_resource_to_bus(bridge, ®ion, res); | |
281 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
282 | l = (region.start >> 16) & 0xfff0; |
283 | l |= region.end & 0xfff00000; | |
c7dabef8 | 284 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
285 | bu = upper_32_bits(region.start); |
286 | lu = upper_32_bits(region.end); | |
1f82de10 | 287 | } |
c7dabef8 | 288 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 289 | } else { |
1da177e4 | 290 | l = 0x0000fff0; |
c7dabef8 | 291 | dev_info(&bridge->dev, " bridge window [mem pref disabled]\n"); |
1da177e4 LT |
292 | } |
293 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
294 | ||
59353ea3 AW |
295 | /* Set the upper 32 bits of PREF base & limit. */ |
296 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
297 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
298 | } |
299 | ||
300 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
301 | { | |
302 | struct pci_dev *bridge = bus->self; | |
303 | ||
7cc5997d YL |
304 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
305 | bus->secondary, bus->subordinate); | |
306 | ||
307 | if (type & IORESOURCE_IO) | |
308 | pci_setup_bridge_io(bus); | |
309 | ||
310 | if (type & IORESOURCE_MEM) | |
311 | pci_setup_bridge_mmio(bus); | |
312 | ||
313 | if (type & IORESOURCE_PREFETCH) | |
314 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
315 | |
316 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
317 | } | |
318 | ||
7cc5997d YL |
319 | static void pci_setup_bridge(struct pci_bus *bus) |
320 | { | |
321 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
322 | IORESOURCE_PREFETCH; | |
323 | ||
324 | __pci_setup_bridge(bus, type); | |
325 | } | |
326 | ||
1da177e4 LT |
327 | /* Check whether the bridge supports optional I/O and |
328 | prefetchable memory ranges. If not, the respective | |
329 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 330 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
331 | { |
332 | u16 io; | |
333 | u32 pmem; | |
334 | struct pci_dev *bridge = bus->self; | |
335 | struct resource *b_res; | |
336 | ||
337 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
338 | b_res[1].flags |= IORESOURCE_MEM; | |
339 | ||
340 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
341 | if (!io) { | |
342 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
343 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
344 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
345 | } | |
346 | if (io) | |
347 | b_res[0].flags |= IORESOURCE_IO; | |
348 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
349 | disconnect boundary by one PCI data phase. | |
350 | Workaround: do not use prefetching on this device. */ | |
351 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
352 | return; | |
353 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
354 | if (!pmem) { | |
355 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
356 | 0xfff0fff0); | |
357 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
358 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
359 | } | |
1f82de10 | 360 | if (pmem) { |
1da177e4 | 361 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
362 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
363 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 364 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
365 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
366 | } | |
1f82de10 YL |
367 | } |
368 | ||
369 | /* double check if bridge does support 64 bit pref */ | |
370 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
371 | u32 mem_base_hi, tmp; | |
372 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
373 | &mem_base_hi); | |
374 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
375 | 0xffffffff); | |
376 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
377 | if (!tmp) | |
378 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
379 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
380 | mem_base_hi); | |
381 | } | |
1da177e4 LT |
382 | } |
383 | ||
384 | /* Helper function for sizing routines: find first available | |
385 | bus resource of a given type. Note: we intentionally skip | |
386 | the bus resources which have already been assigned (that is, | |
387 | have non-NULL parent resource). */ | |
96bde06a | 388 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
389 | { |
390 | int i; | |
391 | struct resource *r; | |
392 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
393 | IORESOURCE_PREFETCH; | |
394 | ||
89a74ecc | 395 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
396 | if (r == &ioport_resource || r == &iomem_resource) |
397 | continue; | |
55a10984 JB |
398 | if (r && (r->flags & type_mask) == type && !r->parent) |
399 | return r; | |
1da177e4 LT |
400 | } |
401 | return NULL; | |
402 | } | |
403 | ||
13583b16 RP |
404 | static resource_size_t calculate_iosize(resource_size_t size, |
405 | resource_size_t min_size, | |
406 | resource_size_t size1, | |
407 | resource_size_t old_size, | |
408 | resource_size_t align) | |
409 | { | |
410 | if (size < min_size) | |
411 | size = min_size; | |
412 | if (old_size == 1 ) | |
413 | old_size = 0; | |
414 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
415 | flag in the struct pci_bus. */ | |
416 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
417 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
418 | #endif | |
419 | size = ALIGN(size + size1, align); | |
420 | if (size < old_size) | |
421 | size = old_size; | |
422 | return size; | |
423 | } | |
424 | ||
425 | static resource_size_t calculate_memsize(resource_size_t size, | |
426 | resource_size_t min_size, | |
427 | resource_size_t size1, | |
428 | resource_size_t old_size, | |
429 | resource_size_t align) | |
430 | { | |
431 | if (size < min_size) | |
432 | size = min_size; | |
433 | if (old_size == 1 ) | |
434 | old_size = 0; | |
435 | if (size < old_size) | |
436 | size = old_size; | |
437 | size = ALIGN(size + size1, align); | |
438 | return size; | |
439 | } | |
440 | ||
1da177e4 LT |
441 | /* Sizing the IO windows of the PCI-PCI bridge is trivial, |
442 | since these windows have 4K granularity and the IO ranges | |
443 | of non-bridge PCI devices are limited to 256 bytes. | |
444 | We must be careful with the ISA aliasing though. */ | |
28760489 | 445 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size) |
1da177e4 LT |
446 | { |
447 | struct pci_dev *dev; | |
448 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
13583b16 | 449 | unsigned long size = 0, size1 = 0; |
1da177e4 LT |
450 | |
451 | if (!b_res) | |
452 | return; | |
453 | ||
454 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
455 | int i; | |
456 | ||
457 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
458 | struct resource *r = &dev->resource[i]; | |
459 | unsigned long r_size; | |
460 | ||
461 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
462 | continue; | |
022edd86 | 463 | r_size = resource_size(r); |
1da177e4 LT |
464 | |
465 | if (r_size < 0x400) | |
466 | /* Might be re-aligned for ISA */ | |
467 | size += r_size; | |
468 | else | |
469 | size1 += r_size; | |
470 | } | |
471 | } | |
13583b16 RP |
472 | size = calculate_iosize(size, min_size, size1, |
473 | resource_size(b_res), 4096); | |
1da177e4 | 474 | if (!size) { |
865df576 BH |
475 | if (b_res->start || b_res->end) |
476 | dev_info(&bus->self->dev, "disabling bridge window " | |
477 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
478 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
479 | b_res->flags = 0; |
480 | return; | |
481 | } | |
482 | /* Alignment of the IO window is always 4K */ | |
483 | b_res->start = 4096; | |
484 | b_res->end = b_res->start + size - 1; | |
88452565 | 485 | b_res->flags |= IORESOURCE_STARTALIGN; |
1da177e4 LT |
486 | } |
487 | ||
488 | /* Calculate the size of the bus and minimal alignment which | |
489 | guarantees that all child resources fit in this size. */ | |
28760489 EB |
490 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
491 | unsigned long type, resource_size_t min_size) | |
1da177e4 LT |
492 | { |
493 | struct pci_dev *dev; | |
13583b16 | 494 | resource_size_t min_align, align, size; |
c40a22e0 | 495 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
496 | int order, max_order; |
497 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 498 | unsigned int mem64_mask = 0; |
1da177e4 LT |
499 | |
500 | if (!b_res) | |
501 | return 0; | |
502 | ||
503 | memset(aligns, 0, sizeof(aligns)); | |
504 | max_order = 0; | |
505 | size = 0; | |
506 | ||
1f82de10 YL |
507 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
508 | b_res->flags &= ~IORESOURCE_MEM_64; | |
509 | ||
1da177e4 LT |
510 | list_for_each_entry(dev, &bus->devices, bus_list) { |
511 | int i; | |
1f82de10 | 512 | |
1da177e4 LT |
513 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
514 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 515 | resource_size_t r_size; |
1da177e4 LT |
516 | |
517 | if (r->parent || (r->flags & mask) != type) | |
518 | continue; | |
022edd86 | 519 | r_size = resource_size(r); |
1da177e4 | 520 | /* For bridges size != alignment */ |
6faf17f6 | 521 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
522 | order = __ffs(align) - 20; |
523 | if (order > 11) { | |
865df576 BH |
524 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
525 | "(bad alignment %#llx)\n", i, r, | |
526 | (unsigned long long) align); | |
1da177e4 LT |
527 | r->flags = 0; |
528 | continue; | |
529 | } | |
530 | size += r_size; | |
531 | if (order < 0) | |
532 | order = 0; | |
533 | /* Exclude ranges with size > align from | |
534 | calculation of the alignment. */ | |
535 | if (r_size == align) | |
536 | aligns[order] += align; | |
537 | if (order > max_order) | |
538 | max_order = order; | |
1f82de10 | 539 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
1da177e4 LT |
540 | } |
541 | } | |
1da177e4 LT |
542 | align = 0; |
543 | min_align = 0; | |
544 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
545 | resource_size_t align1 = 1; |
546 | ||
547 | align1 <<= (order + 20); | |
548 | ||
1da177e4 LT |
549 | if (!align) |
550 | min_align = align1; | |
6f6f8c2f | 551 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
552 | min_align = align1 >> 1; |
553 | align += aligns[order]; | |
554 | } | |
13583b16 | 555 | size = calculate_memsize(size, min_size, 0, resource_size(b_res), align); |
1da177e4 | 556 | if (!size) { |
865df576 BH |
557 | if (b_res->start || b_res->end) |
558 | dev_info(&bus->self->dev, "disabling bridge window " | |
559 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
560 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
561 | b_res->flags = 0; |
562 | return 1; | |
563 | } | |
564 | b_res->start = min_align; | |
565 | b_res->end = size + min_align - 1; | |
88452565 | 566 | b_res->flags |= IORESOURCE_STARTALIGN; |
1f82de10 | 567 | b_res->flags |= mem64_mask; |
1da177e4 LT |
568 | return 1; |
569 | } | |
570 | ||
5468ae61 | 571 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
1da177e4 LT |
572 | { |
573 | struct pci_dev *bridge = bus->self; | |
574 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
575 | u16 ctrl; | |
576 | ||
577 | /* | |
578 | * Reserve some resources for CardBus. We reserve | |
579 | * a fixed amount of bus space for CardBus bridges. | |
580 | */ | |
934b7024 LT |
581 | b_res[0].start = 0; |
582 | b_res[0].end = pci_cardbus_io_size - 1; | |
583 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 | 584 | |
934b7024 LT |
585 | b_res[1].start = 0; |
586 | b_res[1].end = pci_cardbus_io_size - 1; | |
587 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
588 | |
589 | /* | |
590 | * Check whether prefetchable memory is supported | |
591 | * by this bridge. | |
592 | */ | |
593 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
594 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
595 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
596 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
597 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
598 | } | |
599 | ||
600 | /* | |
601 | * If we have prefetchable memory support, allocate | |
602 | * two regions. Otherwise, allocate one region of | |
603 | * twice the size. | |
604 | */ | |
605 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 LT |
606 | b_res[2].start = 0; |
607 | b_res[2].end = pci_cardbus_mem_size - 1; | |
608 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; | |
1da177e4 | 609 | |
934b7024 LT |
610 | b_res[3].start = 0; |
611 | b_res[3].end = pci_cardbus_mem_size - 1; | |
612 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 | 613 | } else { |
934b7024 LT |
614 | b_res[3].start = 0; |
615 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; | |
616 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
617 | } |
618 | } | |
619 | ||
451124a7 | 620 | void __ref pci_bus_size_bridges(struct pci_bus *bus) |
1da177e4 LT |
621 | { |
622 | struct pci_dev *dev; | |
623 | unsigned long mask, prefmask; | |
28760489 | 624 | resource_size_t min_mem_size = 0, min_io_size = 0; |
1da177e4 LT |
625 | |
626 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
627 | struct pci_bus *b = dev->subordinate; | |
628 | if (!b) | |
629 | continue; | |
630 | ||
631 | switch (dev->class >> 8) { | |
632 | case PCI_CLASS_BRIDGE_CARDBUS: | |
633 | pci_bus_size_cardbus(b); | |
634 | break; | |
635 | ||
636 | case PCI_CLASS_BRIDGE_PCI: | |
637 | default: | |
638 | pci_bus_size_bridges(b); | |
639 | break; | |
640 | } | |
641 | } | |
642 | ||
643 | /* The root bus? */ | |
644 | if (!bus->self) | |
645 | return; | |
646 | ||
647 | switch (bus->self->class >> 8) { | |
648 | case PCI_CLASS_BRIDGE_CARDBUS: | |
649 | /* don't size cardbuses yet. */ | |
650 | break; | |
651 | ||
652 | case PCI_CLASS_BRIDGE_PCI: | |
653 | pci_bridge_check_ranges(bus); | |
28760489 EB |
654 | if (bus->self->is_hotplug_bridge) { |
655 | min_io_size = pci_hotplug_io_size; | |
656 | min_mem_size = pci_hotplug_mem_size; | |
657 | } | |
1da177e4 | 658 | default: |
28760489 | 659 | pbus_size_io(bus, min_io_size); |
1da177e4 LT |
660 | /* If the bridge supports prefetchable range, size it |
661 | separately. If it doesn't, or its prefetchable window | |
662 | has already been allocated by arch code, try | |
663 | non-prefetchable range for both types of PCI memory | |
664 | resources. */ | |
665 | mask = IORESOURCE_MEM; | |
666 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
28760489 | 667 | if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size)) |
1da177e4 | 668 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 EB |
669 | else |
670 | min_mem_size += min_mem_size; | |
671 | pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size); | |
1da177e4 LT |
672 | break; |
673 | } | |
674 | } | |
675 | EXPORT_SYMBOL(pci_bus_size_bridges); | |
676 | ||
568ddef8 YL |
677 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
678 | struct resource_list_x *fail_head) | |
1da177e4 LT |
679 | { |
680 | struct pci_bus *b; | |
681 | struct pci_dev *dev; | |
682 | ||
568ddef8 | 683 | pbus_assign_resources_sorted(bus, fail_head); |
1da177e4 | 684 | |
1da177e4 LT |
685 | list_for_each_entry(dev, &bus->devices, bus_list) { |
686 | b = dev->subordinate; | |
687 | if (!b) | |
688 | continue; | |
689 | ||
568ddef8 | 690 | __pci_bus_assign_resources(b, fail_head); |
1da177e4 LT |
691 | |
692 | switch (dev->class >> 8) { | |
693 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
694 | if (!pci_is_enabled(dev)) |
695 | pci_setup_bridge(b); | |
1da177e4 LT |
696 | break; |
697 | ||
698 | case PCI_CLASS_BRIDGE_CARDBUS: | |
699 | pci_setup_cardbus(b); | |
700 | break; | |
701 | ||
702 | default: | |
80ccba11 BH |
703 | dev_info(&dev->dev, "not setting up bridge for bus " |
704 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
705 | break; |
706 | } | |
707 | } | |
708 | } | |
568ddef8 YL |
709 | |
710 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
711 | { | |
712 | __pci_bus_assign_resources(bus, NULL); | |
713 | } | |
1da177e4 LT |
714 | EXPORT_SYMBOL(pci_bus_assign_resources); |
715 | ||
6841ec68 YL |
716 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
717 | struct resource_list_x *fail_head) | |
718 | { | |
719 | struct pci_bus *b; | |
720 | ||
721 | pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head); | |
722 | ||
723 | b = bridge->subordinate; | |
724 | if (!b) | |
725 | return; | |
726 | ||
727 | __pci_bus_assign_resources(b, fail_head); | |
728 | ||
729 | switch (bridge->class >> 8) { | |
730 | case PCI_CLASS_BRIDGE_PCI: | |
731 | pci_setup_bridge(b); | |
732 | break; | |
733 | ||
734 | case PCI_CLASS_BRIDGE_CARDBUS: | |
735 | pci_setup_cardbus(b); | |
736 | break; | |
737 | ||
738 | default: | |
739 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
740 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
741 | break; | |
742 | } | |
743 | } | |
5009b460 YL |
744 | static void pci_bridge_release_resources(struct pci_bus *bus, |
745 | unsigned long type) | |
746 | { | |
747 | int idx; | |
748 | bool changed = false; | |
749 | struct pci_dev *dev; | |
750 | struct resource *r; | |
751 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
752 | IORESOURCE_PREFETCH; | |
753 | ||
754 | dev = bus->self; | |
755 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
756 | idx++) { | |
757 | r = &dev->resource[idx]; | |
758 | if ((r->flags & type_mask) != type) | |
759 | continue; | |
760 | if (!r->parent) | |
761 | continue; | |
762 | /* | |
763 | * if there are children under that, we should release them | |
764 | * all | |
765 | */ | |
766 | release_child_resources(r); | |
767 | if (!release_resource(r)) { | |
768 | dev_printk(KERN_DEBUG, &dev->dev, | |
769 | "resource %d %pR released\n", idx, r); | |
770 | /* keep the old size */ | |
771 | r->end = resource_size(r) - 1; | |
772 | r->start = 0; | |
773 | r->flags = 0; | |
774 | changed = true; | |
775 | } | |
776 | } | |
777 | ||
778 | if (changed) { | |
779 | /* avoiding touch the one without PREF */ | |
780 | if (type & IORESOURCE_PREFETCH) | |
781 | type = IORESOURCE_PREFETCH; | |
782 | __pci_setup_bridge(bus, type); | |
783 | } | |
784 | } | |
785 | ||
786 | enum release_type { | |
787 | leaf_only, | |
788 | whole_subtree, | |
789 | }; | |
790 | /* | |
791 | * try to release pci bridge resources that is from leaf bridge, | |
792 | * so we can allocate big new one later | |
793 | */ | |
794 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
795 | unsigned long type, | |
796 | enum release_type rel_type) | |
797 | { | |
798 | struct pci_dev *dev; | |
799 | bool is_leaf_bridge = true; | |
800 | ||
801 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
802 | struct pci_bus *b = dev->subordinate; | |
803 | if (!b) | |
804 | continue; | |
805 | ||
806 | is_leaf_bridge = false; | |
807 | ||
808 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
809 | continue; | |
810 | ||
811 | if (rel_type == whole_subtree) | |
812 | pci_bus_release_bridge_resources(b, type, | |
813 | whole_subtree); | |
814 | } | |
815 | ||
816 | if (pci_is_root_bus(bus)) | |
817 | return; | |
818 | ||
819 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
820 | return; | |
821 | ||
822 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
823 | pci_bridge_release_resources(bus, type); | |
824 | } | |
825 | ||
76fbc263 YL |
826 | static void pci_bus_dump_res(struct pci_bus *bus) |
827 | { | |
89a74ecc BH |
828 | struct resource *res; |
829 | int i; | |
7c9342b8 | 830 | |
89a74ecc | 831 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 832 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
833 | continue; |
834 | ||
c7dabef8 | 835 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
836 | } |
837 | } | |
838 | ||
839 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
840 | { | |
841 | struct pci_bus *b; | |
842 | struct pci_dev *dev; | |
843 | ||
844 | ||
845 | pci_bus_dump_res(bus); | |
846 | ||
847 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
848 | b = dev->subordinate; | |
849 | if (!b) | |
850 | continue; | |
851 | ||
852 | pci_bus_dump_resources(b); | |
853 | } | |
854 | } | |
855 | ||
1da177e4 LT |
856 | void __init |
857 | pci_assign_unassigned_resources(void) | |
858 | { | |
859 | struct pci_bus *bus; | |
977d17bb | 860 | |
1da177e4 LT |
861 | /* Depth first, calculate sizes and alignments of all |
862 | subordinate buses. */ | |
863 | list_for_each_entry(bus, &pci_root_buses, node) { | |
864 | pci_bus_size_bridges(bus); | |
865 | } | |
866 | /* Depth last, allocate resources and update the hardware. */ | |
867 | list_for_each_entry(bus, &pci_root_buses, node) { | |
769d9968 | 868 | pci_bus_assign_resources(bus); |
977d17bb | 869 | pci_enable_bridges(bus); |
769d9968 | 870 | } |
76fbc263 YL |
871 | |
872 | /* dump the resource on buses */ | |
873 | list_for_each_entry(bus, &pci_root_buses, node) { | |
874 | pci_bus_dump_resources(bus); | |
875 | } | |
1da177e4 | 876 | } |
6841ec68 YL |
877 | |
878 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
879 | { | |
880 | struct pci_bus *parent = bridge->subordinate; | |
32180e40 YL |
881 | int tried_times = 0; |
882 | struct resource_list_x head, *list; | |
6841ec68 | 883 | int retval; |
32180e40 YL |
884 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
885 | IORESOURCE_PREFETCH; | |
886 | ||
887 | head.next = NULL; | |
6841ec68 | 888 | |
32180e40 | 889 | again: |
6841ec68 | 890 | pci_bus_size_bridges(parent); |
32180e40 | 891 | __pci_bridge_assign_resources(bridge, &head); |
32180e40 YL |
892 | |
893 | tried_times++; | |
894 | ||
895 | if (!head.next) | |
3f579c34 | 896 | goto enable_all; |
32180e40 YL |
897 | |
898 | if (tried_times >= 2) { | |
899 | /* still fail, don't need to try more */ | |
094732a5 | 900 | free_list(resource_list_x, &head); |
3f579c34 | 901 | goto enable_all; |
32180e40 YL |
902 | } |
903 | ||
904 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
905 | tried_times + 1); | |
906 | ||
907 | /* | |
908 | * Try to release leaf bridge's resources that doesn't fit resource of | |
909 | * child device under that bridge | |
910 | */ | |
911 | for (list = head.next; list;) { | |
912 | struct pci_bus *bus = list->dev->bus; | |
913 | unsigned long flags = list->flags; | |
914 | ||
915 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
916 | whole_subtree); | |
917 | list = list->next; | |
918 | } | |
919 | /* restore size and flags */ | |
920 | for (list = head.next; list;) { | |
921 | struct resource *res = list->res; | |
922 | ||
923 | res->start = list->start; | |
924 | res->end = list->end; | |
925 | res->flags = list->flags; | |
926 | if (list->dev->subordinate) | |
927 | res->flags = 0; | |
928 | ||
929 | list = list->next; | |
930 | } | |
094732a5 | 931 | free_list(resource_list_x, &head); |
32180e40 YL |
932 | |
933 | goto again; | |
3f579c34 YL |
934 | |
935 | enable_all: | |
936 | retval = pci_reenable_device(bridge); | |
937 | pci_set_master(bridge); | |
938 | pci_enable_bridges(parent); | |
6841ec68 YL |
939 | } |
940 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); |