[deliverable/linux.git] / drivers / pci / setup-bus.c

/*
 *	drivers/pci/setup-bus.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     PCI-PCI bridges cleanup, sorted resource allocation.
 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Converted to allocation in 3 passes, which gives
 *	     tighter packing. Prefetchable range support.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>


#define DEBUG_CONFIG 1
#if DEBUG_CONFIG
#define DBG(x...)     printk(x)
#else
#define DBG(x...)
#endif

static void pbus_assign_resources_sorted(struct pci_bus *bus)
{
	struct pci_dev *dev;
	struct resource *res;
	struct resource_list head, *list, *tmp;
	int idx;

	head.next = NULL;
	list_for_each_entry(dev, &bus->devices, bus_list) {
		u16 class = dev->class >> 8;

		/* Don't touch classless devices or host bridges or ioapics.  */
		if (class == PCI_CLASS_NOT_DEFINED ||
		    class == PCI_CLASS_BRIDGE_HOST)
			continue;

		/* Don't touch ioapic devices already enabled by firmware */
		if (class == PCI_CLASS_SYSTEM_PIC) {
			u16 command;
			pci_read_config_word(dev, PCI_COMMAND, &command);
			if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
				continue;
		}

		pdev_sort_resources(dev, &head);
	}

	for (list = head.next; list;) {
		res = list->res;
		idx = res - &list->dev->resource[0];
		if (pci_assign_resource(list->dev, idx)) {
			res->start = 0;
			res->end = 0;
			res->flags = 0;
		}
		tmp = list;
		list = list->next;
		kfree(tmp);
	}
}

void pci_setup_cardbus(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct pci_bus_region region;

	printk("PCI: Bus %d, cardbus bridge: %s\n",
		bus->number, pci_name(bridge));

	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	if (bus->resource[0]->flags & IORESOURCE_IO) {
		/*
		 * The IO resource is allocated a range twice as large as it
		 * would normally need.  This allows us to set both IO regs.
		 */
		printk(KERN_INFO "  IO window: 0x%08lx-0x%08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	if (bus->resource[1]->flags & IORESOURCE_IO) {
		printk(KERN_INFO "  IO window: 0x%08lx-0x%08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	if (bus->resource[2]->flags & IORESOURCE_MEM) {
		printk(KERN_INFO "  PREFETCH window: 0x%08lx-0x%08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
					region.end);
	}

	pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
	if (bus->resource[3]->flags & IORESOURCE_MEM) {
		printk(KERN_INFO "  MEM window: 0x%08lx-0x%08lx\n",
		       (unsigned long)region.start,
		       (unsigned long)region.end);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
					region.start);
		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
					region.end);
	}
}
EXPORT_SYMBOL(pci_setup_cardbus);

/* Initialize bridges with base/limit values we have collected.
   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
   requires that if there is no I/O ports or memory behind the
   bridge, corresponding range must be turned off by writing base
   value greater than limit to the bridge's base/limit registers.

   Note: care must be taken when updating I/O base/limit registers
   of bridges which support 32-bit I/O. This update requires two
   config space writes, so it's quite possible that an I/O window of
   the bridge will have some undesirable address (e.g. 0) after the
   first write. Ditto 64-bit prefetchable MMIO.  */
static void __devinit
pci_setup_bridge(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct pci_bus_region region;
	u32 l, bu, lu, io_upper16;

	DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));

	/* Set up the top and bottom of the PCI I/O segment for this bus. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	if (bus->resource[0]->flags & IORESOURCE_IO) {
		pci_read_config_dword(bridge, PCI_IO_BASE, &l);
		l &= 0xffff0000;
		l |= (region.start >> 8) & 0x00f0;
		l |= region.end & 0xf000;
		/* Set up upper 16 bits of I/O base/limit. */
		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
		DBG(KERN_INFO "  IO window: %04lx-%04lx\n",
		    (unsigned long)region.start,
		    (unsigned long)region.end);
	}
	else {
		/* Clear upper 16 bits of I/O base/limit. */
		io_upper16 = 0;
		l = 0x00f0;
		DBG(KERN_INFO "  IO window: disabled.\n");
	}
	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	/* Update lower 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE, l);
	/* Update upper 16 bits of I/O base/limit. */
	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);

	/* Set up the top and bottom of the PCI Memory segment
	   for this bus. */
	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	if (bus->resource[1]->flags & IORESOURCE_MEM) {
		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
		DBG(KERN_INFO "  MEM window: 0x%08lx-0x%08lx\n",
		    (unsigned long)region.start,
		    (unsigned long)region.end);
	}
	else {
		l = 0x0000fff0;
		DBG(KERN_INFO "  MEM window: disabled.\n");
	}
	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);

	/* Clear out the upper 32 bits of PREF limit.
	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	   disables PREF range, which is ok. */
	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);

	/* Set up PREF base/limit. */
	bu = lu = 0;
	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
		l = (region.start >> 16) & 0xfff0;
		l |= region.end & 0xfff00000;
		bu = upper_32_bits(region.start);
		lu = upper_32_bits(region.end);
		DBG(KERN_INFO "  PREFETCH window: 0x%016llx-0x%016llx\n",
		    (unsigned long long)region.start,
		    (unsigned long long)region.end);
	}
	else {
		l = 0x0000fff0;
		DBG(KERN_INFO "  PREFETCH window: disabled.\n");
	}
	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);

	/* Set the upper 32 bits of PREF base & limit. */
	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);

	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
}

/* Check whether the bridge supports optional I/O and
   prefetchable memory ranges. If not, the respective
   base/limit registers must be read-only and read as 0. */
static void pci_bridge_check_ranges(struct pci_bus *bus)
{
	u16 io;
	u32 pmem;
	struct pci_dev *bridge = bus->self;
	struct resource *b_res;

	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	b_res[1].flags |= IORESOURCE_MEM;

	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	if (!io) {
		pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
		pci_read_config_word(bridge, PCI_IO_BASE, &io);
 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 	}
 	if (io)
		b_res[0].flags |= IORESOURCE_IO;
	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
	    disconnect boundary by one PCI data phase.
	    Workaround: do not use prefetching on this device. */
	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
		return;
	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	if (!pmem) {
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
					       0xfff0fff0);
		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	}
	if (pmem)
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
}

/* Helper function for sizing routines: find first available
   bus resource of a given type. Note: we intentionally skip
   the bus resources which have already been assigned (that is,
   have non-NULL parent resource). */
static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
{
	int i;
	struct resource *r;
	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
				  IORESOURCE_PREFETCH;

	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
		r = bus->resource[i];
		if (r == &ioport_resource || r == &iomem_resource)
			continue;
		if (r && (r->flags & type_mask) == type && !r->parent)
			return r;
	}
	return NULL;
}

/* Sizing the IO windows of the PCI-PCI bridge is trivial,
   since these windows have 4K granularity and the IO ranges
   of non-bridge PCI devices are limited to 256 bytes.
   We must be careful with the ISA aliasing though. */
static void pbus_size_io(struct pci_bus *bus)
{
	struct pci_dev *dev;
	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
	unsigned long size = 0, size1 = 0;

	if (!b_res)
 		return;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;

		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			unsigned long r_size;

			if (r->parent || !(r->flags & IORESOURCE_IO))
				continue;
			r_size = r->end - r->start + 1;

			if (r_size < 0x400)
				/* Might be re-aligned for ISA */
				size += r_size;
			else
				size1 += r_size;
		}
	}
/* To be fixed in 2.5: we should have sort of HAVE_ISA
   flag in the struct pci_bus. */
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
	size = (size & 0xff) + ((size & ~0xffUL) << 2);
#endif
	size = ALIGN(size + size1, 4096);
	if (!size) {
		b_res->flags = 0;
		return;
	}
	/* Alignment of the IO window is always 4K */
	b_res->start = 4096;
	b_res->end = b_res->start + size - 1;
}

/* Calculate the size of the bus and minimal alignment which
   guarantees that all child resources fit in this size. */
static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
{
	struct pci_dev *dev;
	resource_size_t min_align, align, size;
	resource_size_t aligns[12];	/* Alignments from 1Mb to 2Gb */
	int order, max_order;
	struct resource *b_res = find_free_bus_resource(bus, type);

	if (!b_res)
		return 0;

	memset(aligns, 0, sizeof(aligns));
	max_order = 0;
	size = 0;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		int i;
		
		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
			struct resource *r = &dev->resource[i];
			resource_size_t r_size;

			if (r->parent || (r->flags & mask) != type)
				continue;
			r_size = r->end - r->start + 1;
			/* For bridges size != alignment */
			align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
			order = __ffs(align) - 20;
			if (order > 11) {
				printk(KERN_WARNING "PCI: region %s/%d "
				       "too large: 0x%016llx-0x%016llx\n",
					pci_name(dev), i,
				       (unsigned long long)r->start,
				       (unsigned long long)r->end);
				r->flags = 0;
				continue;
			}
			size += r_size;
			if (order < 0)
				order = 0;
			/* Exclude ranges with size > align from
			   calculation of the alignment. */
			if (r_size == align)
				aligns[order] += align;
			if (order > max_order)
				max_order = order;
		}
	}

	align = 0;
	min_align = 0;
	for (order = 0; order <= max_order; order++) {
#ifdef CONFIG_RESOURCES_64BIT
		resource_size_t align1 = 1ULL << (order + 20);
#else
		resource_size_t align1 = 1U << (order + 20);
#endif
		if (!align)
			min_align = align1;
		else if (ALIGN(align + min_align, min_align) < align1)
			min_align = align1 >> 1;
		align += aligns[order];
	}
	size = ALIGN(size, min_align);
	if (!size) {
		b_res->flags = 0;
		return 1;
	}
	b_res->start = min_align;
	b_res->end = size + min_align - 1;
	return 1;
}

static void __devinit
pci_bus_size_cardbus(struct pci_bus *bus)
{
	struct pci_dev *bridge = bus->self;
	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	u16 ctrl;

	/*
	 * Reserve some resources for CardBus.  We reserve
	 * a fixed amount of bus space for CardBus bridges.
	 */
	b_res[0].start = pci_cardbus_io_size;
	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
	b_res[0].flags |= IORESOURCE_IO;

	b_res[1].start = pci_cardbus_io_size;
	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
	b_res[1].flags |= IORESOURCE_IO;

	/*
	 * Check whether prefetchable memory is supported
	 * by this bridge.
	 */
	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	}

	/*
	 * If we have prefetchable memory support, allocate
	 * two regions.  Otherwise, allocate one region of
	 * twice the size.
	 */
	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
		b_res[2].start = pci_cardbus_mem_size;
		b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;

		b_res[3].start = pci_cardbus_mem_size;
		b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
		b_res[3].flags |= IORESOURCE_MEM;
	} else {
		b_res[3].start = pci_cardbus_mem_size * 2;
		b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
		b_res[3].flags |= IORESOURCE_MEM;
	}
}

void __ref pci_bus_size_bridges(struct pci_bus *bus)
{
	struct pci_dev *dev;
	unsigned long mask, prefmask;

	list_for_each_entry(dev, &bus->devices, bus_list) {
		struct pci_bus *b = dev->subordinate;
		if (!b)
			continue;

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_bus_size_cardbus(b);
			break;

		case PCI_CLASS_BRIDGE_PCI:
		default:
			pci_bus_size_bridges(b);
			break;
		}
	}

	/* The root bus? */
	if (!bus->self)
		return;

	switch (bus->self->class >> 8) {
	case PCI_CLASS_BRIDGE_CARDBUS:
		/* don't size cardbuses yet. */
		break;

	case PCI_CLASS_BRIDGE_PCI:
		/* don't size subtractive decoding (transparent)
		 * PCI-to-PCI bridges */
		if (bus->self->transparent)
			break;
		pci_bridge_check_ranges(bus);
		/* fall through */
	default:
		pbus_size_io(bus);
		/* If the bridge supports prefetchable range, size it
		   separately. If it doesn't, or its prefetchable window
		   has already been allocated by arch code, try
		   non-prefetchable range for both types of PCI memory
		   resources. */
		mask = IORESOURCE_MEM;
		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
		if (pbus_size_mem(bus, prefmask, prefmask))
			mask = prefmask; /* Success, size non-prefetch only. */
		pbus_size_mem(bus, mask, IORESOURCE_MEM);
		break;
	}
}
EXPORT_SYMBOL(pci_bus_size_bridges);

void __ref pci_bus_assign_resources(struct pci_bus *bus)
{
	struct pci_bus *b;
	struct pci_dev *dev;

	pbus_assign_resources_sorted(bus);

	list_for_each_entry(dev, &bus->devices, bus_list) {
		b = dev->subordinate;
		if (!b)
			continue;

		pci_bus_assign_resources(b);

		switch (dev->class >> 8) {
		case PCI_CLASS_BRIDGE_PCI:
			pci_setup_bridge(b);
			break;

		case PCI_CLASS_BRIDGE_CARDBUS:
			pci_setup_cardbus(b);
			break;

		default:
			printk(KERN_INFO "PCI: not setting up bridge %s "
			       "for bus %d\n", pci_name(dev), b->number);
			break;
		}
	}
}
EXPORT_SYMBOL(pci_bus_assign_resources);

void __init
pci_assign_unassigned_resources(void)
{
	struct pci_bus *bus;

	/* Depth first, calculate sizes and alignments of all
	   subordinate buses. */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_size_bridges(bus);
	}
	/* Depth last, allocate resources and update the hardware. */
	list_for_each_entry(bus, &pci_root_buses, node) {
		pci_bus_assign_resources(bus);
		pci_enable_bridges(bus);
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-bus.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/*
	13	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	14	* PCI-PCI bridges cleanup, sorted resource allocation.
	15	* Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Converted to allocation in 3 passes, which gives
	17	* tighter packing. Prefetchable range support.
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
	24	#include <linux/errno.h>
	25	#include <linux/ioport.h>
	26	#include <linux/cache.h>
	27	#include <linux/slab.h>
	28
	29
	30	#define DEBUG_CONFIG 1
	31	#if DEBUG_CONFIG
	32	#define DBG(x...) printk(x)
	33	#else
	34	#define DBG(x...)
	35	#endif
	36
96bde06a	37	static void pbus_assign_resources_sorted(struct pci_bus *bus)
1da177e4 LT	38	{
	39	struct pci_dev *dev;
	40	struct resource *res;
	41	struct resource_list head, list, tmp;
	42	int idx;
	43
1da177e4 LT	44	head.next = NULL;
	45	list_for_each_entry(dev, &bus->devices, bus_list) {
	46	u16 class = dev->class >> 8;
	47
9bded00b	48	/* Don't touch classless devices or host bridges or ioapics. */
1da177e4	49	if (class == PCI_CLASS_NOT_DEFINED \|\|
23186279	50	class == PCI_CLASS_BRIDGE_HOST)
1da177e4 LT	51	continue;
1da177e4 LT	52
9bded00b	53	/* Don't touch ioapic devices already enabled by firmware */
23186279	54	if (class == PCI_CLASS_SYSTEM_PIC) {
9bded00b KK	55	u16 command;
	56	pci_read_config_word(dev, PCI_COMMAND, &command);
	57	if (command & (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY))
23186279 ST	58	continue;
	59	}
	60
1da177e4 LT	61	pdev_sort_resources(dev, &head);
	62	}
	63
	64	for (list = head.next; list;) {
	65	res = list->res;
	66	idx = res - &list->dev->resource[0];
542df5de RS	67	if (pci_assign_resource(list->dev, idx)) {
542df5de RS	68	res->start = 0;
960b8466	69	res->end = 0;
542df5de RS	70	res->flags = 0;
542df5de RS	71	}
1da177e4 LT	72	tmp = list;
	73	list = list->next;
	74	kfree(tmp);
	75	}
	76	}
	77
b3743fa4	78	void pci_setup_cardbus(struct pci_bus *bus)
1da177e4 LT	79	{
	80	struct pci_dev *bridge = bus->self;
	81	struct pci_bus_region region;
	82
	83	printk("PCI: Bus %d, cardbus bridge: %s\n",
	84	bus->number, pci_name(bridge));
	85
	86	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	87	if (bus->resource[0]->flags & IORESOURCE_IO) {
	88	/*
	89	* The IO resource is allocated a range twice as large as it
	90	* would normally need. This allows us to set both IO regs.
	91	*/
c40a22e0 BH	92	printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
	93	(unsigned long)region.start,
	94	(unsigned long)region.end);
1da177e4 LT	95	pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
	96	region.start);
	97	pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
	98	region.end);
	99	}
	100
	101	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	102	if (bus->resource[1]->flags & IORESOURCE_IO) {
c40a22e0 BH	103	printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
	104	(unsigned long)region.start,
	105	(unsigned long)region.end);
1da177e4 LT	106	pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
	107	region.start);
	108	pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
	109	region.end);
	110	}
	111
	112	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	113	if (bus->resource[2]->flags & IORESOURCE_MEM) {
c40a22e0 BH	114	printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n",
	115	(unsigned long)region.start,
	116	(unsigned long)region.end);
1da177e4 LT	117	pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
	118	region.start);
	119	pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
	120	region.end);
	121	}
	122
	123	pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
	124	if (bus->resource[3]->flags & IORESOURCE_MEM) {
c40a22e0 BH	125	printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
	126	(unsigned long)region.start,
	127	(unsigned long)region.end);
1da177e4 LT	128	pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
	129	region.start);
	130	pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
	131	region.end);
	132	}
	133	}
b3743fa4	134	EXPORT_SYMBOL(pci_setup_cardbus);
1da177e4 LT	135
	136	/* Initialize bridges with base/limit values we have collected.
	137	PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
	138	requires that if there is no I/O ports or memory behind the
	139	bridge, corresponding range must be turned off by writing base
	140	value greater than limit to the bridge's base/limit registers.
	141
	142	Note: care must be taken when updating I/O base/limit registers
	143	of bridges which support 32-bit I/O. This update requires two
	144	config space writes, so it's quite possible that an I/O window of
	145	the bridge will have some undesirable address (e.g. 0) after the
	146	first write. Ditto 64-bit prefetchable MMIO. */
	147	static void __devinit
	148	pci_setup_bridge(struct pci_bus *bus)
	149	{
	150	struct pci_dev *bridge = bus->self;
	151	struct pci_bus_region region;
c40a22e0	152	u32 l, bu, lu, io_upper16;
1da177e4 LT	153
	154	DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
	155
	156	/* Set up the top and bottom of the PCI I/O segment for this bus. */
	157	pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
	158	if (bus->resource[0]->flags & IORESOURCE_IO) {
	159	pci_read_config_dword(bridge, PCI_IO_BASE, &l);
	160	l &= 0xffff0000;
	161	l \|= (region.start >> 8) & 0x00f0;
	162	l \|= region.end & 0xf000;
	163	/* Set up upper 16 bits of I/O base/limit. */
	164	io_upper16 = (region.end & 0xffff0000) \| (region.start >> 16);
	165	DBG(KERN_INFO " IO window: %04lx-%04lx\n",
c40a22e0 BH	166	(unsigned long)region.start,
c40a22e0 BH	167	(unsigned long)region.end);
1da177e4 LT	168	}
	169	else {
	170	/* Clear upper 16 bits of I/O base/limit. */
	171	io_upper16 = 0;
	172	l = 0x00f0;
	173	DBG(KERN_INFO " IO window: disabled.\n");
	174	}
	175	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
	176	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
	177	/* Update lower 16 bits of I/O base/limit. */
	178	pci_write_config_dword(bridge, PCI_IO_BASE, l);
	179	/* Update upper 16 bits of I/O base/limit. */
	180	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
	181
	182	/* Set up the top and bottom of the PCI Memory segment
	183	for this bus. */
	184	pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
	185	if (bus->resource[1]->flags & IORESOURCE_MEM) {
	186	l = (region.start >> 16) & 0xfff0;
	187	l \|= region.end & 0xfff00000;
c40a22e0 BH	188	DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
	189	(unsigned long)region.start,
	190	(unsigned long)region.end);
1da177e4 LT	191	}
	192	else {
	193	l = 0x0000fff0;
	194	DBG(KERN_INFO " MEM window: disabled.\n");
	195	}
	196	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
	197
	198	/* Clear out the upper 32 bits of PREF limit.
	199	If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
	200	disables PREF range, which is ok. */
	201	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
	202
	203	/* Set up PREF base/limit. */
c40a22e0	204	bu = lu = 0;
1da177e4 LT	205	pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
	206	if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
	207	l = (region.start >> 16) & 0xfff0;
	208	l \|= region.end & 0xfff00000;
13d36c24 AM	209	bu = upper_32_bits(region.start);
13d36c24 AM	210	lu = upper_32_bits(region.end);
c40a22e0 BH	211	DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n",
	212	(unsigned long long)region.start,
	213	(unsigned long long)region.end);
1da177e4 LT	214	}
	215	else {
	216	l = 0x0000fff0;
	217	DBG(KERN_INFO " PREFETCH window: disabled.\n");
	218	}
	219	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
	220
c40a22e0 BH	221	/* Set the upper 32 bits of PREF base & limit. */
	222	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
	223	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
1da177e4 LT	224
	225	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
	226	}
	227
	228	/* Check whether the bridge supports optional I/O and
	229	prefetchable memory ranges. If not, the respective
	230	base/limit registers must be read-only and read as 0. */
96bde06a	231	static void pci_bridge_check_ranges(struct pci_bus *bus)
1da177e4 LT	232	{
	233	u16 io;
	234	u32 pmem;
	235	struct pci_dev *bridge = bus->self;
	236	struct resource *b_res;
	237
	238	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	239	b_res[1].flags \|= IORESOURCE_MEM;
	240
	241	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	242	if (!io) {
	243	pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
	244	pci_read_config_word(bridge, PCI_IO_BASE, &io);
	245	pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
	246	}
	247	if (io)
	248	b_res[0].flags \|= IORESOURCE_IO;
	249	/* DECchip 21050 pass 2 errata: the bridge may miss an address
	250	disconnect boundary by one PCI data phase.
	251	Workaround: do not use prefetching on this device. */
	252	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
	253	return;
	254	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	255	if (!pmem) {
	256	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
	257	0xfff0fff0);
	258	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
	259	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
	260	}
	261	if (pmem)
	262	b_res[2].flags \|= IORESOURCE_MEM \| IORESOURCE_PREFETCH;
	263	}
	264
	265	/* Helper function for sizing routines: find first available
	266	bus resource of a given type. Note: we intentionally skip
	267	the bus resources which have already been assigned (that is,
	268	have non-NULL parent resource). */
96bde06a	269	static struct resource find_free_bus_resource(struct pci_bus bus, unsigned long type)
1da177e4 LT	270	{
	271	int i;
	272	struct resource *r;
	273	unsigned long type_mask = IORESOURCE_IO \| IORESOURCE_MEM \|
	274	IORESOURCE_PREFETCH;
	275
	276	for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
	277	r = bus->resource[i];
299de034 IK	278	if (r == &ioport_resource \|\| r == &iomem_resource)
299de034 IK	279	continue;
1da177e4 LT	280	if (r && (r->flags & type_mask) == type && !r->parent)
	281	return r;
	282	}
	283	return NULL;
	284	}
	285
	286	/* Sizing the IO windows of the PCI-PCI bridge is trivial,
	287	since these windows have 4K granularity and the IO ranges
	288	of non-bridge PCI devices are limited to 256 bytes.
	289	We must be careful with the ISA aliasing though. */
96bde06a	290	static void pbus_size_io(struct pci_bus *bus)
1da177e4 LT	291	{
	292	struct pci_dev *dev;
	293	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
	294	unsigned long size = 0, size1 = 0;
	295
	296	if (!b_res)
	297	return;
	298
	299	list_for_each_entry(dev, &bus->devices, bus_list) {
	300	int i;
	301
	302	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	303	struct resource *r = &dev->resource[i];
	304	unsigned long r_size;
	305
	306	if (r->parent \|\| !(r->flags & IORESOURCE_IO))
	307	continue;
	308	r_size = r->end - r->start + 1;
	309
	310	if (r_size < 0x400)
	311	/* Might be re-aligned for ISA */
	312	size += r_size;
	313	else
	314	size1 += r_size;
	315	}
	316	}
	317	/* To be fixed in 2.5: we should have sort of HAVE_ISA
	318	flag in the struct pci_bus. */
	319	#if defined(CONFIG_ISA) \|\| defined(CONFIG_EISA)
	320	size = (size & 0xff) + ((size & ~0xffUL) << 2);
	321	#endif
6f6f8c2f	322	size = ALIGN(size + size1, 4096);
1da177e4 LT	323	if (!size) {
	324	b_res->flags = 0;
	325	return;
	326	}
	327	/* Alignment of the IO window is always 4K */
	328	b_res->start = 4096;
	329	b_res->end = b_res->start + size - 1;
	330	}
	331
	332	/* Calculate the size of the bus and minimal alignment which
	333	guarantees that all child resources fit in this size. */
96bde06a	334	static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
1da177e4 LT	335	{
1da177e4 LT	336	struct pci_dev *dev;
c40a22e0 BH	337	resource_size_t min_align, align, size;
c40a22e0 BH	338	resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
1da177e4 LT	339	int order, max_order;
	340	struct resource *b_res = find_free_bus_resource(bus, type);
	341
	342	if (!b_res)
	343	return 0;
	344
	345	memset(aligns, 0, sizeof(aligns));
	346	max_order = 0;
	347	size = 0;
	348
	349	list_for_each_entry(dev, &bus->devices, bus_list) {
	350	int i;
	351
	352	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	353	struct resource *r = &dev->resource[i];
c40a22e0	354	resource_size_t r_size;
1da177e4 LT	355
	356	if (r->parent \|\| (r->flags & mask) != type)
	357	continue;
	358	r_size = r->end - r->start + 1;
	359	/* For bridges size != alignment */
	360	align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
	361	order = __ffs(align) - 20;
	362	if (order > 11) {
	363	printk(KERN_WARNING "PCI: region %s/%d "
c40a22e0	364	"too large: 0x%016llx-0x%016llx\n",
1396a8c3	365	pci_name(dev), i,
c40a22e0 BH	366	(unsigned long long)r->start,
c40a22e0 BH	367	(unsigned long long)r->end);
1da177e4 LT	368	r->flags = 0;
	369	continue;
	370	}
	371	size += r_size;
	372	if (order < 0)
	373	order = 0;
	374	/* Exclude ranges with size > align from
	375	calculation of the alignment. */
	376	if (r_size == align)
	377	aligns[order] += align;
	378	if (order > max_order)
	379	max_order = order;
	380	}
	381	}
	382
	383	align = 0;
	384	min_align = 0;
	385	for (order = 0; order <= max_order; order++) {
c40a22e0 BH	386	#ifdef CONFIG_RESOURCES_64BIT
	387	resource_size_t align1 = 1ULL << (order + 20);
	388	#else
	389	resource_size_t align1 = 1U << (order + 20);
	390	#endif
1da177e4 LT	391	if (!align)
1da177e4 LT	392	min_align = align1;
6f6f8c2f	393	else if (ALIGN(align + min_align, min_align) < align1)
1da177e4 LT	394	min_align = align1 >> 1;
	395	align += aligns[order];
	396	}
6f6f8c2f	397	size = ALIGN(size, min_align);
1da177e4 LT	398	if (!size) {
	399	b_res->flags = 0;
	400	return 1;
	401	}
	402	b_res->start = min_align;
	403	b_res->end = size + min_align - 1;
	404	return 1;
	405	}
	406
	407	static void __devinit
	408	pci_bus_size_cardbus(struct pci_bus *bus)
	409	{
	410	struct pci_dev *bridge = bus->self;
	411	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
	412	u16 ctrl;
	413
	414	/*
	415	* Reserve some resources for CardBus. We reserve
	416	* a fixed amount of bus space for CardBus bridges.
	417	*/
4516a618 AN	418	b_res[0].start = pci_cardbus_io_size;
4516a618 AN	419	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1da177e4 LT	420	b_res[0].flags \|= IORESOURCE_IO;
1da177e4 LT	421
4516a618 AN	422	b_res[1].start = pci_cardbus_io_size;
4516a618 AN	423	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1da177e4 LT	424	b_res[1].flags \|= IORESOURCE_IO;
	425
	426	/*
	427	* Check whether prefetchable memory is supported
	428	* by this bridge.
	429	*/
	430	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	431	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
	432	ctrl \|= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
	433	pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
	434	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
	435	}
	436
	437	/*
	438	* If we have prefetchable memory support, allocate
	439	* two regions. Otherwise, allocate one region of
	440	* twice the size.
	441	*/
	442	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
4516a618 AN	443	b_res[2].start = pci_cardbus_mem_size;
4516a618 AN	444	b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1da177e4 LT	445	b_res[2].flags \|= IORESOURCE_MEM \| IORESOURCE_PREFETCH;
1da177e4 LT	446
4516a618 AN	447	b_res[3].start = pci_cardbus_mem_size;
4516a618 AN	448	b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
1da177e4 LT	449	b_res[3].flags \|= IORESOURCE_MEM;
1da177e4 LT	450	} else {
4516a618 AN	451	b_res[3].start = pci_cardbus_mem_size * 2;
4516a618 AN	452	b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
1da177e4 LT	453	b_res[3].flags \|= IORESOURCE_MEM;
	454	}
	455	}
	456
451124a7	457	void __ref pci_bus_size_bridges(struct pci_bus *bus)
1da177e4 LT	458	{
	459	struct pci_dev *dev;
	460	unsigned long mask, prefmask;
	461
	462	list_for_each_entry(dev, &bus->devices, bus_list) {
	463	struct pci_bus *b = dev->subordinate;
	464	if (!b)
	465	continue;
	466
	467	switch (dev->class >> 8) {
	468	case PCI_CLASS_BRIDGE_CARDBUS:
	469	pci_bus_size_cardbus(b);
	470	break;
	471
	472	case PCI_CLASS_BRIDGE_PCI:
	473	default:
	474	pci_bus_size_bridges(b);
	475	break;
	476	}
	477	}
	478
	479	/* The root bus? */
	480	if (!bus->self)
	481	return;
	482
	483	switch (bus->self->class >> 8) {
	484	case PCI_CLASS_BRIDGE_CARDBUS:
	485	/* don't size cardbuses yet. */
	486	break;
	487
	488	case PCI_CLASS_BRIDGE_PCI:
8fa5913d GH	489	/* don't size subtractive decoding (transparent)
	490	* PCI-to-PCI bridges */
	491	if (bus->self->transparent)
	492	break;
1da177e4	493	pci_bridge_check_ranges(bus);
8fa5913d	494	/* fall through */
1da177e4 LT	495	default:
	496	pbus_size_io(bus);
	497	/* If the bridge supports prefetchable range, size it
	498	separately. If it doesn't, or its prefetchable window
	499	has already been allocated by arch code, try
	500	non-prefetchable range for both types of PCI memory
	501	resources. */
	502	mask = IORESOURCE_MEM;
	503	prefmask = IORESOURCE_MEM \| IORESOURCE_PREFETCH;
	504	if (pbus_size_mem(bus, prefmask, prefmask))
	505	mask = prefmask; /* Success, size non-prefetch only. */
	506	pbus_size_mem(bus, mask, IORESOURCE_MEM);
	507	break;
	508	}
	509	}
	510	EXPORT_SYMBOL(pci_bus_size_bridges);
	511
451124a7	512	void __ref pci_bus_assign_resources(struct pci_bus *bus)
1da177e4 LT	513	{
	514	struct pci_bus *b;
	515	struct pci_dev *dev;
	516
	517	pbus_assign_resources_sorted(bus);
	518
1da177e4 LT	519	list_for_each_entry(dev, &bus->devices, bus_list) {
	520	b = dev->subordinate;
	521	if (!b)
	522	continue;
	523
	524	pci_bus_assign_resources(b);
	525
	526	switch (dev->class >> 8) {
	527	case PCI_CLASS_BRIDGE_PCI:
	528	pci_setup_bridge(b);
	529	break;
	530
	531	case PCI_CLASS_BRIDGE_CARDBUS:
	532	pci_setup_cardbus(b);
	533	break;
	534
	535	default:
	536	printk(KERN_INFO "PCI: not setting up bridge %s "
	537	"for bus %d\n", pci_name(dev), b->number);
	538	break;
	539	}
	540	}
	541	}
	542	EXPORT_SYMBOL(pci_bus_assign_resources);
	543
	544	void __init
	545	pci_assign_unassigned_resources(void)
	546	{
	547	struct pci_bus *bus;
	548
	549	/* Depth first, calculate sizes and alignments of all
	550	subordinate buses. */
	551	list_for_each_entry(bus, &pci_root_buses, node) {
	552	pci_bus_size_bridges(bus);
	553	}
	554	/* Depth last, allocate resources and update the hardware. */
	555	list_for_each_entry(bus, &pci_root_buses, node) {
	556	pci_bus_assign_resources(bus);
	557	pci_enable_bridges(bus);
	558	}
	559	}