rtl8192e: Use PCI Express Capability accessors
[deliverable/linux.git] / drivers / pci / setup-bus.c
CommitLineData
1da177e4
LT
1/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
47087700 28#include <asm-generic/pci-bridge.h>
6faf17f6 29#include "pci.h"
1da177e4 30
844393f4 31unsigned int pci_flags;
47087700 32
bdc4abec
YL
33struct pci_dev_resource {
34 struct list_head list;
2934a0de
YL
35 struct resource *res;
36 struct pci_dev *dev;
568ddef8
YL
37 resource_size_t start;
38 resource_size_t end;
c8adf9a3 39 resource_size_t add_size;
2bbc6942 40 resource_size_t min_align;
568ddef8
YL
41 unsigned long flags;
42};
43
bffc56d4
YL
44static void free_list(struct list_head *head)
45{
46 struct pci_dev_resource *dev_res, *tmp;
47
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
50 kfree(dev_res);
51 }
52}
094732a5 53
c8adf9a3
RP
54/**
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
58 * belongs
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
61 * to the resource
62 */
bdc4abec 63static int add_to_list(struct list_head *head,
c8adf9a3 64 struct pci_dev *dev, struct resource *res,
2bbc6942 65 resource_size_t add_size, resource_size_t min_align)
568ddef8 66{
764242a0 67 struct pci_dev_resource *tmp;
568ddef8 68
bdc4abec 69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
568ddef8 70 if (!tmp) {
c8adf9a3 71 pr_warning("add_to_list: kmalloc() failed!\n");
ef62dfef 72 return -ENOMEM;
568ddef8
YL
73 }
74
568ddef8
YL
75 tmp->res = res;
76 tmp->dev = dev;
77 tmp->start = res->start;
78 tmp->end = res->end;
79 tmp->flags = res->flags;
c8adf9a3 80 tmp->add_size = add_size;
2bbc6942 81 tmp->min_align = min_align;
bdc4abec
YL
82
83 list_add(&tmp->list, head);
ef62dfef
YL
84
85 return 0;
568ddef8
YL
86}
87
b9b0bba9 88static void remove_from_list(struct list_head *head,
3e6e0d80
YL
89 struct resource *res)
90{
b9b0bba9 91 struct pci_dev_resource *dev_res, *tmp;
3e6e0d80 92
b9b0bba9
YL
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
96 kfree(dev_res);
bdc4abec 97 break;
3e6e0d80 98 }
3e6e0d80
YL
99 }
100}
101
b9b0bba9 102static resource_size_t get_res_add_size(struct list_head *head,
1c372353
YL
103 struct resource *res)
104{
b9b0bba9 105 struct pci_dev_resource *dev_res;
bdc4abec 106
b9b0bba9
YL
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
b592443d
YL
109 int idx = res - &dev_res->dev->resource[0];
110
b9b0bba9 111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
b592443d
YL
112 "res[%d]=%pR get_res_add_size add_size %llx\n",
113 idx, dev_res->res,
b9b0bba9 114 (unsigned long long)dev_res->add_size);
b592443d 115
b9b0bba9 116 return dev_res->add_size;
bdc4abec 117 }
3e6e0d80 118 }
1c372353
YL
119
120 return 0;
121}
122
78c3b329 123/* Sort resources by alignment */
bdc4abec 124static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
78c3b329
YL
125{
126 int i;
127
128 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
129 struct resource *r;
bdc4abec 130 struct pci_dev_resource *dev_res, *tmp;
78c3b329 131 resource_size_t r_align;
bdc4abec 132 struct list_head *n;
78c3b329
YL
133
134 r = &dev->resource[i];
135
136 if (r->flags & IORESOURCE_PCI_FIXED)
137 continue;
138
139 if (!(r->flags) || r->parent)
140 continue;
141
142 r_align = pci_resource_alignment(dev, r);
143 if (!r_align) {
144 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
145 i, r);
146 continue;
147 }
78c3b329 148
bdc4abec
YL
149 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
150 if (!tmp)
151 panic("pdev_sort_resources(): "
152 "kmalloc() failed!\n");
153 tmp->res = r;
154 tmp->dev = dev;
155
156 /* fallback is smallest one or list is empty*/
157 n = head;
158 list_for_each_entry(dev_res, head, list) {
159 resource_size_t align;
160
161 align = pci_resource_alignment(dev_res->dev,
162 dev_res->res);
78c3b329
YL
163
164 if (r_align > align) {
bdc4abec 165 n = &dev_res->list;
78c3b329
YL
166 break;
167 }
168 }
bdc4abec
YL
169 /* Insert it just before n*/
170 list_add_tail(&tmp->list, n);
78c3b329
YL
171 }
172}
173
6841ec68 174static void __dev_sort_resources(struct pci_dev *dev,
bdc4abec 175 struct list_head *head)
1da177e4 176{
6841ec68 177 u16 class = dev->class >> 8;
1da177e4 178
6841ec68
YL
179 /* Don't touch classless devices or host bridges or ioapics. */
180 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
181 return;
1da177e4 182
6841ec68
YL
183 /* Don't touch ioapic devices already enabled by firmware */
184 if (class == PCI_CLASS_SYSTEM_PIC) {
185 u16 command;
186 pci_read_config_word(dev, PCI_COMMAND, &command);
187 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
188 return;
189 }
1da177e4 190
6841ec68
YL
191 pdev_sort_resources(dev, head);
192}
23186279 193
fc075e1d
RP
194static inline void reset_resource(struct resource *res)
195{
196 res->start = 0;
197 res->end = 0;
198 res->flags = 0;
199}
200
c8adf9a3 201/**
9e8bf93a 202 * reassign_resources_sorted() - satisfy any additional resource requests
c8adf9a3 203 *
9e8bf93a 204 * @realloc_head : head of the list tracking requests requiring additional
c8adf9a3
RP
205 * resources
206 * @head : head of the list tracking requests with allocated
207 * resources
208 *
9e8bf93a 209 * Walk through each element of the realloc_head and try to procure
c8adf9a3
RP
210 * additional resources for the element, provided the element
211 * is in the head list.
212 */
bdc4abec
YL
213static void reassign_resources_sorted(struct list_head *realloc_head,
214 struct list_head *head)
6841ec68
YL
215{
216 struct resource *res;
b9b0bba9 217 struct pci_dev_resource *add_res, *tmp;
bdc4abec 218 struct pci_dev_resource *dev_res;
c8adf9a3 219 resource_size_t add_size;
6841ec68 220 int idx;
1da177e4 221
b9b0bba9 222 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
bdc4abec
YL
223 bool found_match = false;
224
b9b0bba9 225 res = add_res->res;
c8adf9a3
RP
226 /* skip resource that has been reset */
227 if (!res->flags)
228 goto out;
229
230 /* skip this resource if not found in head list */
bdc4abec
YL
231 list_for_each_entry(dev_res, head, list) {
232 if (dev_res->res == res) {
233 found_match = true;
234 break;
235 }
c8adf9a3 236 }
bdc4abec
YL
237 if (!found_match)/* just skip */
238 continue;
c8adf9a3 239
b9b0bba9
YL
240 idx = res - &add_res->dev->resource[0];
241 add_size = add_res->add_size;
2bbc6942 242 if (!resource_size(res)) {
b9b0bba9 243 res->start = add_res->start;
2bbc6942 244 res->end = res->start + add_size - 1;
b9b0bba9 245 if (pci_assign_resource(add_res->dev, idx))
c8adf9a3 246 reset_resource(res);
2bbc6942 247 } else {
b9b0bba9
YL
248 resource_size_t align = add_res->min_align;
249 res->flags |= add_res->flags &
bdc4abec 250 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
b9b0bba9 251 if (pci_reassign_resource(add_res->dev, idx,
bdc4abec 252 add_size, align))
b9b0bba9 253 dev_printk(KERN_DEBUG, &add_res->dev->dev,
b592443d
YL
254 "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long)add_size,
256 idx, res);
c8adf9a3
RP
257 }
258out:
b9b0bba9
YL
259 list_del(&add_res->list);
260 kfree(add_res);
c8adf9a3
RP
261 }
262}
263
264/**
265 * assign_requested_resources_sorted() - satisfy resource requests
266 *
267 * @head : head of the list tracking requests for resources
8356aad4 268 * @fail_head : head of the list tracking requests that could
c8adf9a3
RP
269 * not be allocated
270 *
271 * Satisfy resource requests of each element in the list. Add
272 * requests that could not satisfied to the failed_list.
273 */
bdc4abec
YL
274static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
c8adf9a3
RP
276{
277 struct resource *res;
bdc4abec 278 struct pci_dev_resource *dev_res;
c8adf9a3 279 int idx;
9a928660 280
bdc4abec
YL
281 list_for_each_entry(dev_res, head, list) {
282 res = dev_res->res;
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
286 if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) {
9a928660
YL
287 /*
288 * if the failed res is for ROM BAR, and it will
289 * be enabled later, don't add it to the list
290 */
291 if (!((idx == PCI_ROM_RESOURCE) &&
292 (!(res->flags & IORESOURCE_ROM_ENABLE))))
67cc7e26
YL
293 add_to_list(fail_head,
294 dev_res->dev, res,
295 0 /* dont care */,
296 0 /* dont care */);
9a928660 297 }
fc075e1d 298 reset_resource(res);
542df5de 299 }
1da177e4
LT
300 }
301}
302
bdc4abec
YL
303static void __assign_resources_sorted(struct list_head *head,
304 struct list_head *realloc_head,
305 struct list_head *fail_head)
c8adf9a3 306{
3e6e0d80
YL
307 /*
308 * Should not assign requested resources at first.
309 * they could be adjacent, so later reassign can not reallocate
310 * them one by one in parent resource window.
367fa982 311 * Try to assign requested + add_size at beginning
3e6e0d80
YL
312 * if could do that, could get out early.
313 * if could not do that, we still try to assign requested at first,
314 * then try to reassign add_size for some resources.
315 */
bdc4abec
YL
316 LIST_HEAD(save_head);
317 LIST_HEAD(local_fail_head);
b9b0bba9 318 struct pci_dev_resource *save_res;
bdc4abec 319 struct pci_dev_resource *dev_res;
3e6e0d80
YL
320
321 /* Check if optional add_size is there */
bdc4abec 322 if (!realloc_head || list_empty(realloc_head))
3e6e0d80
YL
323 goto requested_and_reassign;
324
325 /* Save original start, end, flags etc at first */
bdc4abec
YL
326 list_for_each_entry(dev_res, head, list) {
327 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
bffc56d4 328 free_list(&save_head);
3e6e0d80
YL
329 goto requested_and_reassign;
330 }
bdc4abec 331 }
3e6e0d80
YL
332
333 /* Update res in head list with add_size in realloc_head list */
bdc4abec
YL
334 list_for_each_entry(dev_res, head, list)
335 dev_res->res->end += get_res_add_size(realloc_head,
336 dev_res->res);
3e6e0d80
YL
337
338 /* Try updated head list with add_size added */
3e6e0d80
YL
339 assign_requested_resources_sorted(head, &local_fail_head);
340
341 /* all assigned with add_size ? */
bdc4abec 342 if (list_empty(&local_fail_head)) {
3e6e0d80 343 /* Remove head list from realloc_head list */
bdc4abec
YL
344 list_for_each_entry(dev_res, head, list)
345 remove_from_list(realloc_head, dev_res->res);
bffc56d4
YL
346 free_list(&save_head);
347 free_list(head);
3e6e0d80
YL
348 return;
349 }
350
bffc56d4 351 free_list(&local_fail_head);
3e6e0d80 352 /* Release assigned resource */
bdc4abec
YL
353 list_for_each_entry(dev_res, head, list)
354 if (dev_res->res->parent)
355 release_resource(dev_res->res);
3e6e0d80 356 /* Restore start/end/flags from saved list */
b9b0bba9
YL
357 list_for_each_entry(save_res, &save_head, list) {
358 struct resource *res = save_res->res;
3e6e0d80 359
b9b0bba9
YL
360 res->start = save_res->start;
361 res->end = save_res->end;
362 res->flags = save_res->flags;
3e6e0d80 363 }
bffc56d4 364 free_list(&save_head);
3e6e0d80
YL
365
366requested_and_reassign:
c8adf9a3
RP
367 /* Satisfy the must-have resource requests */
368 assign_requested_resources_sorted(head, fail_head);
369
0a2daa1c 370 /* Try to satisfy any additional optional resource
c8adf9a3 371 requests */
9e8bf93a
RP
372 if (realloc_head)
373 reassign_resources_sorted(realloc_head, head);
bffc56d4 374 free_list(head);
c8adf9a3
RP
375}
376
6841ec68 377static void pdev_assign_resources_sorted(struct pci_dev *dev,
bdc4abec
YL
378 struct list_head *add_head,
379 struct list_head *fail_head)
6841ec68 380{
bdc4abec 381 LIST_HEAD(head);
6841ec68 382
6841ec68 383 __dev_sort_resources(dev, &head);
8424d759 384 __assign_resources_sorted(&head, add_head, fail_head);
6841ec68
YL
385
386}
387
388static void pbus_assign_resources_sorted(const struct pci_bus *bus,
bdc4abec
YL
389 struct list_head *realloc_head,
390 struct list_head *fail_head)
6841ec68
YL
391{
392 struct pci_dev *dev;
bdc4abec 393 LIST_HEAD(head);
6841ec68 394
6841ec68
YL
395 list_for_each_entry(dev, &bus->devices, bus_list)
396 __dev_sort_resources(dev, &head);
397
9e8bf93a 398 __assign_resources_sorted(&head, realloc_head, fail_head);
6841ec68
YL
399}
400
b3743fa4 401void pci_setup_cardbus(struct pci_bus *bus)
1da177e4
LT
402{
403 struct pci_dev *bridge = bus->self;
c7dabef8 404 struct resource *res;
1da177e4
LT
405 struct pci_bus_region region;
406
b918c62e
YL
407 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
408 &bus->busn_res);
1da177e4 409
c7dabef8
BH
410 res = bus->resource[0];
411 pcibios_resource_to_bus(bridge, &region, res);
412 if (res->flags & IORESOURCE_IO) {
1da177e4
LT
413 /*
414 * The IO resource is allocated a range twice as large as it
415 * would normally need. This allows us to set both IO regs.
416 */
c7dabef8 417 dev_info(&bridge->dev, " bridge window %pR\n", res);
1da177e4
LT
418 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
419 region.start);
420 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
421 region.end);
422 }
423
c7dabef8
BH
424 res = bus->resource[1];
425 pcibios_resource_to_bus(bridge, &region, res);
426 if (res->flags & IORESOURCE_IO) {
427 dev_info(&bridge->dev, " bridge window %pR\n", res);
1da177e4
LT
428 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
429 region.start);
430 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
431 region.end);
432 }
433
c7dabef8
BH
434 res = bus->resource[2];
435 pcibios_resource_to_bus(bridge, &region, res);
436 if (res->flags & IORESOURCE_MEM) {
437 dev_info(&bridge->dev, " bridge window %pR\n", res);
1da177e4
LT
438 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
439 region.start);
440 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
441 region.end);
442 }
443
c7dabef8
BH
444 res = bus->resource[3];
445 pcibios_resource_to_bus(bridge, &region, res);
446 if (res->flags & IORESOURCE_MEM) {
447 dev_info(&bridge->dev, " bridge window %pR\n", res);
1da177e4
LT
448 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
449 region.start);
450 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
451 region.end);
452 }
453}
b3743fa4 454EXPORT_SYMBOL(pci_setup_cardbus);
1da177e4
LT
455
456/* Initialize bridges with base/limit values we have collected.
457 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
458 requires that if there is no I/O ports or memory behind the
459 bridge, corresponding range must be turned off by writing base
460 value greater than limit to the bridge's base/limit registers.
461
462 Note: care must be taken when updating I/O base/limit registers
463 of bridges which support 32-bit I/O. This update requires two
464 config space writes, so it's quite possible that an I/O window of
465 the bridge will have some undesirable address (e.g. 0) after the
466 first write. Ditto 64-bit prefetchable MMIO. */
7cc5997d 467static void pci_setup_bridge_io(struct pci_bus *bus)
1da177e4
LT
468{
469 struct pci_dev *bridge = bus->self;
c7dabef8 470 struct resource *res;
1da177e4 471 struct pci_bus_region region;
2b28ae19
BH
472 unsigned long io_mask;
473 u8 io_base_lo, io_limit_lo;
7cc5997d 474 u32 l, io_upper16;
1da177e4 475
2b28ae19
BH
476 io_mask = PCI_IO_RANGE_MASK;
477 if (bridge->io_window_1k)
478 io_mask = PCI_IO_1K_RANGE_MASK;
479
1da177e4 480 /* Set up the top and bottom of the PCI I/O segment for this bus. */
c7dabef8
BH
481 res = bus->resource[0];
482 pcibios_resource_to_bus(bridge, &region, res);
483 if (res->flags & IORESOURCE_IO) {
1da177e4
LT
484 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
485 l &= 0xffff0000;
2b28ae19
BH
486 io_base_lo = (region.start >> 8) & io_mask;
487 io_limit_lo = (region.end >> 8) & io_mask;
488 l |= ((u32) io_limit_lo << 8) | io_base_lo;
1da177e4
LT
489 /* Set up upper 16 bits of I/O base/limit. */
490 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
c7dabef8 491 dev_info(&bridge->dev, " bridge window %pR\n", res);
7cc5997d 492 } else {
1da177e4
LT
493 /* Clear upper 16 bits of I/O base/limit. */
494 io_upper16 = 0;
495 l = 0x00f0;
1da177e4
LT
496 }
497 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
498 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
499 /* Update lower 16 bits of I/O base/limit. */
500 pci_write_config_dword(bridge, PCI_IO_BASE, l);
501 /* Update upper 16 bits of I/O base/limit. */
502 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
7cc5997d
YL
503}
504
505static void pci_setup_bridge_mmio(struct pci_bus *bus)
506{
507 struct pci_dev *bridge = bus->self;
508 struct resource *res;
509 struct pci_bus_region region;
510 u32 l;
1da177e4 511
7cc5997d 512 /* Set up the top and bottom of the PCI Memory segment for this bus. */
c7dabef8
BH
513 res = bus->resource[1];
514 pcibios_resource_to_bus(bridge, &region, res);
515 if (res->flags & IORESOURCE_MEM) {
1da177e4
LT
516 l = (region.start >> 16) & 0xfff0;
517 l |= region.end & 0xfff00000;
c7dabef8 518 dev_info(&bridge->dev, " bridge window %pR\n", res);
7cc5997d 519 } else {
1da177e4 520 l = 0x0000fff0;
1da177e4
LT
521 }
522 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
7cc5997d
YL
523}
524
525static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
526{
527 struct pci_dev *bridge = bus->self;
528 struct resource *res;
529 struct pci_bus_region region;
530 u32 l, bu, lu;
1da177e4
LT
531
532 /* Clear out the upper 32 bits of PREF limit.
533 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
534 disables PREF range, which is ok. */
535 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
536
537 /* Set up PREF base/limit. */
c40a22e0 538 bu = lu = 0;
c7dabef8
BH
539 res = bus->resource[2];
540 pcibios_resource_to_bus(bridge, &region, res);
541 if (res->flags & IORESOURCE_PREFETCH) {
1da177e4
LT
542 l = (region.start >> 16) & 0xfff0;
543 l |= region.end & 0xfff00000;
c7dabef8 544 if (res->flags & IORESOURCE_MEM_64) {
1f82de10
YL
545 bu = upper_32_bits(region.start);
546 lu = upper_32_bits(region.end);
1f82de10 547 }
c7dabef8 548 dev_info(&bridge->dev, " bridge window %pR\n", res);
7cc5997d 549 } else {
1da177e4 550 l = 0x0000fff0;
1da177e4
LT
551 }
552 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
553
59353ea3
AW
554 /* Set the upper 32 bits of PREF base & limit. */
555 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
556 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
7cc5997d
YL
557}
558
559static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
560{
561 struct pci_dev *bridge = bus->self;
562
b918c62e
YL
563 dev_info(&bridge->dev, "PCI bridge to %pR\n",
564 &bus->busn_res);
7cc5997d
YL
565
566 if (type & IORESOURCE_IO)
567 pci_setup_bridge_io(bus);
568
569 if (type & IORESOURCE_MEM)
570 pci_setup_bridge_mmio(bus);
571
572 if (type & IORESOURCE_PREFETCH)
573 pci_setup_bridge_mmio_pref(bus);
1da177e4
LT
574
575 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
576}
577
e2444273 578void pci_setup_bridge(struct pci_bus *bus)
7cc5997d
YL
579{
580 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
581 IORESOURCE_PREFETCH;
582
583 __pci_setup_bridge(bus, type);
584}
585
1da177e4
LT
586/* Check whether the bridge supports optional I/O and
587 prefetchable memory ranges. If not, the respective
588 base/limit registers must be read-only and read as 0. */
96bde06a 589static void pci_bridge_check_ranges(struct pci_bus *bus)
1da177e4
LT
590{
591 u16 io;
592 u32 pmem;
593 struct pci_dev *bridge = bus->self;
594 struct resource *b_res;
595
596 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
597 b_res[1].flags |= IORESOURCE_MEM;
598
599 pci_read_config_word(bridge, PCI_IO_BASE, &io);
600 if (!io) {
601 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
602 pci_read_config_word(bridge, PCI_IO_BASE, &io);
603 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
604 }
605 if (io)
606 b_res[0].flags |= IORESOURCE_IO;
607 /* DECchip 21050 pass 2 errata: the bridge may miss an address
608 disconnect boundary by one PCI data phase.
609 Workaround: do not use prefetching on this device. */
610 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
611 return;
612 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
613 if (!pmem) {
614 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
615 0xfff0fff0);
616 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
617 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
618 }
1f82de10 619 if (pmem) {
1da177e4 620 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
99586105
YL
621 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
622 PCI_PREF_RANGE_TYPE_64) {
1f82de10 623 b_res[2].flags |= IORESOURCE_MEM_64;
99586105
YL
624 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
625 }
1f82de10
YL
626 }
627
628 /* double check if bridge does support 64 bit pref */
629 if (b_res[2].flags & IORESOURCE_MEM_64) {
630 u32 mem_base_hi, tmp;
631 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
632 &mem_base_hi);
633 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
634 0xffffffff);
635 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
636 if (!tmp)
637 b_res[2].flags &= ~IORESOURCE_MEM_64;
638 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
639 mem_base_hi);
640 }
1da177e4
LT
641}
642
643/* Helper function for sizing routines: find first available
644 bus resource of a given type. Note: we intentionally skip
645 the bus resources which have already been assigned (that is,
646 have non-NULL parent resource). */
96bde06a 647static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
1da177e4
LT
648{
649 int i;
650 struct resource *r;
651 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
652 IORESOURCE_PREFETCH;
653
89a74ecc 654 pci_bus_for_each_resource(bus, r, i) {
299de034
IK
655 if (r == &ioport_resource || r == &iomem_resource)
656 continue;
55a10984
JB
657 if (r && (r->flags & type_mask) == type && !r->parent)
658 return r;
1da177e4
LT
659 }
660 return NULL;
661}
662
13583b16
RP
663static resource_size_t calculate_iosize(resource_size_t size,
664 resource_size_t min_size,
665 resource_size_t size1,
666 resource_size_t old_size,
667 resource_size_t align)
668{
669 if (size < min_size)
670 size = min_size;
671 if (old_size == 1 )
672 old_size = 0;
673 /* To be fixed in 2.5: we should have sort of HAVE_ISA
674 flag in the struct pci_bus. */
675#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
676 size = (size & 0xff) + ((size & ~0xffUL) << 2);
677#endif
678 size = ALIGN(size + size1, align);
679 if (size < old_size)
680 size = old_size;
681 return size;
682}
683
684static resource_size_t calculate_memsize(resource_size_t size,
685 resource_size_t min_size,
686 resource_size_t size1,
687 resource_size_t old_size,
688 resource_size_t align)
689{
690 if (size < min_size)
691 size = min_size;
692 if (old_size == 1 )
693 old_size = 0;
694 if (size < old_size)
695 size = old_size;
696 size = ALIGN(size + size1, align);
697 return size;
698}
699
c8adf9a3
RP
700/**
701 * pbus_size_io() - size the io window of a given bus
702 *
703 * @bus : the bus
704 * @min_size : the minimum io window that must to be allocated
705 * @add_size : additional optional io window
9e8bf93a 706 * @realloc_head : track the additional io window on this list
c8adf9a3
RP
707 *
708 * Sizing the IO windows of the PCI-PCI bridge is trivial,
fd591341 709 * since these windows have 1K or 4K granularity and the IO ranges
c8adf9a3
RP
710 * of non-bridge PCI devices are limited to 256 bytes.
711 * We must be careful with the ISA aliasing though.
712 */
713static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
bdc4abec 714 resource_size_t add_size, struct list_head *realloc_head)
1da177e4
LT
715{
716 struct pci_dev *dev;
717 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
c8adf9a3 718 unsigned long size = 0, size0 = 0, size1 = 0;
be768912 719 resource_size_t children_add_size = 0;
fd591341 720 resource_size_t min_align = 4096, align;
1da177e4
LT
721
722 if (!b_res)
723 return;
724
fd591341
YL
725 /*
726 * Per spec, I/O windows are 4K-aligned, but some bridges have an
727 * extension to support 1K alignment.
728 */
729 if (bus->self->io_window_1k)
730 min_align = 1024;
1da177e4
LT
731 list_for_each_entry(dev, &bus->devices, bus_list) {
732 int i;
733
734 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
735 struct resource *r = &dev->resource[i];
736 unsigned long r_size;
737
738 if (r->parent || !(r->flags & IORESOURCE_IO))
739 continue;
022edd86 740 r_size = resource_size(r);
1da177e4
LT
741
742 if (r_size < 0x400)
743 /* Might be re-aligned for ISA */
744 size += r_size;
745 else
746 size1 += r_size;
be768912 747
fd591341
YL
748 align = pci_resource_alignment(dev, r);
749 if (align > min_align)
750 min_align = align;
751
9e8bf93a
RP
752 if (realloc_head)
753 children_add_size += get_res_add_size(realloc_head, r);
1da177e4
LT
754 }
755 }
fd591341
YL
756
757 if (min_align > 4096)
758 min_align = 4096;
759
c8adf9a3 760 size0 = calculate_iosize(size, min_size, size1,
fd591341 761 resource_size(b_res), min_align);
be768912
YL
762 if (children_add_size > add_size)
763 add_size = children_add_size;
9e8bf93a 764 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
a4ac9fea 765 calculate_iosize(size, min_size, add_size + size1,
fd591341 766 resource_size(b_res), min_align);
c8adf9a3 767 if (!size0 && !size1) {
865df576
BH
768 if (b_res->start || b_res->end)
769 dev_info(&bus->self->dev, "disabling bridge window "
b918c62e
YL
770 "%pR to %pR (unused)\n", b_res,
771 &bus->busn_res);
1da177e4
LT
772 b_res->flags = 0;
773 return;
774 }
fd591341
YL
775
776 b_res->start = min_align;
c8adf9a3 777 b_res->end = b_res->start + size0 - 1;
88452565 778 b_res->flags |= IORESOURCE_STARTALIGN;
b592443d 779 if (size1 > size0 && realloc_head) {
fd591341
YL
780 add_to_list(realloc_head, bus->self, b_res, size1-size0,
781 min_align);
b592443d 782 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
b918c62e
YL
783 "%pR to %pR add_size %lx\n", b_res,
784 &bus->busn_res, size1-size0);
b592443d 785 }
1da177e4
LT
786}
787
c8adf9a3
RP
788/**
789 * pbus_size_mem() - size the memory window of a given bus
790 *
791 * @bus : the bus
792 * @min_size : the minimum memory window that must to be allocated
793 * @add_size : additional optional memory window
9e8bf93a 794 * @realloc_head : track the additional memory window on this list
c8adf9a3
RP
795 *
796 * Calculate the size of the bus and minimal alignment which
797 * guarantees that all child resources fit in this size.
798 */
28760489 799static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
c8adf9a3
RP
800 unsigned long type, resource_size_t min_size,
801 resource_size_t add_size,
bdc4abec 802 struct list_head *realloc_head)
1da177e4
LT
803{
804 struct pci_dev *dev;
c8adf9a3 805 resource_size_t min_align, align, size, size0, size1;
c40a22e0 806 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
1da177e4
LT
807 int order, max_order;
808 struct resource *b_res = find_free_bus_resource(bus, type);
1f82de10 809 unsigned int mem64_mask = 0;
be768912 810 resource_size_t children_add_size = 0;
1da177e4
LT
811
812 if (!b_res)
813 return 0;
814
815 memset(aligns, 0, sizeof(aligns));
816 max_order = 0;
817 size = 0;
818
1f82de10
YL
819 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
820 b_res->flags &= ~IORESOURCE_MEM_64;
821
1da177e4
LT
822 list_for_each_entry(dev, &bus->devices, bus_list) {
823 int i;
1f82de10 824
1da177e4
LT
825 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
826 struct resource *r = &dev->resource[i];
c40a22e0 827 resource_size_t r_size;
1da177e4
LT
828
829 if (r->parent || (r->flags & mask) != type)
830 continue;
022edd86 831 r_size = resource_size(r);
2aceefcb
YL
832#ifdef CONFIG_PCI_IOV
833 /* put SRIOV requested res to the optional list */
9e8bf93a 834 if (realloc_head && i >= PCI_IOV_RESOURCES &&
2aceefcb
YL
835 i <= PCI_IOV_RESOURCE_END) {
836 r->end = r->start - 1;
9e8bf93a 837 add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */);
2aceefcb
YL
838 children_add_size += r_size;
839 continue;
840 }
841#endif
1da177e4 842 /* For bridges size != alignment */
6faf17f6 843 align = pci_resource_alignment(dev, r);
1da177e4
LT
844 order = __ffs(align) - 20;
845 if (order > 11) {
865df576
BH
846 dev_warn(&dev->dev, "disabling BAR %d: %pR "
847 "(bad alignment %#llx)\n", i, r,
848 (unsigned long long) align);
1da177e4
LT
849 r->flags = 0;
850 continue;
851 }
852 size += r_size;
853 if (order < 0)
854 order = 0;
855 /* Exclude ranges with size > align from
856 calculation of the alignment. */
857 if (r_size == align)
858 aligns[order] += align;
859 if (order > max_order)
860 max_order = order;
1f82de10 861 mem64_mask &= r->flags & IORESOURCE_MEM_64;
be768912 862
9e8bf93a
RP
863 if (realloc_head)
864 children_add_size += get_res_add_size(realloc_head, r);
1da177e4
LT
865 }
866 }
1da177e4
LT
867 align = 0;
868 min_align = 0;
869 for (order = 0; order <= max_order; order++) {
8308c54d
JF
870 resource_size_t align1 = 1;
871
872 align1 <<= (order + 20);
873
1da177e4
LT
874 if (!align)
875 min_align = align1;
6f6f8c2f 876 else if (ALIGN(align + min_align, min_align) < align1)
1da177e4
LT
877 min_align = align1 >> 1;
878 align += aligns[order];
879 }
b42282e5 880 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
be768912
YL
881 if (children_add_size > add_size)
882 add_size = children_add_size;
9e8bf93a 883 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
a4ac9fea 884 calculate_memsize(size, min_size, add_size,
b42282e5 885 resource_size(b_res), min_align);
c8adf9a3 886 if (!size0 && !size1) {
865df576
BH
887 if (b_res->start || b_res->end)
888 dev_info(&bus->self->dev, "disabling bridge window "
b918c62e
YL
889 "%pR to %pR (unused)\n", b_res,
890 &bus->busn_res);
1da177e4
LT
891 b_res->flags = 0;
892 return 1;
893 }
894 b_res->start = min_align;
c8adf9a3
RP
895 b_res->end = size0 + min_align - 1;
896 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
b592443d 897 if (size1 > size0 && realloc_head) {
9e8bf93a 898 add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align);
b592443d 899 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window "
b918c62e
YL
900 "%pR to %pR add_size %llx\n", b_res,
901 &bus->busn_res, (unsigned long long)size1-size0);
b592443d 902 }
1da177e4
LT
903 return 1;
904}
905
0a2daa1c
RP
906unsigned long pci_cardbus_resource_alignment(struct resource *res)
907{
908 if (res->flags & IORESOURCE_IO)
909 return pci_cardbus_io_size;
910 if (res->flags & IORESOURCE_MEM)
911 return pci_cardbus_mem_size;
912 return 0;
913}
914
915static void pci_bus_size_cardbus(struct pci_bus *bus,
bdc4abec 916 struct list_head *realloc_head)
1da177e4
LT
917{
918 struct pci_dev *bridge = bus->self;
919 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
11848934 920 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1da177e4
LT
921 u16 ctrl;
922
3796f1e2
YL
923 if (b_res[0].parent)
924 goto handle_b_res_1;
1da177e4
LT
925 /*
926 * Reserve some resources for CardBus. We reserve
927 * a fixed amount of bus space for CardBus bridges.
928 */
11848934
YL
929 b_res[0].start = pci_cardbus_io_size;
930 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
931 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
932 if (realloc_head) {
933 b_res[0].end -= pci_cardbus_io_size;
934 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
935 pci_cardbus_io_size);
936 }
1da177e4 937
3796f1e2
YL
938handle_b_res_1:
939 if (b_res[1].parent)
940 goto handle_b_res_2;
11848934
YL
941 b_res[1].start = pci_cardbus_io_size;
942 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
943 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
944 if (realloc_head) {
945 b_res[1].end -= pci_cardbus_io_size;
946 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
947 pci_cardbus_io_size);
948 }
1da177e4 949
3796f1e2 950handle_b_res_2:
dcef0d06
YL
951 /* MEM1 must not be pref mmio */
952 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
953 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
954 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
955 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
956 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
957 }
958
1da177e4
LT
959 /*
960 * Check whether prefetchable memory is supported
961 * by this bridge.
962 */
963 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
964 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
965 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
966 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
967 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
968 }
969
3796f1e2
YL
970 if (b_res[2].parent)
971 goto handle_b_res_3;
1da177e4
LT
972 /*
973 * If we have prefetchable memory support, allocate
974 * two regions. Otherwise, allocate one region of
975 * twice the size.
976 */
977 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
11848934
YL
978 b_res[2].start = pci_cardbus_mem_size;
979 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
980 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
981 IORESOURCE_STARTALIGN;
982 if (realloc_head) {
983 b_res[2].end -= pci_cardbus_mem_size;
984 add_to_list(realloc_head, bridge, b_res+2,
985 pci_cardbus_mem_size, pci_cardbus_mem_size);
986 }
987
988 /* reduce that to half */
989 b_res_3_size = pci_cardbus_mem_size;
990 }
991
3796f1e2
YL
992handle_b_res_3:
993 if (b_res[3].parent)
994 goto handle_done;
11848934
YL
995 b_res[3].start = pci_cardbus_mem_size;
996 b_res[3].end = b_res[3].start + b_res_3_size - 1;
997 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
998 if (realloc_head) {
999 b_res[3].end -= b_res_3_size;
1000 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1001 pci_cardbus_mem_size);
1002 }
3796f1e2
YL
1003
1004handle_done:
1005 ;
1da177e4
LT
1006}
1007
c8adf9a3 1008void __ref __pci_bus_size_bridges(struct pci_bus *bus,
bdc4abec 1009 struct list_head *realloc_head)
1da177e4
LT
1010{
1011 struct pci_dev *dev;
1012 unsigned long mask, prefmask;
c8adf9a3 1013 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1da177e4
LT
1014
1015 list_for_each_entry(dev, &bus->devices, bus_list) {
1016 struct pci_bus *b = dev->subordinate;
1017 if (!b)
1018 continue;
1019
1020 switch (dev->class >> 8) {
1021 case PCI_CLASS_BRIDGE_CARDBUS:
9e8bf93a 1022 pci_bus_size_cardbus(b, realloc_head);
1da177e4
LT
1023 break;
1024
1025 case PCI_CLASS_BRIDGE_PCI:
1026 default:
9e8bf93a 1027 __pci_bus_size_bridges(b, realloc_head);
1da177e4
LT
1028 break;
1029 }
1030 }
1031
1032 /* The root bus? */
1033 if (!bus->self)
1034 return;
1035
1036 switch (bus->self->class >> 8) {
1037 case PCI_CLASS_BRIDGE_CARDBUS:
1038 /* don't size cardbuses yet. */
1039 break;
1040
1041 case PCI_CLASS_BRIDGE_PCI:
1042 pci_bridge_check_ranges(bus);
28760489 1043 if (bus->self->is_hotplug_bridge) {
c8adf9a3
RP
1044 additional_io_size = pci_hotplug_io_size;
1045 additional_mem_size = pci_hotplug_mem_size;
28760489 1046 }
c8adf9a3
RP
1047 /*
1048 * Follow thru
1049 */
1da177e4 1050 default:
19aa7ee4
YL
1051 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1052 additional_io_size, realloc_head);
1da177e4
LT
1053 /* If the bridge supports prefetchable range, size it
1054 separately. If it doesn't, or its prefetchable window
1055 has already been allocated by arch code, try
1056 non-prefetchable range for both types of PCI memory
1057 resources. */
1058 mask = IORESOURCE_MEM;
1059 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
19aa7ee4
YL
1060 if (pbus_size_mem(bus, prefmask, prefmask,
1061 realloc_head ? 0 : additional_mem_size,
1062 additional_mem_size, realloc_head))
1da177e4 1063 mask = prefmask; /* Success, size non-prefetch only. */
28760489 1064 else
c8adf9a3 1065 additional_mem_size += additional_mem_size;
19aa7ee4
YL
1066 pbus_size_mem(bus, mask, IORESOURCE_MEM,
1067 realloc_head ? 0 : additional_mem_size,
1068 additional_mem_size, realloc_head);
1da177e4
LT
1069 break;
1070 }
1071}
c8adf9a3
RP
1072
1073void __ref pci_bus_size_bridges(struct pci_bus *bus)
1074{
1075 __pci_bus_size_bridges(bus, NULL);
1076}
1da177e4
LT
1077EXPORT_SYMBOL(pci_bus_size_bridges);
1078
568ddef8 1079static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
bdc4abec
YL
1080 struct list_head *realloc_head,
1081 struct list_head *fail_head)
1da177e4
LT
1082{
1083 struct pci_bus *b;
1084 struct pci_dev *dev;
1085
9e8bf93a 1086 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1da177e4 1087
1da177e4
LT
1088 list_for_each_entry(dev, &bus->devices, bus_list) {
1089 b = dev->subordinate;
1090 if (!b)
1091 continue;
1092
9e8bf93a 1093 __pci_bus_assign_resources(b, realloc_head, fail_head);
1da177e4
LT
1094
1095 switch (dev->class >> 8) {
1096 case PCI_CLASS_BRIDGE_PCI:
6841ec68
YL
1097 if (!pci_is_enabled(dev))
1098 pci_setup_bridge(b);
1da177e4
LT
1099 break;
1100
1101 case PCI_CLASS_BRIDGE_CARDBUS:
1102 pci_setup_cardbus(b);
1103 break;
1104
1105 default:
80ccba11
BH
1106 dev_info(&dev->dev, "not setting up bridge for bus "
1107 "%04x:%02x\n", pci_domain_nr(b), b->number);
1da177e4
LT
1108 break;
1109 }
1110 }
1111}
568ddef8
YL
1112
1113void __ref pci_bus_assign_resources(const struct pci_bus *bus)
1114{
c8adf9a3 1115 __pci_bus_assign_resources(bus, NULL, NULL);
568ddef8 1116}
1da177e4
LT
1117EXPORT_SYMBOL(pci_bus_assign_resources);
1118
6841ec68 1119static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
bdc4abec
YL
1120 struct list_head *add_head,
1121 struct list_head *fail_head)
6841ec68
YL
1122{
1123 struct pci_bus *b;
1124
8424d759
YL
1125 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1126 add_head, fail_head);
6841ec68
YL
1127
1128 b = bridge->subordinate;
1129 if (!b)
1130 return;
1131
8424d759 1132 __pci_bus_assign_resources(b, add_head, fail_head);
6841ec68
YL
1133
1134 switch (bridge->class >> 8) {
1135 case PCI_CLASS_BRIDGE_PCI:
1136 pci_setup_bridge(b);
1137 break;
1138
1139 case PCI_CLASS_BRIDGE_CARDBUS:
1140 pci_setup_cardbus(b);
1141 break;
1142
1143 default:
1144 dev_info(&bridge->dev, "not setting up bridge for bus "
1145 "%04x:%02x\n", pci_domain_nr(b), b->number);
1146 break;
1147 }
1148}
5009b460
YL
1149static void pci_bridge_release_resources(struct pci_bus *bus,
1150 unsigned long type)
1151{
1152 int idx;
1153 bool changed = false;
1154 struct pci_dev *dev;
1155 struct resource *r;
1156 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1157 IORESOURCE_PREFETCH;
1158
1159 dev = bus->self;
1160 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
1161 idx++) {
1162 r = &dev->resource[idx];
1163 if ((r->flags & type_mask) != type)
1164 continue;
1165 if (!r->parent)
1166 continue;
1167 /*
1168 * if there are children under that, we should release them
1169 * all
1170 */
1171 release_child_resources(r);
1172 if (!release_resource(r)) {
1173 dev_printk(KERN_DEBUG, &dev->dev,
1174 "resource %d %pR released\n", idx, r);
1175 /* keep the old size */
1176 r->end = resource_size(r) - 1;
1177 r->start = 0;
1178 r->flags = 0;
1179 changed = true;
1180 }
1181 }
1182
1183 if (changed) {
1184 /* avoiding touch the one without PREF */
1185 if (type & IORESOURCE_PREFETCH)
1186 type = IORESOURCE_PREFETCH;
1187 __pci_setup_bridge(bus, type);
1188 }
1189}
1190
1191enum release_type {
1192 leaf_only,
1193 whole_subtree,
1194};
1195/*
1196 * try to release pci bridge resources that is from leaf bridge,
1197 * so we can allocate big new one later
1198 */
1199static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
1200 unsigned long type,
1201 enum release_type rel_type)
1202{
1203 struct pci_dev *dev;
1204 bool is_leaf_bridge = true;
1205
1206 list_for_each_entry(dev, &bus->devices, bus_list) {
1207 struct pci_bus *b = dev->subordinate;
1208 if (!b)
1209 continue;
1210
1211 is_leaf_bridge = false;
1212
1213 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1214 continue;
1215
1216 if (rel_type == whole_subtree)
1217 pci_bus_release_bridge_resources(b, type,
1218 whole_subtree);
1219 }
1220
1221 if (pci_is_root_bus(bus))
1222 return;
1223
1224 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1225 return;
1226
1227 if ((rel_type == whole_subtree) || is_leaf_bridge)
1228 pci_bridge_release_resources(bus, type);
1229}
1230
76fbc263
YL
1231static void pci_bus_dump_res(struct pci_bus *bus)
1232{
89a74ecc
BH
1233 struct resource *res;
1234 int i;
7c9342b8 1235
89a74ecc 1236 pci_bus_for_each_resource(bus, res, i) {
7c9342b8 1237 if (!res || !res->end || !res->flags)
76fbc263
YL
1238 continue;
1239
c7dabef8 1240 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
76fbc263
YL
1241 }
1242}
1243
1244static void pci_bus_dump_resources(struct pci_bus *bus)
1245{
1246 struct pci_bus *b;
1247 struct pci_dev *dev;
1248
1249
1250 pci_bus_dump_res(bus);
1251
1252 list_for_each_entry(dev, &bus->devices, bus_list) {
1253 b = dev->subordinate;
1254 if (!b)
1255 continue;
1256
1257 pci_bus_dump_resources(b);
1258 }
1259}
1260
da7822e5
YL
1261static int __init pci_bus_get_depth(struct pci_bus *bus)
1262{
1263 int depth = 0;
1264 struct pci_dev *dev;
1265
1266 list_for_each_entry(dev, &bus->devices, bus_list) {
1267 int ret;
1268 struct pci_bus *b = dev->subordinate;
1269 if (!b)
1270 continue;
1271
1272 ret = pci_bus_get_depth(b);
1273 if (ret + 1 > depth)
1274 depth = ret + 1;
1275 }
1276
1277 return depth;
1278}
1279static int __init pci_get_max_depth(void)
1280{
1281 int depth = 0;
1282 struct pci_bus *bus;
1283
1284 list_for_each_entry(bus, &pci_root_buses, node) {
1285 int ret;
1286
1287 ret = pci_bus_get_depth(bus);
1288 if (ret > depth)
1289 depth = ret;
1290 }
1291
1292 return depth;
1293}
1294
b55438fd
YL
1295/*
1296 * -1: undefined, will auto detect later
1297 * 0: disabled by user
1298 * 1: disabled by auto detect
1299 * 2: enabled by user
1300 * 3: enabled by auto detect
1301 */
1302enum enable_type {
1303 undefined = -1,
1304 user_disabled,
1305 auto_disabled,
1306 user_enabled,
1307 auto_enabled,
1308};
1309
1310static enum enable_type pci_realloc_enable __initdata = undefined;
1311void __init pci_realloc_get_opt(char *str)
1312{
1313 if (!strncmp(str, "off", 3))
1314 pci_realloc_enable = user_disabled;
1315 else if (!strncmp(str, "on", 2))
1316 pci_realloc_enable = user_enabled;
1317}
1318static bool __init pci_realloc_enabled(void)
1319{
1320 return pci_realloc_enable >= user_enabled;
1321}
f483d392 1322
b07f2ebc
YL
1323static void __init pci_realloc_detect(void)
1324{
1325#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1326 struct pci_dev *dev = NULL;
1327
1328 if (pci_realloc_enable != undefined)
1329 return;
1330
1331 for_each_pci_dev(dev) {
1332 int i;
1333
1334 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1335 struct resource *r = &dev->resource[i];
1336
1337 /* Not assigned, or rejected by kernel ? */
1338 if (r->flags && !r->start) {
1339 pci_realloc_enable = auto_enabled;
1340
1341 return;
1342 }
1343 }
1344 }
1345#endif
1346}
1347
da7822e5
YL
1348/*
1349 * first try will not touch pci bridge res
1350 * second and later try will clear small leaf bridge res
1351 * will stop till to the max deepth if can not find good one
1352 */
1da177e4
LT
1353void __init
1354pci_assign_unassigned_resources(void)
1355{
1356 struct pci_bus *bus;
bdc4abec 1357 LIST_HEAD(realloc_head); /* list of resources that
c8adf9a3 1358 want additional resources */
bdc4abec 1359 struct list_head *add_list = NULL;
da7822e5
YL
1360 int tried_times = 0;
1361 enum release_type rel_type = leaf_only;
bdc4abec 1362 LIST_HEAD(fail_head);
b9b0bba9 1363 struct pci_dev_resource *fail_res;
da7822e5
YL
1364 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1365 IORESOURCE_PREFETCH;
19aa7ee4 1366 int pci_try_num = 1;
da7822e5 1367
19aa7ee4 1368 /* don't realloc if asked to do so */
b07f2ebc 1369 pci_realloc_detect();
19aa7ee4
YL
1370 if (pci_realloc_enabled()) {
1371 int max_depth = pci_get_max_depth();
1372
1373 pci_try_num = max_depth + 1;
1374 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1375 max_depth, pci_try_num);
1376 }
da7822e5
YL
1377
1378again:
19aa7ee4
YL
1379 /*
1380 * last try will use add_list, otherwise will try good to have as
1381 * must have, so can realloc parent bridge resource
1382 */
1383 if (tried_times + 1 == pci_try_num)
bdc4abec 1384 add_list = &realloc_head;
1da177e4
LT
1385 /* Depth first, calculate sizes and alignments of all
1386 subordinate buses. */
da7822e5 1387 list_for_each_entry(bus, &pci_root_buses, node)
19aa7ee4 1388 __pci_bus_size_bridges(bus, add_list);
c8adf9a3 1389
1da177e4 1390 /* Depth last, allocate resources and update the hardware. */
da7822e5 1391 list_for_each_entry(bus, &pci_root_buses, node)
bdc4abec 1392 __pci_bus_assign_resources(bus, add_list, &fail_head);
19aa7ee4 1393 if (add_list)
bdc4abec 1394 BUG_ON(!list_empty(add_list));
da7822e5
YL
1395 tried_times++;
1396
1397 /* any device complain? */
bdc4abec 1398 if (list_empty(&fail_head))
da7822e5 1399 goto enable_and_dump;
f483d392 1400
0c5be0cb 1401 if (tried_times >= pci_try_num) {
eb572e7c
YL
1402 if (pci_realloc_enable == undefined)
1403 printk(KERN_INFO "Some PCI device resources are unassigned, try booting with pci=realloc\n");
b07f2ebc
YL
1404 else if (pci_realloc_enable == auto_enabled)
1405 printk(KERN_INFO "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
eb572e7c 1406
bffc56d4 1407 free_list(&fail_head);
da7822e5
YL
1408 goto enable_and_dump;
1409 }
1410
1411 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1412 tried_times + 1);
1413
1414 /* third times and later will not check if it is leaf */
1415 if ((tried_times + 1) > 2)
1416 rel_type = whole_subtree;
1417
1418 /*
1419 * Try to release leaf bridge's resources that doesn't fit resource of
1420 * child device under that bridge
1421 */
b9b0bba9
YL
1422 list_for_each_entry(fail_res, &fail_head, list) {
1423 bus = fail_res->dev->bus;
bdc4abec 1424 pci_bus_release_bridge_resources(bus,
b9b0bba9 1425 fail_res->flags & type_mask,
bdc4abec 1426 rel_type);
da7822e5
YL
1427 }
1428 /* restore size and flags */
b9b0bba9
YL
1429 list_for_each_entry(fail_res, &fail_head, list) {
1430 struct resource *res = fail_res->res;
da7822e5 1431
b9b0bba9
YL
1432 res->start = fail_res->start;
1433 res->end = fail_res->end;
1434 res->flags = fail_res->flags;
1435 if (fail_res->dev->subordinate)
da7822e5 1436 res->flags = 0;
da7822e5 1437 }
bffc56d4 1438 free_list(&fail_head);
da7822e5
YL
1439
1440 goto again;
1441
1442enable_and_dump:
1443 /* Depth last, update the hardware. */
1444 list_for_each_entry(bus, &pci_root_buses, node)
1445 pci_enable_bridges(bus);
76fbc263
YL
1446
1447 /* dump the resource on buses */
da7822e5 1448 list_for_each_entry(bus, &pci_root_buses, node)
76fbc263 1449 pci_bus_dump_resources(bus);
1da177e4 1450}
6841ec68
YL
1451
1452void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1453{
1454 struct pci_bus *parent = bridge->subordinate;
bdc4abec 1455 LIST_HEAD(add_list); /* list of resources that
8424d759 1456 want additional resources */
32180e40 1457 int tried_times = 0;
bdc4abec 1458 LIST_HEAD(fail_head);
b9b0bba9 1459 struct pci_dev_resource *fail_res;
6841ec68 1460 int retval;
32180e40
YL
1461 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1462 IORESOURCE_PREFETCH;
1463
32180e40 1464again:
8424d759 1465 __pci_bus_size_bridges(parent, &add_list);
bdc4abec
YL
1466 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1467 BUG_ON(!list_empty(&add_list));
32180e40
YL
1468 tried_times++;
1469
bdc4abec 1470 if (list_empty(&fail_head))
3f579c34 1471 goto enable_all;
32180e40
YL
1472
1473 if (tried_times >= 2) {
1474 /* still fail, don't need to try more */
bffc56d4 1475 free_list(&fail_head);
3f579c34 1476 goto enable_all;
32180e40
YL
1477 }
1478
1479 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1480 tried_times + 1);
1481
1482 /*
1483 * Try to release leaf bridge's resources that doesn't fit resource of
1484 * child device under that bridge
1485 */
b9b0bba9
YL
1486 list_for_each_entry(fail_res, &fail_head, list) {
1487 struct pci_bus *bus = fail_res->dev->bus;
1488 unsigned long flags = fail_res->flags;
32180e40
YL
1489
1490 pci_bus_release_bridge_resources(bus, flags & type_mask,
1491 whole_subtree);
32180e40
YL
1492 }
1493 /* restore size and flags */
b9b0bba9
YL
1494 list_for_each_entry(fail_res, &fail_head, list) {
1495 struct resource *res = fail_res->res;
32180e40 1496
b9b0bba9
YL
1497 res->start = fail_res->start;
1498 res->end = fail_res->end;
1499 res->flags = fail_res->flags;
1500 if (fail_res->dev->subordinate)
32180e40 1501 res->flags = 0;
32180e40 1502 }
bffc56d4 1503 free_list(&fail_head);
32180e40
YL
1504
1505 goto again;
3f579c34
YL
1506
1507enable_all:
1508 retval = pci_reenable_device(bridge);
1509 pci_set_master(bridge);
1510 pci_enable_bridges(parent);
6841ec68
YL
1511}
1512EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
9b03088f
YL
1513
1514#ifdef CONFIG_HOTPLUG
1515/**
1516 * pci_rescan_bus - scan a PCI bus for devices.
1517 * @bus: PCI bus to scan
1518 *
1519 * Scan a PCI bus and child buses for new devices, adds them,
1520 * and enables them.
1521 *
1522 * Returns the max number of subordinate bus discovered.
1523 */
1524unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1525{
1526 unsigned int max;
1527 struct pci_dev *dev;
bdc4abec 1528 LIST_HEAD(add_list); /* list of resources that
9b03088f
YL
1529 want additional resources */
1530
1531 max = pci_scan_child_bus(bus);
1532
9b03088f
YL
1533 down_read(&pci_bus_sem);
1534 list_for_each_entry(dev, &bus->devices, bus_list)
1535 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1536 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1537 if (dev->subordinate)
1538 __pci_bus_size_bridges(dev->subordinate,
1539 &add_list);
1540 up_read(&pci_bus_sem);
1541 __pci_bus_assign_resources(bus, &add_list, NULL);
bdc4abec 1542 BUG_ON(!list_empty(&add_list));
9b03088f
YL
1543
1544 pci_enable_bridges(bus);
1545 pci_bus_add_devices(bus);
1546
1547 return max;
1548}
1549EXPORT_SYMBOL_GPL(pci_rescan_bus);
1550#endif
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