Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
6faf17f6 | 28 | #include "pci.h" |
1da177e4 | 29 | |
568ddef8 YL |
30 | struct resource_list_x { |
31 | struct resource_list_x *next; | |
32 | struct resource *res; | |
33 | struct pci_dev *dev; | |
34 | resource_size_t start; | |
35 | resource_size_t end; | |
c8adf9a3 | 36 | resource_size_t add_size; |
568ddef8 YL |
37 | unsigned long flags; |
38 | }; | |
39 | ||
094732a5 RP |
40 | #define free_list(type, head) do { \ |
41 | struct type *list, *tmp; \ | |
42 | for (list = (head)->next; list;) { \ | |
43 | tmp = list; \ | |
44 | list = list->next; \ | |
45 | kfree(tmp); \ | |
46 | } \ | |
47 | (head)->next = NULL; \ | |
48 | } while (0) | |
49 | ||
f483d392 RP |
50 | int pci_realloc_enable = 0; |
51 | #define pci_realloc_enabled() pci_realloc_enable | |
52 | void pci_realloc(void) | |
53 | { | |
54 | pci_realloc_enable = 1; | |
55 | } | |
56 | ||
c8adf9a3 RP |
57 | /** |
58 | * add_to_list() - add a new resource tracker to the list | |
59 | * @head: Head of the list | |
60 | * @dev: device corresponding to which the resource | |
61 | * belongs | |
62 | * @res: The resource to be tracked | |
63 | * @add_size: additional size to be optionally added | |
64 | * to the resource | |
65 | */ | |
66 | static void add_to_list(struct resource_list_x *head, | |
67 | struct pci_dev *dev, struct resource *res, | |
68 | resource_size_t add_size) | |
568ddef8 YL |
69 | { |
70 | struct resource_list_x *list = head; | |
71 | struct resource_list_x *ln = list->next; | |
72 | struct resource_list_x *tmp; | |
73 | ||
74 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
75 | if (!tmp) { | |
c8adf9a3 | 76 | pr_warning("add_to_list: kmalloc() failed!\n"); |
568ddef8 YL |
77 | return; |
78 | } | |
79 | ||
80 | tmp->next = ln; | |
81 | tmp->res = res; | |
82 | tmp->dev = dev; | |
83 | tmp->start = res->start; | |
84 | tmp->end = res->end; | |
85 | tmp->flags = res->flags; | |
c8adf9a3 | 86 | tmp->add_size = add_size; |
568ddef8 YL |
87 | list->next = tmp; |
88 | } | |
89 | ||
c8adf9a3 RP |
90 | static void add_to_failed_list(struct resource_list_x *head, |
91 | struct pci_dev *dev, struct resource *res) | |
92 | { | |
93 | add_to_list(head, dev, res, 0); | |
94 | } | |
95 | ||
6841ec68 YL |
96 | static void __dev_sort_resources(struct pci_dev *dev, |
97 | struct resource_list *head) | |
1da177e4 | 98 | { |
6841ec68 | 99 | u16 class = dev->class >> 8; |
1da177e4 | 100 | |
6841ec68 YL |
101 | /* Don't touch classless devices or host bridges or ioapics. */ |
102 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
103 | return; | |
1da177e4 | 104 | |
6841ec68 YL |
105 | /* Don't touch ioapic devices already enabled by firmware */ |
106 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
107 | u16 command; | |
108 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
109 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
110 | return; | |
111 | } | |
1da177e4 | 112 | |
6841ec68 YL |
113 | pdev_sort_resources(dev, head); |
114 | } | |
23186279 | 115 | |
fc075e1d RP |
116 | static inline void reset_resource(struct resource *res) |
117 | { | |
118 | res->start = 0; | |
119 | res->end = 0; | |
120 | res->flags = 0; | |
121 | } | |
122 | ||
c8adf9a3 RP |
123 | /** |
124 | * adjust_resources_sorted() - satisfy any additional resource requests | |
125 | * | |
126 | * @add_head : head of the list tracking requests requiring additional | |
127 | * resources | |
128 | * @head : head of the list tracking requests with allocated | |
129 | * resources | |
130 | * | |
131 | * Walk through each element of the add_head and try to procure | |
132 | * additional resources for the element, provided the element | |
133 | * is in the head list. | |
134 | */ | |
135 | static void adjust_resources_sorted(struct resource_list_x *add_head, | |
136 | struct resource_list *head) | |
6841ec68 YL |
137 | { |
138 | struct resource *res; | |
c8adf9a3 RP |
139 | struct resource_list_x *list, *tmp, *prev; |
140 | struct resource_list *hlist; | |
141 | resource_size_t add_size; | |
6841ec68 | 142 | int idx; |
1da177e4 | 143 | |
c8adf9a3 RP |
144 | prev = add_head; |
145 | for (list = add_head->next; list;) { | |
1da177e4 | 146 | res = list->res; |
c8adf9a3 RP |
147 | /* skip resource that has been reset */ |
148 | if (!res->flags) | |
149 | goto out; | |
150 | ||
151 | /* skip this resource if not found in head list */ | |
152 | for (hlist = head->next; hlist && hlist->res != res; | |
153 | hlist = hlist->next); | |
154 | if (!hlist) { /* just skip */ | |
155 | prev = list; | |
156 | list = list->next; | |
157 | continue; | |
158 | } | |
159 | ||
1da177e4 | 160 | idx = res - &list->dev->resource[0]; |
c8adf9a3 RP |
161 | add_size=list->add_size; |
162 | if (!resource_size(res) && add_size) { | |
163 | res->end = res->start + add_size - 1; | |
164 | if(pci_assign_resource(list->dev, idx)) | |
165 | reset_resource(res); | |
166 | } else if (add_size) { | |
167 | adjust_resource(res, res->start, | |
168 | resource_size(res) + add_size); | |
169 | } | |
170 | out: | |
171 | tmp = list; | |
172 | prev->next = list = list->next; | |
173 | kfree(tmp); | |
174 | } | |
175 | } | |
176 | ||
177 | /** | |
178 | * assign_requested_resources_sorted() - satisfy resource requests | |
179 | * | |
180 | * @head : head of the list tracking requests for resources | |
181 | * @failed_list : head of the list tracking requests that could | |
182 | * not be allocated | |
183 | * | |
184 | * Satisfy resource requests of each element in the list. Add | |
185 | * requests that could not satisfied to the failed_list. | |
186 | */ | |
187 | static void assign_requested_resources_sorted(struct resource_list *head, | |
188 | struct resource_list_x *fail_head) | |
189 | { | |
190 | struct resource *res; | |
191 | struct resource_list *list; | |
192 | int idx; | |
9a928660 | 193 | |
c8adf9a3 RP |
194 | for (list = head->next; list; list = list->next) { |
195 | res = list->res; | |
196 | idx = res - &list->dev->resource[0]; | |
197 | if (resource_size(res) && pci_assign_resource(list->dev, idx)) { | |
9a928660 YL |
198 | if (fail_head && !pci_is_root_bus(list->dev->bus)) { |
199 | /* | |
200 | * if the failed res is for ROM BAR, and it will | |
201 | * be enabled later, don't add it to the list | |
202 | */ | |
203 | if (!((idx == PCI_ROM_RESOURCE) && | |
204 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
205 | add_to_failed_list(fail_head, list->dev, res); | |
206 | } | |
fc075e1d | 207 | reset_resource(res); |
542df5de | 208 | } |
1da177e4 LT |
209 | } |
210 | } | |
211 | ||
c8adf9a3 RP |
212 | static void __assign_resources_sorted(struct resource_list *head, |
213 | struct resource_list_x *add_head, | |
214 | struct resource_list_x *fail_head) | |
215 | { | |
216 | /* Satisfy the must-have resource requests */ | |
217 | assign_requested_resources_sorted(head, fail_head); | |
218 | ||
219 | /* Try to satisfy any additional nice-to-have resource | |
220 | requests */ | |
221 | if (add_head) | |
222 | adjust_resources_sorted(add_head, head); | |
223 | free_list(resource_list, head); | |
224 | } | |
225 | ||
6841ec68 YL |
226 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
227 | struct resource_list_x *fail_head) | |
228 | { | |
229 | struct resource_list head; | |
230 | ||
231 | head.next = NULL; | |
232 | __dev_sort_resources(dev, &head); | |
c8adf9a3 | 233 | __assign_resources_sorted(&head, NULL, fail_head); |
6841ec68 YL |
234 | |
235 | } | |
236 | ||
237 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
c8adf9a3 | 238 | struct resource_list_x *add_head, |
6841ec68 YL |
239 | struct resource_list_x *fail_head) |
240 | { | |
241 | struct pci_dev *dev; | |
242 | struct resource_list head; | |
243 | ||
244 | head.next = NULL; | |
245 | list_for_each_entry(dev, &bus->devices, bus_list) | |
246 | __dev_sort_resources(dev, &head); | |
247 | ||
c8adf9a3 | 248 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
249 | } |
250 | ||
b3743fa4 | 251 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
252 | { |
253 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 254 | struct resource *res; |
1da177e4 LT |
255 | struct pci_bus_region region; |
256 | ||
865df576 BH |
257 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
258 | bus->secondary, bus->subordinate); | |
1da177e4 | 259 | |
c7dabef8 BH |
260 | res = bus->resource[0]; |
261 | pcibios_resource_to_bus(bridge, ®ion, res); | |
262 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
263 | /* |
264 | * The IO resource is allocated a range twice as large as it | |
265 | * would normally need. This allows us to set both IO regs. | |
266 | */ | |
c7dabef8 | 267 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
268 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
269 | region.start); | |
270 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
271 | region.end); | |
272 | } | |
273 | ||
c7dabef8 BH |
274 | res = bus->resource[1]; |
275 | pcibios_resource_to_bus(bridge, ®ion, res); | |
276 | if (res->flags & IORESOURCE_IO) { | |
277 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
278 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
279 | region.start); | |
280 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
281 | region.end); | |
282 | } | |
283 | ||
c7dabef8 BH |
284 | res = bus->resource[2]; |
285 | pcibios_resource_to_bus(bridge, ®ion, res); | |
286 | if (res->flags & IORESOURCE_MEM) { | |
287 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
288 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
289 | region.start); | |
290 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
291 | region.end); | |
292 | } | |
293 | ||
c7dabef8 BH |
294 | res = bus->resource[3]; |
295 | pcibios_resource_to_bus(bridge, ®ion, res); | |
296 | if (res->flags & IORESOURCE_MEM) { | |
297 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
298 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
299 | region.start); | |
300 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
301 | region.end); | |
302 | } | |
303 | } | |
b3743fa4 | 304 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
305 | |
306 | /* Initialize bridges with base/limit values we have collected. | |
307 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
308 | requires that if there is no I/O ports or memory behind the | |
309 | bridge, corresponding range must be turned off by writing base | |
310 | value greater than limit to the bridge's base/limit registers. | |
311 | ||
312 | Note: care must be taken when updating I/O base/limit registers | |
313 | of bridges which support 32-bit I/O. This update requires two | |
314 | config space writes, so it's quite possible that an I/O window of | |
315 | the bridge will have some undesirable address (e.g. 0) after the | |
316 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 317 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
318 | { |
319 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 320 | struct resource *res; |
1da177e4 | 321 | struct pci_bus_region region; |
7cc5997d | 322 | u32 l, io_upper16; |
1da177e4 LT |
323 | |
324 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
325 | res = bus->resource[0]; |
326 | pcibios_resource_to_bus(bridge, ®ion, res); | |
327 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
328 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
329 | l &= 0xffff0000; | |
330 | l |= (region.start >> 8) & 0x00f0; | |
331 | l |= region.end & 0xf000; | |
332 | /* Set up upper 16 bits of I/O base/limit. */ | |
333 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 334 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 335 | } else { |
1da177e4 LT |
336 | /* Clear upper 16 bits of I/O base/limit. */ |
337 | io_upper16 = 0; | |
338 | l = 0x00f0; | |
1da177e4 LT |
339 | } |
340 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
341 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
342 | /* Update lower 16 bits of I/O base/limit. */ | |
343 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
344 | /* Update upper 16 bits of I/O base/limit. */ | |
345 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
346 | } |
347 | ||
348 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
349 | { | |
350 | struct pci_dev *bridge = bus->self; | |
351 | struct resource *res; | |
352 | struct pci_bus_region region; | |
353 | u32 l; | |
1da177e4 | 354 | |
7cc5997d | 355 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
356 | res = bus->resource[1]; |
357 | pcibios_resource_to_bus(bridge, ®ion, res); | |
358 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
359 | l = (region.start >> 16) & 0xfff0; |
360 | l |= region.end & 0xfff00000; | |
c7dabef8 | 361 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 362 | } else { |
1da177e4 | 363 | l = 0x0000fff0; |
1da177e4 LT |
364 | } |
365 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
366 | } |
367 | ||
368 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
369 | { | |
370 | struct pci_dev *bridge = bus->self; | |
371 | struct resource *res; | |
372 | struct pci_bus_region region; | |
373 | u32 l, bu, lu; | |
1da177e4 LT |
374 | |
375 | /* Clear out the upper 32 bits of PREF limit. | |
376 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
377 | disables PREF range, which is ok. */ | |
378 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
379 | ||
380 | /* Set up PREF base/limit. */ | |
c40a22e0 | 381 | bu = lu = 0; |
c7dabef8 BH |
382 | res = bus->resource[2]; |
383 | pcibios_resource_to_bus(bridge, ®ion, res); | |
384 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
385 | l = (region.start >> 16) & 0xfff0; |
386 | l |= region.end & 0xfff00000; | |
c7dabef8 | 387 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
388 | bu = upper_32_bits(region.start); |
389 | lu = upper_32_bits(region.end); | |
1f82de10 | 390 | } |
c7dabef8 | 391 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 392 | } else { |
1da177e4 | 393 | l = 0x0000fff0; |
1da177e4 LT |
394 | } |
395 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
396 | ||
59353ea3 AW |
397 | /* Set the upper 32 bits of PREF base & limit. */ |
398 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
399 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
400 | } |
401 | ||
402 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
403 | { | |
404 | struct pci_dev *bridge = bus->self; | |
405 | ||
7cc5997d YL |
406 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
407 | bus->secondary, bus->subordinate); | |
408 | ||
409 | if (type & IORESOURCE_IO) | |
410 | pci_setup_bridge_io(bus); | |
411 | ||
412 | if (type & IORESOURCE_MEM) | |
413 | pci_setup_bridge_mmio(bus); | |
414 | ||
415 | if (type & IORESOURCE_PREFETCH) | |
416 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
417 | |
418 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
419 | } | |
420 | ||
7cc5997d YL |
421 | static void pci_setup_bridge(struct pci_bus *bus) |
422 | { | |
423 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
424 | IORESOURCE_PREFETCH; | |
425 | ||
426 | __pci_setup_bridge(bus, type); | |
427 | } | |
428 | ||
1da177e4 LT |
429 | /* Check whether the bridge supports optional I/O and |
430 | prefetchable memory ranges. If not, the respective | |
431 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 432 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
433 | { |
434 | u16 io; | |
435 | u32 pmem; | |
436 | struct pci_dev *bridge = bus->self; | |
437 | struct resource *b_res; | |
438 | ||
439 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
440 | b_res[1].flags |= IORESOURCE_MEM; | |
441 | ||
442 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
443 | if (!io) { | |
444 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
445 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
446 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
447 | } | |
448 | if (io) | |
449 | b_res[0].flags |= IORESOURCE_IO; | |
450 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
451 | disconnect boundary by one PCI data phase. | |
452 | Workaround: do not use prefetching on this device. */ | |
453 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
454 | return; | |
455 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
456 | if (!pmem) { | |
457 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
458 | 0xfff0fff0); | |
459 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
460 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
461 | } | |
1f82de10 | 462 | if (pmem) { |
1da177e4 | 463 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
464 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
465 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 466 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
467 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
468 | } | |
1f82de10 YL |
469 | } |
470 | ||
471 | /* double check if bridge does support 64 bit pref */ | |
472 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
473 | u32 mem_base_hi, tmp; | |
474 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
475 | &mem_base_hi); | |
476 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
477 | 0xffffffff); | |
478 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
479 | if (!tmp) | |
480 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
481 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
482 | mem_base_hi); | |
483 | } | |
1da177e4 LT |
484 | } |
485 | ||
486 | /* Helper function for sizing routines: find first available | |
487 | bus resource of a given type. Note: we intentionally skip | |
488 | the bus resources which have already been assigned (that is, | |
489 | have non-NULL parent resource). */ | |
96bde06a | 490 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
491 | { |
492 | int i; | |
493 | struct resource *r; | |
494 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
495 | IORESOURCE_PREFETCH; | |
496 | ||
89a74ecc | 497 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
498 | if (r == &ioport_resource || r == &iomem_resource) |
499 | continue; | |
55a10984 JB |
500 | if (r && (r->flags & type_mask) == type && !r->parent) |
501 | return r; | |
1da177e4 LT |
502 | } |
503 | return NULL; | |
504 | } | |
505 | ||
13583b16 RP |
506 | static resource_size_t calculate_iosize(resource_size_t size, |
507 | resource_size_t min_size, | |
508 | resource_size_t size1, | |
509 | resource_size_t old_size, | |
510 | resource_size_t align) | |
511 | { | |
512 | if (size < min_size) | |
513 | size = min_size; | |
514 | if (old_size == 1 ) | |
515 | old_size = 0; | |
516 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
517 | flag in the struct pci_bus. */ | |
518 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
519 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
520 | #endif | |
521 | size = ALIGN(size + size1, align); | |
522 | if (size < old_size) | |
523 | size = old_size; | |
524 | return size; | |
525 | } | |
526 | ||
527 | static resource_size_t calculate_memsize(resource_size_t size, | |
528 | resource_size_t min_size, | |
529 | resource_size_t size1, | |
530 | resource_size_t old_size, | |
531 | resource_size_t align) | |
532 | { | |
533 | if (size < min_size) | |
534 | size = min_size; | |
535 | if (old_size == 1 ) | |
536 | old_size = 0; | |
537 | if (size < old_size) | |
538 | size = old_size; | |
539 | size = ALIGN(size + size1, align); | |
540 | return size; | |
541 | } | |
542 | ||
c8adf9a3 RP |
543 | /** |
544 | * pbus_size_io() - size the io window of a given bus | |
545 | * | |
546 | * @bus : the bus | |
547 | * @min_size : the minimum io window that must to be allocated | |
548 | * @add_size : additional optional io window | |
549 | * @add_head : track the additional io window on this list | |
550 | * | |
551 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
552 | * since these windows have 4K granularity and the IO ranges | |
553 | * of non-bridge PCI devices are limited to 256 bytes. | |
554 | * We must be careful with the ISA aliasing though. | |
555 | */ | |
556 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
557 | resource_size_t add_size, struct resource_list_x *add_head) | |
1da177e4 LT |
558 | { |
559 | struct pci_dev *dev; | |
560 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 561 | unsigned long size = 0, size0 = 0, size1 = 0; |
1da177e4 LT |
562 | |
563 | if (!b_res) | |
564 | return; | |
565 | ||
566 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
567 | int i; | |
568 | ||
569 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
570 | struct resource *r = &dev->resource[i]; | |
571 | unsigned long r_size; | |
572 | ||
573 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
574 | continue; | |
022edd86 | 575 | r_size = resource_size(r); |
1da177e4 LT |
576 | |
577 | if (r_size < 0x400) | |
578 | /* Might be re-aligned for ISA */ | |
579 | size += r_size; | |
580 | else | |
581 | size1 += r_size; | |
582 | } | |
583 | } | |
c8adf9a3 RP |
584 | size0 = calculate_iosize(size, min_size, size1, |
585 | resource_size(b_res), 4096); | |
93d2175d | 586 | size1 = (!add_head || (add_head && !add_size)) ? size0 : |
c8adf9a3 | 587 | calculate_iosize(size, min_size+add_size, size1, |
13583b16 | 588 | resource_size(b_res), 4096); |
c8adf9a3 | 589 | if (!size0 && !size1) { |
865df576 BH |
590 | if (b_res->start || b_res->end) |
591 | dev_info(&bus->self->dev, "disabling bridge window " | |
592 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
593 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
594 | b_res->flags = 0; |
595 | return; | |
596 | } | |
597 | /* Alignment of the IO window is always 4K */ | |
598 | b_res->start = 4096; | |
c8adf9a3 | 599 | b_res->end = b_res->start + size0 - 1; |
88452565 | 600 | b_res->flags |= IORESOURCE_STARTALIGN; |
c8adf9a3 RP |
601 | if (size1 > size0 && add_head) |
602 | add_to_list(add_head, bus->self, b_res, size1-size0); | |
1da177e4 LT |
603 | } |
604 | ||
c8adf9a3 RP |
605 | /** |
606 | * pbus_size_mem() - size the memory window of a given bus | |
607 | * | |
608 | * @bus : the bus | |
609 | * @min_size : the minimum memory window that must to be allocated | |
610 | * @add_size : additional optional memory window | |
611 | * @add_head : track the additional memory window on this list | |
612 | * | |
613 | * Calculate the size of the bus and minimal alignment which | |
614 | * guarantees that all child resources fit in this size. | |
615 | */ | |
28760489 | 616 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
617 | unsigned long type, resource_size_t min_size, |
618 | resource_size_t add_size, | |
619 | struct resource_list_x *add_head) | |
1da177e4 LT |
620 | { |
621 | struct pci_dev *dev; | |
c8adf9a3 | 622 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 623 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
624 | int order, max_order; |
625 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 626 | unsigned int mem64_mask = 0; |
1da177e4 LT |
627 | |
628 | if (!b_res) | |
629 | return 0; | |
630 | ||
631 | memset(aligns, 0, sizeof(aligns)); | |
632 | max_order = 0; | |
633 | size = 0; | |
634 | ||
1f82de10 YL |
635 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
636 | b_res->flags &= ~IORESOURCE_MEM_64; | |
637 | ||
1da177e4 LT |
638 | list_for_each_entry(dev, &bus->devices, bus_list) { |
639 | int i; | |
1f82de10 | 640 | |
1da177e4 LT |
641 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
642 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 643 | resource_size_t r_size; |
1da177e4 LT |
644 | |
645 | if (r->parent || (r->flags & mask) != type) | |
646 | continue; | |
022edd86 | 647 | r_size = resource_size(r); |
1da177e4 | 648 | /* For bridges size != alignment */ |
6faf17f6 | 649 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
650 | order = __ffs(align) - 20; |
651 | if (order > 11) { | |
865df576 BH |
652 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
653 | "(bad alignment %#llx)\n", i, r, | |
654 | (unsigned long long) align); | |
1da177e4 LT |
655 | r->flags = 0; |
656 | continue; | |
657 | } | |
658 | size += r_size; | |
659 | if (order < 0) | |
660 | order = 0; | |
661 | /* Exclude ranges with size > align from | |
662 | calculation of the alignment. */ | |
663 | if (r_size == align) | |
664 | aligns[order] += align; | |
665 | if (order > max_order) | |
666 | max_order = order; | |
1f82de10 | 667 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
1da177e4 LT |
668 | } |
669 | } | |
1da177e4 LT |
670 | align = 0; |
671 | min_align = 0; | |
672 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
673 | resource_size_t align1 = 1; |
674 | ||
675 | align1 <<= (order + 20); | |
676 | ||
1da177e4 LT |
677 | if (!align) |
678 | min_align = align1; | |
6f6f8c2f | 679 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
680 | min_align = align1 >> 1; |
681 | align += aligns[order]; | |
682 | } | |
b42282e5 | 683 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
93d2175d | 684 | size1 = (!add_head || (add_head && !add_size)) ? size0 : |
c8adf9a3 | 685 | calculate_memsize(size, min_size+add_size, 0, |
b42282e5 | 686 | resource_size(b_res), min_align); |
c8adf9a3 | 687 | if (!size0 && !size1) { |
865df576 BH |
688 | if (b_res->start || b_res->end) |
689 | dev_info(&bus->self->dev, "disabling bridge window " | |
690 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
691 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
692 | b_res->flags = 0; |
693 | return 1; | |
694 | } | |
695 | b_res->start = min_align; | |
c8adf9a3 RP |
696 | b_res->end = size0 + min_align - 1; |
697 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
698 | if (size1 > size0 && add_head) | |
699 | add_to_list(add_head, bus->self, b_res, size1-size0); | |
1da177e4 LT |
700 | return 1; |
701 | } | |
702 | ||
5468ae61 | 703 | static void pci_bus_size_cardbus(struct pci_bus *bus) |
1da177e4 LT |
704 | { |
705 | struct pci_dev *bridge = bus->self; | |
706 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
707 | u16 ctrl; | |
708 | ||
709 | /* | |
710 | * Reserve some resources for CardBus. We reserve | |
711 | * a fixed amount of bus space for CardBus bridges. | |
712 | */ | |
934b7024 LT |
713 | b_res[0].start = 0; |
714 | b_res[0].end = pci_cardbus_io_size - 1; | |
715 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 | 716 | |
934b7024 LT |
717 | b_res[1].start = 0; |
718 | b_res[1].end = pci_cardbus_io_size - 1; | |
719 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
720 | |
721 | /* | |
722 | * Check whether prefetchable memory is supported | |
723 | * by this bridge. | |
724 | */ | |
725 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
726 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
727 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
728 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
729 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
730 | } | |
731 | ||
732 | /* | |
733 | * If we have prefetchable memory support, allocate | |
734 | * two regions. Otherwise, allocate one region of | |
735 | * twice the size. | |
736 | */ | |
737 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
934b7024 LT |
738 | b_res[2].start = 0; |
739 | b_res[2].end = pci_cardbus_mem_size - 1; | |
740 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; | |
1da177e4 | 741 | |
934b7024 LT |
742 | b_res[3].start = 0; |
743 | b_res[3].end = pci_cardbus_mem_size - 1; | |
744 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 | 745 | } else { |
934b7024 LT |
746 | b_res[3].start = 0; |
747 | b_res[3].end = pci_cardbus_mem_size * 2 - 1; | |
748 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; | |
1da177e4 LT |
749 | } |
750 | } | |
751 | ||
c8adf9a3 RP |
752 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
753 | struct resource_list_x *add_head) | |
1da177e4 LT |
754 | { |
755 | struct pci_dev *dev; | |
756 | unsigned long mask, prefmask; | |
c8adf9a3 | 757 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
758 | |
759 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
760 | struct pci_bus *b = dev->subordinate; | |
761 | if (!b) | |
762 | continue; | |
763 | ||
764 | switch (dev->class >> 8) { | |
765 | case PCI_CLASS_BRIDGE_CARDBUS: | |
766 | pci_bus_size_cardbus(b); | |
767 | break; | |
768 | ||
769 | case PCI_CLASS_BRIDGE_PCI: | |
770 | default: | |
c8adf9a3 | 771 | __pci_bus_size_bridges(b, add_head); |
1da177e4 LT |
772 | break; |
773 | } | |
774 | } | |
775 | ||
776 | /* The root bus? */ | |
777 | if (!bus->self) | |
778 | return; | |
779 | ||
780 | switch (bus->self->class >> 8) { | |
781 | case PCI_CLASS_BRIDGE_CARDBUS: | |
782 | /* don't size cardbuses yet. */ | |
783 | break; | |
784 | ||
785 | case PCI_CLASS_BRIDGE_PCI: | |
786 | pci_bridge_check_ranges(bus); | |
28760489 | 787 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
788 | additional_io_size = pci_hotplug_io_size; |
789 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 790 | } |
c8adf9a3 RP |
791 | /* |
792 | * Follow thru | |
793 | */ | |
1da177e4 | 794 | default: |
c8adf9a3 | 795 | pbus_size_io(bus, 0, additional_io_size, add_head); |
1da177e4 LT |
796 | /* If the bridge supports prefetchable range, size it |
797 | separately. If it doesn't, or its prefetchable window | |
798 | has already been allocated by arch code, try | |
799 | non-prefetchable range for both types of PCI memory | |
800 | resources. */ | |
801 | mask = IORESOURCE_MEM; | |
802 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
c8adf9a3 | 803 | if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head)) |
1da177e4 | 804 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 805 | else |
c8adf9a3 RP |
806 | additional_mem_size += additional_mem_size; |
807 | pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head); | |
1da177e4 LT |
808 | break; |
809 | } | |
810 | } | |
c8adf9a3 RP |
811 | |
812 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
813 | { | |
814 | __pci_bus_size_bridges(bus, NULL); | |
815 | } | |
1da177e4 LT |
816 | EXPORT_SYMBOL(pci_bus_size_bridges); |
817 | ||
568ddef8 | 818 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
c8adf9a3 | 819 | struct resource_list_x *add_head, |
568ddef8 | 820 | struct resource_list_x *fail_head) |
1da177e4 LT |
821 | { |
822 | struct pci_bus *b; | |
823 | struct pci_dev *dev; | |
824 | ||
c8adf9a3 | 825 | pbus_assign_resources_sorted(bus, add_head, fail_head); |
1da177e4 | 826 | |
1da177e4 LT |
827 | list_for_each_entry(dev, &bus->devices, bus_list) { |
828 | b = dev->subordinate; | |
829 | if (!b) | |
830 | continue; | |
831 | ||
c8adf9a3 | 832 | __pci_bus_assign_resources(b, add_head, fail_head); |
1da177e4 LT |
833 | |
834 | switch (dev->class >> 8) { | |
835 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
836 | if (!pci_is_enabled(dev)) |
837 | pci_setup_bridge(b); | |
1da177e4 LT |
838 | break; |
839 | ||
840 | case PCI_CLASS_BRIDGE_CARDBUS: | |
841 | pci_setup_cardbus(b); | |
842 | break; | |
843 | ||
844 | default: | |
80ccba11 BH |
845 | dev_info(&dev->dev, "not setting up bridge for bus " |
846 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
847 | break; |
848 | } | |
849 | } | |
850 | } | |
568ddef8 YL |
851 | |
852 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
853 | { | |
c8adf9a3 | 854 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 855 | } |
1da177e4 LT |
856 | EXPORT_SYMBOL(pci_bus_assign_resources); |
857 | ||
6841ec68 YL |
858 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
859 | struct resource_list_x *fail_head) | |
860 | { | |
861 | struct pci_bus *b; | |
862 | ||
863 | pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head); | |
864 | ||
865 | b = bridge->subordinate; | |
866 | if (!b) | |
867 | return; | |
868 | ||
c8adf9a3 | 869 | __pci_bus_assign_resources(b, NULL, fail_head); |
6841ec68 YL |
870 | |
871 | switch (bridge->class >> 8) { | |
872 | case PCI_CLASS_BRIDGE_PCI: | |
873 | pci_setup_bridge(b); | |
874 | break; | |
875 | ||
876 | case PCI_CLASS_BRIDGE_CARDBUS: | |
877 | pci_setup_cardbus(b); | |
878 | break; | |
879 | ||
880 | default: | |
881 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
882 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
883 | break; | |
884 | } | |
885 | } | |
5009b460 YL |
886 | static void pci_bridge_release_resources(struct pci_bus *bus, |
887 | unsigned long type) | |
888 | { | |
889 | int idx; | |
890 | bool changed = false; | |
891 | struct pci_dev *dev; | |
892 | struct resource *r; | |
893 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
894 | IORESOURCE_PREFETCH; | |
895 | ||
896 | dev = bus->self; | |
897 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
898 | idx++) { | |
899 | r = &dev->resource[idx]; | |
900 | if ((r->flags & type_mask) != type) | |
901 | continue; | |
902 | if (!r->parent) | |
903 | continue; | |
904 | /* | |
905 | * if there are children under that, we should release them | |
906 | * all | |
907 | */ | |
908 | release_child_resources(r); | |
909 | if (!release_resource(r)) { | |
910 | dev_printk(KERN_DEBUG, &dev->dev, | |
911 | "resource %d %pR released\n", idx, r); | |
912 | /* keep the old size */ | |
913 | r->end = resource_size(r) - 1; | |
914 | r->start = 0; | |
915 | r->flags = 0; | |
916 | changed = true; | |
917 | } | |
918 | } | |
919 | ||
920 | if (changed) { | |
921 | /* avoiding touch the one without PREF */ | |
922 | if (type & IORESOURCE_PREFETCH) | |
923 | type = IORESOURCE_PREFETCH; | |
924 | __pci_setup_bridge(bus, type); | |
925 | } | |
926 | } | |
927 | ||
928 | enum release_type { | |
929 | leaf_only, | |
930 | whole_subtree, | |
931 | }; | |
932 | /* | |
933 | * try to release pci bridge resources that is from leaf bridge, | |
934 | * so we can allocate big new one later | |
935 | */ | |
936 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
937 | unsigned long type, | |
938 | enum release_type rel_type) | |
939 | { | |
940 | struct pci_dev *dev; | |
941 | bool is_leaf_bridge = true; | |
942 | ||
943 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
944 | struct pci_bus *b = dev->subordinate; | |
945 | if (!b) | |
946 | continue; | |
947 | ||
948 | is_leaf_bridge = false; | |
949 | ||
950 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
951 | continue; | |
952 | ||
953 | if (rel_type == whole_subtree) | |
954 | pci_bus_release_bridge_resources(b, type, | |
955 | whole_subtree); | |
956 | } | |
957 | ||
958 | if (pci_is_root_bus(bus)) | |
959 | return; | |
960 | ||
961 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
962 | return; | |
963 | ||
964 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
965 | pci_bridge_release_resources(bus, type); | |
966 | } | |
967 | ||
76fbc263 YL |
968 | static void pci_bus_dump_res(struct pci_bus *bus) |
969 | { | |
89a74ecc BH |
970 | struct resource *res; |
971 | int i; | |
7c9342b8 | 972 | |
89a74ecc | 973 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 974 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
975 | continue; |
976 | ||
c7dabef8 | 977 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
978 | } |
979 | } | |
980 | ||
981 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
982 | { | |
983 | struct pci_bus *b; | |
984 | struct pci_dev *dev; | |
985 | ||
986 | ||
987 | pci_bus_dump_res(bus); | |
988 | ||
989 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
990 | b = dev->subordinate; | |
991 | if (!b) | |
992 | continue; | |
993 | ||
994 | pci_bus_dump_resources(b); | |
995 | } | |
996 | } | |
997 | ||
da7822e5 YL |
998 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
999 | { | |
1000 | int depth = 0; | |
1001 | struct pci_dev *dev; | |
1002 | ||
1003 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1004 | int ret; | |
1005 | struct pci_bus *b = dev->subordinate; | |
1006 | if (!b) | |
1007 | continue; | |
1008 | ||
1009 | ret = pci_bus_get_depth(b); | |
1010 | if (ret + 1 > depth) | |
1011 | depth = ret + 1; | |
1012 | } | |
1013 | ||
1014 | return depth; | |
1015 | } | |
1016 | static int __init pci_get_max_depth(void) | |
1017 | { | |
1018 | int depth = 0; | |
1019 | struct pci_bus *bus; | |
1020 | ||
1021 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1022 | int ret; | |
1023 | ||
1024 | ret = pci_bus_get_depth(bus); | |
1025 | if (ret > depth) | |
1026 | depth = ret; | |
1027 | } | |
1028 | ||
1029 | return depth; | |
1030 | } | |
1031 | ||
f483d392 | 1032 | |
da7822e5 YL |
1033 | /* |
1034 | * first try will not touch pci bridge res | |
1035 | * second and later try will clear small leaf bridge res | |
1036 | * will stop till to the max deepth if can not find good one | |
1037 | */ | |
1da177e4 LT |
1038 | void __init |
1039 | pci_assign_unassigned_resources(void) | |
1040 | { | |
1041 | struct pci_bus *bus; | |
c8adf9a3 RP |
1042 | struct resource_list_x add_list; /* list of resources that |
1043 | want additional resources */ | |
da7822e5 YL |
1044 | int tried_times = 0; |
1045 | enum release_type rel_type = leaf_only; | |
1046 | struct resource_list_x head, *list; | |
1047 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1048 | IORESOURCE_PREFETCH; | |
1049 | unsigned long failed_type; | |
1050 | int max_depth = pci_get_max_depth(); | |
1051 | int pci_try_num; | |
1052 | ||
1053 | ||
1054 | head.next = NULL; | |
c8adf9a3 | 1055 | add_list.next = NULL; |
da7822e5 YL |
1056 | |
1057 | pci_try_num = max_depth + 1; | |
1058 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1059 | max_depth, pci_try_num); | |
1060 | ||
1061 | again: | |
1da177e4 LT |
1062 | /* Depth first, calculate sizes and alignments of all |
1063 | subordinate buses. */ | |
da7822e5 | 1064 | list_for_each_entry(bus, &pci_root_buses, node) |
c8adf9a3 | 1065 | __pci_bus_size_bridges(bus, &add_list); |
c8adf9a3 | 1066 | |
1da177e4 | 1067 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 YL |
1068 | list_for_each_entry(bus, &pci_root_buses, node) |
1069 | __pci_bus_assign_resources(bus, &add_list, &head); | |
c8adf9a3 | 1070 | BUG_ON(add_list.next); |
da7822e5 YL |
1071 | tried_times++; |
1072 | ||
1073 | /* any device complain? */ | |
1074 | if (!head.next) | |
1075 | goto enable_and_dump; | |
f483d392 RP |
1076 | |
1077 | /* don't realloc if asked to do so */ | |
1078 | if (!pci_realloc_enabled()) { | |
1079 | free_list(resource_list_x, &head); | |
1080 | goto enable_and_dump; | |
1081 | } | |
1082 | ||
da7822e5 YL |
1083 | failed_type = 0; |
1084 | for (list = head.next; list;) { | |
1085 | failed_type |= list->flags; | |
1086 | list = list->next; | |
1087 | } | |
1088 | /* | |
1089 | * io port are tight, don't try extra | |
1090 | * or if reach the limit, don't want to try more | |
1091 | */ | |
1092 | failed_type &= type_mask; | |
1093 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
1094 | free_list(resource_list_x, &head); | |
1095 | goto enable_and_dump; | |
1096 | } | |
1097 | ||
1098 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1099 | tried_times + 1); | |
1100 | ||
1101 | /* third times and later will not check if it is leaf */ | |
1102 | if ((tried_times + 1) > 2) | |
1103 | rel_type = whole_subtree; | |
1104 | ||
1105 | /* | |
1106 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1107 | * child device under that bridge | |
1108 | */ | |
1109 | for (list = head.next; list;) { | |
1110 | bus = list->dev->bus; | |
1111 | pci_bus_release_bridge_resources(bus, list->flags & type_mask, | |
1112 | rel_type); | |
1113 | list = list->next; | |
1114 | } | |
1115 | /* restore size and flags */ | |
1116 | for (list = head.next; list;) { | |
1117 | struct resource *res = list->res; | |
1118 | ||
1119 | res->start = list->start; | |
1120 | res->end = list->end; | |
1121 | res->flags = list->flags; | |
1122 | if (list->dev->subordinate) | |
1123 | res->flags = 0; | |
1124 | ||
1125 | list = list->next; | |
1126 | } | |
1127 | free_list(resource_list_x, &head); | |
1128 | ||
1129 | goto again; | |
1130 | ||
1131 | enable_and_dump: | |
1132 | /* Depth last, update the hardware. */ | |
1133 | list_for_each_entry(bus, &pci_root_buses, node) | |
1134 | pci_enable_bridges(bus); | |
76fbc263 YL |
1135 | |
1136 | /* dump the resource on buses */ | |
da7822e5 | 1137 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1138 | pci_bus_dump_resources(bus); |
1da177e4 | 1139 | } |
6841ec68 YL |
1140 | |
1141 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1142 | { | |
1143 | struct pci_bus *parent = bridge->subordinate; | |
32180e40 YL |
1144 | int tried_times = 0; |
1145 | struct resource_list_x head, *list; | |
6841ec68 | 1146 | int retval; |
32180e40 YL |
1147 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1148 | IORESOURCE_PREFETCH; | |
1149 | ||
1150 | head.next = NULL; | |
6841ec68 | 1151 | |
32180e40 | 1152 | again: |
6841ec68 | 1153 | pci_bus_size_bridges(parent); |
32180e40 | 1154 | __pci_bridge_assign_resources(bridge, &head); |
32180e40 YL |
1155 | |
1156 | tried_times++; | |
1157 | ||
1158 | if (!head.next) | |
3f579c34 | 1159 | goto enable_all; |
32180e40 YL |
1160 | |
1161 | if (tried_times >= 2) { | |
1162 | /* still fail, don't need to try more */ | |
094732a5 | 1163 | free_list(resource_list_x, &head); |
3f579c34 | 1164 | goto enable_all; |
32180e40 YL |
1165 | } |
1166 | ||
1167 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1168 | tried_times + 1); | |
1169 | ||
1170 | /* | |
1171 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1172 | * child device under that bridge | |
1173 | */ | |
1174 | for (list = head.next; list;) { | |
1175 | struct pci_bus *bus = list->dev->bus; | |
1176 | unsigned long flags = list->flags; | |
1177 | ||
1178 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1179 | whole_subtree); | |
1180 | list = list->next; | |
1181 | } | |
1182 | /* restore size and flags */ | |
1183 | for (list = head.next; list;) { | |
1184 | struct resource *res = list->res; | |
1185 | ||
1186 | res->start = list->start; | |
1187 | res->end = list->end; | |
1188 | res->flags = list->flags; | |
1189 | if (list->dev->subordinate) | |
1190 | res->flags = 0; | |
1191 | ||
1192 | list = list->next; | |
1193 | } | |
094732a5 | 1194 | free_list(resource_list_x, &head); |
32180e40 YL |
1195 | |
1196 | goto again; | |
3f579c34 YL |
1197 | |
1198 | enable_all: | |
1199 | retval = pci_reenable_device(bridge); | |
1200 | pci_set_master(bridge); | |
1201 | pci_enable_bridges(parent); | |
6841ec68 YL |
1202 | } |
1203 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); |