Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * drivers/pci/setup-bus.c | |
3 | * | |
4 | * Extruded from code written by | |
5 | * Dave Rusling (david.rusling@reo.mts.dec.com) | |
6 | * David Mosberger (davidm@cs.arizona.edu) | |
7 | * David Miller (davem@redhat.com) | |
8 | * | |
9 | * Support routines for initializing a PCI subsystem. | |
10 | */ | |
11 | ||
12 | /* | |
13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
14 | * PCI-PCI bridges cleanup, sorted resource allocation. | |
15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> | |
16 | * Converted to allocation in 3 passes, which gives | |
17 | * tighter packing. Prefetchable range support. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/cache.h> | |
27 | #include <linux/slab.h> | |
47087700 | 28 | #include <asm-generic/pci-bridge.h> |
6faf17f6 | 29 | #include "pci.h" |
1da177e4 | 30 | |
47087700 BH |
31 | unsigned int __weak pci_flags; |
32 | ||
bdc4abec YL |
33 | struct pci_dev_resource { |
34 | struct list_head list; | |
2934a0de YL |
35 | struct resource *res; |
36 | struct pci_dev *dev; | |
568ddef8 YL |
37 | resource_size_t start; |
38 | resource_size_t end; | |
c8adf9a3 | 39 | resource_size_t add_size; |
2bbc6942 | 40 | resource_size_t min_align; |
568ddef8 YL |
41 | unsigned long flags; |
42 | }; | |
43 | ||
bffc56d4 YL |
44 | static void free_list(struct list_head *head) |
45 | { | |
46 | struct pci_dev_resource *dev_res, *tmp; | |
47 | ||
48 | list_for_each_entry_safe(dev_res, tmp, head, list) { | |
49 | list_del(&dev_res->list); | |
50 | kfree(dev_res); | |
51 | } | |
52 | } | |
094732a5 | 53 | |
f483d392 RP |
54 | int pci_realloc_enable = 0; |
55 | #define pci_realloc_enabled() pci_realloc_enable | |
56 | void pci_realloc(void) | |
57 | { | |
58 | pci_realloc_enable = 1; | |
59 | } | |
60 | ||
c8adf9a3 RP |
61 | /** |
62 | * add_to_list() - add a new resource tracker to the list | |
63 | * @head: Head of the list | |
64 | * @dev: device corresponding to which the resource | |
65 | * belongs | |
66 | * @res: The resource to be tracked | |
67 | * @add_size: additional size to be optionally added | |
68 | * to the resource | |
69 | */ | |
bdc4abec | 70 | static int add_to_list(struct list_head *head, |
c8adf9a3 | 71 | struct pci_dev *dev, struct resource *res, |
2bbc6942 | 72 | resource_size_t add_size, resource_size_t min_align) |
568ddef8 | 73 | { |
764242a0 | 74 | struct pci_dev_resource *tmp; |
568ddef8 | 75 | |
bdc4abec | 76 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
568ddef8 | 77 | if (!tmp) { |
c8adf9a3 | 78 | pr_warning("add_to_list: kmalloc() failed!\n"); |
ef62dfef | 79 | return -ENOMEM; |
568ddef8 YL |
80 | } |
81 | ||
568ddef8 YL |
82 | tmp->res = res; |
83 | tmp->dev = dev; | |
84 | tmp->start = res->start; | |
85 | tmp->end = res->end; | |
86 | tmp->flags = res->flags; | |
c8adf9a3 | 87 | tmp->add_size = add_size; |
2bbc6942 | 88 | tmp->min_align = min_align; |
bdc4abec YL |
89 | |
90 | list_add(&tmp->list, head); | |
ef62dfef YL |
91 | |
92 | return 0; | |
568ddef8 YL |
93 | } |
94 | ||
b9b0bba9 | 95 | static void remove_from_list(struct list_head *head, |
3e6e0d80 YL |
96 | struct resource *res) |
97 | { | |
b9b0bba9 | 98 | struct pci_dev_resource *dev_res, *tmp; |
3e6e0d80 | 99 | |
b9b0bba9 YL |
100 | list_for_each_entry_safe(dev_res, tmp, head, list) { |
101 | if (dev_res->res == res) { | |
102 | list_del(&dev_res->list); | |
103 | kfree(dev_res); | |
bdc4abec | 104 | break; |
3e6e0d80 | 105 | } |
3e6e0d80 YL |
106 | } |
107 | } | |
108 | ||
b9b0bba9 | 109 | static resource_size_t get_res_add_size(struct list_head *head, |
1c372353 YL |
110 | struct resource *res) |
111 | { | |
b9b0bba9 | 112 | struct pci_dev_resource *dev_res; |
bdc4abec | 113 | |
b9b0bba9 YL |
114 | list_for_each_entry(dev_res, head, list) { |
115 | if (dev_res->res == res) { | |
b592443d YL |
116 | int idx = res - &dev_res->dev->resource[0]; |
117 | ||
b9b0bba9 | 118 | dev_printk(KERN_DEBUG, &dev_res->dev->dev, |
b592443d YL |
119 | "res[%d]=%pR get_res_add_size add_size %llx\n", |
120 | idx, dev_res->res, | |
b9b0bba9 | 121 | (unsigned long long)dev_res->add_size); |
b592443d | 122 | |
b9b0bba9 | 123 | return dev_res->add_size; |
bdc4abec | 124 | } |
3e6e0d80 | 125 | } |
1c372353 YL |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
78c3b329 | 130 | /* Sort resources by alignment */ |
bdc4abec | 131 | static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head) |
78c3b329 YL |
132 | { |
133 | int i; | |
134 | ||
135 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
136 | struct resource *r; | |
bdc4abec | 137 | struct pci_dev_resource *dev_res, *tmp; |
78c3b329 | 138 | resource_size_t r_align; |
bdc4abec | 139 | struct list_head *n; |
78c3b329 YL |
140 | |
141 | r = &dev->resource[i]; | |
142 | ||
143 | if (r->flags & IORESOURCE_PCI_FIXED) | |
144 | continue; | |
145 | ||
146 | if (!(r->flags) || r->parent) | |
147 | continue; | |
148 | ||
149 | r_align = pci_resource_alignment(dev, r); | |
150 | if (!r_align) { | |
151 | dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n", | |
152 | i, r); | |
153 | continue; | |
154 | } | |
78c3b329 | 155 | |
bdc4abec YL |
156 | tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); |
157 | if (!tmp) | |
158 | panic("pdev_sort_resources(): " | |
159 | "kmalloc() failed!\n"); | |
160 | tmp->res = r; | |
161 | tmp->dev = dev; | |
162 | ||
163 | /* fallback is smallest one or list is empty*/ | |
164 | n = head; | |
165 | list_for_each_entry(dev_res, head, list) { | |
166 | resource_size_t align; | |
167 | ||
168 | align = pci_resource_alignment(dev_res->dev, | |
169 | dev_res->res); | |
78c3b329 YL |
170 | |
171 | if (r_align > align) { | |
bdc4abec | 172 | n = &dev_res->list; |
78c3b329 YL |
173 | break; |
174 | } | |
175 | } | |
bdc4abec YL |
176 | /* Insert it just before n*/ |
177 | list_add_tail(&tmp->list, n); | |
78c3b329 YL |
178 | } |
179 | } | |
180 | ||
6841ec68 | 181 | static void __dev_sort_resources(struct pci_dev *dev, |
bdc4abec | 182 | struct list_head *head) |
1da177e4 | 183 | { |
6841ec68 | 184 | u16 class = dev->class >> 8; |
1da177e4 | 185 | |
6841ec68 YL |
186 | /* Don't touch classless devices or host bridges or ioapics. */ |
187 | if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST) | |
188 | return; | |
1da177e4 | 189 | |
6841ec68 YL |
190 | /* Don't touch ioapic devices already enabled by firmware */ |
191 | if (class == PCI_CLASS_SYSTEM_PIC) { | |
192 | u16 command; | |
193 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
194 | if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | |
195 | return; | |
196 | } | |
1da177e4 | 197 | |
6841ec68 YL |
198 | pdev_sort_resources(dev, head); |
199 | } | |
23186279 | 200 | |
fc075e1d RP |
201 | static inline void reset_resource(struct resource *res) |
202 | { | |
203 | res->start = 0; | |
204 | res->end = 0; | |
205 | res->flags = 0; | |
206 | } | |
207 | ||
c8adf9a3 | 208 | /** |
9e8bf93a | 209 | * reassign_resources_sorted() - satisfy any additional resource requests |
c8adf9a3 | 210 | * |
9e8bf93a | 211 | * @realloc_head : head of the list tracking requests requiring additional |
c8adf9a3 RP |
212 | * resources |
213 | * @head : head of the list tracking requests with allocated | |
214 | * resources | |
215 | * | |
9e8bf93a | 216 | * Walk through each element of the realloc_head and try to procure |
c8adf9a3 RP |
217 | * additional resources for the element, provided the element |
218 | * is in the head list. | |
219 | */ | |
bdc4abec YL |
220 | static void reassign_resources_sorted(struct list_head *realloc_head, |
221 | struct list_head *head) | |
6841ec68 YL |
222 | { |
223 | struct resource *res; | |
b9b0bba9 | 224 | struct pci_dev_resource *add_res, *tmp; |
bdc4abec | 225 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 226 | resource_size_t add_size; |
6841ec68 | 227 | int idx; |
1da177e4 | 228 | |
b9b0bba9 | 229 | list_for_each_entry_safe(add_res, tmp, realloc_head, list) { |
bdc4abec YL |
230 | bool found_match = false; |
231 | ||
b9b0bba9 | 232 | res = add_res->res; |
c8adf9a3 RP |
233 | /* skip resource that has been reset */ |
234 | if (!res->flags) | |
235 | goto out; | |
236 | ||
237 | /* skip this resource if not found in head list */ | |
bdc4abec YL |
238 | list_for_each_entry(dev_res, head, list) { |
239 | if (dev_res->res == res) { | |
240 | found_match = true; | |
241 | break; | |
242 | } | |
c8adf9a3 | 243 | } |
bdc4abec YL |
244 | if (!found_match)/* just skip */ |
245 | continue; | |
c8adf9a3 | 246 | |
b9b0bba9 YL |
247 | idx = res - &add_res->dev->resource[0]; |
248 | add_size = add_res->add_size; | |
2bbc6942 | 249 | if (!resource_size(res)) { |
b9b0bba9 | 250 | res->start = add_res->start; |
2bbc6942 | 251 | res->end = res->start + add_size - 1; |
b9b0bba9 | 252 | if (pci_assign_resource(add_res->dev, idx)) |
c8adf9a3 | 253 | reset_resource(res); |
2bbc6942 | 254 | } else { |
b9b0bba9 YL |
255 | resource_size_t align = add_res->min_align; |
256 | res->flags |= add_res->flags & | |
bdc4abec | 257 | (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN); |
b9b0bba9 | 258 | if (pci_reassign_resource(add_res->dev, idx, |
bdc4abec | 259 | add_size, align)) |
b9b0bba9 | 260 | dev_printk(KERN_DEBUG, &add_res->dev->dev, |
b592443d YL |
261 | "failed to add %llx res[%d]=%pR\n", |
262 | (unsigned long long)add_size, | |
263 | idx, res); | |
c8adf9a3 RP |
264 | } |
265 | out: | |
b9b0bba9 YL |
266 | list_del(&add_res->list); |
267 | kfree(add_res); | |
c8adf9a3 RP |
268 | } |
269 | } | |
270 | ||
271 | /** | |
272 | * assign_requested_resources_sorted() - satisfy resource requests | |
273 | * | |
274 | * @head : head of the list tracking requests for resources | |
275 | * @failed_list : head of the list tracking requests that could | |
276 | * not be allocated | |
277 | * | |
278 | * Satisfy resource requests of each element in the list. Add | |
279 | * requests that could not satisfied to the failed_list. | |
280 | */ | |
bdc4abec YL |
281 | static void assign_requested_resources_sorted(struct list_head *head, |
282 | struct list_head *fail_head) | |
c8adf9a3 RP |
283 | { |
284 | struct resource *res; | |
bdc4abec | 285 | struct pci_dev_resource *dev_res; |
c8adf9a3 | 286 | int idx; |
9a928660 | 287 | |
bdc4abec YL |
288 | list_for_each_entry(dev_res, head, list) { |
289 | res = dev_res->res; | |
290 | idx = res - &dev_res->dev->resource[0]; | |
291 | if (resource_size(res) && | |
292 | pci_assign_resource(dev_res->dev, idx)) { | |
293 | if (fail_head && !pci_is_root_bus(dev_res->dev->bus)) { | |
9a928660 YL |
294 | /* |
295 | * if the failed res is for ROM BAR, and it will | |
296 | * be enabled later, don't add it to the list | |
297 | */ | |
298 | if (!((idx == PCI_ROM_RESOURCE) && | |
299 | (!(res->flags & IORESOURCE_ROM_ENABLE)))) | |
67cc7e26 YL |
300 | add_to_list(fail_head, |
301 | dev_res->dev, res, | |
302 | 0 /* dont care */, | |
303 | 0 /* dont care */); | |
9a928660 | 304 | } |
fc075e1d | 305 | reset_resource(res); |
542df5de | 306 | } |
1da177e4 LT |
307 | } |
308 | } | |
309 | ||
bdc4abec YL |
310 | static void __assign_resources_sorted(struct list_head *head, |
311 | struct list_head *realloc_head, | |
312 | struct list_head *fail_head) | |
c8adf9a3 | 313 | { |
3e6e0d80 YL |
314 | /* |
315 | * Should not assign requested resources at first. | |
316 | * they could be adjacent, so later reassign can not reallocate | |
317 | * them one by one in parent resource window. | |
318 | * Try to assign requested + add_size at begining | |
319 | * if could do that, could get out early. | |
320 | * if could not do that, we still try to assign requested at first, | |
321 | * then try to reassign add_size for some resources. | |
322 | */ | |
bdc4abec YL |
323 | LIST_HEAD(save_head); |
324 | LIST_HEAD(local_fail_head); | |
b9b0bba9 | 325 | struct pci_dev_resource *save_res; |
bdc4abec | 326 | struct pci_dev_resource *dev_res; |
3e6e0d80 YL |
327 | |
328 | /* Check if optional add_size is there */ | |
bdc4abec | 329 | if (!realloc_head || list_empty(realloc_head)) |
3e6e0d80 YL |
330 | goto requested_and_reassign; |
331 | ||
332 | /* Save original start, end, flags etc at first */ | |
bdc4abec YL |
333 | list_for_each_entry(dev_res, head, list) { |
334 | if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) { | |
bffc56d4 | 335 | free_list(&save_head); |
3e6e0d80 YL |
336 | goto requested_and_reassign; |
337 | } | |
bdc4abec | 338 | } |
3e6e0d80 YL |
339 | |
340 | /* Update res in head list with add_size in realloc_head list */ | |
bdc4abec YL |
341 | list_for_each_entry(dev_res, head, list) |
342 | dev_res->res->end += get_res_add_size(realloc_head, | |
343 | dev_res->res); | |
3e6e0d80 YL |
344 | |
345 | /* Try updated head list with add_size added */ | |
3e6e0d80 YL |
346 | assign_requested_resources_sorted(head, &local_fail_head); |
347 | ||
348 | /* all assigned with add_size ? */ | |
bdc4abec | 349 | if (list_empty(&local_fail_head)) { |
3e6e0d80 | 350 | /* Remove head list from realloc_head list */ |
bdc4abec YL |
351 | list_for_each_entry(dev_res, head, list) |
352 | remove_from_list(realloc_head, dev_res->res); | |
bffc56d4 YL |
353 | free_list(&save_head); |
354 | free_list(head); | |
3e6e0d80 YL |
355 | return; |
356 | } | |
357 | ||
bffc56d4 | 358 | free_list(&local_fail_head); |
3e6e0d80 | 359 | /* Release assigned resource */ |
bdc4abec YL |
360 | list_for_each_entry(dev_res, head, list) |
361 | if (dev_res->res->parent) | |
362 | release_resource(dev_res->res); | |
3e6e0d80 | 363 | /* Restore start/end/flags from saved list */ |
b9b0bba9 YL |
364 | list_for_each_entry(save_res, &save_head, list) { |
365 | struct resource *res = save_res->res; | |
3e6e0d80 | 366 | |
b9b0bba9 YL |
367 | res->start = save_res->start; |
368 | res->end = save_res->end; | |
369 | res->flags = save_res->flags; | |
3e6e0d80 | 370 | } |
bffc56d4 | 371 | free_list(&save_head); |
3e6e0d80 YL |
372 | |
373 | requested_and_reassign: | |
c8adf9a3 RP |
374 | /* Satisfy the must-have resource requests */ |
375 | assign_requested_resources_sorted(head, fail_head); | |
376 | ||
0a2daa1c | 377 | /* Try to satisfy any additional optional resource |
c8adf9a3 | 378 | requests */ |
9e8bf93a RP |
379 | if (realloc_head) |
380 | reassign_resources_sorted(realloc_head, head); | |
bffc56d4 | 381 | free_list(head); |
c8adf9a3 RP |
382 | } |
383 | ||
6841ec68 | 384 | static void pdev_assign_resources_sorted(struct pci_dev *dev, |
bdc4abec YL |
385 | struct list_head *add_head, |
386 | struct list_head *fail_head) | |
6841ec68 | 387 | { |
bdc4abec | 388 | LIST_HEAD(head); |
6841ec68 | 389 | |
6841ec68 | 390 | __dev_sort_resources(dev, &head); |
8424d759 | 391 | __assign_resources_sorted(&head, add_head, fail_head); |
6841ec68 YL |
392 | |
393 | } | |
394 | ||
395 | static void pbus_assign_resources_sorted(const struct pci_bus *bus, | |
bdc4abec YL |
396 | struct list_head *realloc_head, |
397 | struct list_head *fail_head) | |
6841ec68 YL |
398 | { |
399 | struct pci_dev *dev; | |
bdc4abec | 400 | LIST_HEAD(head); |
6841ec68 | 401 | |
6841ec68 YL |
402 | list_for_each_entry(dev, &bus->devices, bus_list) |
403 | __dev_sort_resources(dev, &head); | |
404 | ||
9e8bf93a | 405 | __assign_resources_sorted(&head, realloc_head, fail_head); |
6841ec68 YL |
406 | } |
407 | ||
b3743fa4 | 408 | void pci_setup_cardbus(struct pci_bus *bus) |
1da177e4 LT |
409 | { |
410 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 411 | struct resource *res; |
1da177e4 LT |
412 | struct pci_bus_region region; |
413 | ||
865df576 BH |
414 | dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", |
415 | bus->secondary, bus->subordinate); | |
1da177e4 | 416 | |
c7dabef8 BH |
417 | res = bus->resource[0]; |
418 | pcibios_resource_to_bus(bridge, ®ion, res); | |
419 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
420 | /* |
421 | * The IO resource is allocated a range twice as large as it | |
422 | * would normally need. This allows us to set both IO regs. | |
423 | */ | |
c7dabef8 | 424 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
1da177e4 LT |
425 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
426 | region.start); | |
427 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, | |
428 | region.end); | |
429 | } | |
430 | ||
c7dabef8 BH |
431 | res = bus->resource[1]; |
432 | pcibios_resource_to_bus(bridge, ®ion, res); | |
433 | if (res->flags & IORESOURCE_IO) { | |
434 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
435 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
436 | region.start); | |
437 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, | |
438 | region.end); | |
439 | } | |
440 | ||
c7dabef8 BH |
441 | res = bus->resource[2]; |
442 | pcibios_resource_to_bus(bridge, ®ion, res); | |
443 | if (res->flags & IORESOURCE_MEM) { | |
444 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
445 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
446 | region.start); | |
447 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, | |
448 | region.end); | |
449 | } | |
450 | ||
c7dabef8 BH |
451 | res = bus->resource[3]; |
452 | pcibios_resource_to_bus(bridge, ®ion, res); | |
453 | if (res->flags & IORESOURCE_MEM) { | |
454 | dev_info(&bridge->dev, " bridge window %pR\n", res); | |
1da177e4 LT |
455 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
456 | region.start); | |
457 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, | |
458 | region.end); | |
459 | } | |
460 | } | |
b3743fa4 | 461 | EXPORT_SYMBOL(pci_setup_cardbus); |
1da177e4 LT |
462 | |
463 | /* Initialize bridges with base/limit values we have collected. | |
464 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) | |
465 | requires that if there is no I/O ports or memory behind the | |
466 | bridge, corresponding range must be turned off by writing base | |
467 | value greater than limit to the bridge's base/limit registers. | |
468 | ||
469 | Note: care must be taken when updating I/O base/limit registers | |
470 | of bridges which support 32-bit I/O. This update requires two | |
471 | config space writes, so it's quite possible that an I/O window of | |
472 | the bridge will have some undesirable address (e.g. 0) after the | |
473 | first write. Ditto 64-bit prefetchable MMIO. */ | |
7cc5997d | 474 | static void pci_setup_bridge_io(struct pci_bus *bus) |
1da177e4 LT |
475 | { |
476 | struct pci_dev *bridge = bus->self; | |
c7dabef8 | 477 | struct resource *res; |
1da177e4 | 478 | struct pci_bus_region region; |
7cc5997d | 479 | u32 l, io_upper16; |
1da177e4 LT |
480 | |
481 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ | |
c7dabef8 BH |
482 | res = bus->resource[0]; |
483 | pcibios_resource_to_bus(bridge, ®ion, res); | |
484 | if (res->flags & IORESOURCE_IO) { | |
1da177e4 LT |
485 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
486 | l &= 0xffff0000; | |
487 | l |= (region.start >> 8) & 0x00f0; | |
488 | l |= region.end & 0xf000; | |
489 | /* Set up upper 16 bits of I/O base/limit. */ | |
490 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); | |
c7dabef8 | 491 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 492 | } else { |
1da177e4 LT |
493 | /* Clear upper 16 bits of I/O base/limit. */ |
494 | io_upper16 = 0; | |
495 | l = 0x00f0; | |
1da177e4 LT |
496 | } |
497 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ | |
498 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); | |
499 | /* Update lower 16 bits of I/O base/limit. */ | |
500 | pci_write_config_dword(bridge, PCI_IO_BASE, l); | |
501 | /* Update upper 16 bits of I/O base/limit. */ | |
502 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); | |
7cc5997d YL |
503 | } |
504 | ||
505 | static void pci_setup_bridge_mmio(struct pci_bus *bus) | |
506 | { | |
507 | struct pci_dev *bridge = bus->self; | |
508 | struct resource *res; | |
509 | struct pci_bus_region region; | |
510 | u32 l; | |
1da177e4 | 511 | |
7cc5997d | 512 | /* Set up the top and bottom of the PCI Memory segment for this bus. */ |
c7dabef8 BH |
513 | res = bus->resource[1]; |
514 | pcibios_resource_to_bus(bridge, ®ion, res); | |
515 | if (res->flags & IORESOURCE_MEM) { | |
1da177e4 LT |
516 | l = (region.start >> 16) & 0xfff0; |
517 | l |= region.end & 0xfff00000; | |
c7dabef8 | 518 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 519 | } else { |
1da177e4 | 520 | l = 0x0000fff0; |
1da177e4 LT |
521 | } |
522 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); | |
7cc5997d YL |
523 | } |
524 | ||
525 | static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) | |
526 | { | |
527 | struct pci_dev *bridge = bus->self; | |
528 | struct resource *res; | |
529 | struct pci_bus_region region; | |
530 | u32 l, bu, lu; | |
1da177e4 LT |
531 | |
532 | /* Clear out the upper 32 bits of PREF limit. | |
533 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily | |
534 | disables PREF range, which is ok. */ | |
535 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); | |
536 | ||
537 | /* Set up PREF base/limit. */ | |
c40a22e0 | 538 | bu = lu = 0; |
c7dabef8 BH |
539 | res = bus->resource[2]; |
540 | pcibios_resource_to_bus(bridge, ®ion, res); | |
541 | if (res->flags & IORESOURCE_PREFETCH) { | |
1da177e4 LT |
542 | l = (region.start >> 16) & 0xfff0; |
543 | l |= region.end & 0xfff00000; | |
c7dabef8 | 544 | if (res->flags & IORESOURCE_MEM_64) { |
1f82de10 YL |
545 | bu = upper_32_bits(region.start); |
546 | lu = upper_32_bits(region.end); | |
1f82de10 | 547 | } |
c7dabef8 | 548 | dev_info(&bridge->dev, " bridge window %pR\n", res); |
7cc5997d | 549 | } else { |
1da177e4 | 550 | l = 0x0000fff0; |
1da177e4 LT |
551 | } |
552 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); | |
553 | ||
59353ea3 AW |
554 | /* Set the upper 32 bits of PREF base & limit. */ |
555 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); | |
556 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); | |
7cc5997d YL |
557 | } |
558 | ||
559 | static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) | |
560 | { | |
561 | struct pci_dev *bridge = bus->self; | |
562 | ||
7cc5997d YL |
563 | dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", |
564 | bus->secondary, bus->subordinate); | |
565 | ||
566 | if (type & IORESOURCE_IO) | |
567 | pci_setup_bridge_io(bus); | |
568 | ||
569 | if (type & IORESOURCE_MEM) | |
570 | pci_setup_bridge_mmio(bus); | |
571 | ||
572 | if (type & IORESOURCE_PREFETCH) | |
573 | pci_setup_bridge_mmio_pref(bus); | |
1da177e4 LT |
574 | |
575 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); | |
576 | } | |
577 | ||
e2444273 | 578 | void pci_setup_bridge(struct pci_bus *bus) |
7cc5997d YL |
579 | { |
580 | unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | | |
581 | IORESOURCE_PREFETCH; | |
582 | ||
583 | __pci_setup_bridge(bus, type); | |
584 | } | |
585 | ||
1da177e4 LT |
586 | /* Check whether the bridge supports optional I/O and |
587 | prefetchable memory ranges. If not, the respective | |
588 | base/limit registers must be read-only and read as 0. */ | |
96bde06a | 589 | static void pci_bridge_check_ranges(struct pci_bus *bus) |
1da177e4 LT |
590 | { |
591 | u16 io; | |
592 | u32 pmem; | |
593 | struct pci_dev *bridge = bus->self; | |
594 | struct resource *b_res; | |
595 | ||
596 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
597 | b_res[1].flags |= IORESOURCE_MEM; | |
598 | ||
599 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
600 | if (!io) { | |
601 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); | |
602 | pci_read_config_word(bridge, PCI_IO_BASE, &io); | |
603 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); | |
604 | } | |
605 | if (io) | |
606 | b_res[0].flags |= IORESOURCE_IO; | |
607 | /* DECchip 21050 pass 2 errata: the bridge may miss an address | |
608 | disconnect boundary by one PCI data phase. | |
609 | Workaround: do not use prefetching on this device. */ | |
610 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) | |
611 | return; | |
612 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
613 | if (!pmem) { | |
614 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, | |
615 | 0xfff0fff0); | |
616 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); | |
617 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); | |
618 | } | |
1f82de10 | 619 | if (pmem) { |
1da177e4 | 620 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
99586105 YL |
621 | if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == |
622 | PCI_PREF_RANGE_TYPE_64) { | |
1f82de10 | 623 | b_res[2].flags |= IORESOURCE_MEM_64; |
99586105 YL |
624 | b_res[2].flags |= PCI_PREF_RANGE_TYPE_64; |
625 | } | |
1f82de10 YL |
626 | } |
627 | ||
628 | /* double check if bridge does support 64 bit pref */ | |
629 | if (b_res[2].flags & IORESOURCE_MEM_64) { | |
630 | u32 mem_base_hi, tmp; | |
631 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
632 | &mem_base_hi); | |
633 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
634 | 0xffffffff); | |
635 | pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); | |
636 | if (!tmp) | |
637 | b_res[2].flags &= ~IORESOURCE_MEM_64; | |
638 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, | |
639 | mem_base_hi); | |
640 | } | |
1da177e4 LT |
641 | } |
642 | ||
643 | /* Helper function for sizing routines: find first available | |
644 | bus resource of a given type. Note: we intentionally skip | |
645 | the bus resources which have already been assigned (that is, | |
646 | have non-NULL parent resource). */ | |
96bde06a | 647 | static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
1da177e4 LT |
648 | { |
649 | int i; | |
650 | struct resource *r; | |
651 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
652 | IORESOURCE_PREFETCH; | |
653 | ||
89a74ecc | 654 | pci_bus_for_each_resource(bus, r, i) { |
299de034 IK |
655 | if (r == &ioport_resource || r == &iomem_resource) |
656 | continue; | |
55a10984 JB |
657 | if (r && (r->flags & type_mask) == type && !r->parent) |
658 | return r; | |
1da177e4 LT |
659 | } |
660 | return NULL; | |
661 | } | |
662 | ||
13583b16 RP |
663 | static resource_size_t calculate_iosize(resource_size_t size, |
664 | resource_size_t min_size, | |
665 | resource_size_t size1, | |
666 | resource_size_t old_size, | |
667 | resource_size_t align) | |
668 | { | |
669 | if (size < min_size) | |
670 | size = min_size; | |
671 | if (old_size == 1 ) | |
672 | old_size = 0; | |
673 | /* To be fixed in 2.5: we should have sort of HAVE_ISA | |
674 | flag in the struct pci_bus. */ | |
675 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) | |
676 | size = (size & 0xff) + ((size & ~0xffUL) << 2); | |
677 | #endif | |
678 | size = ALIGN(size + size1, align); | |
679 | if (size < old_size) | |
680 | size = old_size; | |
681 | return size; | |
682 | } | |
683 | ||
684 | static resource_size_t calculate_memsize(resource_size_t size, | |
685 | resource_size_t min_size, | |
686 | resource_size_t size1, | |
687 | resource_size_t old_size, | |
688 | resource_size_t align) | |
689 | { | |
690 | if (size < min_size) | |
691 | size = min_size; | |
692 | if (old_size == 1 ) | |
693 | old_size = 0; | |
694 | if (size < old_size) | |
695 | size = old_size; | |
696 | size = ALIGN(size + size1, align); | |
697 | return size; | |
698 | } | |
699 | ||
c8adf9a3 RP |
700 | /** |
701 | * pbus_size_io() - size the io window of a given bus | |
702 | * | |
703 | * @bus : the bus | |
704 | * @min_size : the minimum io window that must to be allocated | |
705 | * @add_size : additional optional io window | |
9e8bf93a | 706 | * @realloc_head : track the additional io window on this list |
c8adf9a3 RP |
707 | * |
708 | * Sizing the IO windows of the PCI-PCI bridge is trivial, | |
709 | * since these windows have 4K granularity and the IO ranges | |
710 | * of non-bridge PCI devices are limited to 256 bytes. | |
711 | * We must be careful with the ISA aliasing though. | |
712 | */ | |
713 | static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size, | |
bdc4abec | 714 | resource_size_t add_size, struct list_head *realloc_head) |
1da177e4 LT |
715 | { |
716 | struct pci_dev *dev; | |
717 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); | |
c8adf9a3 | 718 | unsigned long size = 0, size0 = 0, size1 = 0; |
be768912 | 719 | resource_size_t children_add_size = 0; |
1da177e4 LT |
720 | |
721 | if (!b_res) | |
722 | return; | |
723 | ||
724 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
725 | int i; | |
726 | ||
727 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
728 | struct resource *r = &dev->resource[i]; | |
729 | unsigned long r_size; | |
730 | ||
731 | if (r->parent || !(r->flags & IORESOURCE_IO)) | |
732 | continue; | |
022edd86 | 733 | r_size = resource_size(r); |
1da177e4 LT |
734 | |
735 | if (r_size < 0x400) | |
736 | /* Might be re-aligned for ISA */ | |
737 | size += r_size; | |
738 | else | |
739 | size1 += r_size; | |
be768912 | 740 | |
9e8bf93a RP |
741 | if (realloc_head) |
742 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
743 | } |
744 | } | |
c8adf9a3 RP |
745 | size0 = calculate_iosize(size, min_size, size1, |
746 | resource_size(b_res), 4096); | |
be768912 YL |
747 | if (children_add_size > add_size) |
748 | add_size = children_add_size; | |
9e8bf93a | 749 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 750 | calculate_iosize(size, min_size, add_size + size1, |
13583b16 | 751 | resource_size(b_res), 4096); |
c8adf9a3 | 752 | if (!size0 && !size1) { |
865df576 BH |
753 | if (b_res->start || b_res->end) |
754 | dev_info(&bus->self->dev, "disabling bridge window " | |
755 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
756 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
757 | b_res->flags = 0; |
758 | return; | |
759 | } | |
760 | /* Alignment of the IO window is always 4K */ | |
761 | b_res->start = 4096; | |
c8adf9a3 | 762 | b_res->end = b_res->start + size0 - 1; |
88452565 | 763 | b_res->flags |= IORESOURCE_STARTALIGN; |
b592443d | 764 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 765 | add_to_list(realloc_head, bus->self, b_res, size1-size0, 4096); |
b592443d YL |
766 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
767 | "%pR to [bus %02x-%02x] add_size %lx\n", b_res, | |
768 | bus->secondary, bus->subordinate, size1-size0); | |
769 | } | |
1da177e4 LT |
770 | } |
771 | ||
c8adf9a3 RP |
772 | /** |
773 | * pbus_size_mem() - size the memory window of a given bus | |
774 | * | |
775 | * @bus : the bus | |
776 | * @min_size : the minimum memory window that must to be allocated | |
777 | * @add_size : additional optional memory window | |
9e8bf93a | 778 | * @realloc_head : track the additional memory window on this list |
c8adf9a3 RP |
779 | * |
780 | * Calculate the size of the bus and minimal alignment which | |
781 | * guarantees that all child resources fit in this size. | |
782 | */ | |
28760489 | 783 | static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, |
c8adf9a3 RP |
784 | unsigned long type, resource_size_t min_size, |
785 | resource_size_t add_size, | |
bdc4abec | 786 | struct list_head *realloc_head) |
1da177e4 LT |
787 | { |
788 | struct pci_dev *dev; | |
c8adf9a3 | 789 | resource_size_t min_align, align, size, size0, size1; |
c40a22e0 | 790 | resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ |
1da177e4 LT |
791 | int order, max_order; |
792 | struct resource *b_res = find_free_bus_resource(bus, type); | |
1f82de10 | 793 | unsigned int mem64_mask = 0; |
be768912 | 794 | resource_size_t children_add_size = 0; |
1da177e4 LT |
795 | |
796 | if (!b_res) | |
797 | return 0; | |
798 | ||
799 | memset(aligns, 0, sizeof(aligns)); | |
800 | max_order = 0; | |
801 | size = 0; | |
802 | ||
1f82de10 YL |
803 | mem64_mask = b_res->flags & IORESOURCE_MEM_64; |
804 | b_res->flags &= ~IORESOURCE_MEM_64; | |
805 | ||
1da177e4 LT |
806 | list_for_each_entry(dev, &bus->devices, bus_list) { |
807 | int i; | |
1f82de10 | 808 | |
1da177e4 LT |
809 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
810 | struct resource *r = &dev->resource[i]; | |
c40a22e0 | 811 | resource_size_t r_size; |
1da177e4 LT |
812 | |
813 | if (r->parent || (r->flags & mask) != type) | |
814 | continue; | |
022edd86 | 815 | r_size = resource_size(r); |
2aceefcb YL |
816 | #ifdef CONFIG_PCI_IOV |
817 | /* put SRIOV requested res to the optional list */ | |
9e8bf93a | 818 | if (realloc_head && i >= PCI_IOV_RESOURCES && |
2aceefcb YL |
819 | i <= PCI_IOV_RESOURCE_END) { |
820 | r->end = r->start - 1; | |
9e8bf93a | 821 | add_to_list(realloc_head, dev, r, r_size, 0/* dont' care */); |
2aceefcb YL |
822 | children_add_size += r_size; |
823 | continue; | |
824 | } | |
825 | #endif | |
1da177e4 | 826 | /* For bridges size != alignment */ |
6faf17f6 | 827 | align = pci_resource_alignment(dev, r); |
1da177e4 LT |
828 | order = __ffs(align) - 20; |
829 | if (order > 11) { | |
865df576 BH |
830 | dev_warn(&dev->dev, "disabling BAR %d: %pR " |
831 | "(bad alignment %#llx)\n", i, r, | |
832 | (unsigned long long) align); | |
1da177e4 LT |
833 | r->flags = 0; |
834 | continue; | |
835 | } | |
836 | size += r_size; | |
837 | if (order < 0) | |
838 | order = 0; | |
839 | /* Exclude ranges with size > align from | |
840 | calculation of the alignment. */ | |
841 | if (r_size == align) | |
842 | aligns[order] += align; | |
843 | if (order > max_order) | |
844 | max_order = order; | |
1f82de10 | 845 | mem64_mask &= r->flags & IORESOURCE_MEM_64; |
be768912 | 846 | |
9e8bf93a RP |
847 | if (realloc_head) |
848 | children_add_size += get_res_add_size(realloc_head, r); | |
1da177e4 LT |
849 | } |
850 | } | |
1da177e4 LT |
851 | align = 0; |
852 | min_align = 0; | |
853 | for (order = 0; order <= max_order; order++) { | |
8308c54d JF |
854 | resource_size_t align1 = 1; |
855 | ||
856 | align1 <<= (order + 20); | |
857 | ||
1da177e4 LT |
858 | if (!align) |
859 | min_align = align1; | |
6f6f8c2f | 860 | else if (ALIGN(align + min_align, min_align) < align1) |
1da177e4 LT |
861 | min_align = align1 >> 1; |
862 | align += aligns[order]; | |
863 | } | |
b42282e5 | 864 | size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align); |
be768912 YL |
865 | if (children_add_size > add_size) |
866 | add_size = children_add_size; | |
9e8bf93a | 867 | size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 : |
a4ac9fea | 868 | calculate_memsize(size, min_size, add_size, |
b42282e5 | 869 | resource_size(b_res), min_align); |
c8adf9a3 | 870 | if (!size0 && !size1) { |
865df576 BH |
871 | if (b_res->start || b_res->end) |
872 | dev_info(&bus->self->dev, "disabling bridge window " | |
873 | "%pR to [bus %02x-%02x] (unused)\n", b_res, | |
874 | bus->secondary, bus->subordinate); | |
1da177e4 LT |
875 | b_res->flags = 0; |
876 | return 1; | |
877 | } | |
878 | b_res->start = min_align; | |
c8adf9a3 RP |
879 | b_res->end = size0 + min_align - 1; |
880 | b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask; | |
b592443d | 881 | if (size1 > size0 && realloc_head) { |
9e8bf93a | 882 | add_to_list(realloc_head, bus->self, b_res, size1-size0, min_align); |
b592443d YL |
883 | dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window " |
884 | "%pR to [bus %02x-%02x] add_size %llx\n", b_res, | |
885 | bus->secondary, bus->subordinate, (unsigned long long)size1-size0); | |
886 | } | |
1da177e4 LT |
887 | return 1; |
888 | } | |
889 | ||
0a2daa1c RP |
890 | unsigned long pci_cardbus_resource_alignment(struct resource *res) |
891 | { | |
892 | if (res->flags & IORESOURCE_IO) | |
893 | return pci_cardbus_io_size; | |
894 | if (res->flags & IORESOURCE_MEM) | |
895 | return pci_cardbus_mem_size; | |
896 | return 0; | |
897 | } | |
898 | ||
899 | static void pci_bus_size_cardbus(struct pci_bus *bus, | |
bdc4abec | 900 | struct list_head *realloc_head) |
1da177e4 LT |
901 | { |
902 | struct pci_dev *bridge = bus->self; | |
903 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; | |
11848934 | 904 | resource_size_t b_res_3_size = pci_cardbus_mem_size * 2; |
1da177e4 LT |
905 | u16 ctrl; |
906 | ||
3796f1e2 YL |
907 | if (b_res[0].parent) |
908 | goto handle_b_res_1; | |
1da177e4 LT |
909 | /* |
910 | * Reserve some resources for CardBus. We reserve | |
911 | * a fixed amount of bus space for CardBus bridges. | |
912 | */ | |
11848934 YL |
913 | b_res[0].start = pci_cardbus_io_size; |
914 | b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1; | |
915 | b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
916 | if (realloc_head) { | |
917 | b_res[0].end -= pci_cardbus_io_size; | |
918 | add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size, | |
919 | pci_cardbus_io_size); | |
920 | } | |
1da177e4 | 921 | |
3796f1e2 YL |
922 | handle_b_res_1: |
923 | if (b_res[1].parent) | |
924 | goto handle_b_res_2; | |
11848934 YL |
925 | b_res[1].start = pci_cardbus_io_size; |
926 | b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1; | |
927 | b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN; | |
928 | if (realloc_head) { | |
929 | b_res[1].end -= pci_cardbus_io_size; | |
930 | add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size, | |
931 | pci_cardbus_io_size); | |
932 | } | |
1da177e4 | 933 | |
3796f1e2 | 934 | handle_b_res_2: |
dcef0d06 YL |
935 | /* MEM1 must not be pref mmio */ |
936 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
937 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) { | |
938 | ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; | |
939 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
940 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
941 | } | |
942 | ||
1da177e4 LT |
943 | /* |
944 | * Check whether prefetchable memory is supported | |
945 | * by this bridge. | |
946 | */ | |
947 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
948 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { | |
949 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; | |
950 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); | |
951 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); | |
952 | } | |
953 | ||
3796f1e2 YL |
954 | if (b_res[2].parent) |
955 | goto handle_b_res_3; | |
1da177e4 LT |
956 | /* |
957 | * If we have prefetchable memory support, allocate | |
958 | * two regions. Otherwise, allocate one region of | |
959 | * twice the size. | |
960 | */ | |
961 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { | |
11848934 YL |
962 | b_res[2].start = pci_cardbus_mem_size; |
963 | b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1; | |
964 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | | |
965 | IORESOURCE_STARTALIGN; | |
966 | if (realloc_head) { | |
967 | b_res[2].end -= pci_cardbus_mem_size; | |
968 | add_to_list(realloc_head, bridge, b_res+2, | |
969 | pci_cardbus_mem_size, pci_cardbus_mem_size); | |
970 | } | |
971 | ||
972 | /* reduce that to half */ | |
973 | b_res_3_size = pci_cardbus_mem_size; | |
974 | } | |
975 | ||
3796f1e2 YL |
976 | handle_b_res_3: |
977 | if (b_res[3].parent) | |
978 | goto handle_done; | |
11848934 YL |
979 | b_res[3].start = pci_cardbus_mem_size; |
980 | b_res[3].end = b_res[3].start + b_res_3_size - 1; | |
981 | b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN; | |
982 | if (realloc_head) { | |
983 | b_res[3].end -= b_res_3_size; | |
984 | add_to_list(realloc_head, bridge, b_res+3, b_res_3_size, | |
985 | pci_cardbus_mem_size); | |
986 | } | |
3796f1e2 YL |
987 | |
988 | handle_done: | |
989 | ; | |
1da177e4 LT |
990 | } |
991 | ||
c8adf9a3 | 992 | void __ref __pci_bus_size_bridges(struct pci_bus *bus, |
bdc4abec | 993 | struct list_head *realloc_head) |
1da177e4 LT |
994 | { |
995 | struct pci_dev *dev; | |
996 | unsigned long mask, prefmask; | |
c8adf9a3 | 997 | resource_size_t additional_mem_size = 0, additional_io_size = 0; |
1da177e4 LT |
998 | |
999 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1000 | struct pci_bus *b = dev->subordinate; | |
1001 | if (!b) | |
1002 | continue; | |
1003 | ||
1004 | switch (dev->class >> 8) { | |
1005 | case PCI_CLASS_BRIDGE_CARDBUS: | |
9e8bf93a | 1006 | pci_bus_size_cardbus(b, realloc_head); |
1da177e4 LT |
1007 | break; |
1008 | ||
1009 | case PCI_CLASS_BRIDGE_PCI: | |
1010 | default: | |
9e8bf93a | 1011 | __pci_bus_size_bridges(b, realloc_head); |
1da177e4 LT |
1012 | break; |
1013 | } | |
1014 | } | |
1015 | ||
1016 | /* The root bus? */ | |
1017 | if (!bus->self) | |
1018 | return; | |
1019 | ||
1020 | switch (bus->self->class >> 8) { | |
1021 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1022 | /* don't size cardbuses yet. */ | |
1023 | break; | |
1024 | ||
1025 | case PCI_CLASS_BRIDGE_PCI: | |
1026 | pci_bridge_check_ranges(bus); | |
28760489 | 1027 | if (bus->self->is_hotplug_bridge) { |
c8adf9a3 RP |
1028 | additional_io_size = pci_hotplug_io_size; |
1029 | additional_mem_size = pci_hotplug_mem_size; | |
28760489 | 1030 | } |
c8adf9a3 RP |
1031 | /* |
1032 | * Follow thru | |
1033 | */ | |
1da177e4 | 1034 | default: |
19aa7ee4 YL |
1035 | pbus_size_io(bus, realloc_head ? 0 : additional_io_size, |
1036 | additional_io_size, realloc_head); | |
1da177e4 LT |
1037 | /* If the bridge supports prefetchable range, size it |
1038 | separately. If it doesn't, or its prefetchable window | |
1039 | has already been allocated by arch code, try | |
1040 | non-prefetchable range for both types of PCI memory | |
1041 | resources. */ | |
1042 | mask = IORESOURCE_MEM; | |
1043 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; | |
19aa7ee4 YL |
1044 | if (pbus_size_mem(bus, prefmask, prefmask, |
1045 | realloc_head ? 0 : additional_mem_size, | |
1046 | additional_mem_size, realloc_head)) | |
1da177e4 | 1047 | mask = prefmask; /* Success, size non-prefetch only. */ |
28760489 | 1048 | else |
c8adf9a3 | 1049 | additional_mem_size += additional_mem_size; |
19aa7ee4 YL |
1050 | pbus_size_mem(bus, mask, IORESOURCE_MEM, |
1051 | realloc_head ? 0 : additional_mem_size, | |
1052 | additional_mem_size, realloc_head); | |
1da177e4 LT |
1053 | break; |
1054 | } | |
1055 | } | |
c8adf9a3 RP |
1056 | |
1057 | void __ref pci_bus_size_bridges(struct pci_bus *bus) | |
1058 | { | |
1059 | __pci_bus_size_bridges(bus, NULL); | |
1060 | } | |
1da177e4 LT |
1061 | EXPORT_SYMBOL(pci_bus_size_bridges); |
1062 | ||
568ddef8 | 1063 | static void __ref __pci_bus_assign_resources(const struct pci_bus *bus, |
bdc4abec YL |
1064 | struct list_head *realloc_head, |
1065 | struct list_head *fail_head) | |
1da177e4 LT |
1066 | { |
1067 | struct pci_bus *b; | |
1068 | struct pci_dev *dev; | |
1069 | ||
9e8bf93a | 1070 | pbus_assign_resources_sorted(bus, realloc_head, fail_head); |
1da177e4 | 1071 | |
1da177e4 LT |
1072 | list_for_each_entry(dev, &bus->devices, bus_list) { |
1073 | b = dev->subordinate; | |
1074 | if (!b) | |
1075 | continue; | |
1076 | ||
9e8bf93a | 1077 | __pci_bus_assign_resources(b, realloc_head, fail_head); |
1da177e4 LT |
1078 | |
1079 | switch (dev->class >> 8) { | |
1080 | case PCI_CLASS_BRIDGE_PCI: | |
6841ec68 YL |
1081 | if (!pci_is_enabled(dev)) |
1082 | pci_setup_bridge(b); | |
1da177e4 LT |
1083 | break; |
1084 | ||
1085 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1086 | pci_setup_cardbus(b); | |
1087 | break; | |
1088 | ||
1089 | default: | |
80ccba11 BH |
1090 | dev_info(&dev->dev, "not setting up bridge for bus " |
1091 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1da177e4 LT |
1092 | break; |
1093 | } | |
1094 | } | |
1095 | } | |
568ddef8 YL |
1096 | |
1097 | void __ref pci_bus_assign_resources(const struct pci_bus *bus) | |
1098 | { | |
c8adf9a3 | 1099 | __pci_bus_assign_resources(bus, NULL, NULL); |
568ddef8 | 1100 | } |
1da177e4 LT |
1101 | EXPORT_SYMBOL(pci_bus_assign_resources); |
1102 | ||
6841ec68 | 1103 | static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge, |
bdc4abec YL |
1104 | struct list_head *add_head, |
1105 | struct list_head *fail_head) | |
6841ec68 YL |
1106 | { |
1107 | struct pci_bus *b; | |
1108 | ||
8424d759 YL |
1109 | pdev_assign_resources_sorted((struct pci_dev *)bridge, |
1110 | add_head, fail_head); | |
6841ec68 YL |
1111 | |
1112 | b = bridge->subordinate; | |
1113 | if (!b) | |
1114 | return; | |
1115 | ||
8424d759 | 1116 | __pci_bus_assign_resources(b, add_head, fail_head); |
6841ec68 YL |
1117 | |
1118 | switch (bridge->class >> 8) { | |
1119 | case PCI_CLASS_BRIDGE_PCI: | |
1120 | pci_setup_bridge(b); | |
1121 | break; | |
1122 | ||
1123 | case PCI_CLASS_BRIDGE_CARDBUS: | |
1124 | pci_setup_cardbus(b); | |
1125 | break; | |
1126 | ||
1127 | default: | |
1128 | dev_info(&bridge->dev, "not setting up bridge for bus " | |
1129 | "%04x:%02x\n", pci_domain_nr(b), b->number); | |
1130 | break; | |
1131 | } | |
1132 | } | |
5009b460 YL |
1133 | static void pci_bridge_release_resources(struct pci_bus *bus, |
1134 | unsigned long type) | |
1135 | { | |
1136 | int idx; | |
1137 | bool changed = false; | |
1138 | struct pci_dev *dev; | |
1139 | struct resource *r; | |
1140 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | | |
1141 | IORESOURCE_PREFETCH; | |
1142 | ||
1143 | dev = bus->self; | |
1144 | for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END; | |
1145 | idx++) { | |
1146 | r = &dev->resource[idx]; | |
1147 | if ((r->flags & type_mask) != type) | |
1148 | continue; | |
1149 | if (!r->parent) | |
1150 | continue; | |
1151 | /* | |
1152 | * if there are children under that, we should release them | |
1153 | * all | |
1154 | */ | |
1155 | release_child_resources(r); | |
1156 | if (!release_resource(r)) { | |
1157 | dev_printk(KERN_DEBUG, &dev->dev, | |
1158 | "resource %d %pR released\n", idx, r); | |
1159 | /* keep the old size */ | |
1160 | r->end = resource_size(r) - 1; | |
1161 | r->start = 0; | |
1162 | r->flags = 0; | |
1163 | changed = true; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | if (changed) { | |
1168 | /* avoiding touch the one without PREF */ | |
1169 | if (type & IORESOURCE_PREFETCH) | |
1170 | type = IORESOURCE_PREFETCH; | |
1171 | __pci_setup_bridge(bus, type); | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | enum release_type { | |
1176 | leaf_only, | |
1177 | whole_subtree, | |
1178 | }; | |
1179 | /* | |
1180 | * try to release pci bridge resources that is from leaf bridge, | |
1181 | * so we can allocate big new one later | |
1182 | */ | |
1183 | static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus, | |
1184 | unsigned long type, | |
1185 | enum release_type rel_type) | |
1186 | { | |
1187 | struct pci_dev *dev; | |
1188 | bool is_leaf_bridge = true; | |
1189 | ||
1190 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1191 | struct pci_bus *b = dev->subordinate; | |
1192 | if (!b) | |
1193 | continue; | |
1194 | ||
1195 | is_leaf_bridge = false; | |
1196 | ||
1197 | if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1198 | continue; | |
1199 | ||
1200 | if (rel_type == whole_subtree) | |
1201 | pci_bus_release_bridge_resources(b, type, | |
1202 | whole_subtree); | |
1203 | } | |
1204 | ||
1205 | if (pci_is_root_bus(bus)) | |
1206 | return; | |
1207 | ||
1208 | if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI) | |
1209 | return; | |
1210 | ||
1211 | if ((rel_type == whole_subtree) || is_leaf_bridge) | |
1212 | pci_bridge_release_resources(bus, type); | |
1213 | } | |
1214 | ||
76fbc263 YL |
1215 | static void pci_bus_dump_res(struct pci_bus *bus) |
1216 | { | |
89a74ecc BH |
1217 | struct resource *res; |
1218 | int i; | |
7c9342b8 | 1219 | |
89a74ecc | 1220 | pci_bus_for_each_resource(bus, res, i) { |
7c9342b8 | 1221 | if (!res || !res->end || !res->flags) |
76fbc263 YL |
1222 | continue; |
1223 | ||
c7dabef8 | 1224 | dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); |
76fbc263 YL |
1225 | } |
1226 | } | |
1227 | ||
1228 | static void pci_bus_dump_resources(struct pci_bus *bus) | |
1229 | { | |
1230 | struct pci_bus *b; | |
1231 | struct pci_dev *dev; | |
1232 | ||
1233 | ||
1234 | pci_bus_dump_res(bus); | |
1235 | ||
1236 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1237 | b = dev->subordinate; | |
1238 | if (!b) | |
1239 | continue; | |
1240 | ||
1241 | pci_bus_dump_resources(b); | |
1242 | } | |
1243 | } | |
1244 | ||
da7822e5 YL |
1245 | static int __init pci_bus_get_depth(struct pci_bus *bus) |
1246 | { | |
1247 | int depth = 0; | |
1248 | struct pci_dev *dev; | |
1249 | ||
1250 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1251 | int ret; | |
1252 | struct pci_bus *b = dev->subordinate; | |
1253 | if (!b) | |
1254 | continue; | |
1255 | ||
1256 | ret = pci_bus_get_depth(b); | |
1257 | if (ret + 1 > depth) | |
1258 | depth = ret + 1; | |
1259 | } | |
1260 | ||
1261 | return depth; | |
1262 | } | |
1263 | static int __init pci_get_max_depth(void) | |
1264 | { | |
1265 | int depth = 0; | |
1266 | struct pci_bus *bus; | |
1267 | ||
1268 | list_for_each_entry(bus, &pci_root_buses, node) { | |
1269 | int ret; | |
1270 | ||
1271 | ret = pci_bus_get_depth(bus); | |
1272 | if (ret > depth) | |
1273 | depth = ret; | |
1274 | } | |
1275 | ||
1276 | return depth; | |
1277 | } | |
1278 | ||
f483d392 | 1279 | |
da7822e5 YL |
1280 | /* |
1281 | * first try will not touch pci bridge res | |
1282 | * second and later try will clear small leaf bridge res | |
1283 | * will stop till to the max deepth if can not find good one | |
1284 | */ | |
1da177e4 LT |
1285 | void __init |
1286 | pci_assign_unassigned_resources(void) | |
1287 | { | |
1288 | struct pci_bus *bus; | |
bdc4abec | 1289 | LIST_HEAD(realloc_head); /* list of resources that |
c8adf9a3 | 1290 | want additional resources */ |
bdc4abec | 1291 | struct list_head *add_list = NULL; |
da7822e5 YL |
1292 | int tried_times = 0; |
1293 | enum release_type rel_type = leaf_only; | |
bdc4abec | 1294 | LIST_HEAD(fail_head); |
b9b0bba9 | 1295 | struct pci_dev_resource *fail_res; |
da7822e5 YL |
1296 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1297 | IORESOURCE_PREFETCH; | |
1298 | unsigned long failed_type; | |
19aa7ee4 | 1299 | int pci_try_num = 1; |
da7822e5 | 1300 | |
19aa7ee4 YL |
1301 | /* don't realloc if asked to do so */ |
1302 | if (pci_realloc_enabled()) { | |
1303 | int max_depth = pci_get_max_depth(); | |
1304 | ||
1305 | pci_try_num = max_depth + 1; | |
1306 | printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n", | |
1307 | max_depth, pci_try_num); | |
1308 | } | |
da7822e5 YL |
1309 | |
1310 | again: | |
19aa7ee4 YL |
1311 | /* |
1312 | * last try will use add_list, otherwise will try good to have as | |
1313 | * must have, so can realloc parent bridge resource | |
1314 | */ | |
1315 | if (tried_times + 1 == pci_try_num) | |
bdc4abec | 1316 | add_list = &realloc_head; |
1da177e4 LT |
1317 | /* Depth first, calculate sizes and alignments of all |
1318 | subordinate buses. */ | |
da7822e5 | 1319 | list_for_each_entry(bus, &pci_root_buses, node) |
19aa7ee4 | 1320 | __pci_bus_size_bridges(bus, add_list); |
c8adf9a3 | 1321 | |
1da177e4 | 1322 | /* Depth last, allocate resources and update the hardware. */ |
da7822e5 | 1323 | list_for_each_entry(bus, &pci_root_buses, node) |
bdc4abec | 1324 | __pci_bus_assign_resources(bus, add_list, &fail_head); |
19aa7ee4 | 1325 | if (add_list) |
bdc4abec | 1326 | BUG_ON(!list_empty(add_list)); |
da7822e5 YL |
1327 | tried_times++; |
1328 | ||
1329 | /* any device complain? */ | |
bdc4abec | 1330 | if (list_empty(&fail_head)) |
da7822e5 | 1331 | goto enable_and_dump; |
f483d392 | 1332 | |
da7822e5 | 1333 | failed_type = 0; |
b9b0bba9 YL |
1334 | list_for_each_entry(fail_res, &fail_head, list) |
1335 | failed_type |= fail_res->flags; | |
bdc4abec | 1336 | |
da7822e5 YL |
1337 | /* |
1338 | * io port are tight, don't try extra | |
1339 | * or if reach the limit, don't want to try more | |
1340 | */ | |
1341 | failed_type &= type_mask; | |
1342 | if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) { | |
bffc56d4 | 1343 | free_list(&fail_head); |
da7822e5 YL |
1344 | goto enable_and_dump; |
1345 | } | |
1346 | ||
1347 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1348 | tried_times + 1); | |
1349 | ||
1350 | /* third times and later will not check if it is leaf */ | |
1351 | if ((tried_times + 1) > 2) | |
1352 | rel_type = whole_subtree; | |
1353 | ||
1354 | /* | |
1355 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1356 | * child device under that bridge | |
1357 | */ | |
b9b0bba9 YL |
1358 | list_for_each_entry(fail_res, &fail_head, list) { |
1359 | bus = fail_res->dev->bus; | |
bdc4abec | 1360 | pci_bus_release_bridge_resources(bus, |
b9b0bba9 | 1361 | fail_res->flags & type_mask, |
bdc4abec | 1362 | rel_type); |
da7822e5 YL |
1363 | } |
1364 | /* restore size and flags */ | |
b9b0bba9 YL |
1365 | list_for_each_entry(fail_res, &fail_head, list) { |
1366 | struct resource *res = fail_res->res; | |
da7822e5 | 1367 | |
b9b0bba9 YL |
1368 | res->start = fail_res->start; |
1369 | res->end = fail_res->end; | |
1370 | res->flags = fail_res->flags; | |
1371 | if (fail_res->dev->subordinate) | |
da7822e5 | 1372 | res->flags = 0; |
da7822e5 | 1373 | } |
bffc56d4 | 1374 | free_list(&fail_head); |
da7822e5 YL |
1375 | |
1376 | goto again; | |
1377 | ||
1378 | enable_and_dump: | |
1379 | /* Depth last, update the hardware. */ | |
1380 | list_for_each_entry(bus, &pci_root_buses, node) | |
1381 | pci_enable_bridges(bus); | |
76fbc263 YL |
1382 | |
1383 | /* dump the resource on buses */ | |
da7822e5 | 1384 | list_for_each_entry(bus, &pci_root_buses, node) |
76fbc263 | 1385 | pci_bus_dump_resources(bus); |
1da177e4 | 1386 | } |
6841ec68 YL |
1387 | |
1388 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) | |
1389 | { | |
1390 | struct pci_bus *parent = bridge->subordinate; | |
bdc4abec | 1391 | LIST_HEAD(add_list); /* list of resources that |
8424d759 | 1392 | want additional resources */ |
32180e40 | 1393 | int tried_times = 0; |
bdc4abec | 1394 | LIST_HEAD(fail_head); |
b9b0bba9 | 1395 | struct pci_dev_resource *fail_res; |
6841ec68 | 1396 | int retval; |
32180e40 YL |
1397 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
1398 | IORESOURCE_PREFETCH; | |
1399 | ||
32180e40 | 1400 | again: |
8424d759 | 1401 | __pci_bus_size_bridges(parent, &add_list); |
bdc4abec YL |
1402 | __pci_bridge_assign_resources(bridge, &add_list, &fail_head); |
1403 | BUG_ON(!list_empty(&add_list)); | |
32180e40 YL |
1404 | tried_times++; |
1405 | ||
bdc4abec | 1406 | if (list_empty(&fail_head)) |
3f579c34 | 1407 | goto enable_all; |
32180e40 YL |
1408 | |
1409 | if (tried_times >= 2) { | |
1410 | /* still fail, don't need to try more */ | |
bffc56d4 | 1411 | free_list(&fail_head); |
3f579c34 | 1412 | goto enable_all; |
32180e40 YL |
1413 | } |
1414 | ||
1415 | printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n", | |
1416 | tried_times + 1); | |
1417 | ||
1418 | /* | |
1419 | * Try to release leaf bridge's resources that doesn't fit resource of | |
1420 | * child device under that bridge | |
1421 | */ | |
b9b0bba9 YL |
1422 | list_for_each_entry(fail_res, &fail_head, list) { |
1423 | struct pci_bus *bus = fail_res->dev->bus; | |
1424 | unsigned long flags = fail_res->flags; | |
32180e40 YL |
1425 | |
1426 | pci_bus_release_bridge_resources(bus, flags & type_mask, | |
1427 | whole_subtree); | |
32180e40 YL |
1428 | } |
1429 | /* restore size and flags */ | |
b9b0bba9 YL |
1430 | list_for_each_entry(fail_res, &fail_head, list) { |
1431 | struct resource *res = fail_res->res; | |
32180e40 | 1432 | |
b9b0bba9 YL |
1433 | res->start = fail_res->start; |
1434 | res->end = fail_res->end; | |
1435 | res->flags = fail_res->flags; | |
1436 | if (fail_res->dev->subordinate) | |
32180e40 | 1437 | res->flags = 0; |
32180e40 | 1438 | } |
bffc56d4 | 1439 | free_list(&fail_head); |
32180e40 YL |
1440 | |
1441 | goto again; | |
3f579c34 YL |
1442 | |
1443 | enable_all: | |
1444 | retval = pci_reenable_device(bridge); | |
1445 | pci_set_master(bridge); | |
1446 | pci_enable_bridges(parent); | |
6841ec68 YL |
1447 | } |
1448 | EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources); | |
9b03088f YL |
1449 | |
1450 | #ifdef CONFIG_HOTPLUG | |
1451 | /** | |
1452 | * pci_rescan_bus - scan a PCI bus for devices. | |
1453 | * @bus: PCI bus to scan | |
1454 | * | |
1455 | * Scan a PCI bus and child buses for new devices, adds them, | |
1456 | * and enables them. | |
1457 | * | |
1458 | * Returns the max number of subordinate bus discovered. | |
1459 | */ | |
1460 | unsigned int __ref pci_rescan_bus(struct pci_bus *bus) | |
1461 | { | |
1462 | unsigned int max; | |
1463 | struct pci_dev *dev; | |
bdc4abec | 1464 | LIST_HEAD(add_list); /* list of resources that |
9b03088f YL |
1465 | want additional resources */ |
1466 | ||
1467 | max = pci_scan_child_bus(bus); | |
1468 | ||
9b03088f YL |
1469 | down_read(&pci_bus_sem); |
1470 | list_for_each_entry(dev, &bus->devices, bus_list) | |
1471 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
1472 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
1473 | if (dev->subordinate) | |
1474 | __pci_bus_size_bridges(dev->subordinate, | |
1475 | &add_list); | |
1476 | up_read(&pci_bus_sem); | |
1477 | __pci_bus_assign_resources(bus, &add_list, NULL); | |
bdc4abec | 1478 | BUG_ON(!list_empty(&add_list)); |
9b03088f YL |
1479 | |
1480 | pci_enable_bridges(bus); | |
1481 | pci_bus_add_devices(bus); | |
1482 | ||
1483 | return max; | |
1484 | } | |
1485 | EXPORT_SYMBOL_GPL(pci_rescan_bus); | |
1486 | #endif |