[deliverable/linux.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	bool disable;
	u16 cmd;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	if (res->flags & IORESOURCE_UNSET)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev->bus, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	/*
	 * We can't update a 64-bit BAR atomically, so when possible,
	 * disable decoding so that a half-updated BAR won't conflict
	 * with another device.
	 */
	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	if (disable) {
		pci_read_config_word(dev, PCI_COMMAND, &cmd);
		pci_write_config_word(dev, PCI_COMMAND,
				      cmd & ~PCI_COMMAND_MEMORY);
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}

	if (disable)
		pci_write_config_word(dev, PCI_COMMAND, cmd);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	if (res->flags & IORESOURCE_UNSET) {
		dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
			 resource, res);
		return -EINVAL;
	}

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
			 resource, res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
			 resource, res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}

/*
 * Generic function that returns a value indicating that the device's
 * original BIOS BAR address was not saved and so is not available for
 * reinstatement.
 *
 * Can be over-ridden by architecture specific code that implements
 * reinstatement functionality rather than leaving it disabled when
 * normal allocation attempts fail.
 */
resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
{
	return 0;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t fw_addr, start, end;
	int ret = 0;

	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	if (!fw_addr)
		return 1;

	start = res->start;
	end = res->end;
	res->start = fw_addr;
	res->end = res->start + size - 1;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		if (res->flags & IORESOURCE_IO)
			root = &ioport_resource;
		else
			root = &iomem_resource;
	}

	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "BAR %d: %pR conflicts with %s %pR\n", resno,
			 res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		ret = 1;
	}
	return ret;
}

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
				     pcibios_align_resource, dev);

	if (ret < 0 &&
	    (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
	     (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
		/*
		 * That failed.
		 *
		 * Try 32bit pref
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min,
					     IORESOURCE_PREFETCH,
					     pcibios_align_resource, dev);
	}

	if (ret < 0 &&
	    (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 *
		 * Also can put 64bit under 32bit range. (below 4g).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}
	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno,
				resource_size_t size, resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	struct pci_bus *bus;
	int ret;
	char *type;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	if (ret) {
		if (res->flags & IORESOURCE_MEM)
			if (res->flags & IORESOURCE_PREFETCH)
				type = "mem pref";
			else
				type = "mem";
		else if (res->flags & IORESOURCE_IO)
			type = "io";
		else
			type = "unknown";
		dev_info(&dev->dev,
			 "BAR %d: can't assign %s (size %#llx)\n",
			 resno, type, (unsigned long long) resource_size(res));
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	int ret;

	res->flags |= IORESOURCE_UNSET;
	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0)
		ret = pci_revert_fw_address(res, dev, resno, size);

	if (!ret) {
		res->flags &= ~IORESOURCE_UNSET;
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t new_size;
	int ret;

	res->flags |= IORESOURCE_UNSET;
	if (!res->parent) {
		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
			 "\n", resno, res);
		return -EINVAL;
	}

	/* already aligned with min_align */
	new_size = resource_size(res) + addsize;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (!ret) {
		res->flags &= ~IORESOURCE_UNSET;
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (r->flags & IORESOURCE_UNSET) {
			dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
				i, r);
			return -EINVAL;
		}

		if (!r->parent) {
			dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
				i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
363c75db	21	#include <linux/export.h>
1da177e4 LT	22	#include <linux/pci.h>
	23	#include <linux/errno.h>
	24	#include <linux/ioport.h>
	25	#include <linux/cache.h>
	26	#include <linux/slab.h>
	27	#include "pci.h"
	28
	29
14add80b	30	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	31	{
1da177e4 LT	32	struct pci_bus_region region;
9aac537e BH	33	bool disable;
9aac537e BH	34	u16 cmd;
1da177e4 LT	35	u32 new, check, mask;
1da177e4 LT	36	int reg;
613e7ed6	37	enum pci_bar_type type;
14add80b	38	struct resource *res = dev->resource + resno;
1da177e4	39
fb0f2b40 RB	40	/*
	41	* Ignore resources for unimplemented BARs and unused resource slots
	42	* for 64 bit BARs.
	43	*/
cf7bee5a IK	44	if (!res->flags)
	45	return;
	46
cd8a4d36 BH	47	if (res->flags & IORESOURCE_UNSET)
	48	return;
	49
fb0f2b40 RB	50	/*
	51	* Ignore non-moveable resources. This might be legacy resources for
	52	* which no functional BAR register exists or another important
80ccba11	53	* system resource we shouldn't move around.
fb0f2b40 RB	54	*/
	55	if (res->flags & IORESOURCE_PCI_FIXED)
	56	return;
	57
fc279850	58	pcibios_resource_to_bus(dev->bus, &region, res);
1da177e4	59
1da177e4 LT	60	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	61	if (res->flags & IORESOURCE_IO)
	62	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	63	else
	64	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	65
613e7ed6 YZ	66	reg = pci_resource_bar(dev, resno, &type);
	67	if (!reg)
	68	return;
	69	if (type != pci_bar_unknown) {
755528c8 LT	70	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	71	return;
	72	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	73	}
1da177e4 LT	74
9aac537e BH	75	/*
	76	* We can't update a 64-bit BAR atomically, so when possible,
	77	* disable decoding so that a half-updated BAR won't conflict
	78	* with another device.
	79	*/
	80	disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
	81	if (disable) {
	82	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	83	pci_write_config_word(dev, PCI_COMMAND,
	84	cmd & ~PCI_COMMAND_MEMORY);
	85	}
	86
1da177e4 LT	87	pci_write_config_dword(dev, reg, new);
	88	pci_read_config_dword(dev, reg, &check);
	89
	90	if ((new ^ check) & mask) {
80ccba11 BH	91	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	92	resno, new, check);
1da177e4 LT	93	}
1da177e4 LT	94
28c6821a	95	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	96	new = region.start >> 16 >> 16;
1da177e4 LT	97	pci_write_config_dword(dev, reg + 4, new);
	98	pci_read_config_dword(dev, reg + 4, &check);
	99	if (check != new) {
80ccba11 BH	100	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	101	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	102	}
1da177e4 LT	103	}
9aac537e BH	104
	105	if (disable)
	106	pci_write_config_word(dev, PCI_COMMAND, cmd);
1da177e4 LT	107	}
1da177e4 LT	108
96bde06a	109	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	110	{
1da177e4 LT	111	struct resource *res = &dev->resource[resource];
966f3a75	112	struct resource root, conflict;
1da177e4	113
29003beb BH	114	if (res->flags & IORESOURCE_UNSET) {
	115	dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
	116	resource, res);
	117	return -EINVAL;
	118	}
	119
cebd78a8	120	root = pci_find_parent_resource(dev, res);
865df576	121	if (!root) {
29003beb BH	122	dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
29003beb BH	123	resource, res);
865df576	124	return -EINVAL;
1da177e4 LT	125	}
1da177e4 LT	126
966f3a75 BH	127	conflict = request_resource_conflict(root, res);
966f3a75 BH	128	if (conflict) {
29003beb BH	129	dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
29003beb BH	130	resource, res, conflict->name, conflict);
966f3a75 BH	131	return -EBUSY;
966f3a75 BH	132	}
865df576	133
966f3a75	134	return 0;
1da177e4	135	}
eaa959df	136	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	137
32a9a682 YS	138	void pci_disable_bridge_window(struct pci_dev *dev)
32a9a682 YS	139	{
865df576	140	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	141
	142	/* MMIO Base/Limit */
	143	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	144
	145	/* Prefetchable MMIO Base/Limit */
	146	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	147	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	148	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	149	}
2bbc6942	150
6535943f MS	151	/*
	152	* Generic function that returns a value indicating that the device's
	153	* original BIOS BAR address was not saved and so is not available for
	154	* reinstatement.
	155	*
	156	* Can be over-ridden by architecture specific code that implements
	157	* reinstatement functionality rather than leaving it disabled when
	158	* normal allocation attempts fail.
	159	*/
	160	resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
	161	{
	162	return 0;
	163	}
	164
f7625980	165	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
2bbc6942 RP	166	int resno, resource_size_t size)
	167	{
	168	struct resource root, conflict;
6535943f	169	resource_size_t fw_addr, start, end;
2bbc6942	170	int ret = 0;
58c84eda	171
6535943f MS	172	fw_addr = pcibios_retrieve_fw_addr(dev, resno);
	173	if (!fw_addr)
	174	return 1;
	175
2bbc6942 RP	176	start = res->start;
2bbc6942 RP	177	end = res->end;
6535943f	178	res->start = fw_addr;
2bbc6942	179	res->end = res->start + size - 1;
351fc6d1 MS	180
	181	root = pci_find_parent_resource(dev, res);
	182	if (!root) {
	183	if (res->flags & IORESOURCE_IO)
	184	root = &ioport_resource;
	185	else
	186	root = &iomem_resource;
	187	}
	188
2bbc6942 RP	189	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	190	resno, res);
	191	conflict = request_resource_conflict(root, res);
	192	if (conflict) {
	193	dev_info(&dev->dev,
	194	"BAR %d: %pR conflicts with %s %pR\n", resno,
	195	res, conflict->name, conflict);
	196	res->start = start;
	197	res->end = end;
	198	ret = 1;
	199	}
	200	return ret;
	201	}
	202
fe6dacdb BH	203	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
	204	int resno, resource_size_t size, resource_size_t align)
	205	{
	206	struct resource *res = dev->resource + resno;
	207	resource_size_t min;
	208	int ret;
	209
	210	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	211
	212	/* First, try exact prefetching match.. */
	213	ret = pci_bus_alloc_resource(bus, res, size, align, min,
5b285415	214	IORESOURCE_PREFETCH \| IORESOURCE_MEM_64,
fe6dacdb BH	215	pcibios_align_resource, dev);
fe6dacdb BH	216
5b285415 YL	217	if (ret < 0 &&
	218	(res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) ==
	219	(IORESOURCE_PREFETCH \| IORESOURCE_MEM_64)) {
	220	/*
	221	* That failed.
	222	*
	223	* Try 32bit pref
	224	*/
	225	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	226	IORESOURCE_PREFETCH,
	227	pcibios_align_resource, dev);
	228	}
	229
	230	if (ret < 0 &&
	231	(res->flags & (IORESOURCE_PREFETCH \| IORESOURCE_MEM_64))) {
fe6dacdb BH	232	/*
	233	* That failed.
	234	*
	235	* But a prefetching area can handle a non-prefetching
	236	* window (it will just not perform as well).
5b285415 YL	237	*
5b285415 YL	238	* Also can put 64bit under 32bit range. (below 4g).
fe6dacdb BH	239	*/
	240	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	241	pcibios_align_resource, dev);
	242	}
	243	return ret;
	244	}
	245
d6776e6d NR	246	static int _pci_assign_resource(struct pci_dev *dev, int resno,
d6776e6d NR	247	resource_size_t size, resource_size_t min_align)
2bbc6942 RP	248	{
	249	struct resource *res = dev->resource + resno;
	250	struct pci_bus *bus;
	251	int ret;
	252	char *type;
58c84eda	253
2bbc6942 RP	254	bus = dev->bus;
	255	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	256	if (!bus->parent \|\| !bus->self->transparent)
	257	break;
	258	bus = bus->parent;
	259	}
	260
	261	if (ret) {
	262	if (res->flags & IORESOURCE_MEM)
	263	if (res->flags & IORESOURCE_PREFETCH)
	264	type = "mem pref";
	265	else
	266	type = "mem";
	267	else if (res->flags & IORESOURCE_IO)
	268	type = "io";
58c84eda	269	else
2bbc6942 RP	270	type = "unknown";
	271	dev_info(&dev->dev,
	272	"BAR %d: can't assign %s (size %#llx)\n",
	273	resno, type, (unsigned long long) resource_size(res));
58c84eda BH	274	}
58c84eda BH	275
2bbc6942 RP	276	return ret;
	277	}
	278
d09ee968 YL	279	int pci_assign_resource(struct pci_dev *dev, int resno)
	280	{
	281	struct resource *res = dev->resource + resno;
2bbc6942	282	resource_size_t align, size;
d09ee968 YL	283	int ret;
d09ee968 YL	284
bd064f0a	285	res->flags \|= IORESOURCE_UNSET;
6faf17f6	286	align = pci_resource_alignment(dev, res);
d09ee968	287	if (!align) {
865df576	288	dev_info(&dev->dev, "BAR %d: can't assign %pR "
a369c791	289	"(bogus alignment)\n", resno, res);
d09ee968 YL	290	return -EINVAL;
	291	}
	292
2bbc6942 RP	293	size = resource_size(res);
2bbc6942 RP	294	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	295
2bbc6942 RP	296	/*
	297	* If we failed to assign anything, let's try the address
	298	* where firmware left it. That at least has a chance of
	299	* working, which is better than just leaving it disabled.
	300	*/
6535943f	301	if (ret < 0)
2bbc6942	302	ret = pci_revert_fw_address(res, dev, resno, size);
d09ee968	303
2bbc6942	304	if (!ret) {
bd064f0a	305	res->flags &= ~IORESOURCE_UNSET;
2bbc6942 RP	306	res->flags &= ~IORESOURCE_STARTALIGN;
	307	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	308	if (resno < PCI_BRIDGE_RESOURCES)
	309	pci_update_resource(dev, resno);
	310	}
d09ee968 YL	311	return ret;
	312	}
	313
fe6dacdb BH	314	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	315	resource_size_t min_align)
	316	{
	317	struct resource *res = dev->resource + resno;
	318	resource_size_t new_size;
	319	int ret;
	320
bd064f0a	321	res->flags \|= IORESOURCE_UNSET;
fe6dacdb BH	322	if (!res->parent) {
	323	dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR "
	324	"\n", resno, res);
	325	return -EINVAL;
	326	}
	327
	328	/* already aligned with min_align */
	329	new_size = resource_size(res) + addsize;
	330	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	331	if (!ret) {
bd064f0a	332	res->flags &= ~IORESOURCE_UNSET;
fe6dacdb BH	333	res->flags &= ~IORESOURCE_STARTALIGN;
	334	dev_info(&dev->dev, "BAR %d: reassigned %pR\n", resno, res);
	335	if (resno < PCI_BRIDGE_RESOURCES)
	336	pci_update_resource(dev, resno);
	337	}
	338	return ret;
	339	}
	340
842de40d BH	341	int pci_enable_resources(struct pci_dev *dev, int mask)
	342	{
	343	u16 cmd, old_cmd;
	344	int i;
	345	struct resource *r;
	346
	347	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	348	old_cmd = cmd;
	349
	350	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	351	if (!(mask & (1 << i)))
	352	continue;
	353
	354	r = &dev->resource[i];
	355
	356	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	357	continue;
	358	if ((i == PCI_ROM_RESOURCE) &&
	359	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	360	continue;
	361
3cedcc36 BH	362	if (r->flags & IORESOURCE_UNSET) {
	363	dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
	364	i, r);
	365	return -EINVAL;
	366	}
	367
842de40d	368	if (!r->parent) {
3cedcc36 BH	369	dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
3cedcc36 BH	370	i, r);
842de40d BH	371	return -EINVAL;
	372	}
	373
	374	if (r->flags & IORESOURCE_IO)
	375	cmd \|= PCI_COMMAND_IO;
	376	if (r->flags & IORESOURCE_MEM)
	377	cmd \|= PCI_COMMAND_MEMORY;
	378	}
	379
	380	if (cmd != old_cmd) {
	381	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	382	old_cmd, cmd);
	383	pci_write_config_word(dev, PCI_COMMAND, cmd);
	384	}
	385	return 0;
	386	}