[deliverable/linux.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if (res->flags & IORESOURCE_MEM_64) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}
	res->flags &= ~IORESOURCE_UNSET;
	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
		resno, res, (unsigned long long)region.start,
		(unsigned long long)region.end);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root, *conflict;

	root = pci_find_parent_resource(dev, res);
	if (!root) {
		dev_info(&dev->dev, "no compatible bridge window for %pR\n",
			 res);
		return -EINVAL;
	}

	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "address space collision: %pR conflicts with %s %pR\n",
			 res, conflict->name, conflict);
		return -EBUSY;
	}

	return 0;
}
EXPORT_SYMBOL(pci_claim_resource);

#ifdef CONFIG_PCI_QUIRKS
void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_info(&dev->dev, "disabling bridge mem windows\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}
#endif	/* CONFIG_PCI_QUIRKS */


static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
		int resno, resource_size_t size, resource_size_t align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t min;
	int ret;

	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}
	return ret;
}

static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev, 
		int resno, resource_size_t size)
{
	struct resource *root, *conflict;
	resource_size_t start, end;
	int ret = 0;

	if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;
	else
		root = &iomem_resource;

	start = res->start;
	end = res->end;
	res->start = dev->fw_addr[resno];
	res->end = res->start + size - 1;
	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
		 resno, res);
	conflict = request_resource_conflict(root, res);
	if (conflict) {
		dev_info(&dev->dev,
			 "BAR %d: %pR conflicts with %s %pR\n", resno,
			 res, conflict->name, conflict);
		res->start = start;
		res->end = end;
		ret = 1;
	}
	return ret;
}

static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	struct pci_bus *bus;
	int ret;
	char *type;

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
		if (!bus->parent || !bus->self->transparent)
			break;
		bus = bus->parent;
	}

	if (ret) {
		if (res->flags & IORESOURCE_MEM)
			if (res->flags & IORESOURCE_PREFETCH)
				type = "mem pref";
			else
				type = "mem";
		else if (res->flags & IORESOURCE_IO)
			type = "io";
		else
			type = "unknown";
		dev_info(&dev->dev,
			 "BAR %d: can't assign %s (size %#llx)\n",
			 resno, type, (unsigned long long) resource_size(res));
	}

	return ret;
}

int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
			resource_size_t min_align)
{
	struct resource *res = dev->resource + resno;
	resource_size_t new_size;
	int ret;

	if (!res->parent) {
		dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
			 "\n", resno, res);
		return -EINVAL;
	}

	new_size = resource_size(res) + addsize + min_align;
	ret = _pci_assign_resource(dev, resno, new_size, min_align);
	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align, size;
	struct pci_bus *bus;
	int ret;

	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't assign %pR "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	bus = dev->bus;
	size = resource_size(res);
	ret = _pci_assign_resource(dev, resno, size, align);

	/*
	 * If we failed to assign anything, let's try the address
	 * where firmware left it.  That at least has a chance of
	 * working, which is better than just leaving it disabled.
	 */
	if (ret < 0 && dev->fw_addr[resno])
		ret = pci_revert_fw_address(res, dev, resno, size);

	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}
	return ret;
}


/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
{
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		struct resource *r;
		struct resource_list *list, *tmp;
		resource_size_t r_align;

		r = &dev->resource[i];

		if (r->flags & IORESOURCE_PCI_FIXED)
			continue;

		if (!(r->flags) || r->parent)
			continue;

		r_align = pci_resource_alignment(dev, r);
		if (!r_align) {
			dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
				 i, r);
			continue;
		}
		for (list = head; ; list = list->next) {
			resource_size_t align = 0;
			struct resource_list *ln = list->next;

			if (ln)
				align = pci_resource_alignment(ln->dev, ln->res);

			if (r_align > align) {
				tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
				if (!tmp)
					panic("pdev_sort_resources(): "
					      "kmalloc() failed!\n");
				tmp->next = ln;
				tmp->res = r;
				tmp->dev = dev;
				list->next = tmp;
				break;
			}
		}
	}
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available "
				"(can't reserve %pR)\n", r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
363c75db	21	#include <linux/export.h>
1da177e4 LT	22	#include <linux/pci.h>
	23	#include <linux/errno.h>
	24	#include <linux/ioport.h>
	25	#include <linux/cache.h>
	26	#include <linux/slab.h>
	27	#include "pci.h"
	28
	29
14add80b	30	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	31	{
	32	struct pci_bus_region region;
	33	u32 new, check, mask;
	34	int reg;
613e7ed6	35	enum pci_bar_type type;
14add80b	36	struct resource *res = dev->resource + resno;
1da177e4	37
fb0f2b40 RB	38	/*
	39	* Ignore resources for unimplemented BARs and unused resource slots
	40	* for 64 bit BARs.
	41	*/
cf7bee5a IK	42	if (!res->flags)
	43	return;
	44
fb0f2b40 RB	45	/*
	46	* Ignore non-moveable resources. This might be legacy resources for
	47	* which no functional BAR register exists or another important
80ccba11	48	* system resource we shouldn't move around.
fb0f2b40 RB	49	*/
	50	if (res->flags & IORESOURCE_PCI_FIXED)
	51	return;
	52
1da177e4 LT	53	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	54
1da177e4 LT	55	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	56	if (res->flags & IORESOURCE_IO)
	57	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	58	else
	59	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	60
613e7ed6 YZ	61	reg = pci_resource_bar(dev, resno, &type);
	62	if (!reg)
	63	return;
	64	if (type != pci_bar_unknown) {
755528c8 LT	65	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	66	return;
	67	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	68	}
	69
	70	pci_write_config_dword(dev, reg, new);
	71	pci_read_config_dword(dev, reg, &check);
	72
	73	if ((new ^ check) & mask) {
80ccba11 BH	74	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	75	resno, new, check);
1da177e4 LT	76	}
1da177e4 LT	77
28c6821a	78	if (res->flags & IORESOURCE_MEM_64) {
cf7bee5a	79	new = region.start >> 16 >> 16;
1da177e4 LT	80	pci_write_config_dword(dev, reg + 4, new);
	81	pci_read_config_dword(dev, reg + 4, &check);
	82	if (check != new) {
80ccba11 BH	83	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	84	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	85	}
	86	}
	87	res->flags &= ~IORESOURCE_UNSET;
85b8582d VP	88	dev_dbg(&dev->dev, "BAR %d: set to %pR (PCI address [%#llx-%#llx])\n",
	89	resno, res, (unsigned long long)region.start,
	90	(unsigned long long)region.end);
1da177e4 LT	91	}
1da177e4 LT	92
96bde06a	93	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	94	{
1da177e4 LT	95	struct resource *res = &dev->resource[resource];
966f3a75	96	struct resource root, conflict;
1da177e4	97
cebd78a8	98	root = pci_find_parent_resource(dev, res);
865df576	99	if (!root) {
f6d440da BH	100	dev_info(&dev->dev, "no compatible bridge window for %pR\n",
f6d440da BH	101	res);
865df576	102	return -EINVAL;
1da177e4 LT	103	}
1da177e4 LT	104
966f3a75 BH	105	conflict = request_resource_conflict(root, res);
966f3a75 BH	106	if (conflict) {
f6d440da BH	107	dev_info(&dev->dev,
	108	"address space collision: %pR conflicts with %s %pR\n",
	109	res, conflict->name, conflict);
966f3a75 BH	110	return -EBUSY;
966f3a75 BH	111	}
865df576	112
966f3a75	113	return 0;
1da177e4	114	}
eaa959df	115	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	116
32a9a682 YS	117	#ifdef CONFIG_PCI_QUIRKS
	118	void pci_disable_bridge_window(struct pci_dev *dev)
	119	{
865df576	120	dev_info(&dev->dev, "disabling bridge mem windows\n");
32a9a682 YS	121
	122	/* MMIO Base/Limit */
	123	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	124
	125	/* Prefetchable MMIO Base/Limit */
	126	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	127	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	128	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	129	}
	130	#endif /* CONFIG_PCI_QUIRKS */
	131
2bbc6942 RP	132
2bbc6942 RP	133
d09ee968	134	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
2bbc6942	135	int resno, resource_size_t size, resource_size_t align)
1da177e4	136	{
1da177e4	137	struct resource *res = dev->resource + resno;
2bbc6942	138	resource_size_t min;
1da177e4 LT	139	int ret;
1da177e4 LT	140
1da177e4	141	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
1da177e4 LT	142
	143	/* First, try exact prefetching match.. */
	144	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	145	IORESOURCE_PREFETCH,
	146	pcibios_align_resource, dev);
	147
	148	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	149	/*
	150	* That failed.
	151	*
	152	* But a prefetching area can handle a non-prefetching
	153	* window (it will just not perform as well).
	154	*/
	155	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	156	pcibios_align_resource, dev);
	157	}
2bbc6942 RP	158	return ret;
2bbc6942 RP	159	}
1da177e4	160
2bbc6942 RP	161	static int pci_revert_fw_address(struct resource res, struct pci_dev dev,
	162	int resno, resource_size_t size)
	163	{
	164	struct resource root, conflict;
	165	resource_size_t start, end;
	166	int ret = 0;
58c84eda	167
2bbc6942 RP	168	if (res->flags & IORESOURCE_IO)
	169	root = &ioport_resource;
	170	else
	171	root = &iomem_resource;
	172
	173	start = res->start;
	174	end = res->end;
	175	res->start = dev->fw_addr[resno];
	176	res->end = res->start + size - 1;
	177	dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
	178	resno, res);
	179	conflict = request_resource_conflict(root, res);
	180	if (conflict) {
	181	dev_info(&dev->dev,
	182	"BAR %d: %pR conflicts with %s %pR\n", resno,
	183	res, conflict->name, conflict);
	184	res->start = start;
	185	res->end = end;
	186	ret = 1;
	187	}
	188	return ret;
	189	}
	190
	191	static int _pci_assign_resource(struct pci_dev *dev, int resno, int size, resource_size_t min_align)
	192	{
	193	struct resource *res = dev->resource + resno;
	194	struct pci_bus *bus;
	195	int ret;
	196	char *type;
58c84eda	197
2bbc6942 RP	198	bus = dev->bus;
	199	while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
	200	if (!bus->parent \|\| !bus->self->transparent)
	201	break;
	202	bus = bus->parent;
	203	}
	204
	205	if (ret) {
	206	if (res->flags & IORESOURCE_MEM)
	207	if (res->flags & IORESOURCE_PREFETCH)
	208	type = "mem pref";
	209	else
	210	type = "mem";
	211	else if (res->flags & IORESOURCE_IO)
	212	type = "io";
58c84eda	213	else
2bbc6942 RP	214	type = "unknown";
	215	dev_info(&dev->dev,
	216	"BAR %d: can't assign %s (size %#llx)\n",
	217	resno, type, (unsigned long long) resource_size(res));
58c84eda BH	218	}
58c84eda BH	219
2bbc6942 RP	220	return ret;
	221	}
	222
	223	int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
	224	resource_size_t min_align)
	225	{
	226	struct resource *res = dev->resource + resno;
	227	resource_size_t new_size;
	228	int ret;
	229
	230	if (!res->parent) {
	231	dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resouce %pR "
	232	"\n", resno, res);
	233	return -EINVAL;
	234	}
	235
	236	new_size = resource_size(res) + addsize + min_align;
	237	ret = _pci_assign_resource(dev, resno, new_size, min_align);
d09ee968	238	if (!ret) {
88452565	239	res->flags &= ~IORESOURCE_STARTALIGN;
865df576	240	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
88452565	241	if (resno < PCI_BRIDGE_RESOURCES)
14add80b	242	pci_update_resource(dev, resno);
1da177e4	243	}
1da177e4 LT	244	return ret;
	245	}
	246
d09ee968 YL	247	int pci_assign_resource(struct pci_dev *dev, int resno)
	248	{
	249	struct resource *res = dev->resource + resno;
2bbc6942	250	resource_size_t align, size;
d09ee968 YL	251	struct pci_bus *bus;
	252	int ret;
	253
6faf17f6	254	align = pci_resource_alignment(dev, res);
d09ee968	255	if (!align) {
865df576	256	dev_info(&dev->dev, "BAR %d: can't assign %pR "
a369c791	257	"(bogus alignment)\n", resno, res);
d09ee968 YL	258	return -EINVAL;
	259	}
	260
	261	bus = dev->bus;
2bbc6942 RP	262	size = resource_size(res);
2bbc6942 RP	263	ret = _pci_assign_resource(dev, resno, size, align);
d09ee968	264
2bbc6942 RP	265	/*
	266	* If we failed to assign anything, let's try the address
	267	* where firmware left it. That at least has a chance of
	268	* working, which is better than just leaving it disabled.
	269	*/
	270	if (ret < 0 && dev->fw_addr[resno])
	271	ret = pci_revert_fw_address(res, dev, resno, size);
d09ee968	272
2bbc6942 RP	273	if (!ret) {
	274	res->flags &= ~IORESOURCE_STARTALIGN;
	275	dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
	276	if (resno < PCI_BRIDGE_RESOURCES)
	277	pci_update_resource(dev, resno);
	278	}
d09ee968 YL	279	return ret;
	280	}
	281
2bbc6942	282
1da177e4	283	/* Sort resources by alignment */
96bde06a	284	void pdev_sort_resources(struct pci_dev dev, struct resource_list head)
1da177e4 LT	285	{
	286	int i;
	287
	288	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	289	struct resource *r;
	290	struct resource_list list, tmp;
e31dd6e4	291	resource_size_t r_align;
1da177e4 LT	292
1da177e4 LT	293	r = &dev->resource[i];
fb0f2b40 RB	294
	295	if (r->flags & IORESOURCE_PCI_FIXED)
	296	continue;
	297
1da177e4 LT	298	if (!(r->flags) \|\| r->parent)
1da177e4 LT	299	continue;
88452565	300
6faf17f6	301	r_align = pci_resource_alignment(dev, r);
1da177e4	302	if (!r_align) {
c7dabef8	303	dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
a369c791	304	i, r);
1da177e4 LT	305	continue;
1da177e4 LT	306	}
1da177e4	307	for (list = head; ; list = list->next) {
e31dd6e4	308	resource_size_t align = 0;
1da177e4	309	struct resource_list *ln = list->next;
88452565 IK	310
88452565 IK	311	if (ln)
6faf17f6	312	align = pci_resource_alignment(ln->dev, ln->res);
88452565	313
1da177e4 LT	314	if (r_align > align) {
	315	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	316	if (!tmp)
	317	panic("pdev_sort_resources(): "
	318	"kmalloc() failed!\n");
	319	tmp->next = ln;
	320	tmp->res = r;
	321	tmp->dev = dev;
	322	list->next = tmp;
	323	break;
	324	}
	325	}
	326	}
	327	}
842de40d BH	328
	329	int pci_enable_resources(struct pci_dev *dev, int mask)
	330	{
	331	u16 cmd, old_cmd;
	332	int i;
	333	struct resource *r;
	334
	335	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	336	old_cmd = cmd;
	337
	338	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	339	if (!(mask & (1 << i)))
	340	continue;
	341
	342	r = &dev->resource[i];
	343
	344	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	345	continue;
	346	if ((i == PCI_ROM_RESOURCE) &&
	347	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	348	continue;
	349
	350	if (!r->parent) {
865df576 BH	351	dev_err(&dev->dev, "device not available "
865df576 BH	352	"(can't reserve %pR)\n", r);
842de40d BH	353	return -EINVAL;
	354	}
	355
	356	if (r->flags & IORESOURCE_IO)
	357	cmd \|= PCI_COMMAND_IO;
	358	if (r->flags & IORESOURCE_MEM)
	359	cmd \|= PCI_COMMAND_MEMORY;
	360	}
	361
	362	if (cmd != old_cmd) {
	363	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	364	old_cmd, cmd);
	365	pci_write_config_word(dev, PCI_COMMAND, cmd);
	366	}
	367	return 0;
	368	}