[deliverable/linux.git] / drivers / pci / setup-res.c

/*
 *	drivers/pci/setup-res.c
 *
 * Extruded from code written by
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
 *      David Mosberger (davidm@cs.arizona.edu)
 *	David Miller (davem@redhat.com)
 *
 * Support routines for initializing a PCI subsystem.
 */

/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */

/*
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
 *	     Resource sorting
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/cache.h>
#include <linux/slab.h>
#include "pci.h"


void pci_update_resource(struct pci_dev *dev, int resno)
{
	struct pci_bus_region region;
	u32 new, check, mask;
	int reg;
	enum pci_bar_type type;
	struct resource *res = dev->resource + resno;

	/*
	 * Ignore resources for unimplemented BARs and unused resource slots
	 * for 64 bit BARs.
	 */
	if (!res->flags)
		return;

	/*
	 * Ignore non-moveable resources.  This might be legacy resources for
	 * which no functional BAR register exists or another important
	 * system resource we shouldn't move around.
	 */
	if (res->flags & IORESOURCE_PCI_FIXED)
		return;

	pcibios_resource_to_bus(dev, &region, res);

	dev_dbg(&dev->dev, "BAR %d: got %pRf (bus addr [%#llx-%#llx])\n",
		resno, res, (unsigned long long)region.start,
		(unsigned long long)region.end);

	new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
	if (res->flags & IORESOURCE_IO)
		mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	else
		mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;

	reg = pci_resource_bar(dev, resno, &type);
	if (!reg)
		return;
	if (type != pci_bar_unknown) {
		if (!(res->flags & IORESOURCE_ROM_ENABLE))
			return;
		new |= PCI_ROM_ADDRESS_ENABLE;
	}

	pci_write_config_dword(dev, reg, new);
	pci_read_config_dword(dev, reg, &check);

	if ((new ^ check) & mask) {
		dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
			resno, new, check);
	}

	if ((new & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	    (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
		new = region.start >> 16 >> 16;
		pci_write_config_dword(dev, reg + 4, new);
		pci_read_config_dword(dev, reg + 4, &check);
		if (check != new) {
			dev_err(&dev->dev, "BAR %d: error updating "
			       "(high %#08x != %#08x)\n", resno, new, check);
		}
	}
	res->flags &= ~IORESOURCE_UNSET;
	dev_dbg(&dev->dev, "BAR %d: moved to bus addr [%#llx-%#llx]\n",
		resno, (unsigned long long)region.start,
		(unsigned long long)region.end);
}

int pci_claim_resource(struct pci_dev *dev, int resource)
{
	struct resource *res = &dev->resource[resource];
	struct resource *root;
	int err;

	root = pci_find_parent_resource(dev, res);

	err = -EINVAL;
	if (root != NULL)
		err = request_resource(root, res);

	if (err) {
		const char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
		dev_err(&dev->dev, "BAR %d: %s %s %pRt\n",
			resource,
			root ? "address space collision on" :
				"no parent found for",
			dtype, res);
	}

	return err;
}
EXPORT_SYMBOL(pci_claim_resource);

#ifdef CONFIG_PCI_QUIRKS
void pci_disable_bridge_window(struct pci_dev *dev)
{
	dev_dbg(&dev->dev, "Disabling bridge window.\n");

	/* MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);

	/* Prefetchable MMIO Base/Limit */
	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
}
#endif	/* CONFIG_PCI_QUIRKS */

static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
				 int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t size, min, align;
	int ret;

	size = resource_size(res);
	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
	align = pci_resource_alignment(dev, res);

	/* First, try exact prefetching match.. */
	ret = pci_bus_alloc_resource(bus, res, size, align, min,
				     IORESOURCE_PREFETCH,
				     pcibios_align_resource, dev);

	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
		/*
		 * That failed.
		 *
		 * But a prefetching area can handle a non-prefetching
		 * window (it will just not perform as well).
		 */
		ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
					     pcibios_align_resource, dev);
	}

	if (!ret) {
		res->flags &= ~IORESOURCE_STARTALIGN;
		if (resno < PCI_BRIDGE_RESOURCES)
			pci_update_resource(dev, resno);
	}

	return ret;
}

int pci_assign_resource(struct pci_dev *dev, int resno)
{
	struct resource *res = dev->resource + resno;
	resource_size_t align;
	struct pci_bus *bus;
	int ret;

	align = pci_resource_alignment(dev, res);
	if (!align) {
		dev_info(&dev->dev, "BAR %d: can't allocate %pRf "
			 "(bogus alignment)\n", resno, res);
		return -EINVAL;
	}

	bus = dev->bus;
	while ((ret = __pci_assign_resource(bus, dev, resno))) {
		if (bus->parent && bus->self->transparent)
			bus = bus->parent;
		else
			bus = NULL;
		if (bus)
			continue;
		break;
	}

	if (ret)
		dev_info(&dev->dev, "BAR %d: can't allocate %pRt\n",
			 resno, res);

	return ret;
}

/* Sort resources by alignment */
void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
{
	int i;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		struct resource *r;
		struct resource_list *list, *tmp;
		resource_size_t r_align;

		r = &dev->resource[i];

		if (r->flags & IORESOURCE_PCI_FIXED)
			continue;

		if (!(r->flags) || r->parent)
			continue;

		r_align = pci_resource_alignment(dev, r);
		if (!r_align) {
			dev_warn(&dev->dev, "BAR %d: bogus alignment %pRf\n",
				 i, r);
			continue;
		}
		for (list = head; ; list = list->next) {
			resource_size_t align = 0;
			struct resource_list *ln = list->next;

			if (ln)
				align = pci_resource_alignment(ln->dev, ln->res);

			if (r_align > align) {
				tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
				if (!tmp)
					panic("pdev_sort_resources(): "
					      "kmalloc() failed!\n");
				tmp->next = ln;
				tmp->res = r;
				tmp->dev = dev;
				list->next = tmp;
				break;
			}
		}
	}
}

int pci_enable_resources(struct pci_dev *dev, int mask)
{
	u16 cmd, old_cmd;
	int i;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;

	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
		if (!(mask & (1 << i)))
			continue;

		r = &dev->resource[i];

		if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if ((i == PCI_ROM_RESOURCE) &&
				(!(r->flags & IORESOURCE_ROM_ENABLE)))
			continue;

		if (!r->parent) {
			dev_err(&dev->dev, "device not available because of "
				"BAR %d %pR collisions\n", i, r);
			return -EINVAL;
		}

		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}

	if (cmd != old_cmd) {
		dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
			 old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pci/setup-res.c
	3	*
	4	* Extruded from code written by
	5	* Dave Rusling (david.rusling@reo.mts.dec.com)
	6	* David Mosberger (davidm@cs.arizona.edu)
	7	* David Miller (davem@redhat.com)
	8	*
	9	* Support routines for initializing a PCI subsystem.
	10	*/
	11
	12	/* fixed for multiple pci buses, 1999 Andrea Arcangeli <andrea@suse.de> */
	13
	14	/*
	15	* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
	16	* Resource sorting
	17	*/
	18
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/pci.h>
	22	#include <linux/errno.h>
	23	#include <linux/ioport.h>
	24	#include <linux/cache.h>
	25	#include <linux/slab.h>
	26	#include "pci.h"
	27
	28
14add80b	29	void pci_update_resource(struct pci_dev *dev, int resno)
1da177e4 LT	30	{
	31	struct pci_bus_region region;
	32	u32 new, check, mask;
	33	int reg;
613e7ed6	34	enum pci_bar_type type;
14add80b	35	struct resource *res = dev->resource + resno;
1da177e4	36
fb0f2b40 RB	37	/*
	38	* Ignore resources for unimplemented BARs and unused resource slots
	39	* for 64 bit BARs.
	40	*/
cf7bee5a IK	41	if (!res->flags)
	42	return;
	43
fb0f2b40 RB	44	/*
	45	* Ignore non-moveable resources. This might be legacy resources for
	46	* which no functional BAR register exists or another important
80ccba11	47	* system resource we shouldn't move around.
fb0f2b40 RB	48	*/
	49	if (res->flags & IORESOURCE_PCI_FIXED)
	50	return;
	51
1da177e4 LT	52	pcibios_resource_to_bus(dev, &region, res);
1da177e4 LT	53
a369c791 BH	54	dev_dbg(&dev->dev, "BAR %d: got %pRf (bus addr [%#llx-%#llx])\n",
	55	resno, res, (unsigned long long)region.start,
	56	(unsigned long long)region.end);
1da177e4 LT	57
	58	new = region.start \| (res->flags & PCI_REGION_FLAG_MASK);
	59	if (res->flags & IORESOURCE_IO)
	60	mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
	61	else
	62	mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
	63
613e7ed6 YZ	64	reg = pci_resource_bar(dev, resno, &type);
	65	if (!reg)
	66	return;
	67	if (type != pci_bar_unknown) {
755528c8 LT	68	if (!(res->flags & IORESOURCE_ROM_ENABLE))
	69	return;
	70	new \|= PCI_ROM_ADDRESS_ENABLE;
1da177e4 LT	71	}
	72
	73	pci_write_config_dword(dev, reg, new);
	74	pci_read_config_dword(dev, reg, &check);
	75
	76	if ((new ^ check) & mask) {
80ccba11 BH	77	dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
80ccba11 BH	78	resno, new, check);
1da177e4 LT	79	}
	80
	81	if ((new & (PCI_BASE_ADDRESS_SPACE\|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	82	(PCI_BASE_ADDRESS_SPACE_MEMORY\|PCI_BASE_ADDRESS_MEM_TYPE_64)) {
cf7bee5a	83	new = region.start >> 16 >> 16;
1da177e4 LT	84	pci_write_config_dword(dev, reg + 4, new);
	85	pci_read_config_dword(dev, reg + 4, &check);
	86	if (check != new) {
80ccba11 BH	87	dev_err(&dev->dev, "BAR %d: error updating "
80ccba11 BH	88	"(high %#08x != %#08x)\n", resno, new, check);
1da177e4 LT	89	}
	90	}
	91	res->flags &= ~IORESOURCE_UNSET;
a369c791	92	dev_dbg(&dev->dev, "BAR %d: moved to bus addr [%#llx-%#llx]\n",
80ccba11	93	resno, (unsigned long long)region.start,
a369c791	94	(unsigned long long)region.end);
1da177e4 LT	95	}
1da177e4 LT	96
96bde06a	97	int pci_claim_resource(struct pci_dev *dev, int resource)
1da177e4 LT	98	{
1da177e4 LT	99	struct resource *res = &dev->resource[resource];
cebd78a8	100	struct resource *root;
1da177e4 LT	101	int err;
1da177e4 LT	102
cebd78a8	103	root = pci_find_parent_resource(dev, res);
1da177e4 LT	104
	105	err = -EINVAL;
	106	if (root != NULL)
79896cf4	107	err = request_resource(root, res);
1da177e4 LT	108
1da177e4 LT	109	if (err) {
79896cf4	110	const char *dtype = resource < PCI_BRIDGE_RESOURCES ? "device" : "bridge";
a369c791	111	dev_err(&dev->dev, "BAR %d: %s %s %pRt\n",
80ccba11 BH	112	resource,
	113	root ? "address space collision on" :
	114	"no parent found for",
096e6f67	115	dtype, res);
1da177e4 LT	116	}
	117
	118	return err;
	119	}
eaa959df	120	EXPORT_SYMBOL(pci_claim_resource);
1da177e4	121
32a9a682 YS	122	#ifdef CONFIG_PCI_QUIRKS
	123	void pci_disable_bridge_window(struct pci_dev *dev)
	124	{
	125	dev_dbg(&dev->dev, "Disabling bridge window.\n");
	126
	127	/* MMIO Base/Limit */
	128	pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
	129
	130	/* Prefetchable MMIO Base/Limit */
	131	pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
	132	pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
	133	pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
	134	}
	135	#endif /* CONFIG_PCI_QUIRKS */
	136
d09ee968 YL	137	static int __pci_assign_resource(struct pci_bus bus, struct pci_dev dev,
d09ee968 YL	138	int resno)
1da177e4	139	{
1da177e4	140	struct resource *res = dev->resource + resno;
e31dd6e4	141	resource_size_t size, min, align;
1da177e4 LT	142	int ret;
1da177e4 LT	143
022edd86	144	size = resource_size(res);
1da177e4	145	min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
6faf17f6	146	align = pci_resource_alignment(dev, res);
1da177e4 LT	147
	148	/* First, try exact prefetching match.. */
	149	ret = pci_bus_alloc_resource(bus, res, size, align, min,
	150	IORESOURCE_PREFETCH,
	151	pcibios_align_resource, dev);
	152
	153	if (ret < 0 && (res->flags & IORESOURCE_PREFETCH)) {
	154	/*
	155	* That failed.
	156	*
	157	* But a prefetching area can handle a non-prefetching
	158	* window (it will just not perform as well).
	159	*/
	160	ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
	161	pcibios_align_resource, dev);
	162	}
	163
d09ee968	164	if (!ret) {
88452565 IK	165	res->flags &= ~IORESOURCE_STARTALIGN;
88452565 IK	166	if (resno < PCI_BRIDGE_RESOURCES)
14add80b	167	pci_update_resource(dev, resno);
1da177e4 LT	168	}
	169
	170	return ret;
	171	}
	172
d09ee968 YL	173	int pci_assign_resource(struct pci_dev *dev, int resno)
	174	{
	175	struct resource *res = dev->resource + resno;
	176	resource_size_t align;
	177	struct pci_bus *bus;
	178	int ret;
	179
6faf17f6	180	align = pci_resource_alignment(dev, res);
d09ee968	181	if (!align) {
a369c791 BH	182	dev_info(&dev->dev, "BAR %d: can't allocate %pRf "
a369c791 BH	183	"(bogus alignment)\n", resno, res);
d09ee968 YL	184	return -EINVAL;
	185	}
	186
	187	bus = dev->bus;
	188	while ((ret = __pci_assign_resource(bus, dev, resno))) {
	189	if (bus->parent && bus->self->transparent)
	190	bus = bus->parent;
	191	else
	192	bus = NULL;
	193	if (bus)
	194	continue;
	195	break;
	196	}
	197
	198	if (ret)
a369c791 BH	199	dev_info(&dev->dev, "BAR %d: can't allocate %pRt\n",
a369c791 BH	200	resno, res);
d09ee968 YL	201
	202	return ret;
	203	}
	204
1da177e4	205	/* Sort resources by alignment */
96bde06a	206	void pdev_sort_resources(struct pci_dev dev, struct resource_list head)
1da177e4 LT	207	{
	208	int i;
	209
	210	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	211	struct resource *r;
	212	struct resource_list list, tmp;
e31dd6e4	213	resource_size_t r_align;
1da177e4 LT	214
1da177e4 LT	215	r = &dev->resource[i];
fb0f2b40 RB	216
	217	if (r->flags & IORESOURCE_PCI_FIXED)
	218	continue;
	219
1da177e4 LT	220	if (!(r->flags) \|\| r->parent)
1da177e4 LT	221	continue;
88452565	222
6faf17f6	223	r_align = pci_resource_alignment(dev, r);
1da177e4	224	if (!r_align) {
a369c791 BH	225	dev_warn(&dev->dev, "BAR %d: bogus alignment %pRf\n",
a369c791 BH	226	i, r);
1da177e4 LT	227	continue;
1da177e4 LT	228	}
1da177e4	229	for (list = head; ; list = list->next) {
e31dd6e4	230	resource_size_t align = 0;
1da177e4	231	struct resource_list *ln = list->next;
88452565 IK	232
88452565 IK	233	if (ln)
6faf17f6	234	align = pci_resource_alignment(ln->dev, ln->res);
88452565	235
1da177e4 LT	236	if (r_align > align) {
	237	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
	238	if (!tmp)
	239	panic("pdev_sort_resources(): "
	240	"kmalloc() failed!\n");
	241	tmp->next = ln;
	242	tmp->res = r;
	243	tmp->dev = dev;
	244	list->next = tmp;
	245	break;
	246	}
	247	}
	248	}
	249	}
842de40d BH	250
	251	int pci_enable_resources(struct pci_dev *dev, int mask)
	252	{
	253	u16 cmd, old_cmd;
	254	int i;
	255	struct resource *r;
	256
	257	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	258	old_cmd = cmd;
	259
	260	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
	261	if (!(mask & (1 << i)))
	262	continue;
	263
	264	r = &dev->resource[i];
	265
	266	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	267	continue;
	268	if ((i == PCI_ROM_RESOURCE) &&
	269	(!(r->flags & IORESOURCE_ROM_ENABLE)))
	270	continue;
	271
	272	if (!r->parent) {
	273	dev_err(&dev->dev, "device not available because of "
096e6f67	274	"BAR %d %pR collisions\n", i, r);
842de40d BH	275	return -EINVAL;
	276	}
	277
	278	if (r->flags & IORESOURCE_IO)
	279	cmd \|= PCI_COMMAND_IO;
	280	if (r->flags & IORESOURCE_MEM)
	281	cmd \|= PCI_COMMAND_MEMORY;
	282	}
	283
	284	if (cmd != old_cmd) {
	285	dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
	286	old_cmd, cmd);
	287	pci_write_config_word(dev, PCI_COMMAND, cmd);
	288	}
	289	return 0;
	290	}