[deliverable/linux.git] / drivers / pcmcia / m32r_pcc.c

/*
 *  drivers/pcmcia/m32r_pcc.c
 *
 *  Device driver for the PCMCIA functionality of M32R.
 *
 *  Copyright (c) 2001, 2002, 2003, 2004
 *    Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/config.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/timer.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/ioport.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <asm/system.h>
#include <asm/addrspace.h>

#include <pcmcia/cs_types.h>
#include <pcmcia/ss.h>
#include <pcmcia/cs.h>

/* XXX: should be moved into asm/irq.h */
#define PCC0_IRQ 24
#define PCC1_IRQ 25

#include "m32r_pcc.h"

#define CHAOS_PCC_DEBUG
#ifdef CHAOS_PCC_DEBUG
	static volatile u_short dummy_readbuf;
#endif

#define PCC_DEBUG_DBEX

#ifdef DEBUG
static int m32r_pcc_debug;
module_param(m32r_pcc_debug, int, 0644);
#define debug(lvl, fmt, arg...) do {				\
	if (m32r_pcc_debug > (lvl))				\
		printk(KERN_DEBUG "m32r_pcc: " fmt , ## arg);	\
} while (0)
#else
#define debug(n, args...) do { } while (0)
#endif

/* Poll status interval -- 0 means default to interrupt */
static int poll_interval = 0;

typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;

typedef struct pcc_socket {
	u_short			type, flags;
	struct pcmcia_socket	socket;
	unsigned int		number;
 	kio_addr_t		ioaddr;
	u_long			mapaddr;
	u_long			base;	/* PCC register base */
	u_char			cs_irq, intr;
	pccard_io_map		io_map[MAX_IO_WIN];
	pccard_mem_map		mem_map[MAX_WIN];
	u_char			io_win;
	u_char			mem_win;
	pcc_as_t		current_space;
	u_char			last_iodbex;
#ifdef CHAOS_PCC_DEBUG
	u_char			last_iosize;
#endif
#ifdef CONFIG_PROC_FS
	struct proc_dir_entry *proc;
#endif
} pcc_socket_t;

static int pcc_sockets = 0;
static pcc_socket_t socket[M32R_MAX_PCC] = {
	{ 0, }, /* ... */
};

/*====================================================================*/

static unsigned int pcc_get(u_short, unsigned int);
static void pcc_set(u_short, unsigned int , unsigned int );

static DEFINE_SPINLOCK(pcc_lock);

void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
{
	u_long addr;
	u_long flags;
	int need_ex;
#ifdef PCC_DEBUG_DBEX
	int _dbex;
#endif
	pcc_socket_t *t = &socket[sock];
#ifdef CHAOS_PCC_DEBUG
	int map_changed = 0;
#endif

	/* Need lock ? */
	spin_lock_irqsave(&pcc_lock, flags);

	/*
	 * Check if need dbex
	 */
	need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
#ifdef PCC_DEBUG_DBEX
	_dbex = need_ex;
	need_ex = 0;
#endif

	/*
	 * calculate access address
	 */
	addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */

	/*
	 * Check current mapping
	 */
	if (t->current_space != as_io || t->last_iodbex != need_ex) {

		u_long cbsz;

		/*
		 * Disable first
		 */
		pcc_set(sock, PCCR, 0);

		/*
		 * Set mode and io address
		 */
		cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
		pcc_set(sock, PCMOD, PCMOD_AS_IO | cbsz | need_ex);
		pcc_set(sock, PCADR, addr & 0x1ff00000);

		/*
		 * Enable and read it
		 */
		pcc_set(sock, PCCR, 1);

#ifdef CHAOS_PCC_DEBUG
#if 0
		map_changed = (t->current_space == as_attr && size == 2); /* XXX */
#else
		map_changed = 1;
#endif
#endif
		t->current_space = as_io;
	}

	/*
	 * access to IO space
	 */
	if (size == 1) {
		/* Byte */
		unsigned char *bp = (unsigned char *)buf;

#ifdef CHAOS_DEBUG
		if (map_changed) {
			dummy_readbuf = readb(addr);
		}
#endif
		if (wr) {
			/* write Byte */
			while (nmemb--) {
				writeb(*bp++, addr);
			}
		} else {
			/* read Byte */
			while (nmemb--) {
	    		*bp++ = readb(addr);
			}
		}
	} else {
		/* Word */
		unsigned short *bp = (unsigned short *)buf;

#ifdef CHAOS_PCC_DEBUG
		if (map_changed) {
			dummy_readbuf = readw(addr);
		}
#endif
		if (wr) {
			/* write Word */
			while (nmemb--) {
#ifdef PCC_DEBUG_DBEX
				if (_dbex) {
					unsigned char *cp = (unsigned char *)bp;
					unsigned short tmp;
					tmp = cp[1] << 8 | cp[0];
					writew(tmp, addr);
					bp++;
				} else
#endif
				writew(*bp++, addr);
	    	}
	    } else {
	    	/* read Word */
	    	while (nmemb--) {
#ifdef  PCC_DEBUG_DBEX
				if (_dbex) {
					unsigned char *cp = (unsigned char *)bp;
					unsigned short tmp;
					tmp = readw(addr);
					cp[0] = tmp & 0xff;
					cp[1] = (tmp >> 8) & 0xff;
					bp++;
				} else
#endif
				*bp++ = readw(addr);
	    	}
	    }
	}

#if 1
	/* addr is no longer used */
	if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
	  printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
			 port, size * 8);
	  pcc_set(sock, PCIRC, addr);
	}
#endif
	/*
	 * save state
	 */
	t->last_iosize = size;
	t->last_iodbex = need_ex;

	/* Need lock ? */

	spin_unlock_irqrestore(&pcc_lock,flags);

	return;
}

void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
	pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
}

void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
    pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
}

/*====================================================================*/

#define IS_REGISTERED		0x2000
#define IS_ALIVE		0x8000

typedef struct pcc_t {
	char			*name;
	u_short			flags;
} pcc_t;

static pcc_t pcc[] = {
	{ "xnux2", 0 }, { "xnux2", 0 },
};

static irqreturn_t pcc_interrupt(int, void *, struct pt_regs *);

/*====================================================================*/

static struct timer_list poll_timer;

static unsigned int pcc_get(u_short sock, unsigned int reg)
{
	return inl(socket[sock].base + reg);
}


static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
{
  	outl(data, socket[sock].base + reg);
}

/*======================================================================

	See if a card is present, powered up, in IO mode, and already
	bound to a (non PC Card) Linux driver.  We leave these alone.

	We make an exception for cards that seem to be serial devices.

======================================================================*/

static int __init is_alive(u_short sock)
{
	unsigned int stat;
	unsigned int f;

	stat = pcc_get(sock, PCIRC);
	f = (stat & (PCIRC_CDIN1 | PCIRC_CDIN2)) >> 16;
	if(!f){
		printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
		return 0;
	}
	if(f!=3)
		printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
	else
		printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
	return 0;
}

static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr)
{
  	pcc_socket_t *t = &socket[pcc_sockets];

	/* add sockets */
	t->ioaddr = ioaddr;
	t->mapaddr = mapaddr;
	t->base = base;
#ifdef CHAOS_PCC_DEBUG
	t->flags = MAP_16BIT;
#else
	t->flags = 0;
#endif
	if (is_alive(pcc_sockets))
		t->flags |= IS_ALIVE;

	/* add pcc */
	if (t->base > 0) {
		request_region(t->base, 0x20, "m32r-pcc");
	}

	printk(KERN_INFO "  %s ", pcc[pcc_sockets].name);
	printk("pcc at 0x%08lx\n", t->base);

	/* Update socket interrupt information, capabilities */
	t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
	t->socket.map_size = M32R_PCC_MAPSIZE;
	t->socket.io_offset = ioaddr;	/* use for io access offset */
	t->socket.irq_mask = 0;
	t->socket.pci_irq = 2 + pcc_sockets; /* XXX */

	request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);

	pcc_sockets++;

	return;
}


/*====================================================================*/

static irqreturn_t pcc_interrupt(int irq, void *dev, struct pt_regs *regs)
{
	int i, j, irc;
	u_int events, active;
	int handled = 0;

	debug(4, "m32r: pcc_interrupt(%d)\n", irq);

	for (j = 0; j < 20; j++) {
		active = 0;
		for (i = 0; i < pcc_sockets; i++) {
			if ((socket[i].cs_irq != irq) &&
				(socket[i].socket.pci_irq != irq))
				continue;
			handled = 1;
			irc = pcc_get(i, PCIRC);
			irc >>=16;
			debug(2, "m32r-pcc:interrput: socket %d pcirc 0x%02x ", i, irc);
			if (!irc)
				continue;

			events = (irc) ? SS_DETECT : 0;
			events |= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
			debug(2, " event 0x%02x\n", events);

			if (events)
				pcmcia_parse_events(&socket[i].socket, events);

			active |= events;
			active = 0;
		}
		if (!active) break;
	}
	if (j == 20)
		printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");

	debug(4, "m32r-pcc: interrupt done\n");

	return IRQ_RETVAL(handled);
} /* pcc_interrupt */

static void pcc_interrupt_wrapper(u_long data)
{
	pcc_interrupt(0, NULL, NULL);
	init_timer(&poll_timer);
	poll_timer.expires = jiffies + poll_interval;
	add_timer(&poll_timer);
}

/*====================================================================*/

static int _pcc_get_status(u_short sock, u_int *value)
{
	u_int status;

	status = pcc_get(sock,PCIRC);
	*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
		? SS_DETECT : 0;

	status = pcc_get(sock,PCCR);

#if 0
	*value |= (status & PCCR_PCEN) ? SS_READY : 0;
#else
	*value |= SS_READY; /* XXX: always */
#endif

	status = pcc_get(sock,PCCSIGCR);
	*value |= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;

	debug(3, "m32r-pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
	return 0;
} /* _get_status */

/*====================================================================*/

static int _pcc_set_socket(u_short sock, socket_state_t *state)
{
	u_long reg = 0;

	debug(3, "m32r-pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
		  "io_irq %d, csc_mask %#2.2x)", sock, state->flags,
		  state->Vcc, state->Vpp, state->io_irq, state->csc_mask);

	if (state->Vcc) {
		/*
		 * 5V only
		 */
		if (state->Vcc == 50) {
			reg |= PCCSIGCR_VEN;
		} else {
			return -EINVAL;
		}
	}

	if (state->flags & SS_RESET) {
		debug(3, ":RESET\n");
		reg |= PCCSIGCR_CRST;
	}
	if (state->flags & SS_OUTPUT_ENA){
		debug(3, ":OUTPUT_ENA\n");
		/* bit clear */
	} else {
		reg |= PCCSIGCR_SEN;
	}

	pcc_set(sock,PCCSIGCR,reg);

#ifdef DEBUG
	if(state->flags & SS_IOCARD){
		debug(3, ":IOCARD");
	}
	if (state->flags & SS_PWR_AUTO) {
		debug(3, ":PWR_AUTO");
	}
	if (state->csc_mask & SS_DETECT)
		debug(3, ":csc-SS_DETECT");
	if (state->flags & SS_IOCARD) {
		if (state->csc_mask & SS_STSCHG)
			debug(3, ":STSCHG");
	} else {
		if (state->csc_mask & SS_BATDEAD)
			debug(3, ":BATDEAD");
		if (state->csc_mask & SS_BATWARN)
			debug(3, ":BATWARN");
		if (state->csc_mask & SS_READY)
			debug(3, ":READY");
	}
	debug(3, "\n");
#endif
	return 0;
} /* _set_socket */

/*====================================================================*/

static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
{
	u_char map;

	debug(3, "m32r-pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
		  "%#lx-%#lx)\n", sock, io->map, io->flags,
		  io->speed, io->start, io->stop);
	map = io->map;

	return 0;
} /* _set_io_map */

/*====================================================================*/

static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
{

	u_char map = mem->map;
	u_long mode;
	u_long addr;
	pcc_socket_t *t = &socket[sock];
#ifdef CHAOS_PCC_DEBUG
#if 0
	pcc_as_t last = t->current_space;
#endif
#endif

	debug(3, "m32r-pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
		 "%#lx,  %#x)\n", sock, map, mem->flags,
		 mem->speed, mem->static_start, mem->card_start);

	/*
	 * sanity check
	 */
	if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
		return -EINVAL;
	}

	/*
	 * de-activate
	 */
	if ((mem->flags & MAP_ACTIVE) == 0) {
		t->current_space = as_none;
		return 0;
	}

	/*
	 * Disable first
	 */
	pcc_set(sock, PCCR, 0);

	/*
	 * Set mode
	 */
	if (mem->flags & MAP_ATTRIB) {
		mode = PCMOD_AS_ATTRIB | PCMOD_CBSZ;
		t->current_space = as_attr;
	} else {
		mode = 0; /* common memory */
		t->current_space = as_comm;
	}
	pcc_set(sock, PCMOD, mode);

	/*
	 * Set address
	 */
	addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
	pcc_set(sock, PCADR, addr);

	mem->static_start = addr + mem->card_start;

	/*
	 * Enable again
	 */
	pcc_set(sock, PCCR, 1);

#ifdef CHAOS_PCC_DEBUG
#if 0
	if (last != as_attr) {
#else
	if (1) {
#endif
		dummy_readbuf = *(u_char *)(addr + KSEG1);
	}
#endif

	return 0;

} /* _set_mem_map */

#if 0 /* driver model ordering issue */
/*======================================================================

	Routines for accessing socket information and register dumps via
	/proc/bus/pccard/...

======================================================================*/

static ssize_t show_info(struct class_device *class_dev, char *buf)
{
	pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
		socket.dev);

	return sprintf(buf, "type:     %s\nbase addr:    0x%08lx\n",
		pcc[s->type].name, s->base);
}

static ssize_t show_exca(struct class_device *class_dev, char *buf)
{
	/* FIXME */

	return 0;
}

static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
#endif

/*====================================================================*/

/* this is horribly ugly... proper locking needs to be done here at
 * some time... */
#define LOCKED(x) do {					\
	int retval;					\
	unsigned long flags;				\
	spin_lock_irqsave(&pcc_lock, flags);		\
	retval = x;					\
	spin_unlock_irqrestore(&pcc_lock, flags);	\
	return retval;					\
} while (0)


static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE) {
		*value = 0;
		return -EINVAL;
	}
	LOCKED(_pcc_get_status(sock, value));
}

static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;

	LOCKED(_pcc_set_socket(sock, state));
}

static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;
	LOCKED(_pcc_set_io_map(sock, io));
}

static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
{
	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;

	if (socket[sock].flags & IS_ALIVE)
		return -EINVAL;
	LOCKED(_pcc_set_mem_map(sock, mem));
}

static int pcc_init(struct pcmcia_socket *s)
{
	debug(4, "m32r-pcc: init call\n");
	return 0;
}

static struct pccard_operations pcc_operations = {
	.init			= pcc_init,
	.get_status		= pcc_get_status,
	.set_socket		= pcc_set_socket,
	.set_io_map		= pcc_set_io_map,
	.set_mem_map		= pcc_set_mem_map,
};

/*====================================================================*/

static struct device_driver pcc_driver = {
	.name = "pcc",
	.bus = &platform_bus_type,
	.suspend = pcmcia_socket_dev_suspend,
	.resume = pcmcia_socket_dev_resume,
};

static struct platform_device pcc_device = {
	.name = "pcc",
	.id = 0,
};

/*====================================================================*/

static int __init init_m32r_pcc(void)
{
	int i, ret;

	ret = driver_register(&pcc_driver);
	if (ret)
		return ret;

	ret = platform_device_register(&pcc_device);
	if (ret){
		driver_unregister(&pcc_driver);
		return ret;
	}

	printk(KERN_INFO "m32r PCC probe:\n");

	pcc_sockets = 0;

	add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);

#ifdef CONFIG_M32RPCC_SLOT2
	add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
#endif

	if (pcc_sockets == 0) {
		printk("socket is not found.\n");
		platform_device_unregister(&pcc_device);
		driver_unregister(&pcc_driver);
		return -ENODEV;
	}

	/* Set up interrupt handler(s) */

	for (i = 0 ; i < pcc_sockets ; i++) {
		socket[i].socket.dev.dev = &pcc_device.dev;
		socket[i].socket.ops = &pcc_operations;
		socket[i].socket.resource_ops = &pccard_static_ops;
		socket[i].socket.owner = THIS_MODULE;
		socket[i].number = i;
		ret = pcmcia_register_socket(&socket[i].socket);
		if (!ret)
			socket[i].flags |= IS_REGISTERED;

#if 0	/* driver model ordering issue */
		class_device_create_file(&socket[i].socket.dev,
					 &class_device_attr_info);
		class_device_create_file(&socket[i].socket.dev,
					 &class_device_attr_exca);
#endif
	}

	/* Finally, schedule a polling interrupt */
	if (poll_interval != 0) {
		poll_timer.function = pcc_interrupt_wrapper;
		poll_timer.data = 0;
		init_timer(&poll_timer);
		poll_timer.expires = jiffies + poll_interval;
		add_timer(&poll_timer);
	}

	return 0;
} /* init_m32r_pcc */

static void __exit exit_m32r_pcc(void)
{
	int i;

	for (i = 0; i < pcc_sockets; i++)
		if (socket[i].flags & IS_REGISTERED)
			pcmcia_unregister_socket(&socket[i].socket);

	platform_device_unregister(&pcc_device);
	if (poll_interval != 0)
		del_timer_sync(&poll_timer);

	driver_unregister(&pcc_driver);
} /* exit_m32r_pcc */

module_init(init_m32r_pcc);
module_exit(exit_m32r_pcc);
MODULE_LICENSE("Dual MPL/GPL");
/*====================================================================*/
Commit	Line	Data
1da177e4 LT	1	/*
	2	* drivers/pcmcia/m32r_pcc.c
	3	*
	4	* Device driver for the PCMCIA functionality of M32R.
	5	*
	6	* Copyright (c) 2001, 2002, 2003, 2004
	7	* Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
	8	*/
	9
	10	#include <linux/module.h>
	11	#include <linux/moduleparam.h>
	12	#include <linux/init.h>
	13	#include <linux/config.h>
	14	#include <linux/types.h>
	15	#include <linux/fcntl.h>
	16	#include <linux/string.h>
	17	#include <linux/kernel.h>
	18	#include <linux/errno.h>
	19	#include <linux/timer.h>
	20	#include <linux/sched.h>
	21	#include <linux/slab.h>
	22	#include <linux/ioport.h>
	23	#include <linux/delay.h>
	24	#include <linux/workqueue.h>
	25	#include <linux/interrupt.h>
d052d1be	26	#include <linux/platform_device.h>
1da177e4 LT	27	#include <asm/irq.h>
	28	#include <asm/io.h>
	29	#include <asm/bitops.h>
	30	#include <asm/system.h>
	31	#include <asm/addrspace.h>
	32
1da177e4 LT	33	#include <pcmcia/cs_types.h>
	34	#include <pcmcia/ss.h>
	35	#include <pcmcia/cs.h>
	36
	37	/* XXX: should be moved into asm/irq.h */
	38	#define PCC0_IRQ 24
	39	#define PCC1_IRQ 25
	40
	41	#include "m32r_pcc.h"
	42
	43	#define CHAOS_PCC_DEBUG
	44	#ifdef CHAOS_PCC_DEBUG
	45	static volatile u_short dummy_readbuf;
	46	#endif
	47
	48	#define PCC_DEBUG_DBEX
	49
	50	#ifdef DEBUG
	51	static int m32r_pcc_debug;
	52	module_param(m32r_pcc_debug, int, 0644);
	53	#define debug(lvl, fmt, arg...) do { \
	54	if (m32r_pcc_debug > (lvl)) \
	55	printk(KERN_DEBUG "m32r_pcc: " fmt , ## arg); \
	56	} while (0)
	57	#else
	58	#define debug(n, args...) do { } while (0)
	59	#endif
	60
	61	/* Poll status interval -- 0 means default to interrupt */
	62	static int poll_interval = 0;
	63
	64	typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
	65
	66	typedef struct pcc_socket {
	67	u_short type, flags;
	68	struct pcmcia_socket socket;
	69	unsigned int number;
	70	kio_addr_t ioaddr;
	71	u_long mapaddr;
	72	u_long base; /* PCC register base */
	73	u_char cs_irq, intr;
	74	pccard_io_map io_map[MAX_IO_WIN];
	75	pccard_mem_map mem_map[MAX_WIN];
	76	u_char io_win;
	77	u_char mem_win;
	78	pcc_as_t current_space;
	79	u_char last_iodbex;
	80	#ifdef CHAOS_PCC_DEBUG
	81	u_char last_iosize;
	82	#endif
	83	#ifdef CONFIG_PROC_FS
	84	struct proc_dir_entry *proc;
	85	#endif
	86	} pcc_socket_t;
	87
	88	static int pcc_sockets = 0;
	89	static pcc_socket_t socket[M32R_MAX_PCC] = {
	90	{ 0, }, /* ... */
	91	};
	92
	93	/====================================================================/
	94
	95	static unsigned int pcc_get(u_short, unsigned int);
	96	static void pcc_set(u_short, unsigned int , unsigned int );
97
98	static DEFINE_SPINLOCK(pcc_lock);
99
100	void pcc_iorw(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int wr, int flag)
101	{
102	u_long addr;
103	u_long flags;
104	int need_ex;
105	#ifdef PCC_DEBUG_DBEX
106	int _dbex;
107	#endif
108	pcc_socket_t *t = &socket[sock];
109	#ifdef CHAOS_PCC_DEBUG
110	int map_changed = 0;
111	#endif
112
113	/* Need lock ? */
114	spin_lock_irqsave(&pcc_lock, flags);
115
116	/*
117	* Check if need dbex
118	*/
119	need_ex = (size > 1 && flag == 0) ? PCMOD_DBEX : 0;
120	#ifdef PCC_DEBUG_DBEX
121	_dbex = need_ex;
122	need_ex = 0;
123	#endif
124
125	/*
126	* calculate access address
127	*/
128	addr = t->mapaddr + port - t->ioaddr + KSEG1; /* XXX */
129
130	/*
131	* Check current mapping
132	*/
133	if (t->current_space != as_io \|\| t->last_iodbex != need_ex) {
134
135	u_long cbsz;
136
137	/*
138	* Disable first
139	*/
140	pcc_set(sock, PCCR, 0);
141
142	/*
143	* Set mode and io address
144	*/
145	cbsz = (t->flags & MAP_16BIT) ? 0 : PCMOD_CBSZ;
146	pcc_set(sock, PCMOD, PCMOD_AS_IO \| cbsz \| need_ex);
147	pcc_set(sock, PCADR, addr & 0x1ff00000);
148
149	/*
150	* Enable and read it
151	*/
152	pcc_set(sock, PCCR, 1);
153
154	#ifdef CHAOS_PCC_DEBUG
155	#if 0
156	map_changed = (t->current_space == as_attr && size == 2); /* XXX */
157	#else
158	map_changed = 1;
159	#endif
160	#endif
161	t->current_space = as_io;
162	}
163
164	/*
165	* access to IO space
166	*/
167	if (size == 1) {
168	/* Byte */
169	unsigned char bp = (unsigned char )buf;
170
171	#ifdef CHAOS_DEBUG
172	if (map_changed) {
173	dummy_readbuf = readb(addr);
174	}
175	#endif
176	if (wr) {
177	/* write Byte */
178	while (nmemb--) {
179	writeb(*bp++, addr);
180	}
181	} else {
182	/* read Byte */
183	while (nmemb--) {
184	*bp++ = readb(addr);
185	}
186	}
187	} else {
188	/* Word */
189	unsigned short bp = (unsigned short )buf;
190
191	#ifdef CHAOS_PCC_DEBUG
192	if (map_changed) {
193	dummy_readbuf = readw(addr);
194	}
195	#endif
196	if (wr) {
197	/* write Word */
198	while (nmemb--) {
199	#ifdef PCC_DEBUG_DBEX
200	if (_dbex) {
201	unsigned char cp = (unsigned char )bp;
202	unsigned short tmp;
203	tmp = cp[1] << 8 \| cp[0];
204	writew(tmp, addr);
205	bp++;
206	} else
207	#endif
208	writew(*bp++, addr);
209	}
210	} else {
211	/* read Word */
212	while (nmemb--) {
213	#ifdef PCC_DEBUG_DBEX
214	if (_dbex) {
215	unsigned char cp = (unsigned char )bp;
216	unsigned short tmp;
217	tmp = readw(addr);
218	cp[0] = tmp & 0xff;
219	cp[1] = (tmp >> 8) & 0xff;
220	bp++;
221	} else
222	#endif
223	*bp++ = readw(addr);
224	}
225	}
226	}
227
228	#if 1
229	/* addr is no longer used */
230	if ((addr = pcc_get(sock, PCIRC)) & PCIRC_BWERR) {
231	printk("m32r_pcc: BWERR detected : port 0x%04lx : iosize %dbit\n",
232	port, size * 8);
233	pcc_set(sock, PCIRC, addr);
234	}
235	#endif
236	/*
237	* save state
238	*/
239	t->last_iosize = size;
240	t->last_iodbex = need_ex;
241
242	/* Need lock ? */
243
244	spin_unlock_irqrestore(&pcc_lock,flags);
245
246	return;
247	}
248
249	void pcc_ioread(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
250	pcc_iorw(sock, port, buf, size, nmemb, 0, flag);
251	}
252
253	void pcc_iowrite(int sock, unsigned long port, void *buf, size_t size, size_t nmemb, int flag) {
254	pcc_iorw(sock, port, buf, size, nmemb, 1, flag);
255	}
256
257	/====================================================================/
258
259	#define IS_REGISTERED 0x2000
260	#define IS_ALIVE 0x8000
261
262	typedef struct pcc_t {
263	char *name;
264	u_short flags;
265	} pcc_t;
266
267	static pcc_t pcc[] = {
268	{ "xnux2", 0 }, { "xnux2", 0 },
269	};
270
271	static irqreturn_t pcc_interrupt(int, void , struct pt_regs );
272
273	/====================================================================/
274
275	static struct timer_list poll_timer;
276
277	static unsigned int pcc_get(u_short sock, unsigned int reg)
278	{
279	return inl(socket[sock].base + reg);
280	}
281
282
283	static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
284	{
285	outl(data, socket[sock].base + reg);
286	}
287
288	/*======================================================================
289
290	See if a card is present, powered up, in IO mode, and already
291	bound to a (non PC Card) Linux driver. We leave these alone.
292
293	We make an exception for cards that seem to be serial devices.
294
295	======================================================================*/
296
297	static int __init is_alive(u_short sock)
298	{
299	unsigned int stat;
300	unsigned int f;
301
302	stat = pcc_get(sock, PCIRC);
303	f = (stat & (PCIRC_CDIN1 \| PCIRC_CDIN2)) >> 16;
304	if(!f){
305	printk("m32r_pcc: No Card is detected at socket %d : stat = 0x%08x\n",stat,sock);
306	return 0;
307	}
308	if(f!=3)
309	printk("m32r_pcc: Insertion fail (%.8x) at socket %d\n",stat,sock);
310	else
311	printk("m32r_pcc: Card is Inserted at socket %d(%.8x)\n",sock,stat);
312	return 0;
313	}
314
315	static void add_pcc_socket(ulong base, int irq, ulong mapaddr, kio_addr_t ioaddr)
316	{
317	pcc_socket_t *t = &socket[pcc_sockets];
318
319	/* add sockets */
320	t->ioaddr = ioaddr;
321	t->mapaddr = mapaddr;
322	t->base = base;
323	#ifdef CHAOS_PCC_DEBUG
324	t->flags = MAP_16BIT;
325	#else
326	t->flags = 0;
327	#endif
328	if (is_alive(pcc_sockets))
329	t->flags \|= IS_ALIVE;
330
331	/* add pcc */
332	if (t->base > 0) {
333	request_region(t->base, 0x20, "m32r-pcc");
334	}
335
336	printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
337	printk("pcc at 0x%08lx\n", t->base);
338
339	/* Update socket interrupt information, capabilities */
340	t->socket.features \|= (SS_CAP_PCCARD \| SS_CAP_STATIC_MAP);
341	t->socket.map_size = M32R_PCC_MAPSIZE;
342	t->socket.io_offset = ioaddr; /* use for io access offset */
343	t->socket.irq_mask = 0;
344	t->socket.pci_irq = 2 + pcc_sockets; /* XXX */
345
346	request_irq(irq, pcc_interrupt, 0, "m32r-pcc", pcc_interrupt);
347
348	pcc_sockets++;
349
350	return;
351	}
352
353
354	/====================================================================/
355
356	static irqreturn_t pcc_interrupt(int irq, void dev, struct pt_regs regs)
357	{
358	int i, j, irc;
359	u_int events, active;
360	int handled = 0;
361
362	debug(4, "m32r: pcc_interrupt(%d)\n", irq);
363
364	for (j = 0; j < 20; j++) {
365	active = 0;
366	for (i = 0; i < pcc_sockets; i++) {
367	if ((socket[i].cs_irq != irq) &&
368	(socket[i].socket.pci_irq != irq))
369	continue;
370	handled = 1;
371	irc = pcc_get(i, PCIRC);
372	irc >>=16;
373	debug(2, "m32r-pcc:interrput: socket %d pcirc 0x%02x ", i, irc);
374	if (!irc)
375	continue;
376
377	events = (irc) ? SS_DETECT : 0;
378	events \|= (pcc_get(i,PCCR) & PCCR_PCEN) ? SS_READY : 0;
379	debug(2, " event 0x%02x\n", events);
380
381	if (events)
382	pcmcia_parse_events(&socket[i].socket, events);
383
384	active \|= events;
385	active = 0;
386	}
387	if (!active) break;
388	}
389	if (j == 20)
390	printk(KERN_NOTICE "m32r-pcc: infinite loop in interrupt handler\n");
391
392	debug(4, "m32r-pcc: interrupt done\n");
393
394	return IRQ_RETVAL(handled);
395	} /* pcc_interrupt */
396
397	static void pcc_interrupt_wrapper(u_long data)
398	{
399	pcc_interrupt(0, NULL, NULL);
400	init_timer(&poll_timer);
401	poll_timer.expires = jiffies + poll_interval;
402	add_timer(&poll_timer);
403	}
404
405	/====================================================================/
406
407	static int _pcc_get_status(u_short sock, u_int *value)
408	{
409	u_int status;
410
411	status = pcc_get(sock,PCIRC);
412	*value = ((status & PCIRC_CDIN1) && (status & PCIRC_CDIN2))
413	? SS_DETECT : 0;
414
415	status = pcc_get(sock,PCCR);
416
417	#if 0
418	*value \|= (status & PCCR_PCEN) ? SS_READY : 0;
419	#else
420	value \|= SS_READY; / XXX: always */
421	#endif
422
423	status = pcc_get(sock,PCCSIGCR);
424	*value \|= (status & PCCSIGCR_VEN) ? SS_POWERON : 0;
425
426	debug(3, "m32r-pcc: GetStatus(%d) = %#4.4x\n", sock, *value);
427	return 0;
428	} /* _get_status */
429
430	/====================================================================/
431
1da177e4 LT	432	static int _pcc_set_socket(u_short sock, socket_state_t *state)
	433	{
	434	u_long reg = 0;
	435
	436	debug(3, "m32r-pcc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
	437	"io_irq %d, csc_mask %#2.2x)", sock, state->flags,
	438	state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
	439
	440	if (state->Vcc) {
	441	/*
	442	* 5V only
	443	*/
	444	if (state->Vcc == 50) {
	445	reg \|= PCCSIGCR_VEN;
	446	} else {
	447	return -EINVAL;
	448	}
	449	}
	450
	451	if (state->flags & SS_RESET) {
	452	debug(3, ":RESET\n");
	453	reg \|= PCCSIGCR_CRST;
	454	}
	455	if (state->flags & SS_OUTPUT_ENA){
	456	debug(3, ":OUTPUT_ENA\n");
	457	/* bit clear */
	458	} else {
	459	reg \|= PCCSIGCR_SEN;
	460	}
	461
	462	pcc_set(sock,PCCSIGCR,reg);
	463
	464	#ifdef DEBUG
	465	if(state->flags & SS_IOCARD){
	466	debug(3, ":IOCARD");
	467	}
	468	if (state->flags & SS_PWR_AUTO) {
	469	debug(3, ":PWR_AUTO");
	470	}
	471	if (state->csc_mask & SS_DETECT)
	472	debug(3, ":csc-SS_DETECT");
	473	if (state->flags & SS_IOCARD) {
	474	if (state->csc_mask & SS_STSCHG)
	475	debug(3, ":STSCHG");
	476	} else {
	477	if (state->csc_mask & SS_BATDEAD)
	478	debug(3, ":BATDEAD");
	479	if (state->csc_mask & SS_BATWARN)
	480	debug(3, ":BATWARN");
	481	if (state->csc_mask & SS_READY)
	482	debug(3, ":READY");
	483	}
	484	debug(3, "\n");
	485	#endif
	486	return 0;
	487	} /* _set_socket */
	488
	489	/====================================================================/
	490
	491	static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
	492	{
	493	u_char map;
	494
	495	debug(3, "m32r-pcc: SetIOMap(%d, %d, %#2.2x, %d ns, "
496	"%#lx-%#lx)\n", sock, io->map, io->flags,
497	io->speed, io->start, io->stop);
498	map = io->map;
499
500	return 0;
501	} /* _set_io_map */
502
503	/====================================================================/
504
505	static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
506	{
507
508	u_char map = mem->map;
509	u_long mode;
510	u_long addr;
511	pcc_socket_t *t = &socket[sock];
512	#ifdef CHAOS_PCC_DEBUG
513	#if 0
514	pcc_as_t last = t->current_space;
515	#endif
516	#endif
517
518	debug(3, "m32r-pcc: SetMemMap(%d, %d, %#2.2x, %d ns, "
519	"%#lx, %#x)\n", sock, map, mem->flags,
520	mem->speed, mem->static_start, mem->card_start);
521
522	/*
523	* sanity check
524	*/
525	if ((map > MAX_WIN) \|\| (mem->card_start > 0x3ffffff)){
526	return -EINVAL;
527	}
528
529	/*
530	* de-activate
531	*/
532	if ((mem->flags & MAP_ACTIVE) == 0) {
533	t->current_space = as_none;
534	return 0;
535	}
536
537	/*
538	* Disable first
539	*/
540	pcc_set(sock, PCCR, 0);
541
542	/*
543	* Set mode
544	*/
545	if (mem->flags & MAP_ATTRIB) {
546	mode = PCMOD_AS_ATTRIB \| PCMOD_CBSZ;
547	t->current_space = as_attr;
548	} else {
549	mode = 0; /* common memory */
550	t->current_space = as_comm;
551	}
552	pcc_set(sock, PCMOD, mode);
553
554	/*
555	* Set address
556	*/
557	addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
558	pcc_set(sock, PCADR, addr);
559
560	mem->static_start = addr + mem->card_start;
561
562	/*
563	* Enable again
564	*/
565	pcc_set(sock, PCCR, 1);
566
567	#ifdef CHAOS_PCC_DEBUG
568	#if 0
569	if (last != as_attr) {
570	#else
571	if (1) {
572	#endif
573	dummy_readbuf = (u_char )(addr + KSEG1);
574	}
575	#endif
576
577	return 0;
578
579	} /* _set_mem_map */
580
581	#if 0 /* driver model ordering issue */
582	/*======================================================================
583
584	Routines for accessing socket information and register dumps via
585	/proc/bus/pccard/...
586
587	======================================================================*/
588
589	static ssize_t show_info(struct class_device class_dev, char buf)
590	{
591	pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
592	socket.dev);
593
594	return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
595	pcc[s->type].name, s->base);
596	}
597
598	static ssize_t show_exca(struct class_device class_dev, char buf)
599	{
600	/* FIXME */
601
602	return 0;
603	}
604
605	static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
606	static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
607	#endif
608
609	/====================================================================/
610
611	/* this is horribly ugly... proper locking needs to be done here at
612	* some time... */
613	#define LOCKED(x) do { \
614	int retval; \
615	unsigned long flags; \
616	spin_lock_irqsave(&pcc_lock, flags); \
617	retval = x; \
618	spin_unlock_irqrestore(&pcc_lock, flags); \
619	return retval; \
620	} while (0)
621
622
623	static int pcc_get_status(struct pcmcia_socket s, u_int value)
624	{
625	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
626
627	if (socket[sock].flags & IS_ALIVE) {
628	*value = 0;
629	return -EINVAL;
630	}
631	LOCKED(_pcc_get_status(sock, value));
632	}
633
1da177e4 LT	634	static int pcc_set_socket(struct pcmcia_socket s, socket_state_t state)
	635	{
	636	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	637
	638	if (socket[sock].flags & IS_ALIVE)
	639	return -EINVAL;
	640
	641	LOCKED(_pcc_set_socket(sock, state));
	642	}
	643
	644	static int pcc_set_io_map(struct pcmcia_socket s, struct pccard_io_map io)
	645	{
	646	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	647
	648	if (socket[sock].flags & IS_ALIVE)
	649	return -EINVAL;
	650	LOCKED(_pcc_set_io_map(sock, io));
	651	}
	652
	653	static int pcc_set_mem_map(struct pcmcia_socket s, struct pccard_mem_map mem)
	654	{
	655	unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
	656
	657	if (socket[sock].flags & IS_ALIVE)
	658	return -EINVAL;
	659	LOCKED(_pcc_set_mem_map(sock, mem));
	660	}
	661
	662	static int pcc_init(struct pcmcia_socket *s)
	663	{
	664	debug(4, "m32r-pcc: init call\n");
	665	return 0;
	666	}
	667
	668	static struct pccard_operations pcc_operations = {
	669	.init = pcc_init,
	670	.get_status = pcc_get_status,
1da177e4 LT	671	.set_socket = pcc_set_socket,
	672	.set_io_map = pcc_set_io_map,
	673	.set_mem_map = pcc_set_mem_map,
	674	};
	675
	676	/====================================================================/
	677
1da177e4 LT	678	static struct device_driver pcc_driver = {
	679	.name = "pcc",
	680	.bus = &platform_bus_type,
9480e307 RK	681	.suspend = pcmcia_socket_dev_suspend,
9480e307 RK	682	.resume = pcmcia_socket_dev_resume,
1da177e4 LT	683	};
	684
	685	static struct platform_device pcc_device = {
	686	.name = "pcc",
	687	.id = 0,
	688	};
	689
	690	/====================================================================/
	691
	692	static int __init init_m32r_pcc(void)
	693	{
	694	int i, ret;
	695
	696	ret = driver_register(&pcc_driver);
	697	if (ret)
	698	return ret;
	699
	700	ret = platform_device_register(&pcc_device);
	701	if (ret){
	702	driver_unregister(&pcc_driver);
	703	return ret;
	704	}
	705
	706	printk(KERN_INFO "m32r PCC probe:\n");
	707
	708	pcc_sockets = 0;
	709
	710	add_pcc_socket(M32R_PCC0_BASE, PCC0_IRQ, M32R_PCC0_MAPBASE, 0x1000);
	711
	712	#ifdef CONFIG_M32RPCC_SLOT2
	713	add_pcc_socket(M32R_PCC1_BASE, PCC1_IRQ, M32R_PCC1_MAPBASE, 0x2000);
	714	#endif
	715
	716	if (pcc_sockets == 0) {
	717	printk("socket is not found.\n");
	718	platform_device_unregister(&pcc_device);
	719	driver_unregister(&pcc_driver);
	720	return -ENODEV;
	721	}
	722
	723	/* Set up interrupt handler(s) */
	724
	725	for (i = 0 ; i < pcc_sockets ; i++) {
	726	socket[i].socket.dev.dev = &pcc_device.dev;
	727	socket[i].socket.ops = &pcc_operations;
	728	socket[i].socket.resource_ops = &pccard_static_ops;
	729	socket[i].socket.owner = THIS_MODULE;
	730	socket[i].number = i;
	731	ret = pcmcia_register_socket(&socket[i].socket);
	732	if (!ret)
	733	socket[i].flags \|= IS_REGISTERED;
	734
	735	#if 0 /* driver model ordering issue */
	736	class_device_create_file(&socket[i].socket.dev,
	737	&class_device_attr_info);
	738	class_device_create_file(&socket[i].socket.dev,
	739	&class_device_attr_exca);
	740	#endif
	741	}
	742
	743	/* Finally, schedule a polling interrupt */
	744	if (poll_interval != 0) {
	745	poll_timer.function = pcc_interrupt_wrapper;
	746	poll_timer.data = 0;
747	init_timer(&poll_timer);
748	poll_timer.expires = jiffies + poll_interval;
749	add_timer(&poll_timer);
750	}
751
752	return 0;
753	} /* init_m32r_pcc */
754
755	static void __exit exit_m32r_pcc(void)
756	{
757	int i;
758
759	for (i = 0; i < pcc_sockets; i++)
760	if (socket[i].flags & IS_REGISTERED)
761	pcmcia_unregister_socket(&socket[i].socket);
762
763	platform_device_unregister(&pcc_device);
764	if (poll_interval != 0)
765	del_timer_sync(&poll_timer);
766
767	driver_unregister(&pcc_driver);
768	} /* exit_m32r_pcc */
769
770	module_init(init_m32r_pcc);
771	module_exit(exit_m32r_pcc);
772	MODULE_LICENSE("Dual MPL/GPL");
773	/====================================================================/