Commit | Line | Data |
---|---|---|
f74e48a5 DB |
1 | /* |
2 | * omap_cf.c -- OMAP 16xx CompactFlash controller driver | |
3 | * | |
4 | * Copyright (c) 2005 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
d052d1be | 14 | #include <linux/platform_device.h> |
f74e48a5 DB |
15 | #include <linux/errno.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | ||
20 | #include <pcmcia/ss.h> | |
21 | ||
22 | #include <asm/hardware.h> | |
23 | #include <asm/io.h> | |
f74e48a5 DB |
24 | #include <asm/sizes.h> |
25 | ||
26 | #include <asm/arch/mux.h> | |
27 | #include <asm/arch/tc.h> | |
28 | ||
29 | ||
30 | /* NOTE: don't expect this to support many I/O cards. The 16xx chips have | |
31 | * hard-wired timings to support Compact Flash memory cards; they won't work | |
32 | * with various other devices (like WLAN adapters) without some external | |
33 | * logic to help out. | |
34 | * | |
35 | * NOTE: CF controller docs disagree with address space docs as to where | |
36 | * CF_BASE really lives; this is a doc erratum. | |
37 | */ | |
38 | #define CF_BASE 0xfffe2800 | |
39 | ||
40 | /* status; read after IRQ */ | |
41 | #define CF_STATUS_REG __REG16(CF_BASE + 0x00) | |
42 | # define CF_STATUS_BAD_READ (1 << 2) | |
43 | # define CF_STATUS_BAD_WRITE (1 << 1) | |
44 | # define CF_STATUS_CARD_DETECT (1 << 0) | |
45 | ||
46 | /* which chipselect (CS0..CS3) is used for CF (active low) */ | |
47 | #define CF_CFG_REG __REG16(CF_BASE + 0x02) | |
48 | ||
49 | /* card reset */ | |
50 | #define CF_CONTROL_REG __REG16(CF_BASE + 0x04) | |
51 | # define CF_CONTROL_RESET (1 << 0) | |
52 | ||
53 | #define omap_cf_present() (!(CF_STATUS_REG & CF_STATUS_CARD_DETECT)) | |
54 | ||
55 | /*--------------------------------------------------------------------------*/ | |
56 | ||
57 | static const char driver_name[] = "omap_cf"; | |
58 | ||
59 | struct omap_cf_socket { | |
60 | struct pcmcia_socket socket; | |
61 | ||
62 | struct timer_list timer; | |
63 | unsigned present:1; | |
64 | unsigned active:1; | |
65 | ||
66 | struct platform_device *pdev; | |
67 | unsigned long phys_cf; | |
68 | u_int irq; | |
dcb9c392 | 69 | struct resource iomem; |
f74e48a5 DB |
70 | }; |
71 | ||
72 | #define POLL_INTERVAL (2 * HZ) | |
73 | ||
74 | #define SZ_2K (2 * SZ_1K) | |
75 | ||
76 | /*--------------------------------------------------------------------------*/ | |
77 | ||
78 | static int omap_cf_ss_init(struct pcmcia_socket *s) | |
79 | { | |
80 | return 0; | |
81 | } | |
82 | ||
83 | /* the timer is primarily to kick this socket's pccardd */ | |
84 | static void omap_cf_timer(unsigned long _cf) | |
85 | { | |
86 | struct omap_cf_socket *cf = (void *) _cf; | |
87 | unsigned present = omap_cf_present(); | |
88 | ||
89 | if (present != cf->present) { | |
90 | cf->present = present; | |
91 | pr_debug("%s: card %s\n", driver_name, | |
92 | present ? "present" : "gone"); | |
93 | pcmcia_parse_events(&cf->socket, SS_DETECT); | |
94 | } | |
95 | ||
96 | if (cf->active) | |
97 | mod_timer(&cf->timer, jiffies + POLL_INTERVAL); | |
98 | } | |
99 | ||
100 | /* This irq handler prevents "irqNNN: nobody cared" messages as drivers | |
101 | * claim the card's IRQ. It may also detect some card insertions, but | |
102 | * not removals; it can't always eliminate timer irqs. | |
103 | */ | |
7d12e780 | 104 | static irqreturn_t omap_cf_irq(int irq, void *_cf) |
f74e48a5 DB |
105 | { |
106 | omap_cf_timer((unsigned long)_cf); | |
107 | return IRQ_HANDLED; | |
108 | } | |
109 | ||
110 | static int omap_cf_get_status(struct pcmcia_socket *s, u_int *sp) | |
111 | { | |
112 | if (!sp) | |
113 | return -EINVAL; | |
114 | ||
dcb9c392 | 115 | /* NOTE CF is always 3VCARD */ |
f74e48a5 DB |
116 | if (omap_cf_present()) { |
117 | struct omap_cf_socket *cf; | |
118 | ||
119 | *sp = SS_READY | SS_DETECT | SS_POWERON | SS_3VCARD; | |
120 | cf = container_of(s, struct omap_cf_socket, socket); | |
dcb9c392 DB |
121 | s->irq.AssignedIRQ = 0; |
122 | s->pci_irq = cf->irq; | |
f74e48a5 DB |
123 | } else |
124 | *sp = 0; | |
125 | return 0; | |
126 | } | |
127 | ||
128 | static int | |
129 | omap_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s) | |
130 | { | |
131 | u16 control; | |
132 | ||
dcb9c392 | 133 | /* REVISIT some non-OSK boards may support power switching */ |
f74e48a5 DB |
134 | switch (s->Vcc) { |
135 | case 0: | |
136 | case 33: | |
137 | break; | |
138 | default: | |
139 | return -EINVAL; | |
140 | } | |
141 | ||
142 | control = CF_CONTROL_REG; | |
143 | if (s->flags & SS_RESET) | |
144 | CF_CONTROL_REG = CF_CONTROL_RESET; | |
145 | else | |
146 | CF_CONTROL_REG = 0; | |
147 | ||
148 | pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n", | |
149 | driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static int omap_cf_ss_suspend(struct pcmcia_socket *s) | |
155 | { | |
156 | pr_debug("%s: %s\n", driver_name, __FUNCTION__); | |
157 | return omap_cf_set_socket(s, &dead_socket); | |
158 | } | |
159 | ||
160 | /* regions are 2K each: mem, attrib, io (and reserved-for-ide) */ | |
161 | ||
162 | static int | |
163 | omap_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io) | |
164 | { | |
165 | struct omap_cf_socket *cf; | |
166 | ||
167 | cf = container_of(s, struct omap_cf_socket, socket); | |
168 | io->flags &= MAP_ACTIVE|MAP_ATTRIB|MAP_16BIT; | |
169 | io->start = cf->phys_cf + SZ_4K; | |
170 | io->stop = io->start + SZ_2K - 1; | |
171 | return 0; | |
172 | } | |
173 | ||
174 | static int | |
175 | omap_cf_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *map) | |
176 | { | |
177 | struct omap_cf_socket *cf; | |
178 | ||
179 | if (map->card_start) | |
180 | return -EINVAL; | |
181 | cf = container_of(s, struct omap_cf_socket, socket); | |
182 | map->static_start = cf->phys_cf; | |
183 | map->flags &= MAP_ACTIVE|MAP_ATTRIB|MAP_16BIT; | |
184 | if (map->flags & MAP_ATTRIB) | |
185 | map->static_start += SZ_2K; | |
186 | return 0; | |
187 | } | |
188 | ||
189 | static struct pccard_operations omap_cf_ops = { | |
190 | .init = omap_cf_ss_init, | |
191 | .suspend = omap_cf_ss_suspend, | |
192 | .get_status = omap_cf_get_status, | |
193 | .set_socket = omap_cf_set_socket, | |
194 | .set_io_map = omap_cf_set_io_map, | |
195 | .set_mem_map = omap_cf_set_mem_map, | |
196 | }; | |
197 | ||
198 | /*--------------------------------------------------------------------------*/ | |
199 | ||
200 | /* | |
201 | * NOTE: right now the only board-specific platform_data is | |
202 | * "what chipselect is used". Boards could want more. | |
203 | */ | |
204 | ||
b6d2cccb | 205 | static int __init omap_cf_probe(struct platform_device *pdev) |
f74e48a5 DB |
206 | { |
207 | unsigned seg; | |
208 | struct omap_cf_socket *cf; | |
f74e48a5 DB |
209 | int irq; |
210 | int status; | |
211 | ||
b6d2cccb | 212 | seg = (int) pdev->dev.platform_data; |
f74e48a5 DB |
213 | if (seg == 0 || seg > 3) |
214 | return -ENODEV; | |
215 | ||
216 | /* either CFLASH.IREQ (INT_1610_CF) or some GPIO */ | |
217 | irq = platform_get_irq(pdev, 0); | |
48944738 | 218 | if (irq < 0) |
f74e48a5 DB |
219 | return -EINVAL; |
220 | ||
cd861280 | 221 | cf = kzalloc(sizeof *cf, GFP_KERNEL); |
f74e48a5 DB |
222 | if (!cf) |
223 | return -ENOMEM; | |
224 | init_timer(&cf->timer); | |
225 | cf->timer.function = omap_cf_timer; | |
226 | cf->timer.data = (unsigned long) cf; | |
227 | ||
228 | cf->pdev = pdev; | |
b6d2cccb | 229 | platform_set_drvdata(pdev, cf); |
f74e48a5 DB |
230 | |
231 | /* this primarily just shuts up irq handling noise */ | |
dace1453 | 232 | status = request_irq(irq, omap_cf_irq, IRQF_SHARED, |
f74e48a5 DB |
233 | driver_name, cf); |
234 | if (status < 0) | |
235 | goto fail0; | |
236 | cf->irq = irq; | |
237 | cf->socket.pci_irq = irq; | |
238 | ||
239 | switch (seg) { | |
240 | /* NOTE: CS0 could be configured too ... */ | |
241 | case 1: | |
242 | cf->phys_cf = OMAP_CS1_PHYS; | |
243 | break; | |
244 | case 2: | |
245 | cf->phys_cf = OMAP_CS2_PHYS; | |
246 | break; | |
247 | case 3: | |
248 | cf->phys_cf = omap_cs3_phys(); | |
249 | break; | |
250 | default: | |
251 | goto fail1; | |
252 | } | |
dcb9c392 DB |
253 | cf->iomem.start = cf->phys_cf; |
254 | cf->iomem.end = cf->iomem.end + SZ_8K - 1; | |
255 | cf->iomem.flags = IORESOURCE_MEM; | |
f74e48a5 DB |
256 | |
257 | /* pcmcia layer only remaps "real" memory */ | |
258 | cf->socket.io_offset = (unsigned long) | |
259 | ioremap(cf->phys_cf + SZ_4K, SZ_2K); | |
260 | if (!cf->socket.io_offset) | |
261 | goto fail1; | |
262 | ||
263 | if (!request_mem_region(cf->phys_cf, SZ_8K, driver_name)) | |
264 | goto fail1; | |
265 | ||
266 | /* NOTE: CF conflicts with MMC1 */ | |
267 | omap_cfg_reg(W11_1610_CF_CD1); | |
268 | omap_cfg_reg(P11_1610_CF_CD2); | |
269 | omap_cfg_reg(R11_1610_CF_IOIS16); | |
270 | omap_cfg_reg(V10_1610_CF_IREQ); | |
271 | omap_cfg_reg(W10_1610_CF_RESET); | |
272 | ||
273 | CF_CFG_REG = ~(1 << seg); | |
274 | ||
275 | pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq); | |
276 | ||
277 | /* NOTE: better EMIFS setup might support more cards; but the | |
278 | * TRM only shows how to affect regular flash signals, not their | |
279 | * CF/PCMCIA variants... | |
280 | */ | |
281 | pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name, | |
282 | seg, EMIFS_CCS(seg), EMIFS_ACS(seg)); | |
283 | EMIFS_CCS(seg) = 0x0004a1b3; /* synch mode 4 etc */ | |
284 | EMIFS_ACS(seg) = 0x00000000; /* OE hold/setup */ | |
285 | ||
286 | /* CF uses armxor_ck, which is "always" available */ | |
287 | ||
288 | pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name, | |
289 | CF_STATUS_REG, CF_CFG_REG, CF_CONTROL_REG, | |
290 | omap_cf_present() ? "present" : "(not present)"); | |
291 | ||
292 | cf->socket.owner = THIS_MODULE; | |
b6d2cccb | 293 | cf->socket.dev.parent = &pdev->dev; |
f74e48a5 DB |
294 | cf->socket.ops = &omap_cf_ops; |
295 | cf->socket.resource_ops = &pccard_static_ops; | |
296 | cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP | |
297 | | SS_CAP_MEM_ALIGN; | |
298 | cf->socket.map_size = SZ_2K; | |
dcb9c392 | 299 | cf->socket.io[0].res = &cf->iomem; |
f74e48a5 DB |
300 | |
301 | status = pcmcia_register_socket(&cf->socket); | |
302 | if (status < 0) | |
303 | goto fail2; | |
304 | ||
305 | cf->active = 1; | |
306 | mod_timer(&cf->timer, jiffies + POLL_INTERVAL); | |
307 | return 0; | |
308 | ||
309 | fail2: | |
f74e48a5 DB |
310 | release_mem_region(cf->phys_cf, SZ_8K); |
311 | fail1: | |
3efa9970 AL |
312 | if (cf->socket.io_offset) |
313 | iounmap((void __iomem *) cf->socket.io_offset); | |
f74e48a5 DB |
314 | free_irq(irq, cf); |
315 | fail0: | |
316 | kfree(cf); | |
317 | return status; | |
318 | } | |
319 | ||
b6d2cccb | 320 | static int __exit omap_cf_remove(struct platform_device *pdev) |
f74e48a5 | 321 | { |
b6d2cccb | 322 | struct omap_cf_socket *cf = platform_get_drvdata(pdev); |
f74e48a5 DB |
323 | |
324 | cf->active = 0; | |
325 | pcmcia_unregister_socket(&cf->socket); | |
326 | del_timer_sync(&cf->timer); | |
327 | iounmap((void __iomem *) cf->socket.io_offset); | |
328 | release_mem_region(cf->phys_cf, SZ_8K); | |
329 | free_irq(cf->irq, cf); | |
330 | kfree(cf); | |
331 | return 0; | |
332 | } | |
333 | ||
b6d2cccb DB |
334 | static int omap_cf_suspend(struct platform_device *pdev, pm_message_t mesg) |
335 | { | |
336 | return pcmcia_socket_dev_suspend(&pdev->dev, mesg); | |
337 | } | |
338 | ||
339 | static int omap_cf_resume(struct platform_device *pdev) | |
340 | { | |
341 | return pcmcia_socket_dev_resume(&pdev->dev); | |
342 | } | |
343 | ||
344 | static struct platform_driver omap_cf_driver = { | |
345 | .driver = { | |
346 | .name = (char *) driver_name, | |
12c2c019 | 347 | .owner = THIS_MODULE, |
b6d2cccb DB |
348 | }, |
349 | .remove = __exit_p(omap_cf_remove), | |
350 | .suspend = omap_cf_suspend, | |
351 | .resume = omap_cf_resume, | |
f74e48a5 DB |
352 | }; |
353 | ||
354 | static int __init omap_cf_init(void) | |
355 | { | |
356 | if (cpu_is_omap16xx()) | |
b6d2cccb | 357 | return platform_driver_probe(&omap_cf_driver, omap_cf_probe); |
dcb9c392 | 358 | return -ENODEV; |
f74e48a5 DB |
359 | } |
360 | ||
361 | static void __exit omap_cf_exit(void) | |
362 | { | |
363 | if (cpu_is_omap16xx()) | |
b6d2cccb | 364 | platform_driver_unregister(&omap_cf_driver); |
f74e48a5 DB |
365 | } |
366 | ||
367 | module_init(omap_cf_init); | |
368 | module_exit(omap_cf_exit); | |
369 | ||
370 | MODULE_DESCRIPTION("OMAP CF Driver"); | |
371 | MODULE_LICENSE("GPL"); | |
12c2c019 | 372 | MODULE_ALIAS("platform:omap_cf"); |