[deliverable/linux.git] / drivers / phy / phy-brcmstb-sata.c

/*
 * Broadcom SATA3 AHCI Controller PHY Driver
 *
 * Copyright © 2009-2015 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/device.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>

#define SATA_MDIO_BANK_OFFSET				0x23c
#define SATA_MDIO_REG_OFFSET(ofs)			((ofs) * 4)

#define MAX_PORTS					2

/* Register offset between PHYs in PCB space */
#define SATA_MDIO_REG_28NM_SPACE_SIZE			0x1000

enum brcm_sata_phy_version {
	BRCM_SATA_PHY_28NM,
};

struct brcm_sata_port {
	int portnum;
	struct phy *phy;
	struct brcm_sata_phy *phy_priv;
	bool ssc_en;
};

struct brcm_sata_phy {
	struct device *dev;
	void __iomem *phy_base;
	enum brcm_sata_phy_version version;

	struct brcm_sata_port phys[MAX_PORTS];
};

enum sata_mdio_phy_regs_28nm {
	PLL_REG_BANK_0				= 0x50,
	PLL_REG_BANK_0_PLLCONTROL_0		= 0x81,

	TXPMD_REG_BANK				= 0x1a0,
	TXPMD_CONTROL1				= 0x81,
	TXPMD_CONTROL1_TX_SSC_EN_FRC		= BIT(0),
	TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL	= BIT(1),
	TXPMD_TX_FREQ_CTRL_CONTROL1		= 0x82,
	TXPMD_TX_FREQ_CTRL_CONTROL2		= 0x83,
	TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK	= 0x3ff,
	TXPMD_TX_FREQ_CTRL_CONTROL3		= 0x84,
	TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK	= 0x3ff,
};

static inline void __iomem *brcm_sata_phy_base(struct brcm_sata_port *port)
{
	struct brcm_sata_phy *priv = port->phy_priv;
	u32 offset;

	if (priv->version == BRCM_SATA_PHY_28NM)
		offset = SATA_MDIO_REG_28NM_SPACE_SIZE;

	return priv->phy_base + (port->portnum * offset);
}

static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
			      u32 msk, u32 value)
{
	u32 tmp;

	writel(bank, addr + SATA_MDIO_BANK_OFFSET);
	tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs));
	tmp = (tmp & msk) | value;
	writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs));
}

/* These defaults were characterized by H/W group */
#define FMIN_VAL_DEFAULT	0x3df
#define FMAX_VAL_DEFAULT	0x3df
#define FMAX_VAL_SSC		0x83

static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
{
	void __iomem *base = brcm_sata_phy_base(port);
	struct brcm_sata_phy *priv = port->phy_priv;
	u32 tmp;

	/* override the TX spread spectrum setting */
	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
	brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);

	/* set fixed min freq */
	brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
			  ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
			  FMIN_VAL_DEFAULT);

	/* set fixed max freq depending on SSC config */
	if (port->ssc_en) {
		dev_info(priv->dev, "enabling SSC on port %d\n", port->portnum);
		tmp = FMAX_VAL_SSC;
	} else {
		tmp = FMAX_VAL_DEFAULT;
	}

	brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
			  ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
}

static int brcm_sata_phy_init(struct phy *phy)
{
	struct brcm_sata_port *port = phy_get_drvdata(phy);

	brcm_sata_cfg_ssc_28nm(port);

	return 0;
}

static const struct phy_ops phy_ops_28nm = {
	.init		= brcm_sata_phy_init,
	.owner		= THIS_MODULE,
};

static const struct of_device_id brcm_sata_phy_of_match[] = {
	{ .compatible	= "brcm,bcm7445-sata-phy",
	  .data = (void *)BRCM_SATA_PHY_28NM },
	{},
};
MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);

static int brcm_sata_phy_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *dn = dev->of_node, *child;
	const struct of_device_id *of_id;
	struct brcm_sata_phy *priv;
	struct resource *res;
	struct phy_provider *provider;
	int ret, count = 0;

	if (of_get_child_count(dn) == 0)
		return -ENODEV;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;
	dev_set_drvdata(dev, priv);
	priv->dev = dev;

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
	priv->phy_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(priv->phy_base))
		return PTR_ERR(priv->phy_base);

	of_id = of_match_node(brcm_sata_phy_of_match, dn);
	if (of_id)
		priv->version = (enum brcm_sata_phy_version)of_id->data;
	else
		priv->version = BRCM_SATA_PHY_28NM;

	for_each_available_child_of_node(dn, child) {
		unsigned int id;
		struct brcm_sata_port *port;

		if (of_property_read_u32(child, "reg", &id)) {
			dev_err(dev, "missing reg property in node %s\n",
					child->name);
			ret = -EINVAL;
			goto put_child;
		}

		if (id >= MAX_PORTS) {
			dev_err(dev, "invalid reg: %u\n", id);
			ret = -EINVAL;
			goto put_child;
		}
		if (priv->phys[id].phy) {
			dev_err(dev, "already registered port %u\n", id);
			ret = -EINVAL;
			goto put_child;
		}

		port = &priv->phys[id];
		port->portnum = id;
		port->phy_priv = priv;
		port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
		port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
		if (IS_ERR(port->phy)) {
			dev_err(dev, "failed to create PHY\n");
			ret = PTR_ERR(port->phy);
			goto put_child;
		}

		phy_set_drvdata(port->phy, port);
		count++;
	}

	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	if (IS_ERR(provider)) {
		dev_err(dev, "could not register PHY provider\n");
		return PTR_ERR(provider);
	}

	dev_info(dev, "registered %d port(s)\n", count);

	return 0;
put_child:
	of_node_put(child);
	return ret;
}

static struct platform_driver brcm_sata_phy_driver = {
	.probe	= brcm_sata_phy_probe,
	.driver	= {
		.of_match_table	= brcm_sata_phy_of_match,
		.name		= "brcmstb-sata-phy",
	}
};
module_platform_driver(brcm_sata_phy_driver);

MODULE_DESCRIPTION("Broadcom STB SATA PHY driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Marc Carino");
MODULE_AUTHOR("Brian Norris");
MODULE_ALIAS("platform:phy-brcmstb-sata");
Commit	Line	Data
0d486806 BN	1	/*
	2	* Broadcom SATA3 AHCI Controller PHY Driver
	3	*
	4	* Copyright © 2009-2015 Broadcom Corporation
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/device.h>
	18	#include <linux/init.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/io.h>
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/of.h>
	24	#include <linux/phy/phy.h>
	25	#include <linux/platform_device.h>
	26
	27	#define SATA_MDIO_BANK_OFFSET 0x23c
	28	#define SATA_MDIO_REG_OFFSET(ofs) ((ofs) * 4)
0d486806 BN	29
	30	#define MAX_PORTS 2
	31
	32	/* Register offset between PHYs in PCB space */
810c6f16 JS	33	#define SATA_MDIO_REG_28NM_SPACE_SIZE 0x1000
	34
	35	enum brcm_sata_phy_version {
	36	BRCM_SATA_PHY_28NM,
	37	};
0d486806 BN	38
	39	struct brcm_sata_port {
	40	int portnum;
	41	struct phy *phy;
	42	struct brcm_sata_phy *phy_priv;
	43	bool ssc_en;
	44	};
	45
	46	struct brcm_sata_phy {
	47	struct device *dev;
	48	void __iomem *phy_base;
810c6f16	49	enum brcm_sata_phy_version version;
0d486806 BN	50
	51	struct brcm_sata_port phys[MAX_PORTS];
	52	};
	53
	54	enum sata_mdio_phy_regs_28nm {
	55	PLL_REG_BANK_0 = 0x50,
	56	PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
	57
	58	TXPMD_REG_BANK = 0x1a0,
	59	TXPMD_CONTROL1 = 0x81,
	60	TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
	61	TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
	62	TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
	63	TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
	64	TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
	65	TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
	66	TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
	67	};
	68
	69	static inline void __iomem brcm_sata_phy_base(struct brcm_sata_port port)
	70	{
	71	struct brcm_sata_phy *priv = port->phy_priv;
810c6f16	72	u32 offset;
0d486806	73
810c6f16 JS	74	if (priv->version == BRCM_SATA_PHY_28NM)
	75	offset = SATA_MDIO_REG_28NM_SPACE_SIZE;
	76
	77	return priv->phy_base + (port->portnum * offset);
0d486806 BN	78	}
	79
	80	static void brcm_sata_mdio_wr(void __iomem *addr, u32 bank, u32 ofs,
	81	u32 msk, u32 value)
	82	{
	83	u32 tmp;
	84
	85	writel(bank, addr + SATA_MDIO_BANK_OFFSET);
	86	tmp = readl(addr + SATA_MDIO_REG_OFFSET(ofs));
	87	tmp = (tmp & msk) \| value;
	88	writel(tmp, addr + SATA_MDIO_REG_OFFSET(ofs));
	89	}
	90
	91	/* These defaults were characterized by H/W group */
	92	#define FMIN_VAL_DEFAULT 0x3df
	93	#define FMAX_VAL_DEFAULT 0x3df
	94	#define FMAX_VAL_SSC 0x83
	95
	96	static void brcm_sata_cfg_ssc_28nm(struct brcm_sata_port *port)
	97	{
	98	void __iomem *base = brcm_sata_phy_base(port);
	99	struct brcm_sata_phy *priv = port->phy_priv;
	100	u32 tmp;
	101
	102	/* override the TX spread spectrum setting */
	103	tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL \| TXPMD_CONTROL1_TX_SSC_EN_FRC;
	104	brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
	105
	106	/* set fixed min freq */
	107	brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
	108	~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
	109	FMIN_VAL_DEFAULT);
	110
	111	/* set fixed max freq depending on SSC config */
	112	if (port->ssc_en) {
	113	dev_info(priv->dev, "enabling SSC on port %d\n", port->portnum);
	114	tmp = FMAX_VAL_SSC;
	115	} else {
	116	tmp = FMAX_VAL_DEFAULT;
	117	}
	118
	119	brcm_sata_mdio_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
	120	~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
	121	}
	122
	123	static int brcm_sata_phy_init(struct phy *phy)
	124	{
	125	struct brcm_sata_port *port = phy_get_drvdata(phy);
	126
	127	brcm_sata_cfg_ssc_28nm(port);
	128
	129	return 0;
	130	}
	131
4a9e5ca1	132	static const struct phy_ops phy_ops_28nm = {
0d486806 BN	133	.init = brcm_sata_phy_init,
	134	.owner = THIS_MODULE,
	135	};
	136
	137	static const struct of_device_id brcm_sata_phy_of_match[] = {
810c6f16 JS	138	{ .compatible = "brcm,bcm7445-sata-phy",
810c6f16 JS	139	.data = (void *)BRCM_SATA_PHY_28NM },
0d486806 BN	140	{},
	141	};
	142	MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
	143
	144	static int brcm_sata_phy_probe(struct platform_device *pdev)
	145	{
	146	struct device *dev = &pdev->dev;
	147	struct device_node dn = dev->of_node, child;
810c6f16	148	const struct of_device_id *of_id;
0d486806 BN	149	struct brcm_sata_phy *priv;
	150	struct resource *res;
	151	struct phy_provider *provider;
0b25ff86	152	int ret, count = 0;
0d486806 BN	153
	154	if (of_get_child_count(dn) == 0)
	155	return -ENODEV;
	156
	157	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	158	if (!priv)
	159	return -ENOMEM;
	160	dev_set_drvdata(dev, priv);
	161	priv->dev = dev;
	162
	163	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
	164	priv->phy_base = devm_ioremap_resource(dev, res);
	165	if (IS_ERR(priv->phy_base))
	166	return PTR_ERR(priv->phy_base);
	167
810c6f16 JS	168	of_id = of_match_node(brcm_sata_phy_of_match, dn);
	169	if (of_id)
	170	priv->version = (enum brcm_sata_phy_version)of_id->data;
	171	else
	172	priv->version = BRCM_SATA_PHY_28NM;
	173
0d486806 BN	174	for_each_available_child_of_node(dn, child) {
	175	unsigned int id;
	176	struct brcm_sata_port *port;
	177
	178	if (of_property_read_u32(child, "reg", &id)) {
	179	dev_err(dev, "missing reg property in node %s\n",
	180	child->name);
0b25ff86 JL	181	ret = -EINVAL;
0b25ff86 JL	182	goto put_child;
0d486806 BN	183	}
	184
	185	if (id >= MAX_PORTS) {
	186	dev_err(dev, "invalid reg: %u\n", id);
0b25ff86 JL	187	ret = -EINVAL;
0b25ff86 JL	188	goto put_child;
0d486806 BN	189	}
	190	if (priv->phys[id].phy) {
	191	dev_err(dev, "already registered port %u\n", id);
0b25ff86 JL	192	ret = -EINVAL;
0b25ff86 JL	193	goto put_child;
0d486806 BN	194	}
	195
	196	port = &priv->phys[id];
	197	port->portnum = id;
	198	port->phy_priv = priv;
	199	port->phy = devm_phy_create(dev, child, &phy_ops_28nm);
	200	port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
	201	if (IS_ERR(port->phy)) {
	202	dev_err(dev, "failed to create PHY\n");
0b25ff86 JL	203	ret = PTR_ERR(port->phy);
0b25ff86 JL	204	goto put_child;
0d486806 BN	205	}
	206
	207	phy_set_drvdata(port->phy, port);
	208	count++;
	209	}
	210
	211	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	212	if (IS_ERR(provider)) {
	213	dev_err(dev, "could not register PHY provider\n");
	214	return PTR_ERR(provider);
	215	}
	216
	217	dev_info(dev, "registered %d port(s)\n", count);
	218
	219	return 0;
0b25ff86 JL	220	put_child:
	221	of_node_put(child);
	222	return ret;
0d486806 BN	223	}
	224
	225	static struct platform_driver brcm_sata_phy_driver = {
	226	.probe = brcm_sata_phy_probe,
	227	.driver = {
	228	.of_match_table = brcm_sata_phy_of_match,
	229	.name = "brcmstb-sata-phy",
	230	}
	231	};
	232	module_platform_driver(brcm_sata_phy_driver);
	233
	234	MODULE_DESCRIPTION("Broadcom STB SATA PHY driver");
	235	MODULE_LICENSE("GPL");
	236	MODULE_AUTHOR("Marc Carino");
	237	MODULE_AUTHOR("Brian Norris");
	238	MODULE_ALIAS("platform:phy-brcmstb-sata");