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069d2e26 SN |
1 | /* |
2 | * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * Author: Sylwester Nawrocki <s.nawrocki@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
22fda307 | 12 | #include <linux/err.h> |
069d2e26 SN |
13 | #include <linux/io.h> |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/phy/phy.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/spinlock.h> | |
21 | ||
22 | /* MIPI_PHYn_CONTROL register offset: n = 0..1 */ | |
23 | #define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4) | |
24 | #define EXYNOS_MIPI_PHY_ENABLE (1 << 0) | |
25 | #define EXYNOS_MIPI_PHY_SRESETN (1 << 1) | |
26 | #define EXYNOS_MIPI_PHY_MRESETN (1 << 2) | |
27 | #define EXYNOS_MIPI_PHY_RESET_MASK (3 << 1) | |
28 | ||
29 | enum exynos_mipi_phy_id { | |
30 | EXYNOS_MIPI_PHY_ID_CSIS0, | |
31 | EXYNOS_MIPI_PHY_ID_DSIM0, | |
32 | EXYNOS_MIPI_PHY_ID_CSIS1, | |
33 | EXYNOS_MIPI_PHY_ID_DSIM1, | |
34 | EXYNOS_MIPI_PHYS_NUM | |
35 | }; | |
36 | ||
37 | #define is_mipi_dsim_phy_id(id) \ | |
38 | ((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1) | |
39 | ||
40 | struct exynos_mipi_video_phy { | |
41 | spinlock_t slock; | |
42 | struct video_phy_desc { | |
43 | struct phy *phy; | |
44 | unsigned int index; | |
45 | } phys[EXYNOS_MIPI_PHYS_NUM]; | |
46 | void __iomem *regs; | |
47 | }; | |
48 | ||
49 | static int __set_phy_state(struct exynos_mipi_video_phy *state, | |
50 | enum exynos_mipi_phy_id id, unsigned int on) | |
51 | { | |
52 | void __iomem *addr; | |
53 | u32 reg, reset; | |
54 | ||
55 | addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2); | |
56 | ||
57 | if (is_mipi_dsim_phy_id(id)) | |
58 | reset = EXYNOS_MIPI_PHY_MRESETN; | |
59 | else | |
60 | reset = EXYNOS_MIPI_PHY_SRESETN; | |
61 | ||
62 | spin_lock(&state->slock); | |
63 | reg = readl(addr); | |
64 | if (on) | |
65 | reg |= reset; | |
66 | else | |
67 | reg &= ~reset; | |
68 | writel(reg, addr); | |
69 | ||
70 | /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set. */ | |
71 | if (on) | |
72 | reg |= EXYNOS_MIPI_PHY_ENABLE; | |
73 | else if (!(reg & EXYNOS_MIPI_PHY_RESET_MASK)) | |
74 | reg &= ~EXYNOS_MIPI_PHY_ENABLE; | |
75 | ||
76 | writel(reg, addr); | |
77 | spin_unlock(&state->slock); | |
78 | return 0; | |
79 | } | |
80 | ||
81 | #define to_mipi_video_phy(desc) \ | |
82 | container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]); | |
83 | ||
84 | static int exynos_mipi_video_phy_power_on(struct phy *phy) | |
85 | { | |
86 | struct video_phy_desc *phy_desc = phy_get_drvdata(phy); | |
87 | struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc); | |
88 | ||
89 | return __set_phy_state(state, phy_desc->index, 1); | |
90 | } | |
91 | ||
92 | static int exynos_mipi_video_phy_power_off(struct phy *phy) | |
93 | { | |
94 | struct video_phy_desc *phy_desc = phy_get_drvdata(phy); | |
95 | struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc); | |
96 | ||
e3967e7b | 97 | return __set_phy_state(state, phy_desc->index, 0); |
069d2e26 SN |
98 | } |
99 | ||
100 | static struct phy *exynos_mipi_video_phy_xlate(struct device *dev, | |
101 | struct of_phandle_args *args) | |
102 | { | |
103 | struct exynos_mipi_video_phy *state = dev_get_drvdata(dev); | |
104 | ||
98c3b322 | 105 | if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM)) |
069d2e26 SN |
106 | return ERR_PTR(-ENODEV); |
107 | ||
108 | return state->phys[args->args[0]].phy; | |
109 | } | |
110 | ||
111 | static struct phy_ops exynos_mipi_video_phy_ops = { | |
112 | .power_on = exynos_mipi_video_phy_power_on, | |
113 | .power_off = exynos_mipi_video_phy_power_off, | |
114 | .owner = THIS_MODULE, | |
115 | }; | |
116 | ||
117 | static int exynos_mipi_video_phy_probe(struct platform_device *pdev) | |
118 | { | |
119 | struct exynos_mipi_video_phy *state; | |
120 | struct device *dev = &pdev->dev; | |
121 | struct resource *res; | |
122 | struct phy_provider *phy_provider; | |
123 | unsigned int i; | |
124 | ||
125 | state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); | |
126 | if (!state) | |
127 | return -ENOMEM; | |
128 | ||
129 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130 | ||
131 | state->regs = devm_ioremap_resource(dev, res); | |
132 | if (IS_ERR(state->regs)) | |
133 | return PTR_ERR(state->regs); | |
134 | ||
135 | dev_set_drvdata(dev, state); | |
136 | spin_lock_init(&state->slock); | |
137 | ||
069d2e26 | 138 | for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) { |
f0ed8176 | 139 | struct phy *phy = devm_phy_create(dev, NULL, |
069d2e26 SN |
140 | &exynos_mipi_video_phy_ops, NULL); |
141 | if (IS_ERR(phy)) { | |
142 | dev_err(dev, "failed to create PHY %d\n", i); | |
143 | return PTR_ERR(phy); | |
144 | } | |
145 | ||
146 | state->phys[i].phy = phy; | |
147 | state->phys[i].index = i; | |
148 | phy_set_drvdata(phy, &state->phys[i]); | |
149 | } | |
150 | ||
64fe1891 KVA |
151 | phy_provider = devm_of_phy_provider_register(dev, |
152 | exynos_mipi_video_phy_xlate); | |
64fe1891 | 153 | |
22fda307 | 154 | return PTR_ERR_OR_ZERO(phy_provider); |
069d2e26 SN |
155 | } |
156 | ||
157 | static const struct of_device_id exynos_mipi_video_phy_of_match[] = { | |
158 | { .compatible = "samsung,s5pv210-mipi-video-phy" }, | |
159 | { }, | |
160 | }; | |
161 | MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match); | |
162 | ||
163 | static struct platform_driver exynos_mipi_video_phy_driver = { | |
164 | .probe = exynos_mipi_video_phy_probe, | |
165 | .driver = { | |
166 | .of_match_table = exynos_mipi_video_phy_of_match, | |
167 | .name = "exynos-mipi-video-phy", | |
168 | .owner = THIS_MODULE, | |
169 | } | |
170 | }; | |
171 | module_platform_driver(exynos_mipi_video_phy_driver); | |
172 | ||
173 | MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver"); | |
174 | MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); | |
175 | MODULE_LICENSE("GPL v2"); |