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2c14e9be GF |
1 | /* |
2 | * Copyright (C) 2014 STMicroelectronics | |
3 | * | |
4 | * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). | |
5 | * | |
6 | * Author: Alexandre Torgue <alexandre.torgue@st.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2, as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/platform_device.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_platform.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/phy/phy.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/mfd/syscon.h> | |
25 | #include <linux/regmap.h> | |
26 | #include <linux/reset.h> | |
27 | ||
28 | #include <dt-bindings/phy/phy.h> | |
29 | ||
30 | /* MiPHY registers */ | |
31 | #define MIPHY_CONF_RESET 0x00 | |
32 | #define RST_APPLI_SW BIT(0) | |
33 | #define RST_CONF_SW BIT(1) | |
34 | #define RST_MACRO_SW BIT(2) | |
35 | ||
36 | #define MIPHY_RESET 0x01 | |
37 | #define RST_PLL_SW BIT(0) | |
38 | #define RST_COMP_SW BIT(2) | |
39 | ||
40 | #define MIPHY_STATUS_1 0x02 | |
41 | #define PHY_RDY BIT(0) | |
42 | #define HFC_RDY BIT(1) | |
43 | #define HFC_PLL BIT(2) | |
44 | ||
45 | #define MIPHY_CONTROL 0x04 | |
46 | #define TERM_EN_SW BIT(2) | |
47 | #define DIS_LINK_RST BIT(3) | |
48 | #define AUTO_RST_RX BIT(4) | |
49 | #define PX_RX_POL BIT(5) | |
50 | ||
51 | #define MIPHY_BOUNDARY_SEL 0x0a | |
52 | #define TX_SEL BIT(6) | |
53 | #define SSC_SEL BIT(4) | |
54 | #define GENSEL_SEL BIT(0) | |
55 | ||
56 | #define MIPHY_BOUNDARY_1 0x0b | |
57 | #define MIPHY_BOUNDARY_2 0x0c | |
58 | #define SSC_EN_SW BIT(2) | |
59 | ||
60 | #define MIPHY_PLL_CLKREF_FREQ 0x0d | |
61 | #define MIPHY_SPEED 0x0e | |
62 | #define TX_SPDSEL_80DEC 0 | |
63 | #define TX_SPDSEL_40DEC 1 | |
64 | #define TX_SPDSEL_20DEC 2 | |
65 | #define RX_SPDSEL_80DEC 0 | |
66 | #define RX_SPDSEL_40DEC (1 << 2) | |
67 | #define RX_SPDSEL_20DEC (2 << 2) | |
68 | ||
69 | #define MIPHY_CONF 0x0f | |
70 | #define MIPHY_CTRL_TEST_SEL 0x20 | |
71 | #define MIPHY_CTRL_TEST_1 0x21 | |
72 | #define MIPHY_CTRL_TEST_2 0x22 | |
73 | #define MIPHY_CTRL_TEST_3 0x23 | |
74 | #define MIPHY_CTRL_TEST_4 0x24 | |
75 | #define MIPHY_FEEDBACK_TEST 0x25 | |
76 | #define MIPHY_DEBUG_BUS 0x26 | |
77 | #define MIPHY_DEBUG_STATUS_MSB 0x27 | |
78 | #define MIPHY_DEBUG_STATUS_LSB 0x28 | |
79 | #define MIPHY_PWR_RAIL_1 0x29 | |
80 | #define MIPHY_PWR_RAIL_2 0x2a | |
81 | #define MIPHY_SYNCHAR_CONTROL 0x30 | |
82 | ||
83 | #define MIPHY_COMP_FSM_1 0x3a | |
84 | #define COMP_START BIT(6) | |
85 | ||
86 | #define MIPHY_COMP_FSM_6 0x3f | |
87 | #define COMP_DONE BIT(7) | |
88 | ||
89 | #define MIPHY_COMP_POSTP 0x42 | |
90 | #define MIPHY_TX_CTRL_1 0x49 | |
91 | #define TX_REG_STEP_0V 0 | |
92 | #define TX_REG_STEP_P_25MV 1 | |
93 | #define TX_REG_STEP_P_50MV 2 | |
94 | #define TX_REG_STEP_N_25MV 7 | |
95 | #define TX_REG_STEP_N_50MV 6 | |
96 | #define TX_REG_STEP_N_75MV 5 | |
97 | ||
98 | #define MIPHY_TX_CTRL_2 0x4a | |
99 | #define TX_SLEW_SW_40_PS 0 | |
100 | #define TX_SLEW_SW_80_PS 1 | |
101 | #define TX_SLEW_SW_120_PS 2 | |
102 | ||
103 | #define MIPHY_TX_CTRL_3 0x4b | |
104 | #define MIPHY_TX_CAL_MAN 0x4e | |
105 | #define TX_SLEW_CAL_MAN_EN BIT(0) | |
106 | ||
107 | #define MIPHY_TST_BIAS_BOOST_2 0x62 | |
108 | #define MIPHY_BIAS_BOOST_1 0x63 | |
109 | #define MIPHY_BIAS_BOOST_2 0x64 | |
110 | #define MIPHY_RX_DESBUFF_FDB_2 0x67 | |
111 | #define MIPHY_RX_DESBUFF_FDB_3 0x68 | |
112 | #define MIPHY_SIGDET_COMPENS1 0x69 | |
113 | #define MIPHY_SIGDET_COMPENS2 0x6a | |
114 | #define MIPHY_JITTER_PERIOD 0x6b | |
115 | #define MIPHY_JITTER_AMPLITUDE_1 0x6c | |
116 | #define MIPHY_JITTER_AMPLITUDE_2 0x6d | |
117 | #define MIPHY_JITTER_AMPLITUDE_3 0x6e | |
118 | #define MIPHY_RX_K_GAIN 0x78 | |
119 | #define MIPHY_RX_BUFFER_CTRL 0x7a | |
120 | #define VGA_GAIN BIT(0) | |
121 | #define EQ_DC_GAIN BIT(2) | |
122 | #define EQ_BOOST_GAIN BIT(3) | |
123 | ||
124 | #define MIPHY_RX_VGA_GAIN 0x7b | |
125 | #define MIPHY_RX_EQU_GAIN_1 0x7f | |
126 | #define MIPHY_RX_EQU_GAIN_2 0x80 | |
127 | #define MIPHY_RX_EQU_GAIN_3 0x81 | |
128 | #define MIPHY_RX_CAL_CTRL_1 0x97 | |
129 | #define MIPHY_RX_CAL_CTRL_2 0x98 | |
130 | ||
131 | #define MIPHY_RX_CAL_OFFSET_CTRL 0x99 | |
132 | #define CAL_OFFSET_VGA_64 (0x03 << 0) | |
133 | #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2) | |
134 | #define VGA_OFFSET_POLARITY BIT(4) | |
135 | #define OFFSET_COMPENSATION_EN BIT(6) | |
136 | ||
137 | #define MIPHY_RX_CAL_VGA_STEP 0x9a | |
138 | #define MIPHY_RX_CAL_EYE_MIN 0x9d | |
139 | #define MIPHY_RX_CAL_OPT_LENGTH 0x9f | |
140 | #define MIPHY_RX_LOCK_CTRL_1 0xc1 | |
141 | #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2 | |
142 | #define MIPHY_RX_LOCK_STEP 0xc4 | |
143 | ||
144 | #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9 | |
145 | #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca | |
146 | #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb | |
147 | #define MIPHY_RX_SIGDET_DATA_SEL 0xcc | |
148 | #define EN_ULTRA_LOW_POWER BIT(0) | |
149 | #define EN_FIRST_HALF BIT(1) | |
150 | #define EN_SECOND_HALF BIT(2) | |
151 | #define EN_DIGIT_SIGNAL_CHECK BIT(3) | |
152 | ||
153 | #define MIPHY_RX_POWER_CTRL_1 0xcd | |
154 | #define MIPHY_RX_POWER_CTRL_2 0xce | |
155 | #define MIPHY_PLL_CALSET_CTRL 0xd3 | |
156 | #define MIPHY_PLL_CALSET_1 0xd4 | |
157 | #define MIPHY_PLL_CALSET_2 0xd5 | |
158 | #define MIPHY_PLL_CALSET_3 0xd6 | |
159 | #define MIPHY_PLL_CALSET_4 0xd7 | |
160 | #define MIPHY_PLL_SBR_1 0xe3 | |
161 | #define SET_NEW_CHANGE BIT(1) | |
162 | ||
163 | #define MIPHY_PLL_SBR_2 0xe4 | |
164 | #define MIPHY_PLL_SBR_3 0xe5 | |
165 | #define MIPHY_PLL_SBR_4 0xe6 | |
166 | #define MIPHY_PLL_COMMON_MISC_2 0xe9 | |
167 | #define START_ACT_FILT BIT(6) | |
168 | ||
169 | #define MIPHY_PLL_SPAREIN 0xeb | |
170 | ||
171 | /* | |
172 | * On STiH407 the glue logic can be different among MiPHY devices; for example: | |
173 | * MiPHY0: OSC_FORCE_EXT means: | |
174 | * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 | |
175 | * MiPHY1: OSC_FORCE_EXT means: | |
176 | * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 | |
177 | * Some devices have not the possibility to check if the osc is ready. | |
178 | */ | |
179 | #define MIPHY_OSC_FORCE_EXT BIT(3) | |
180 | #define MIPHY_OSC_RDY BIT(5) | |
181 | ||
182 | #define MIPHY_CTRL_MASK 0x0f | |
183 | #define MIPHY_CTRL_DEFAULT 0 | |
184 | #define MIPHY_CTRL_SYNC_D_EN BIT(2) | |
185 | ||
186 | /* SATA / PCIe defines */ | |
187 | #define SATA_CTRL_MASK 0x07 | |
188 | #define PCIE_CTRL_MASK 0xff | |
189 | #define SATA_CTRL_SELECT_SATA 1 | |
190 | #define SATA_CTRL_SELECT_PCIE 0 | |
191 | #define SYSCFG_PCIE_PCIE_VAL 0x80 | |
192 | #define SATA_SPDMODE 1 | |
193 | ||
2b041b27 | 194 | #define MIPHY_SATA_BANK_NB 3 |
a2108dee | 195 | #define MIPHY_PCIE_BANK_NB 2 |
2b041b27 | 196 | |
de6e0f84 GF |
197 | enum { |
198 | SYSCFG_CTRL, | |
199 | SYSCFG_STATUS, | |
200 | SYSCFG_PCI, | |
201 | SYSCFG_SATA, | |
202 | SYSCFG_REG_MAX, | |
203 | }; | |
204 | ||
2c14e9be GF |
205 | struct miphy28lp_phy { |
206 | struct phy *phy; | |
207 | struct miphy28lp_dev *phydev; | |
208 | void __iomem *base; | |
209 | void __iomem *pipebase; | |
210 | ||
211 | bool osc_force_ext; | |
212 | bool osc_rdy; | |
213 | bool px_rx_pol_inv; | |
2b041b27 | 214 | bool ssc; |
28ba384d | 215 | bool tx_impedance; |
2c14e9be GF |
216 | |
217 | struct reset_control *miphy_rst; | |
218 | ||
219 | u32 sata_gen; | |
220 | ||
221 | /* Sysconfig registers offsets needed to configure the device */ | |
de6e0f84 | 222 | u32 syscfg_reg[SYSCFG_REG_MAX]; |
2c14e9be GF |
223 | u8 type; |
224 | }; | |
225 | ||
226 | struct miphy28lp_dev { | |
227 | struct device *dev; | |
228 | struct regmap *regmap; | |
229 | struct mutex miphy_mutex; | |
230 | struct miphy28lp_phy **phys; | |
231 | }; | |
232 | ||
233 | struct miphy_initval { | |
234 | u16 reg; | |
235 | u16 val; | |
236 | }; | |
237 | ||
238 | enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; | |
239 | ||
240 | static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" }; | |
241 | ||
242 | struct pll_ratio { | |
243 | int clk_ref; | |
244 | int calset_1; | |
245 | int calset_2; | |
246 | int calset_3; | |
247 | int calset_4; | |
248 | int cal_ctrl; | |
249 | }; | |
250 | ||
251 | static struct pll_ratio sata_pll_ratio = { | |
252 | .clk_ref = 0x1e, | |
253 | .calset_1 = 0xc8, | |
254 | .calset_2 = 0x00, | |
255 | .calset_3 = 0x00, | |
256 | .calset_4 = 0x00, | |
257 | .cal_ctrl = 0x00, | |
258 | }; | |
259 | ||
260 | static struct pll_ratio pcie_pll_ratio = { | |
261 | .clk_ref = 0x1e, | |
262 | .calset_1 = 0xa6, | |
263 | .calset_2 = 0xaa, | |
264 | .calset_3 = 0xaa, | |
265 | .calset_4 = 0x00, | |
266 | .cal_ctrl = 0x00, | |
267 | }; | |
268 | ||
269 | static struct pll_ratio usb3_pll_ratio = { | |
270 | .clk_ref = 0x1e, | |
271 | .calset_1 = 0xa6, | |
272 | .calset_2 = 0xaa, | |
273 | .calset_3 = 0xaa, | |
274 | .calset_4 = 0x04, | |
275 | .cal_ctrl = 0x00, | |
276 | }; | |
277 | ||
278 | struct miphy28lp_pll_gen { | |
279 | int bank; | |
280 | int speed; | |
281 | int bias_boost_1; | |
282 | int bias_boost_2; | |
283 | int tx_ctrl_1; | |
284 | int tx_ctrl_2; | |
285 | int tx_ctrl_3; | |
286 | int rx_k_gain; | |
287 | int rx_vga_gain; | |
288 | int rx_equ_gain_1; | |
289 | int rx_equ_gain_2; | |
290 | int rx_equ_gain_3; | |
291 | int rx_buff_ctrl; | |
292 | }; | |
293 | ||
294 | static struct miphy28lp_pll_gen sata_pll_gen[] = { | |
295 | { | |
296 | .bank = 0x00, | |
297 | .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC, | |
298 | .bias_boost_1 = 0x00, | |
299 | .bias_boost_2 = 0xae, | |
300 | .tx_ctrl_2 = 0x53, | |
301 | .tx_ctrl_3 = 0x00, | |
302 | .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, | |
303 | .rx_vga_gain = 0x00, | |
304 | .rx_equ_gain_1 = 0x7d, | |
305 | .rx_equ_gain_2 = 0x56, | |
306 | .rx_equ_gain_3 = 0x00, | |
307 | }, | |
308 | { | |
309 | .bank = 0x01, | |
310 | .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC, | |
311 | .bias_boost_1 = 0x00, | |
312 | .bias_boost_2 = 0xae, | |
313 | .tx_ctrl_2 = 0x72, | |
314 | .tx_ctrl_3 = 0x20, | |
315 | .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, | |
316 | .rx_vga_gain = 0x00, | |
317 | .rx_equ_gain_1 = 0x7d, | |
318 | .rx_equ_gain_2 = 0x56, | |
319 | .rx_equ_gain_3 = 0x00, | |
320 | }, | |
321 | { | |
322 | .bank = 0x02, | |
323 | .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC, | |
324 | .bias_boost_1 = 0x00, | |
325 | .bias_boost_2 = 0xae, | |
326 | .tx_ctrl_2 = 0xc0, | |
327 | .tx_ctrl_3 = 0x20, | |
328 | .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, | |
329 | .rx_vga_gain = 0x00, | |
330 | .rx_equ_gain_1 = 0x7d, | |
331 | .rx_equ_gain_2 = 0x56, | |
332 | .rx_equ_gain_3 = 0x00, | |
333 | }, | |
334 | }; | |
335 | ||
336 | static struct miphy28lp_pll_gen pcie_pll_gen[] = { | |
337 | { | |
338 | .bank = 0x00, | |
339 | .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC, | |
340 | .bias_boost_1 = 0x00, | |
341 | .bias_boost_2 = 0xa5, | |
342 | .tx_ctrl_1 = TX_REG_STEP_N_25MV, | |
343 | .tx_ctrl_2 = 0x71, | |
344 | .tx_ctrl_3 = 0x60, | |
345 | .rx_k_gain = 0x98, | |
346 | .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, | |
347 | .rx_vga_gain = 0x00, | |
348 | .rx_equ_gain_1 = 0x79, | |
349 | .rx_equ_gain_2 = 0x56, | |
350 | }, | |
351 | { | |
352 | .bank = 0x01, | |
353 | .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC, | |
354 | .bias_boost_1 = 0x00, | |
355 | .bias_boost_2 = 0xa5, | |
356 | .tx_ctrl_1 = TX_REG_STEP_N_25MV, | |
357 | .tx_ctrl_2 = 0x70, | |
358 | .tx_ctrl_3 = 0x60, | |
359 | .rx_k_gain = 0xcc, | |
360 | .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, | |
361 | .rx_vga_gain = 0x00, | |
362 | .rx_equ_gain_1 = 0x78, | |
363 | .rx_equ_gain_2 = 0x07, | |
364 | }, | |
365 | }; | |
366 | ||
367 | static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy) | |
368 | { | |
369 | void *base = miphy_phy->base; | |
370 | u8 val; | |
371 | ||
372 | /* Putting Macro in reset */ | |
373 | writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); | |
374 | ||
375 | val = RST_APPLI_SW | RST_CONF_SW; | |
376 | writeb_relaxed(val, base + MIPHY_CONF_RESET); | |
377 | ||
378 | writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); | |
379 | ||
380 | /* Bringing the MIPHY-CPU registers out of reset */ | |
381 | if (miphy_phy->type == PHY_TYPE_PCIE) { | |
382 | val = AUTO_RST_RX | TERM_EN_SW; | |
383 | writeb_relaxed(val, base + MIPHY_CONTROL); | |
384 | } else { | |
385 | val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST; | |
386 | writeb_relaxed(val, base + MIPHY_CONTROL); | |
387 | } | |
388 | } | |
389 | ||
390 | static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy, | |
391 | struct pll_ratio *pll_ratio) | |
392 | { | |
393 | void *base = miphy_phy->base; | |
394 | u8 val; | |
395 | ||
396 | /* Applying PLL Settings */ | |
397 | writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); | |
398 | writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); | |
399 | ||
400 | /* PLL Ratio */ | |
401 | writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); | |
402 | writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); | |
403 | writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); | |
404 | writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); | |
405 | writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); | |
406 | ||
407 | writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL); | |
408 | ||
409 | val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN; | |
410 | writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); | |
411 | ||
412 | val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64; | |
413 | ||
414 | if (miphy_phy->type != PHY_TYPE_SATA) | |
415 | val |= OFFSET_COMPENSATION_EN; | |
416 | ||
417 | writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); | |
418 | ||
419 | if (miphy_phy->type == PHY_TYPE_USB3) { | |
420 | writeb_relaxed(0x00, base + MIPHY_CONF); | |
421 | writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP); | |
422 | writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA); | |
423 | writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL); | |
424 | writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL); | |
425 | ||
426 | val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF; | |
427 | writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); | |
428 | } | |
429 | ||
430 | } | |
431 | ||
432 | static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy) | |
433 | { | |
434 | void __iomem *base = miphy_phy->base; | |
435 | int i; | |
436 | ||
437 | for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) { | |
438 | struct miphy28lp_pll_gen *gen = &sata_pll_gen[i]; | |
439 | ||
440 | /* Banked settings */ | |
441 | writeb_relaxed(gen->bank, base + MIPHY_CONF); | |
442 | writeb_relaxed(gen->speed, base + MIPHY_SPEED); | |
443 | writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); | |
444 | writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); | |
445 | ||
446 | /* TX buffer Settings */ | |
447 | writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); | |
448 | writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); | |
449 | ||
450 | /* RX Buffer Settings */ | |
451 | writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); | |
452 | writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); | |
453 | writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); | |
454 | writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); | |
455 | writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); | |
456 | } | |
457 | } | |
458 | ||
459 | static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy) | |
460 | { | |
461 | void __iomem *base = miphy_phy->base; | |
462 | int i; | |
463 | ||
464 | for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) { | |
465 | struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i]; | |
466 | ||
467 | /* Banked settings */ | |
468 | writeb_relaxed(gen->bank, base + MIPHY_CONF); | |
469 | writeb_relaxed(gen->speed, base + MIPHY_SPEED); | |
470 | writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); | |
471 | writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); | |
472 | ||
473 | /* TX buffer Settings */ | |
474 | writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); | |
475 | writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); | |
476 | writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); | |
477 | ||
478 | writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); | |
479 | ||
480 | /* RX Buffer Settings */ | |
481 | writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); | |
482 | writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); | |
483 | writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); | |
484 | writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); | |
485 | } | |
486 | } | |
487 | ||
488 | static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy) | |
489 | { | |
490 | unsigned long finish = jiffies + 5 * HZ; | |
491 | u8 val; | |
492 | ||
493 | /* Waiting for Compensation to complete */ | |
494 | do { | |
495 | val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); | |
496 | ||
497 | if (time_after_eq(jiffies, finish)) | |
498 | return -EBUSY; | |
499 | cpu_relax(); | |
500 | } while (!(val & COMP_DONE)); | |
501 | ||
502 | return 0; | |
503 | } | |
504 | ||
505 | ||
506 | static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy, | |
507 | struct pll_ratio *pll_ratio) | |
508 | { | |
509 | void __iomem *base = miphy_phy->base; | |
510 | ||
511 | /* Poll for HFC ready after reset release */ | |
512 | /* Compensation measurement */ | |
513 | writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET); | |
514 | ||
515 | writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); | |
516 | writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); | |
517 | writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); | |
518 | ||
519 | if (miphy_phy->type == PHY_TYPE_PCIE) | |
520 | writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); | |
521 | ||
522 | writeb_relaxed(0x00, base + MIPHY_RESET); | |
523 | writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); | |
524 | writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); | |
525 | ||
526 | /* TX compensation offset to re-center TX impedance */ | |
527 | writeb_relaxed(0x00, base + MIPHY_COMP_POSTP); | |
528 | ||
529 | if (miphy_phy->type == PHY_TYPE_PCIE) | |
530 | return miphy28lp_wait_compensation(miphy_phy); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy) | |
536 | { | |
537 | void __iomem *base = miphy_phy->base; | |
538 | u8 val; | |
539 | ||
540 | /* MIPHY Reset */ | |
541 | writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); | |
542 | writeb_relaxed(0x00, base + MIPHY_CONF_RESET); | |
543 | writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET); | |
544 | ||
545 | val = RST_COMP_SW | RST_PLL_SW; | |
546 | writeb_relaxed(val, base + MIPHY_RESET); | |
547 | ||
548 | writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); | |
549 | writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ); | |
550 | writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); | |
551 | writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); | |
552 | writeb_relaxed(0x00, base + MIPHY_RESET); | |
553 | writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); | |
554 | writeb_relaxed(0x00, base + MIPHY_CONF); | |
555 | writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1); | |
556 | writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2); | |
557 | writeb_relaxed(0x00, base + MIPHY_CONF); | |
558 | writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); | |
559 | writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS); | |
560 | writeb_relaxed(0x00, base + MIPHY_CONF); | |
561 | } | |
562 | ||
2b041b27 GF |
563 | static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy) |
564 | { | |
565 | void __iomem *base = miphy_phy->base; | |
566 | u8 val; | |
567 | ||
568 | /* Compensate Tx impedance to avoid out of range values */ | |
569 | /* | |
570 | * Enable the SSC on PLL for all banks | |
571 | * SSC Modulation @ 31 KHz and 4000 ppm modulation amp | |
572 | */ | |
573 | val = readb_relaxed(base + MIPHY_BOUNDARY_2); | |
574 | val |= SSC_EN_SW; | |
575 | writeb_relaxed(val, base + MIPHY_BOUNDARY_2); | |
576 | ||
577 | val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); | |
578 | val |= SSC_SEL; | |
579 | writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); | |
580 | ||
581 | for (val = 0; val < MIPHY_SATA_BANK_NB; val++) { | |
582 | writeb_relaxed(val, base + MIPHY_CONF); | |
583 | ||
584 | /* Add value to each reference clock cycle */ | |
585 | /* and define the period length of the SSC */ | |
586 | writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); | |
587 | writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3); | |
588 | writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4); | |
589 | ||
590 | /* Clear any previous request */ | |
591 | writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); | |
592 | ||
593 | /* requests the PLL to take in account new parameters */ | |
594 | writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); | |
595 | ||
596 | /* To be sure there is no other pending requests */ | |
597 | writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); | |
598 | } | |
599 | } | |
600 | ||
a2108dee GF |
601 | static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy) |
602 | { | |
603 | void __iomem *base = miphy_phy->base; | |
604 | u8 val; | |
605 | ||
606 | /* Compensate Tx impedance to avoid out of range values */ | |
607 | /* | |
608 | * Enable the SSC on PLL for all banks | |
609 | * SSC Modulation @ 31 KHz and 4000 ppm modulation amp | |
610 | */ | |
611 | val = readb_relaxed(base + MIPHY_BOUNDARY_2); | |
612 | val |= SSC_EN_SW; | |
613 | writeb_relaxed(val, base + MIPHY_BOUNDARY_2); | |
614 | ||
615 | val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); | |
616 | val |= SSC_SEL; | |
617 | writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); | |
618 | ||
619 | for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) { | |
620 | writeb_relaxed(val, base + MIPHY_CONF); | |
621 | ||
622 | /* Validate Step component */ | |
623 | writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3); | |
624 | writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); | |
625 | ||
626 | /* Validate Period component */ | |
627 | writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); | |
628 | writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); | |
629 | ||
630 | /* Clear any previous request */ | |
631 | writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); | |
632 | ||
633 | /* requests the PLL to take in account new parameters */ | |
634 | writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); | |
635 | ||
636 | /* To be sure there is no other pending requests */ | |
637 | writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); | |
638 | } | |
639 | } | |
640 | ||
28ba384d GF |
641 | static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy) |
642 | { | |
643 | /* Compensate Tx impedance to avoid out of range values */ | |
644 | writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); | |
645 | } | |
646 | ||
2c14e9be GF |
647 | static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy) |
648 | { | |
649 | void __iomem *base = miphy_phy->base; | |
650 | int err; | |
651 | u8 val; | |
652 | ||
653 | /* Putting Macro in reset */ | |
654 | miphy28lp_set_reset(miphy_phy); | |
655 | ||
656 | /* PLL calibration */ | |
657 | miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio); | |
658 | ||
659 | /* Banked settings Gen1/Gen2/Gen3 */ | |
660 | miphy28lp_sata_config_gen(miphy_phy); | |
661 | ||
662 | /* Power control */ | |
663 | /* Input bridge enable, manual input bridge control */ | |
664 | writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); | |
665 | ||
666 | /* Macro out of reset */ | |
667 | writeb_relaxed(0x00, base + MIPHY_CONF_RESET); | |
668 | ||
669 | /* Poll for HFC ready after reset release */ | |
670 | /* Compensation measurement */ | |
671 | err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio); | |
672 | if (err) | |
673 | return err; | |
674 | ||
675 | if (miphy_phy->px_rx_pol_inv) { | |
676 | /* Invert Rx polarity */ | |
677 | val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); | |
678 | val |= PX_RX_POL; | |
679 | writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); | |
680 | } | |
681 | ||
2b041b27 GF |
682 | if (miphy_phy->ssc) |
683 | miphy_sata_tune_ssc(miphy_phy); | |
684 | ||
28ba384d GF |
685 | if (miphy_phy->tx_impedance) |
686 | miphy_tune_tx_impedance(miphy_phy); | |
687 | ||
2c14e9be GF |
688 | return 0; |
689 | } | |
690 | ||
691 | static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy) | |
692 | { | |
693 | void __iomem *base = miphy_phy->base; | |
694 | int err; | |
695 | ||
696 | /* Putting Macro in reset */ | |
697 | miphy28lp_set_reset(miphy_phy); | |
698 | ||
699 | /* PLL calibration */ | |
700 | miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio); | |
701 | ||
702 | /* Banked settings Gen1/Gen2 */ | |
703 | miphy28lp_pcie_config_gen(miphy_phy); | |
704 | ||
705 | /* Power control */ | |
706 | /* Input bridge enable, manual input bridge control */ | |
707 | writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); | |
708 | ||
709 | /* Macro out of reset */ | |
710 | writeb_relaxed(0x00, base + MIPHY_CONF_RESET); | |
711 | ||
712 | /* Poll for HFC ready after reset release */ | |
713 | /* Compensation measurement */ | |
714 | err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio); | |
715 | if (err) | |
716 | return err; | |
717 | ||
a2108dee GF |
718 | if (miphy_phy->ssc) |
719 | miphy_pcie_tune_ssc(miphy_phy); | |
720 | ||
28ba384d GF |
721 | if (miphy_phy->tx_impedance) |
722 | miphy_tune_tx_impedance(miphy_phy); | |
723 | ||
2c14e9be GF |
724 | return 0; |
725 | } | |
726 | ||
727 | ||
728 | static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy) | |
729 | { | |
730 | void __iomem *base = miphy_phy->base; | |
731 | u8 val; | |
732 | ||
733 | /* Putting Macro in reset */ | |
734 | miphy28lp_set_reset(miphy_phy); | |
735 | ||
736 | /* PLL calibration */ | |
737 | miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio); | |
738 | ||
739 | /* Writing The Speed Rate */ | |
740 | writeb_relaxed(0x00, base + MIPHY_CONF); | |
741 | ||
742 | val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC; | |
743 | writeb_relaxed(val, base + MIPHY_SPEED); | |
744 | ||
745 | /* RX Channel compensation and calibration */ | |
746 | writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT); | |
747 | writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1); | |
748 | writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2); | |
749 | ||
750 | val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY | | |
751 | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64; | |
752 | writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); | |
753 | writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP); | |
754 | writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH); | |
755 | ||
756 | val = EQ_DC_GAIN | VGA_GAIN; | |
757 | writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); | |
758 | writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1); | |
759 | writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL); | |
760 | ||
761 | /* TX compensation offset to re-center TX impedance */ | |
762 | writeb_relaxed(0x02, base + MIPHY_COMP_POSTP); | |
763 | ||
764 | /* Enable GENSEL_SEL and SSC */ | |
765 | /* TX_SEL=0 swing preemp forced by pipe registres */ | |
766 | val = SSC_SEL | GENSEL_SEL; | |
767 | writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); | |
768 | ||
769 | /* MIPHY Bias boost */ | |
770 | writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1); | |
771 | writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2); | |
772 | ||
773 | /* SSC modulation */ | |
774 | writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2); | |
775 | ||
776 | /* MIPHY TX control */ | |
777 | writeb_relaxed(0x00, base + MIPHY_CONF); | |
778 | ||
779 | /* Validate Step component */ | |
780 | writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3); | |
781 | writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4); | |
782 | ||
783 | /* Validate Period component */ | |
784 | writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); | |
785 | writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4); | |
786 | ||
787 | /* Clear any previous request */ | |
788 | writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); | |
789 | ||
790 | /* requests the PLL to take in account new parameters */ | |
791 | writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1); | |
792 | ||
793 | /* To be sure there is no other pending requests */ | |
794 | writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); | |
795 | ||
796 | /* Rx PI controller settings */ | |
797 | writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN); | |
798 | ||
799 | /* MIPHY RX input bridge control */ | |
800 | /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */ | |
801 | writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); | |
802 | writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1); | |
803 | writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2); | |
804 | ||
805 | /* MIPHY Reset for usb3 */ | |
806 | miphy28_usb3_miphy_reset(miphy_phy); | |
807 | } | |
808 | ||
809 | static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) | |
810 | { | |
811 | unsigned long finish = jiffies + 5 * HZ; | |
812 | u8 mask = HFC_PLL | HFC_RDY; | |
813 | u8 val; | |
814 | ||
815 | /* | |
816 | * For PCIe and USB3 check only that PLL and HFC are ready | |
817 | * For SATA check also that phy is ready! | |
818 | */ | |
819 | if (miphy_phy->type == PHY_TYPE_SATA) | |
820 | mask |= PHY_RDY; | |
821 | ||
822 | do { | |
823 | val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); | |
824 | if ((val & mask) != mask) | |
825 | cpu_relax(); | |
826 | else | |
827 | return 0; | |
828 | } while (!time_after_eq(jiffies, finish)); | |
829 | ||
830 | return -EBUSY; | |
831 | } | |
832 | ||
833 | static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) | |
834 | { | |
835 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
836 | unsigned long finish = jiffies + 5 * HZ; | |
837 | u32 val; | |
838 | ||
839 | if (!miphy_phy->osc_rdy) | |
840 | return 0; | |
841 | ||
de6e0f84 | 842 | if (!miphy_phy->syscfg_reg[SYSCFG_STATUS]) |
2c14e9be GF |
843 | return -EINVAL; |
844 | ||
845 | do { | |
de6e0f84 GF |
846 | regmap_read(miphy_dev->regmap, |
847 | miphy_phy->syscfg_reg[SYSCFG_STATUS], &val); | |
2c14e9be GF |
848 | |
849 | if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) | |
850 | cpu_relax(); | |
851 | else | |
852 | return 0; | |
853 | } while (!time_after_eq(jiffies, finish)); | |
854 | ||
855 | return -EBUSY; | |
856 | } | |
857 | ||
858 | static int miphy28lp_get_resource_byname(struct device_node *child, | |
859 | char *rname, struct resource *res) | |
860 | { | |
861 | int index; | |
862 | ||
863 | index = of_property_match_string(child, "reg-names", rname); | |
864 | if (index < 0) | |
865 | return -ENODEV; | |
866 | ||
867 | return of_address_to_resource(child, index, res); | |
868 | } | |
869 | ||
870 | static int miphy28lp_get_one_addr(struct device *dev, | |
871 | struct device_node *child, char *rname, | |
872 | void __iomem **base) | |
873 | { | |
874 | struct resource res; | |
875 | int ret; | |
876 | ||
877 | ret = miphy28lp_get_resource_byname(child, rname, &res); | |
878 | if (!ret) { | |
879 | *base = devm_ioremap(dev, res.start, resource_size(&res)); | |
880 | if (!*base) { | |
881 | dev_err(dev, "failed to ioremap %s address region\n" | |
882 | , rname); | |
883 | return -ENOENT; | |
884 | } | |
885 | } | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | /* MiPHY reset and sysconf setup */ | |
891 | static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val) | |
892 | { | |
893 | int err; | |
894 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
895 | ||
de6e0f84 | 896 | if (!miphy_phy->syscfg_reg[SYSCFG_CTRL]) |
2c14e9be GF |
897 | return -EINVAL; |
898 | ||
899 | err = reset_control_assert(miphy_phy->miphy_rst); | |
900 | if (err) { | |
901 | dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); | |
902 | return err; | |
903 | } | |
904 | ||
905 | if (miphy_phy->osc_force_ext) | |
906 | miphy_val |= MIPHY_OSC_FORCE_EXT; | |
907 | ||
de6e0f84 GF |
908 | regmap_update_bits(miphy_dev->regmap, |
909 | miphy_phy->syscfg_reg[SYSCFG_CTRL], | |
2c14e9be GF |
910 | MIPHY_CTRL_MASK, miphy_val); |
911 | ||
912 | err = reset_control_deassert(miphy_phy->miphy_rst); | |
913 | if (err) { | |
914 | dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); | |
915 | return err; | |
916 | } | |
917 | ||
918 | return miphy_osc_is_ready(miphy_phy); | |
919 | } | |
920 | ||
921 | static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy) | |
922 | { | |
923 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
924 | int err, sata_conf = SATA_CTRL_SELECT_SATA; | |
925 | ||
de6e0f84 GF |
926 | if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || |
927 | (!miphy_phy->syscfg_reg[SYSCFG_PCI]) || | |
928 | (!miphy_phy->base)) | |
2c14e9be GF |
929 | return -EINVAL; |
930 | ||
931 | dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); | |
932 | ||
933 | /* Configure the glue-logic */ | |
934 | sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE); | |
935 | ||
de6e0f84 GF |
936 | regmap_update_bits(miphy_dev->regmap, |
937 | miphy_phy->syscfg_reg[SYSCFG_SATA], | |
2c14e9be GF |
938 | SATA_CTRL_MASK, sata_conf); |
939 | ||
de6e0f84 | 940 | regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], |
2c14e9be GF |
941 | PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE); |
942 | ||
943 | /* MiPHY path and clocking init */ | |
944 | err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); | |
945 | ||
946 | if (err) { | |
947 | dev_err(miphy_dev->dev, "SATA phy setup failed\n"); | |
948 | return err; | |
949 | } | |
950 | ||
951 | /* initialize miphy */ | |
952 | miphy28lp_configure_sata(miphy_phy); | |
953 | ||
954 | return miphy_is_ready(miphy_phy); | |
955 | } | |
956 | ||
957 | static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy) | |
958 | { | |
959 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
960 | int err; | |
961 | ||
de6e0f84 GF |
962 | if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || |
963 | (!miphy_phy->syscfg_reg[SYSCFG_PCI]) | |
2c14e9be GF |
964 | || (!miphy_phy->base) || (!miphy_phy->pipebase)) |
965 | return -EINVAL; | |
966 | ||
967 | dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); | |
968 | ||
969 | /* Configure the glue-logic */ | |
de6e0f84 GF |
970 | regmap_update_bits(miphy_dev->regmap, |
971 | miphy_phy->syscfg_reg[SYSCFG_SATA], | |
2c14e9be GF |
972 | SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE); |
973 | ||
de6e0f84 | 974 | regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], |
2c14e9be GF |
975 | PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL); |
976 | ||
977 | /* MiPHY path and clocking init */ | |
978 | err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); | |
979 | ||
980 | if (err) { | |
981 | dev_err(miphy_dev->dev, "PCIe phy setup failed\n"); | |
982 | return err; | |
983 | } | |
984 | ||
985 | /* initialize miphy */ | |
986 | err = miphy28lp_configure_pcie(miphy_phy); | |
987 | if (err) | |
988 | return err; | |
989 | ||
990 | /* PIPE Wrapper Configuration */ | |
991 | writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ | |
992 | writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ | |
993 | writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ | |
994 | writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ | |
995 | writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */ | |
996 | writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ | |
997 | ||
998 | /* Wait for phy_ready */ | |
999 | return miphy_is_ready(miphy_phy); | |
1000 | } | |
1001 | ||
1002 | static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy) | |
1003 | { | |
1004 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
1005 | int err; | |
1006 | ||
1007 | if ((!miphy_phy->base) || (!miphy_phy->pipebase)) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); | |
1011 | ||
1012 | /* MiPHY path and clocking init */ | |
1013 | err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN); | |
1014 | if (err) { | |
1015 | dev_err(miphy_dev->dev, "USB3 phy setup failed\n"); | |
1016 | return err; | |
1017 | } | |
1018 | ||
1019 | /* initialize miphy */ | |
1020 | miphy28lp_configure_usb3(miphy_phy); | |
1021 | ||
1022 | /* PIPE Wrapper Configuration */ | |
1023 | writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); | |
1024 | writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); | |
1025 | writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); | |
1026 | writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); | |
1027 | writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); | |
1028 | writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a); | |
1029 | ||
1030 | /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */ | |
1031 | writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); | |
1032 | writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); | |
1033 | writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); | |
1034 | writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); | |
1035 | writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); | |
1036 | writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); | |
1037 | writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); | |
1038 | writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); | |
1039 | ||
1040 | return miphy_is_ready(miphy_phy); | |
1041 | } | |
1042 | ||
1043 | static int miphy28lp_init(struct phy *phy) | |
1044 | { | |
1045 | struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy); | |
1046 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
1047 | int ret; | |
1048 | ||
1049 | mutex_lock(&miphy_dev->miphy_mutex); | |
1050 | ||
1051 | switch (miphy_phy->type) { | |
1052 | ||
1053 | case PHY_TYPE_SATA: | |
1054 | ret = miphy28lp_init_sata(miphy_phy); | |
1055 | break; | |
1056 | case PHY_TYPE_PCIE: | |
1057 | ret = miphy28lp_init_pcie(miphy_phy); | |
1058 | break; | |
1059 | case PHY_TYPE_USB3: | |
1060 | ret = miphy28lp_init_usb3(miphy_phy); | |
1061 | break; | |
1062 | default: | |
4e038e89 DC |
1063 | ret = -EINVAL; |
1064 | break; | |
2c14e9be GF |
1065 | } |
1066 | ||
1067 | mutex_unlock(&miphy_dev->miphy_mutex); | |
1068 | ||
1069 | return ret; | |
1070 | } | |
1071 | ||
1072 | static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy) | |
1073 | { | |
1074 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
1075 | struct device_node *phynode = miphy_phy->phy->dev.of_node; | |
1076 | int err; | |
1077 | ||
1078 | if ((miphy_phy->type != PHY_TYPE_SATA) && | |
1079 | (miphy_phy->type != PHY_TYPE_PCIE) && | |
1080 | (miphy_phy->type != PHY_TYPE_USB3)) { | |
1081 | return -EINVAL; | |
1082 | } | |
1083 | ||
1084 | err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, | |
1085 | PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA], | |
1086 | &miphy_phy->base); | |
1087 | if (err) | |
1088 | return err; | |
1089 | ||
1090 | if ((miphy_phy->type == PHY_TYPE_PCIE) || | |
1091 | (miphy_phy->type == PHY_TYPE_USB3)) { | |
1092 | err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew", | |
1093 | &miphy_phy->pipebase); | |
1094 | if (err) | |
1095 | return err; | |
1096 | } | |
1097 | ||
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | static struct phy *miphy28lp_xlate(struct device *dev, | |
1102 | struct of_phandle_args *args) | |
1103 | { | |
1104 | struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev); | |
1105 | struct miphy28lp_phy *miphy_phy = NULL; | |
1106 | struct device_node *phynode = args->np; | |
1107 | int ret, index = 0; | |
1108 | ||
1109 | if (!of_device_is_available(phynode)) { | |
1110 | dev_warn(dev, "Requested PHY is disabled\n"); | |
1111 | return ERR_PTR(-ENODEV); | |
1112 | } | |
1113 | ||
1114 | if (args->args_count != 1) { | |
1115 | dev_err(dev, "Invalid number of cells in 'phy' property\n"); | |
1116 | return ERR_PTR(-EINVAL); | |
1117 | } | |
1118 | ||
1119 | for (index = 0; index < of_get_child_count(dev->of_node); index++) | |
1120 | if (phynode == miphy_dev->phys[index]->phy->dev.of_node) { | |
1121 | miphy_phy = miphy_dev->phys[index]; | |
1122 | break; | |
1123 | } | |
1124 | ||
1125 | if (!miphy_phy) { | |
1126 | dev_err(dev, "Failed to find appropriate phy\n"); | |
1127 | return ERR_PTR(-EINVAL); | |
1128 | } | |
1129 | ||
1130 | miphy_phy->type = args->args[0]; | |
1131 | ||
1132 | ret = miphy28lp_get_addr(miphy_phy); | |
1133 | if (ret < 0) | |
1134 | return ERR_PTR(ret); | |
1135 | ||
1136 | return miphy_phy->phy; | |
1137 | } | |
1138 | ||
1139 | static struct phy_ops miphy28lp_ops = { | |
1140 | .init = miphy28lp_init, | |
1141 | }; | |
1142 | ||
1143 | static int miphy28lp_probe_resets(struct device_node *node, | |
1144 | struct miphy28lp_phy *miphy_phy) | |
1145 | { | |
1146 | struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; | |
1147 | int err; | |
1148 | ||
1149 | miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst"); | |
1150 | ||
1151 | if (IS_ERR(miphy_phy->miphy_rst)) { | |
1152 | dev_err(miphy_dev->dev, | |
1153 | "miphy soft reset control not defined\n"); | |
1154 | return PTR_ERR(miphy_phy->miphy_rst); | |
1155 | } | |
1156 | ||
1157 | err = reset_control_deassert(miphy_phy->miphy_rst); | |
1158 | if (err) { | |
1159 | dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); | |
1160 | return err; | |
1161 | } | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static int miphy28lp_of_probe(struct device_node *np, | |
1167 | struct miphy28lp_phy *miphy_phy) | |
1168 | { | |
de6e0f84 GF |
1169 | int i; |
1170 | u32 ctrlreg; | |
2c14e9be GF |
1171 | |
1172 | miphy_phy->osc_force_ext = | |
1173 | of_property_read_bool(np, "st,osc-force-ext"); | |
1174 | ||
1175 | miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy"); | |
1176 | ||
1177 | miphy_phy->px_rx_pol_inv = | |
1178 | of_property_read_bool(np, "st,px_rx_pol_inv"); | |
1179 | ||
2b041b27 GF |
1180 | miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on"); |
1181 | ||
28ba384d GF |
1182 | miphy_phy->tx_impedance = |
1183 | of_property_read_bool(np, "st,tx-impedance-comp"); | |
1184 | ||
2c14e9be GF |
1185 | of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); |
1186 | if (!miphy_phy->sata_gen) | |
1187 | miphy_phy->sata_gen = SATA_GEN1; | |
1188 | ||
de6e0f84 GF |
1189 | for (i = 0; i < SYSCFG_REG_MAX; i++) { |
1190 | if (!of_property_read_u32_index(np, "st,syscfg", i, &ctrlreg)) | |
1191 | miphy_phy->syscfg_reg[i] = ctrlreg; | |
1192 | } | |
2c14e9be GF |
1193 | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int miphy28lp_probe(struct platform_device *pdev) | |
1198 | { | |
1199 | struct device_node *child, *np = pdev->dev.of_node; | |
1200 | struct miphy28lp_dev *miphy_dev; | |
1201 | struct phy_provider *provider; | |
1202 | struct phy *phy; | |
1203 | int chancount, port = 0; | |
1204 | int ret; | |
1205 | ||
1206 | miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL); | |
1207 | if (!miphy_dev) | |
1208 | return -ENOMEM; | |
1209 | ||
1210 | chancount = of_get_child_count(np); | |
1211 | miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount, | |
1212 | GFP_KERNEL); | |
1213 | if (!miphy_dev->phys) | |
1214 | return -ENOMEM; | |
1215 | ||
1216 | miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); | |
1217 | if (IS_ERR(miphy_dev->regmap)) { | |
1218 | dev_err(miphy_dev->dev, "No syscfg phandle specified\n"); | |
1219 | return PTR_ERR(miphy_dev->regmap); | |
1220 | } | |
1221 | ||
1222 | miphy_dev->dev = &pdev->dev; | |
1223 | ||
1224 | dev_set_drvdata(&pdev->dev, miphy_dev); | |
1225 | ||
1226 | mutex_init(&miphy_dev->miphy_mutex); | |
1227 | ||
1228 | for_each_child_of_node(np, child) { | |
1229 | struct miphy28lp_phy *miphy_phy; | |
1230 | ||
1231 | miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy), | |
1232 | GFP_KERNEL); | |
1233 | if (!miphy_phy) | |
1234 | return -ENOMEM; | |
1235 | ||
1236 | miphy_dev->phys[port] = miphy_phy; | |
1237 | ||
dbc98635 | 1238 | phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops); |
2c14e9be GF |
1239 | if (IS_ERR(phy)) { |
1240 | dev_err(&pdev->dev, "failed to create PHY\n"); | |
1241 | return PTR_ERR(phy); | |
1242 | } | |
1243 | ||
1244 | miphy_dev->phys[port]->phy = phy; | |
1245 | miphy_dev->phys[port]->phydev = miphy_dev; | |
1246 | ||
1247 | ret = miphy28lp_of_probe(child, miphy_phy); | |
1248 | if (ret) | |
1249 | return ret; | |
1250 | ||
1251 | ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]); | |
1252 | if (ret) | |
1253 | return ret; | |
1254 | ||
1255 | phy_set_drvdata(phy, miphy_dev->phys[port]); | |
1256 | port++; | |
1257 | ||
1258 | } | |
1259 | ||
1260 | provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate); | |
320c3fce | 1261 | return PTR_ERR_OR_ZERO(provider); |
2c14e9be GF |
1262 | } |
1263 | ||
1264 | static const struct of_device_id miphy28lp_of_match[] = { | |
1265 | {.compatible = "st,miphy28lp-phy", }, | |
1266 | {}, | |
1267 | }; | |
1268 | ||
1269 | MODULE_DEVICE_TABLE(of, miphy28lp_of_match); | |
1270 | ||
1271 | static struct platform_driver miphy28lp_driver = { | |
1272 | .probe = miphy28lp_probe, | |
1273 | .driver = { | |
1274 | .name = "miphy28lp-phy", | |
1275 | .owner = THIS_MODULE, | |
1276 | .of_match_table = miphy28lp_of_match, | |
1277 | } | |
1278 | }; | |
1279 | ||
1280 | module_platform_driver(miphy28lp_driver); | |
1281 | ||
1282 | MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>"); | |
1283 | MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver"); | |
1284 | MODULE_LICENSE("GPL v2"); |