[deliverable/linux.git] / drivers / phy / phy-omap-control.c

/*
 * omap-control-phy.c - The PHY part of control module.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/phy/omap_control_phy.h>

/**
 * omap_control_pcie_pcs - set the PCS delay count
 * @dev: the control module device
 * @id: index of the pcie PHY (should be 1 or 2)
 * @delay: 8 bit delay value
 */
void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
{
	u32 val;
	struct omap_control_phy	*control_phy;

	if (IS_ERR(dev) || !dev) {
		pr_err("%s: invalid device\n", __func__);
		return;
	}

	control_phy = dev_get_drvdata(dev);
	if (!control_phy) {
		dev_err(dev, "%s: invalid control phy device\n", __func__);
		return;
	}

	if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
		dev_err(dev, "%s: unsupported operation\n", __func__);
		return;
	}

	val = readl(control_phy->pcie_pcs);
	val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
		(id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
	val |= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
	writel(val, control_phy->pcie_pcs);
}
EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);

/**
 * omap_control_phy_power - power on/off the phy using control module reg
 * @dev: the control module device
 * @on: 0 or 1, based on powering on or off the PHY
 */
void omap_control_phy_power(struct device *dev, int on)
{
	u32 val;
	unsigned long rate;
	struct omap_control_phy	*control_phy;

	if (IS_ERR(dev) || !dev) {
		pr_err("%s: invalid device\n", __func__);
		return;
	}

	control_phy = dev_get_drvdata(dev);
	if (!control_phy) {
		dev_err(dev, "%s: invalid control phy device\n", __func__);
		return;
	}

	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
		return;

	val = readl(control_phy->power);

	switch (control_phy->type) {
	case OMAP_CTRL_TYPE_USB2:
		if (on)
			val &= ~OMAP_CTRL_DEV_PHY_PD;
		else
			val |= OMAP_CTRL_DEV_PHY_PD;
		break;

	case OMAP_CTRL_TYPE_PCIE:
	case OMAP_CTRL_TYPE_PIPE3:
		rate = clk_get_rate(control_phy->sys_clk);
		rate = rate/1000000;

		if (on) {
			val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
			val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
			val |= rate <<
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
		} else {
			val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
			val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
		}
		break;

	case OMAP_CTRL_TYPE_DRA7USB2:
		if (on)
			val &= ~OMAP_CTRL_USB2_PHY_PD;
		else
			val |= OMAP_CTRL_USB2_PHY_PD;
		break;

	case OMAP_CTRL_TYPE_AM437USB2:
		if (on) {
			val &= ~(AM437X_CTRL_USB2_PHY_PD |
					AM437X_CTRL_USB2_OTG_PD);
			val |= (AM437X_CTRL_USB2_OTGVDET_EN |
					AM437X_CTRL_USB2_OTGSESSEND_EN);
		} else {
			val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
					AM437X_CTRL_USB2_OTGSESSEND_EN);
			val |= (AM437X_CTRL_USB2_PHY_PD |
					 AM437X_CTRL_USB2_OTG_PD);
		}
		break;
	default:
		dev_err(dev, "%s: type %d not recognized\n",
			__func__, control_phy->type);
		break;
	}

	writel(val, control_phy->power);
}
EXPORT_SYMBOL_GPL(omap_control_phy_power);

/**
 * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
 * @ctrl_phy: struct omap_control_phy *
 *
 * Writes to the mailbox register to notify the usb core that a usb
 * device has been connected.
 */
static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
{
	u32 val;

	val = readl(ctrl_phy->otghs_control);
	val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
	val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
	writel(val, ctrl_phy->otghs_control);
}

/**
 * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
 * impedance
 * @ctrl_phy: struct omap_control_phy *
 *
 * Writes to the mailbox register to notify the usb core that it has been
 * connected to a usb host.
 */
static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
{
	u32 val;

	val = readl(ctrl_phy->otghs_control);
	val &= ~OMAP_CTRL_DEV_SESSEND;
	val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
		OMAP_CTRL_DEV_VBUSVALID;
	writel(val, ctrl_phy->otghs_control);
}

/**
 * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
 * impedance
 * @ctrl_phy: struct omap_control_phy *
 *
 * Writes to the mailbox register to notify the usb core it's now in
 * disconnected state.
 */
static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
{
	u32 val;

	val = readl(ctrl_phy->otghs_control);
	val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
	val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
	writel(val, ctrl_phy->otghs_control);
}

/**
 * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
 * or device mode or to denote disconnected state
 * @dev: the control module device
 * @mode: The mode to which usb should be configured
 *
 * This is an API to write to the mailbox register to notify the usb core that
 * a usb device has been connected.
 */
void omap_control_usb_set_mode(struct device *dev,
	enum omap_control_usb_mode mode)
{
	struct omap_control_phy	*ctrl_phy;

	if (IS_ERR(dev) || !dev)
		return;

	ctrl_phy = dev_get_drvdata(dev);

	if (!ctrl_phy) {
		dev_err(dev, "Invalid control phy device\n");
		return;
	}

	if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
		return;

	switch (mode) {
	case USB_MODE_HOST:
		omap_control_usb_host_mode(ctrl_phy);
		break;
	case USB_MODE_DEVICE:
		omap_control_usb_device_mode(ctrl_phy);
		break;
	case USB_MODE_DISCONNECT:
		omap_control_usb_set_sessionend(ctrl_phy);
		break;
	default:
		dev_vdbg(dev, "invalid omap control usb mode\n");
	}
}
EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);

#ifdef CONFIG_OF

static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;

static const struct of_device_id omap_control_phy_id_table[] = {
	{
		.compatible = "ti,control-phy-otghs",
		.data = &otghs_data,
	},
	{
		.compatible = "ti,control-phy-usb2",
		.data = &usb2_data,
	},
	{
		.compatible = "ti,control-phy-pipe3",
		.data = &pipe3_data,
	},
	{
		.compatible = "ti,control-phy-pcie",
		.data = &pcie_data,
	},
	{
		.compatible = "ti,control-phy-usb2-dra7",
		.data = &dra7usb2_data,
	},
	{
		.compatible = "ti,control-phy-usb2-am437",
		.data = &am437usb2_data,
	},
	{},
};
MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
#endif


static int omap_control_phy_probe(struct platform_device *pdev)
{
	struct resource	*res;
	const struct of_device_id *of_id;
	struct omap_control_phy *control_phy;

	of_id = of_match_device(of_match_ptr(omap_control_phy_id_table),
				&pdev->dev);
	if (!of_id)
		return -EINVAL;

	control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
		GFP_KERNEL);
	if (!control_phy)
		return -ENOMEM;

	control_phy->dev = &pdev->dev;
	control_phy->type = *(enum omap_control_phy_type *)of_id->data;

	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
			"otghs_control");
		control_phy->otghs_control = devm_ioremap_resource(
			&pdev->dev, res);
		if (IS_ERR(control_phy->otghs_control))
			return PTR_ERR(control_phy->otghs_control);
	} else {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
				"power");
		control_phy->power = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(control_phy->power)) {
			dev_err(&pdev->dev, "Couldn't get power register\n");
			return PTR_ERR(control_phy->power);
		}
	}

	if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
	    control_phy->type == OMAP_CTRL_TYPE_PCIE) {
		control_phy->sys_clk = devm_clk_get(control_phy->dev,
			"sys_clkin");
		if (IS_ERR(control_phy->sys_clk)) {
			pr_err("%s: unable to get sys_clkin\n", __func__);
			return -EINVAL;
		}
	}

	if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						   "pcie_pcs");
		control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(control_phy->pcie_pcs))
			return PTR_ERR(control_phy->pcie_pcs);
	}

	dev_set_drvdata(control_phy->dev, control_phy);

	return 0;
}

static struct platform_driver omap_control_phy_driver = {
	.probe		= omap_control_phy_probe,
	.driver		= {
		.name	= "omap-control-phy",
		.of_match_table = of_match_ptr(omap_control_phy_id_table),
	},
};

static int __init omap_control_phy_init(void)
{
	return platform_driver_register(&omap_control_phy_driver);
}
subsys_initcall(omap_control_phy_init);

static void __exit omap_control_phy_exit(void)
{
	platform_driver_unregister(&omap_control_phy_driver);
}
module_exit(omap_control_phy_exit);

MODULE_ALIAS("platform: omap_control_phy");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
01658f0f	1	/*
14da699b	2	* omap-control-phy.c - The PHY part of control module.
01658f0f KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
	22	#include <linux/of.h>
6cb9310a	23	#include <linux/of_device.h>
01658f0f KVA	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/clk.h>
14da699b	27	#include <linux/phy/omap_control_phy.h>
01658f0f	28
f0e2cf7b KVA	29	/**
	30	* omap_control_pcie_pcs - set the PCS delay count
	31	* @dev: the control module device
	32	* @id: index of the pcie PHY (should be 1 or 2)
	33	* @delay: 8 bit delay value
	34	*/
	35	void omap_control_pcie_pcs(struct device *dev, u8 id, u8 delay)
	36	{
	37	u32 val;
	38	struct omap_control_phy *control_phy;
	39
	40	if (IS_ERR(dev) \|\| !dev) {
	41	pr_err("%s: invalid device\n", __func__);
	42	return;
	43	}
	44
	45	control_phy = dev_get_drvdata(dev);
	46	if (!control_phy) {
	47	dev_err(dev, "%s: invalid control phy device\n", __func__);
	48	return;
	49	}
	50
	51	if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
	52	dev_err(dev, "%s: unsupported operation\n", __func__);
	53	return;
	54	}
	55
	56	val = readl(control_phy->pcie_pcs);
	57	val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
	58	(id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT));
	59	val \|= delay << (id * OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
	60	writel(val, control_phy->pcie_pcs);
	61	}
	62	EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
	63
01658f0f	64	/**
14da699b	65	* omap_control_phy_power - power on/off the phy using control module reg
01658f0f	66	* @dev: the control module device
6cb9310a	67	* @on: 0 or 1, based on powering on or off the PHY
01658f0f	68	*/
14da699b	69	void omap_control_phy_power(struct device *dev, int on)
01658f0f KVA	70	{
	71	u32 val;
	72	unsigned long rate;
14da699b	73	struct omap_control_phy *control_phy;
01658f0f	74
6cb9310a RQ	75	if (IS_ERR(dev) \|\| !dev) {
6cb9310a RQ	76	pr_err("%s: invalid device\n", __func__);
01658f0f	77	return;
6cb9310a	78	}
01658f0f	79
14da699b KVA	80	control_phy = dev_get_drvdata(dev);
	81	if (!control_phy) {
	82	dev_err(dev, "%s: invalid control phy device\n", __func__);
6cb9310a	83	return;
01658f0f KVA	84	}
01658f0f KVA	85
14da699b	86	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
6cb9310a	87	return;
01658f0f	88
14da699b	89	val = readl(control_phy->power);
6cb9310a	90
14da699b	91	switch (control_phy->type) {
6cb9310a RQ	92	case OMAP_CTRL_TYPE_USB2:
	93	if (on)
	94	val &= ~OMAP_CTRL_DEV_PHY_PD;
	95	else
	96	val \|= OMAP_CTRL_DEV_PHY_PD;
	97	break;
01658f0f	98
f0e2cf7b	99	case OMAP_CTRL_TYPE_PCIE:
6cb9310a	100	case OMAP_CTRL_TYPE_PIPE3:
14da699b	101	rate = clk_get_rate(control_phy->sys_clk);
6cb9310a RQ	102	rate = rate/1000000;
	103
	104	if (on) {
14da699b KVA	105	val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK \|
	106	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
	107	val \|= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
	108	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
	109	val \|= rate <<
	110	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
6cb9310a	111	} else {
14da699b KVA	112	val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
	113	val \|= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
	114	OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
6cb9310a RQ	115	}
6cb9310a RQ	116	break;
01658f0f	117
6cb9310a RQ	118	case OMAP_CTRL_TYPE_DRA7USB2:
	119	if (on)
	120	val &= ~OMAP_CTRL_USB2_PHY_PD;
	121	else
	122	val \|= OMAP_CTRL_USB2_PHY_PD;
	123	break;
c4b34a3b GC	124
	125	case OMAP_CTRL_TYPE_AM437USB2:
	126	if (on) {
	127	val &= ~(AM437X_CTRL_USB2_PHY_PD \|
	128	AM437X_CTRL_USB2_OTG_PD);
	129	val \|= (AM437X_CTRL_USB2_OTGVDET_EN \|
	130	AM437X_CTRL_USB2_OTGSESSEND_EN);
	131	} else {
	132	val &= ~(AM437X_CTRL_USB2_OTGVDET_EN \|
	133	AM437X_CTRL_USB2_OTGSESSEND_EN);
	134	val \|= (AM437X_CTRL_USB2_PHY_PD \|
	135	AM437X_CTRL_USB2_OTG_PD);
	136	}
	137	break;
6cb9310a RQ	138	default:
6cb9310a RQ	139	dev_err(dev, "%s: type %d not recognized\n",
14da699b	140	__func__, control_phy->type);
6cb9310a RQ	141	break;
6cb9310a RQ	142	}
01658f0f	143
14da699b	144	writel(val, control_phy->power);
01658f0f	145	}
14da699b	146	EXPORT_SYMBOL_GPL(omap_control_phy_power);
01658f0f KVA	147
	148	/**
	149	* omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
14da699b	150	* @ctrl_phy: struct omap_control_phy *
01658f0f KVA	151	*
	152	* Writes to the mailbox register to notify the usb core that a usb
	153	* device has been connected.
	154	*/
14da699b	155	static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
01658f0f KVA	156	{
	157	u32 val;
	158
14da699b	159	val = readl(ctrl_phy->otghs_control);
01658f0f KVA	160	val &= ~(OMAP_CTRL_DEV_IDDIG \| OMAP_CTRL_DEV_SESSEND);
01658f0f KVA	161	val \|= OMAP_CTRL_DEV_AVALID \| OMAP_CTRL_DEV_VBUSVALID;
14da699b	162	writel(val, ctrl_phy->otghs_control);
01658f0f KVA	163	}
	164
	165	/**
	166	* omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
	167	* impedance
14da699b	168	* @ctrl_phy: struct omap_control_phy *
01658f0f KVA	169	*
	170	* Writes to the mailbox register to notify the usb core that it has been
	171	* connected to a usb host.
	172	*/
14da699b	173	static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
01658f0f KVA	174	{
	175	u32 val;
	176
14da699b	177	val = readl(ctrl_phy->otghs_control);
01658f0f KVA	178	val &= ~OMAP_CTRL_DEV_SESSEND;
	179	val \|= OMAP_CTRL_DEV_IDDIG \| OMAP_CTRL_DEV_AVALID \|
	180	OMAP_CTRL_DEV_VBUSVALID;
14da699b	181	writel(val, ctrl_phy->otghs_control);
01658f0f KVA	182	}
	183
	184	/**
	185	* omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
	186	* impedance
14da699b	187	* @ctrl_phy: struct omap_control_phy *
01658f0f KVA	188	*
	189	* Writes to the mailbox register to notify the usb core it's now in
	190	* disconnected state.
	191	*/
14da699b	192	static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
01658f0f KVA	193	{
	194	u32 val;
	195
14da699b	196	val = readl(ctrl_phy->otghs_control);
01658f0f KVA	197	val &= ~(OMAP_CTRL_DEV_AVALID \| OMAP_CTRL_DEV_VBUSVALID);
01658f0f KVA	198	val \|= OMAP_CTRL_DEV_IDDIG \| OMAP_CTRL_DEV_SESSEND;
14da699b	199	writel(val, ctrl_phy->otghs_control);
01658f0f KVA	200	}
	201
	202	/**
	203	* omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
	204	* or device mode or to denote disconnected state
	205	* @dev: the control module device
	206	* @mode: The mode to which usb should be configured
	207	*
	208	* This is an API to write to the mailbox register to notify the usb core that
	209	* a usb device has been connected.
	210	*/
	211	void omap_control_usb_set_mode(struct device *dev,
	212	enum omap_control_usb_mode mode)
	213	{
14da699b	214	struct omap_control_phy *ctrl_phy;
01658f0f	215
0bb85dc2	216	if (IS_ERR(dev) \|\| !dev)
01658f0f KVA	217	return;
01658f0f KVA	218
14da699b	219	ctrl_phy = dev_get_drvdata(dev);
01658f0f	220
14da699b KVA	221	if (!ctrl_phy) {
14da699b KVA	222	dev_err(dev, "Invalid control phy device\n");
0bb85dc2 RQ	223	return;
	224	}
	225
14da699b	226	if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
0bb85dc2 RQ	227	return;
0bb85dc2 RQ	228
01658f0f KVA	229	switch (mode) {
01658f0f KVA	230	case USB_MODE_HOST:
14da699b	231	omap_control_usb_host_mode(ctrl_phy);
01658f0f KVA	232	break;
01658f0f KVA	233	case USB_MODE_DEVICE:
14da699b	234	omap_control_usb_device_mode(ctrl_phy);
01658f0f KVA	235	break;
01658f0f KVA	236	case USB_MODE_DISCONNECT:
14da699b	237	omap_control_usb_set_sessionend(ctrl_phy);
01658f0f KVA	238	break;
	239	default:
	240	dev_vdbg(dev, "invalid omap control usb mode\n");
	241	}
	242	}
	243	EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
	244
6cb9310a RQ	245	#ifdef CONFIG_OF
6cb9310a RQ	246
14da699b KVA	247	static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
	248	static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
	249	static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
f0e2cf7b	250	static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
14da699b KVA	251	static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
14da699b KVA	252	static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
6cb9310a	253
14da699b	254	static const struct of_device_id omap_control_phy_id_table[] = {
6cb9310a RQ	255	{
	256	.compatible = "ti,control-phy-otghs",
	257	.data = &otghs_data,
	258	},
	259	{
	260	.compatible = "ti,control-phy-usb2",
	261	.data = &usb2_data,
	262	},
	263	{
	264	.compatible = "ti,control-phy-pipe3",
	265	.data = &pipe3_data,
	266	},
f0e2cf7b KVA	267	{
	268	.compatible = "ti,control-phy-pcie",
	269	.data = &pcie_data,
	270	},
6cb9310a	271	{
51c9f4ad	272	.compatible = "ti,control-phy-usb2-dra7",
6cb9310a RQ	273	.data = &dra7usb2_data,
6cb9310a RQ	274	},
c4b34a3b	275	{
51c9f4ad	276	.compatible = "ti,control-phy-usb2-am437",
c4b34a3b GC	277	.data = &am437usb2_data,
c4b34a3b GC	278	},
6cb9310a RQ	279	{},
6cb9310a RQ	280	};
14da699b	281	MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
6cb9310a RQ	282	#endif
	283
	284
14da699b	285	static int omap_control_phy_probe(struct platform_device *pdev)
01658f0f KVA	286	{
01658f0f KVA	287	struct resource *res;
6cb9310a	288	const struct of_device_id *of_id;
14da699b	289	struct omap_control_phy *control_phy;
6cb9310a	290
14da699b KVA	291	of_id = of_match_device(of_match_ptr(omap_control_phy_id_table),
14da699b KVA	292	&pdev->dev);
6cb9310a RQ	293	if (!of_id)
6cb9310a RQ	294	return -EINVAL;
01658f0f	295
14da699b	296	control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
01658f0f	297	GFP_KERNEL);
437a6bc4	298	if (!control_phy)
01658f0f	299	return -ENOMEM;
01658f0f	300
14da699b KVA	301	control_phy->dev = &pdev->dev;
14da699b KVA	302	control_phy->type = (enum omap_control_phy_type )of_id->data;
01658f0f	303
14da699b	304	if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
01658f0f KVA	305	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
01658f0f KVA	306	"otghs_control");
14da699b	307	control_phy->otghs_control = devm_ioremap_resource(
01658f0f	308	&pdev->dev, res);
14da699b KVA	309	if (IS_ERR(control_phy->otghs_control))
14da699b KVA	310	return PTR_ERR(control_phy->otghs_control);
6cb9310a	311	} else {
01658f0f	312	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
6cb9310a	313	"power");
14da699b KVA	314	control_phy->power = devm_ioremap_resource(&pdev->dev, res);
14da699b KVA	315	if (IS_ERR(control_phy->power)) {
6cb9310a	316	dev_err(&pdev->dev, "Couldn't get power register\n");
14da699b	317	return PTR_ERR(control_phy->power);
6cb9310a RQ	318	}
6cb9310a RQ	319	}
01658f0f	320
f0e2cf7b KVA	321	if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 \|\|
f0e2cf7b KVA	322	control_phy->type == OMAP_CTRL_TYPE_PCIE) {
14da699b	323	control_phy->sys_clk = devm_clk_get(control_phy->dev,
01658f0f	324	"sys_clkin");
14da699b	325	if (IS_ERR(control_phy->sys_clk)) {
01658f0f KVA	326	pr_err("%s: unable to get sys_clkin\n", __func__);
	327	return -EINVAL;
	328	}
	329	}
	330
f0e2cf7b KVA	331	if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
	332	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	333	"pcie_pcs");
	334	control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
	335	if (IS_ERR(control_phy->pcie_pcs))
	336	return PTR_ERR(control_phy->pcie_pcs);
	337	}
	338
14da699b	339	dev_set_drvdata(control_phy->dev, control_phy);
01658f0f KVA	340
	341	return 0;
	342	}
	343
14da699b KVA	344	static struct platform_driver omap_control_phy_driver = {
14da699b KVA	345	.probe = omap_control_phy_probe,
01658f0f	346	.driver = {
14da699b	347	.name = "omap-control-phy",
14da699b	348	.of_match_table = of_match_ptr(omap_control_phy_id_table),
01658f0f KVA	349	},
	350	};
	351
14da699b	352	static int __init omap_control_phy_init(void)
01658f0f	353	{
14da699b	354	return platform_driver_register(&omap_control_phy_driver);
01658f0f	355	}
14da699b	356	subsys_initcall(omap_control_phy_init);
01658f0f	357
14da699b	358	static void __exit omap_control_phy_exit(void)
01658f0f	359	{
14da699b	360	platform_driver_unregister(&omap_control_phy_driver);
01658f0f	361	}
14da699b	362	module_exit(omap_control_phy_exit);
01658f0f	363
14da699b	364	MODULE_ALIAS("platform: omap_control_phy");
01658f0f	365	MODULE_AUTHOR("Texas Instruments Inc.");
14da699b	366	MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
01658f0f	367	MODULE_LICENSE("GPL v2");