[deliverable/linux.git] / drivers / phy / phy-rcar-gen3-usb2.c

/*
 * Renesas R-Car Gen3 for USB2.0 PHY driver
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 *
 * This is based on the phy-rcar-gen2 driver:
 * Copyright (C) 2014 Renesas Solutions Corp.
 * Copyright (C) 2014 Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>

/******* USB2.0 Host registers (original offset is +0x200) *******/
#define USB2_INT_ENABLE		0x000
#define USB2_USBCTR		0x00c
#define USB2_SPD_RSM_TIMSET	0x10c
#define USB2_OC_TIMSET		0x110
#define USB2_COMMCTRL		0x600
#define USB2_OBINTSTA		0x604
#define USB2_OBINTEN		0x608
#define USB2_VBCTRL		0x60c
#define USB2_LINECTRL1		0x610
#define USB2_ADPCTRL		0x630

/* INT_ENABLE */
#define USB2_INT_ENABLE_UCOM_INTEN	BIT(3)
#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
#define USB2_INT_ENABLE_INIT		(USB2_INT_ENABLE_UCOM_INTEN | \
					 USB2_INT_ENABLE_USBH_INTB_EN | \
					 USB2_INT_ENABLE_USBH_INTA_EN)

/* USBCTR */
#define USB2_USBCTR_DIRPD	BIT(2)
#define USB2_USBCTR_PLL_RST	BIT(1)

/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b

/* OC_TIMSET */
#define USB2_OC_TIMSET_INIT		0x000209ab

/* COMMCTRL */
#define USB2_COMMCTRL_OTG_PERI		BIT(31)	/* 1 = Peripheral mode */

/* OBINTSTA and OBINTEN */
#define USB2_OBINT_SESSVLDCHG		BIT(12)
#define USB2_OBINT_IDDIGCHG		BIT(11)
#define USB2_OBINT_BITS			(USB2_OBINT_SESSVLDCHG | \
					 USB2_OBINT_IDDIGCHG)

/* VBCTRL */
#define USB2_VBCTRL_DRVVBUSSEL		BIT(8)

/* LINECTRL1 */
#define USB2_LINECTRL1_DPRPD_EN		BIT(19)
#define USB2_LINECTRL1_DP_RPD		BIT(18)
#define USB2_LINECTRL1_DMRPD_EN		BIT(17)
#define USB2_LINECTRL1_DM_RPD		BIT(16)

/* ADPCTRL */
#define USB2_ADPCTRL_OTGSESSVLD		BIT(20)
#define USB2_ADPCTRL_IDDIG		BIT(19)
#define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
#define USB2_ADPCTRL_DRVVBUS		BIT(4)

struct rcar_gen3_chan {
	void __iomem *base;
	struct phy *phy;
	bool has_otg;
};

static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
{
	void __iomem *usb2_base = ch->base;
	u32 val = readl(usb2_base + USB2_COMMCTRL);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
	if (host)
		val &= ~USB2_COMMCTRL_OTG_PERI;
	else
		val |= USB2_COMMCTRL_OTG_PERI;
	writel(val, usb2_base + USB2_COMMCTRL);
}

static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
{
	void __iomem *usb2_base = ch->base;
	u32 val = readl(usb2_base + USB2_LINECTRL1);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
	val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
	if (dp)
		val |= USB2_LINECTRL1_DP_RPD;
	if (dm)
		val |= USB2_LINECTRL1_DM_RPD;
	writel(val, usb2_base + USB2_LINECTRL1);
}

static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
{
	void __iomem *usb2_base = ch->base;
	u32 val = readl(usb2_base + USB2_ADPCTRL);

	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
	if (vbus)
		val |= USB2_ADPCTRL_DRVVBUS;
	else
		val &= ~USB2_ADPCTRL_DRVVBUS;
	writel(val, usb2_base + USB2_ADPCTRL);
}

static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
{
	rcar_gen3_set_linectrl(ch, 1, 1);
	rcar_gen3_set_host_mode(ch, 1);
	rcar_gen3_enable_vbus_ctrl(ch, 1);
}

static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
{
	rcar_gen3_set_linectrl(ch, 0, 1);
	rcar_gen3_set_host_mode(ch, 0);
	rcar_gen3_enable_vbus_ctrl(ch, 0);
}

static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
{
	return !!(readl(ch->base + USB2_ADPCTRL) &
		  USB2_ADPCTRL_OTGSESSVLD);
}

static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
{
	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
}

static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
{
	bool is_host = true;

	/* B-device? */
	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
		is_host = false;

	if (is_host)
		rcar_gen3_init_for_host(ch);
	else
		rcar_gen3_init_for_peri(ch);
}

static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
{
	void __iomem *usb2_base = ch->base;
	u32 val;

	val = readl(usb2_base + USB2_VBCTRL);
	writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	val = readl(usb2_base + USB2_OBINTEN);
	writel(val | USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
	val = readl(usb2_base + USB2_ADPCTRL);
	writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
	val = readl(usb2_base + USB2_LINECTRL1);
	rcar_gen3_set_linectrl(ch, 0, 0);
	writel(val | USB2_LINECTRL1_DPRPD_EN | USB2_LINECTRL1_DMRPD_EN,
	       usb2_base + USB2_LINECTRL1);

	rcar_gen3_device_recognition(ch);
}

static int rcar_gen3_phy_usb2_init(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *usb2_base = channel->base;

	/* Initialize USB2 part */
	writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
	writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);

	/* Initialize otg part */
	if (channel->has_otg)
		rcar_gen3_init_otg(channel);

	return 0;
}

static int rcar_gen3_phy_usb2_exit(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);

	writel(0, channel->base + USB2_INT_ENABLE);

	return 0;
}

static int rcar_gen3_phy_usb2_power_on(struct phy *p)
{
	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	void __iomem *usb2_base = channel->base;
	u32 val;

	val = readl(usb2_base + USB2_USBCTR);
	val |= USB2_USBCTR_PLL_RST;
	writel(val, usb2_base + USB2_USBCTR);
	val &= ~USB2_USBCTR_PLL_RST;
	writel(val, usb2_base + USB2_USBCTR);

	return 0;
}

static struct phy_ops rcar_gen3_phy_usb2_ops = {
	.init		= rcar_gen3_phy_usb2_init,
	.exit		= rcar_gen3_phy_usb2_exit,
	.power_on	= rcar_gen3_phy_usb2_power_on,
	.owner		= THIS_MODULE,
};

static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
{
	struct rcar_gen3_chan *ch = _ch;
	void __iomem *usb2_base = ch->base;
	u32 status = readl(usb2_base + USB2_OBINTSTA);
	irqreturn_t ret = IRQ_NONE;

	if (status & USB2_OBINT_BITS) {
		dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
		writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
		rcar_gen3_device_recognition(ch);
		ret = IRQ_HANDLED;
	}

	return ret;
}

static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
	{ .compatible = "renesas,usb2-phy-r8a7795" },
	{ .compatible = "renesas,rcar-gen3-usb2-phy" },
	{ }
};
MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);

static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rcar_gen3_chan *channel;
	struct phy_provider *provider;
	struct resource *res;
	int irq;

	if (!dev->of_node) {
		dev_err(dev, "This driver needs device tree\n");
		return -EINVAL;
	}

	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
	if (!channel)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	channel->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(channel->base))
		return PTR_ERR(channel->base);

	/* call request_irq for OTG */
	irq = platform_get_irq(pdev, 0);
	if (irq >= 0) {
		irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
				       IRQF_SHARED, dev_name(dev), channel);
		if (irq < 0)
			dev_err(dev, "No irq handler (%d)\n", irq);
		channel->has_otg = true;
	}

	/* devm_phy_create() will call pm_runtime_enable(dev); */
	channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
	if (IS_ERR(channel->phy)) {
		dev_err(dev, "Failed to create USB2 PHY\n");
		return PTR_ERR(channel->phy);
	}

	phy_set_drvdata(channel->phy, channel);

	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	if (IS_ERR(provider))
		dev_err(dev, "Failed to register PHY provider\n");

	return PTR_ERR_OR_ZERO(provider);
}

static struct platform_driver rcar_gen3_phy_usb2_driver = {
	.driver = {
		.name		= "phy_rcar_gen3_usb2",
		.of_match_table	= rcar_gen3_phy_usb2_match_table,
	},
	.probe	= rcar_gen3_phy_usb2_probe,
};
module_platform_driver(rcar_gen3_phy_usb2_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
Commit	Line	Data
f3b5a8d9 YS	1	/*
	2	* Renesas R-Car Gen3 for USB2.0 PHY driver
	3	*
	4	* Copyright (C) 2015 Renesas Electronics Corporation
	5	*
	6	* This is based on the phy-rcar-gen2 driver:
	7	* Copyright (C) 2014 Renesas Solutions Corp.
	8	* Copyright (C) 2014 Cogent Embedded, Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
9f391c57	15	#include <linux/interrupt.h>
f3b5a8d9 YS	16	#include <linux/io.h>
	17	#include <linux/module.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/phy/phy.h>
	21	#include <linux/platform_device.h>
	22
	23	/***** USB2.0 Host registers (original offset is +0x200) *****/
	24	#define USB2_INT_ENABLE 0x000
	25	#define USB2_USBCTR 0x00c
	26	#define USB2_SPD_RSM_TIMSET 0x10c
	27	#define USB2_OC_TIMSET 0x110
1114e2d3	28	#define USB2_COMMCTRL 0x600
9f391c57 YS	29	#define USB2_OBINTSTA 0x604
9f391c57 YS	30	#define USB2_OBINTEN 0x608
1114e2d3 YS	31	#define USB2_VBCTRL 0x60c
	32	#define USB2_LINECTRL1 0x610
	33	#define USB2_ADPCTRL 0x630
f3b5a8d9 YS	34
f3b5a8d9 YS	35	/* INT_ENABLE */
9f391c57	36	#define USB2_INT_ENABLE_UCOM_INTEN BIT(3)
f3b5a8d9 YS	37	#define USB2_INT_ENABLE_USBH_INTB_EN BIT(2)
f3b5a8d9 YS	38	#define USB2_INT_ENABLE_USBH_INTA_EN BIT(1)
9f391c57 YS	39	#define USB2_INT_ENABLE_INIT (USB2_INT_ENABLE_UCOM_INTEN \| \
9f391c57 YS	40	USB2_INT_ENABLE_USBH_INTB_EN \| \
f3b5a8d9 YS	41	USB2_INT_ENABLE_USBH_INTA_EN)
	42
	43	/* USBCTR */
	44	#define USB2_USBCTR_DIRPD BIT(2)
	45	#define USB2_USBCTR_PLL_RST BIT(1)
	46
	47	/* SPD_RSM_TIMSET */
	48	#define USB2_SPD_RSM_TIMSET_INIT 0x014e029b
	49
	50	/* OC_TIMSET */
	51	#define USB2_OC_TIMSET_INIT 0x000209ab
	52
1114e2d3 YS	53	/* COMMCTRL */
	54	#define USB2_COMMCTRL_OTG_PERI BIT(31) /* 1 = Peripheral mode */
	55
9f391c57 YS	56	/* OBINTSTA and OBINTEN */
	57	#define USB2_OBINT_SESSVLDCHG BIT(12)
	58	#define USB2_OBINT_IDDIGCHG BIT(11)
	59	#define USB2_OBINT_BITS (USB2_OBINT_SESSVLDCHG \| \
	60	USB2_OBINT_IDDIGCHG)
	61
1114e2d3 YS	62	/* VBCTRL */
	63	#define USB2_VBCTRL_DRVVBUSSEL BIT(8)
	64
	65	/* LINECTRL1 */
	66	#define USB2_LINECTRL1_DPRPD_EN BIT(19)
	67	#define USB2_LINECTRL1_DP_RPD BIT(18)
	68	#define USB2_LINECTRL1_DMRPD_EN BIT(17)
	69	#define USB2_LINECTRL1_DM_RPD BIT(16)
	70
	71	/* ADPCTRL */
	72	#define USB2_ADPCTRL_OTGSESSVLD BIT(20)
	73	#define USB2_ADPCTRL_IDDIG BIT(19)
	74	#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
	75	#define USB2_ADPCTRL_DRVVBUS BIT(4)
	76
f3b5a8d9	77	struct rcar_gen3_chan {
801a69c7	78	void __iomem *base;
f3b5a8d9	79	struct phy *phy;
b9564016	80	bool has_otg;
f3b5a8d9 YS	81	};
f3b5a8d9 YS	82
1114e2d3 YS	83	static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
1114e2d3 YS	84	{
801a69c7	85	void __iomem *usb2_base = ch->base;
1114e2d3 YS	86	u32 val = readl(usb2_base + USB2_COMMCTRL);
	87
	88	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, host);
	89	if (host)
	90	val &= ~USB2_COMMCTRL_OTG_PERI;
	91	else
	92	val \|= USB2_COMMCTRL_OTG_PERI;
	93	writel(val, usb2_base + USB2_COMMCTRL);
	94	}
	95
	96	static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
	97	{
801a69c7	98	void __iomem *usb2_base = ch->base;
1114e2d3 YS	99	u32 val = readl(usb2_base + USB2_LINECTRL1);
	100
	101	dev_vdbg(&ch->phy->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
	102	val &= ~(USB2_LINECTRL1_DP_RPD \| USB2_LINECTRL1_DM_RPD);
	103	if (dp)
	104	val \|= USB2_LINECTRL1_DP_RPD;
	105	if (dm)
	106	val \|= USB2_LINECTRL1_DM_RPD;
	107	writel(val, usb2_base + USB2_LINECTRL1);
	108	}
	109
	110	static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
	111	{
801a69c7	112	void __iomem *usb2_base = ch->base;
1114e2d3 YS	113	u32 val = readl(usb2_base + USB2_ADPCTRL);
	114
	115	dev_vdbg(&ch->phy->dev, "%s: %08x, %d\n", __func__, val, vbus);
	116	if (vbus)
	117	val \|= USB2_ADPCTRL_DRVVBUS;
	118	else
	119	val &= ~USB2_ADPCTRL_DRVVBUS;
	120	writel(val, usb2_base + USB2_ADPCTRL);
	121	}
	122
	123	static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
	124	{
	125	rcar_gen3_set_linectrl(ch, 1, 1);
	126	rcar_gen3_set_host_mode(ch, 1);
	127	rcar_gen3_enable_vbus_ctrl(ch, 1);
	128	}
	129
	130	static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
	131	{
	132	rcar_gen3_set_linectrl(ch, 0, 1);
	133	rcar_gen3_set_host_mode(ch, 0);
	134	rcar_gen3_enable_vbus_ctrl(ch, 0);
	135	}
	136
	137	static bool rcar_gen3_check_vbus(struct rcar_gen3_chan *ch)
	138	{
801a69c7	139	return !!(readl(ch->base + USB2_ADPCTRL) &
1114e2d3 YS	140	USB2_ADPCTRL_OTGSESSVLD);
	141	}
	142
	143	static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
	144	{
801a69c7	145	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
1114e2d3 YS	146	}
	147
	148	static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
	149	{
	150	bool is_host = true;
	151
	152	/* B-device? */
	153	if (rcar_gen3_check_id(ch) && rcar_gen3_check_vbus(ch))
	154	is_host = false;
	155
	156	if (is_host)
	157	rcar_gen3_init_for_host(ch);
	158	else
	159	rcar_gen3_init_for_peri(ch);
	160	}
	161
	162	static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
	163	{
801a69c7	164	void __iomem *usb2_base = ch->base;
1114e2d3 YS	165	u32 val;
	166
	167	val = readl(usb2_base + USB2_VBCTRL);
	168	writel(val \| USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
9f391c57 YS	169	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	170	val = readl(usb2_base + USB2_OBINTEN);
	171	writel(val \| USB2_OBINT_BITS, usb2_base + USB2_OBINTEN);
1114e2d3 YS	172	val = readl(usb2_base + USB2_ADPCTRL);
	173	writel(val \| USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
	174	val = readl(usb2_base + USB2_LINECTRL1);
	175	rcar_gen3_set_linectrl(ch, 0, 0);
	176	writel(val \| USB2_LINECTRL1_DPRPD_EN \| USB2_LINECTRL1_DMRPD_EN,
	177	usb2_base + USB2_LINECTRL1);
	178
	179	rcar_gen3_device_recognition(ch);
	180	}
	181
f3b5a8d9 YS	182	static int rcar_gen3_phy_usb2_init(struct phy *p)
	183	{
	184	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
801a69c7	185	void __iomem *usb2_base = channel->base;
f3b5a8d9 YS	186
	187	/* Initialize USB2 part */
	188	writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
	189	writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
	190	writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
	191
b9564016 YS	192	/* Initialize otg part */
b9564016 YS	193	if (channel->has_otg)
1114e2d3	194	rcar_gen3_init_otg(channel);
f3b5a8d9 YS	195
	196	return 0;
	197	}
	198
	199	static int rcar_gen3_phy_usb2_exit(struct phy *p)
	200	{
	201	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
	202
801a69c7	203	writel(0, channel->base + USB2_INT_ENABLE);
f3b5a8d9 YS	204
	205	return 0;
	206	}
	207
	208	static int rcar_gen3_phy_usb2_power_on(struct phy *p)
	209	{
	210	struct rcar_gen3_chan *channel = phy_get_drvdata(p);
801a69c7	211	void __iomem *usb2_base = channel->base;
f3b5a8d9 YS	212	u32 val;
	213
	214	val = readl(usb2_base + USB2_USBCTR);
	215	val \|= USB2_USBCTR_PLL_RST;
	216	writel(val, usb2_base + USB2_USBCTR);
	217	val &= ~USB2_USBCTR_PLL_RST;
	218	writel(val, usb2_base + USB2_USBCTR);
	219
f3b5a8d9 YS	220	return 0;
	221	}
	222
	223	static struct phy_ops rcar_gen3_phy_usb2_ops = {
	224	.init = rcar_gen3_phy_usb2_init,
	225	.exit = rcar_gen3_phy_usb2_exit,
	226	.power_on = rcar_gen3_phy_usb2_power_on,
f3b5a8d9 YS	227	.owner = THIS_MODULE,
	228	};
	229
9f391c57 YS	230	static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
	231	{
	232	struct rcar_gen3_chan *ch = _ch;
801a69c7	233	void __iomem *usb2_base = ch->base;
9f391c57 YS	234	u32 status = readl(usb2_base + USB2_OBINTSTA);
	235	irqreturn_t ret = IRQ_NONE;
	236
	237	if (status & USB2_OBINT_BITS) {
	238	dev_vdbg(&ch->phy->dev, "%s: %08x\n", __func__, status);
	239	writel(USB2_OBINT_BITS, usb2_base + USB2_OBINTSTA);
	240	rcar_gen3_device_recognition(ch);
	241	ret = IRQ_HANDLED;
	242	}
	243
	244	return ret;
	245	}
	246
f3b5a8d9 YS	247	static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
f3b5a8d9 YS	248	{ .compatible = "renesas,usb2-phy-r8a7795" },
cde7bc36	249	{ .compatible = "renesas,rcar-gen3-usb2-phy" },
f3b5a8d9 YS	250	{ }
	251	};
	252	MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
	253
	254	static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
	255	{
	256	struct device *dev = &pdev->dev;
	257	struct rcar_gen3_chan *channel;
	258	struct phy_provider *provider;
	259	struct resource *res;
b9564016	260	int irq;
f3b5a8d9 YS	261
	262	if (!dev->of_node) {
	263	dev_err(dev, "This driver needs device tree\n");
	264	return -EINVAL;
	265	}
	266
	267	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
	268	if (!channel)
	269	return -ENOMEM;
	270
b9564016	271	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801a69c7 YS	272	channel->base = devm_ioremap_resource(dev, res);
	273	if (IS_ERR(channel->base))
	274	return PTR_ERR(channel->base);
f3b5a8d9	275
b9564016 YS	276	/* call request_irq for OTG */
	277	irq = platform_get_irq(pdev, 0);
	278	if (irq >= 0) {
	279	irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
	280	IRQF_SHARED, dev_name(dev), channel);
9f391c57 YS	281	if (irq < 0)
9f391c57 YS	282	dev_err(dev, "No irq handler (%d)\n", irq);
b9564016	283	channel->has_otg = true;
f3b5a8d9 YS	284	}
	285
	286	/* devm_phy_create() will call pm_runtime_enable(dev); */
	287	channel->phy = devm_phy_create(dev, NULL, &rcar_gen3_phy_usb2_ops);
	288	if (IS_ERR(channel->phy)) {
	289	dev_err(dev, "Failed to create USB2 PHY\n");
	290	return PTR_ERR(channel->phy);
	291	}
	292
	293	phy_set_drvdata(channel->phy, channel);
	294
	295	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	296	if (IS_ERR(provider))
	297	dev_err(dev, "Failed to register PHY provider\n");
	298
	299	return PTR_ERR_OR_ZERO(provider);
	300	}
	301
	302	static struct platform_driver rcar_gen3_phy_usb2_driver = {
	303	.driver = {
	304	.name = "phy_rcar_gen3_usb2",
	305	.of_match_table = rcar_gen3_phy_usb2_match_table,
	306	},
	307	.probe = rcar_gen3_phy_usb2_probe,
	308	};
	309	module_platform_driver(rcar_gen3_phy_usb2_driver);
	310
	311	MODULE_LICENSE("GPL v2");
	312	MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
	313	MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");