[deliverable/linux.git] / drivers / phy / phy-rockchip-usb.c

/*
 * Rockchip usb PHY driver
 *
 * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

static int enable_usb_uart;

#define HIWORD_UPDATE(val, mask) \
		((val) | (mask) << 16)

#define UOC_CON0_SIDDQ BIT(13)

struct rockchip_usb_phys {
	int reg;
	const char *pll_name;
};

struct rockchip_usb_phy_base;
struct rockchip_usb_phy_pdata {
	struct rockchip_usb_phys *phys;
	int (*init_usb_uart)(struct regmap *grf);
	int usb_uart_phy;
};

struct rockchip_usb_phy_base {
	struct device *dev;
	struct regmap *reg_base;
	const struct rockchip_usb_phy_pdata *pdata;
};

struct rockchip_usb_phy {
	struct rockchip_usb_phy_base *base;
	struct device_node *np;
	unsigned int	reg_offset;
	struct clk	*clk;
	struct clk      *clk480m;
	struct clk_hw	clk480m_hw;
	struct phy	*phy;
	bool		uart_enabled;
};

static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
					   bool siddq)
{
	u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);

	return regmap_write(phy->base->reg_base, phy->reg_offset, val);
}

static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
						unsigned long parent_rate)
{
	return 480000000;
}

static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
{
	struct rockchip_usb_phy *phy = container_of(hw,
						    struct rockchip_usb_phy,
						    clk480m_hw);

	/* Power down usb phy analog blocks by set siddq 1 */
	rockchip_usb_phy_power(phy, 1);
}

static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
{
	struct rockchip_usb_phy *phy = container_of(hw,
						    struct rockchip_usb_phy,
						    clk480m_hw);

	/* Power up usb phy analog blocks by set siddq 0 */
	return rockchip_usb_phy_power(phy, 0);
}

static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
{
	struct rockchip_usb_phy *phy = container_of(hw,
						    struct rockchip_usb_phy,
						    clk480m_hw);
	int ret;
	u32 val;

	ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
	if (ret < 0)
		return ret;

	return (val & UOC_CON0_SIDDQ) ? 0 : 1;
}

static const struct clk_ops rockchip_usb_phy480m_ops = {
	.enable = rockchip_usb_phy480m_enable,
	.disable = rockchip_usb_phy480m_disable,
	.is_enabled = rockchip_usb_phy480m_is_enabled,
	.recalc_rate = rockchip_usb_phy480m_recalc_rate,
};

static int rockchip_usb_phy_power_off(struct phy *_phy)
{
	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);

	if (phy->uart_enabled)
		return -EBUSY;

	clk_disable_unprepare(phy->clk480m);

	return 0;
}

static int rockchip_usb_phy_power_on(struct phy *_phy)
{
	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);

	if (phy->uart_enabled)
		return -EBUSY;

	return clk_prepare_enable(phy->clk480m);
}

static const struct phy_ops ops = {
	.power_on	= rockchip_usb_phy_power_on,
	.power_off	= rockchip_usb_phy_power_off,
	.owner		= THIS_MODULE,
};

static void rockchip_usb_phy_action(void *data)
{
	struct rockchip_usb_phy *rk_phy = data;

	if (!rk_phy->uart_enabled) {
		of_clk_del_provider(rk_phy->np);
		clk_unregister(rk_phy->clk480m);
	}

	if (rk_phy->clk)
		clk_put(rk_phy->clk);
}

static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
				 struct device_node *child)
{
	struct rockchip_usb_phy *rk_phy;
	unsigned int reg_offset;
	const char *clk_name;
	struct clk_init_data init;
	int err, i;

	rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
	if (!rk_phy)
		return -ENOMEM;

	rk_phy->base = base;
	rk_phy->np = child;

	if (of_property_read_u32(child, "reg", &reg_offset)) {
		dev_err(base->dev, "missing reg property in node %s\n",
			child->name);
		return -EINVAL;
	}

	rk_phy->reg_offset = reg_offset;

	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
	if (IS_ERR(rk_phy->clk))
		rk_phy->clk = NULL;

	i = 0;
	init.name = NULL;
	while (base->pdata->phys[i].reg) {
		if (base->pdata->phys[i].reg == reg_offset) {
			init.name = base->pdata->phys[i].pll_name;
			break;
		}
		i++;
	}

	if (!init.name) {
		dev_err(base->dev, "phy data not found\n");
		return -EINVAL;
	}

	if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
		dev_dbg(base->dev, "phy%d used as uart output\n", i);
		rk_phy->uart_enabled = true;
	} else {
		if (rk_phy->clk) {
			clk_name = __clk_get_name(rk_phy->clk);
			init.flags = 0;
			init.parent_names = &clk_name;
			init.num_parents = 1;
		} else {
			init.flags = 0;
			init.parent_names = NULL;
			init.num_parents = 0;
		}

		init.ops = &rockchip_usb_phy480m_ops;
		rk_phy->clk480m_hw.init = &init;

		rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
		if (IS_ERR(rk_phy->clk480m)) {
			err = PTR_ERR(rk_phy->clk480m);
			goto err_clk;
		}

		err = of_clk_add_provider(child, of_clk_src_simple_get,
					rk_phy->clk480m);
		if (err < 0)
			goto err_clk_prov;
	}

	err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
	if (err)
		goto err_devm_action;

	rk_phy->phy = devm_phy_create(base->dev, child, &ops);
	if (IS_ERR(rk_phy->phy)) {
		dev_err(base->dev, "failed to create PHY\n");
		return PTR_ERR(rk_phy->phy);
	}
	phy_set_drvdata(rk_phy->phy, rk_phy);

	/*
	 * When acting as uart-pipe, just keep clock on otherwise
	 * only power up usb phy when it use, so disable it when init
	 */
	if (rk_phy->uart_enabled)
		return clk_prepare_enable(rk_phy->clk);
	else
		return rockchip_usb_phy_power(rk_phy, 1);

err_devm_action:
	if (!rk_phy->uart_enabled)
		of_clk_del_provider(child);
err_clk_prov:
	if (!rk_phy->uart_enabled)
		clk_unregister(rk_phy->clk480m);
err_clk:
	if (rk_phy->clk)
		clk_put(rk_phy->clk);
	return err;
}

static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
	.phys = (struct rockchip_usb_phys[]){
		{ .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
		{ .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
		{ /* sentinel */ }
	},
};

static const struct rockchip_usb_phy_pdata rk3188_pdata = {
	.phys = (struct rockchip_usb_phys[]){
		{ .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
		{ .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
		{ /* sentinel */ }
	},
};

#define RK3288_UOC0_CON0				0x320
#define RK3288_UOC0_CON0_COMMON_ON_N			BIT(0)
#define RK3288_UOC0_CON0_DISABLE			BIT(4)

#define RK3288_UOC0_CON2				0x328
#define RK3288_UOC0_CON2_SOFT_CON_SEL			BIT(2)

#define RK3288_UOC0_CON3				0x32c
#define RK3288_UOC0_CON3_UTMI_SUSPENDN			BIT(0)
#define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING		(1 << 1)
#define RK3288_UOC0_CON3_UTMI_OPMODE_MASK		(3 << 1)
#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC	(1 << 3)
#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK		(3 << 3)
#define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED		BIT(5)
#define RK3288_UOC0_CON3_BYPASSDMEN			BIT(6)
#define RK3288_UOC0_CON3_BYPASSSEL			BIT(7)

/*
 * Enable the bypass of uart2 data through the otg usb phy.
 * Original description in the TRM.
 * 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
 * 2. Disable the pull-up resistance on the D+ line by setting
 *    OPMODE0[1:0] to 2’b01.
 * 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
 *    mode, set COMMONONN to 1’b1.
 * 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
 * 5. Set BYPASSSEL0 to 1’b1.
 * 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
 * To receive data, monitor FSVPLUS0.
 *
 * The actual code in the vendor kernel does some things differently.
 */
static int __init rk3288_init_usb_uart(struct regmap *grf)
{
	u32 val;
	int ret;

	/*
	 * COMMON_ON and DISABLE settings are described in the TRM,
	 * but were not present in the original code.
	 * Also disable the analog phy components to save power.
	 */
	val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N
				| RK3288_UOC0_CON0_DISABLE
				| UOC_CON0_SIDDQ,
			    RK3288_UOC0_CON0_COMMON_ON_N
				| RK3288_UOC0_CON0_DISABLE
				| UOC_CON0_SIDDQ);
	ret = regmap_write(grf, RK3288_UOC0_CON0, val);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
			    RK3288_UOC0_CON2_SOFT_CON_SEL);
	ret = regmap_write(grf, RK3288_UOC0_CON2, val);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING
				| RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC
				| RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED,
			    RK3288_UOC0_CON3_UTMI_SUSPENDN
				| RK3288_UOC0_CON3_UTMI_OPMODE_MASK
				| RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK
				| RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED);
	ret = regmap_write(grf, RK3288_UOC0_CON3, val);
	if (ret)
		return ret;

	val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
				| RK3288_UOC0_CON3_BYPASSDMEN,
			    RK3288_UOC0_CON3_BYPASSSEL
				| RK3288_UOC0_CON3_BYPASSDMEN);
	ret = regmap_write(grf, RK3288_UOC0_CON3, val);
	if (ret)
		return ret;

	return 0;
}

static const struct rockchip_usb_phy_pdata rk3288_pdata = {
	.phys = (struct rockchip_usb_phys[]){
		{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
		{ .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
		{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
		{ /* sentinel */ }
	},
	.init_usb_uart = rk3288_init_usb_uart,
	.usb_uart_phy = 0,
};

static int rockchip_usb_phy_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct rockchip_usb_phy_base *phy_base;
	struct phy_provider *phy_provider;
	const struct of_device_id *match;
	struct device_node *child;
	int err;

	phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
	if (!phy_base)
		return -ENOMEM;

	match = of_match_device(dev->driver->of_match_table, dev);
	if (!match || !match->data) {
		dev_err(dev, "missing phy data\n");
		return -EINVAL;
	}

	phy_base->pdata = match->data;

	phy_base->dev = dev;
	phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
							     "rockchip,grf");
	if (IS_ERR(phy_base->reg_base)) {
		dev_err(&pdev->dev, "Missing rockchip,grf property\n");
		return PTR_ERR(phy_base->reg_base);
	}

	for_each_available_child_of_node(dev->of_node, child) {
		err = rockchip_usb_phy_init(phy_base, child);
		if (err) {
			of_node_put(child);
			return err;
		}
	}

	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	return PTR_ERR_OR_ZERO(phy_provider);
}

static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
	{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
	{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
	{}
};

MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);

static struct platform_driver rockchip_usb_driver = {
	.probe		= rockchip_usb_phy_probe,
	.driver		= {
		.name	= "rockchip-usb-phy",
		.of_match_table = rockchip_usb_phy_dt_ids,
	},
};

module_platform_driver(rockchip_usb_driver);

#ifndef MODULE
static int __init rockchip_init_usb_uart(void)
{
	const struct of_device_id *match;
	const struct rockchip_usb_phy_pdata *data;
	struct device_node *np;
	struct regmap *grf;
	int ret;

	if (!enable_usb_uart)
		return 0;

	np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
					     &match);
	if (!np) {
		pr_err("%s: failed to find usbphy node\n", __func__);
		return -ENOTSUPP;
	}

	pr_debug("%s: using settings for %s\n", __func__, match->compatible);
	data = match->data;

	if (!data->init_usb_uart) {
		pr_err("%s: usb-uart not available on %s\n",
		       __func__, match->compatible);
		return -ENOTSUPP;
	}

	grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	if (IS_ERR(grf)) {
		pr_err("%s: Missing rockchip,grf property, %lu\n",
		       __func__, PTR_ERR(grf));
		return PTR_ERR(grf);
	}

	ret = data->init_usb_uart(grf);
	if (ret) {
		pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
		enable_usb_uart = 0;
		return ret;
	}

	return 0;
}
early_initcall(rockchip_init_usb_uart);

static int __init rockchip_usb_uart(char *buf)
{
	enable_usb_uart = true;
	return 0;
}
early_param("rockchip.usb_uart", rockchip_usb_uart);
#endif

MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
64d11406 YL	1	/*
	2	* Rockchip usb PHY driver
	3	*
	4	* Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
	5	* Copyright (C) 2014 ROCKCHIP, Inc.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/clk.h>
b74fe7c7	18	#include <linux/clk-provider.h>
64d11406 YL	19	#include <linux/io.h>
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/mutex.h>
	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
b74fe7c7	25	#include <linux/of_platform.h>
64d11406 YL	26	#include <linux/phy/phy.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/regulator/consumer.h>
	29	#include <linux/reset.h>
	30	#include <linux/regmap.h>
	31	#include <linux/mfd/syscon.h>
	32
605df8af HS	33	static int enable_usb_uart;
	34
	35	#define HIWORD_UPDATE(val, mask) \
	36	((val) \| (mask) << 16)
	37
	38	#define UOC_CON0_SIDDQ BIT(13)
64d11406	39
b74fe7c7 HS	40	struct rockchip_usb_phys {
	41	int reg;
	42	const char *pll_name;
	43	};
	44
605df8af	45	struct rockchip_usb_phy_base;
b74fe7c7 HS	46	struct rockchip_usb_phy_pdata {
b74fe7c7 HS	47	struct rockchip_usb_phys *phys;
605df8af HS	48	int (init_usb_uart)(struct regmap grf);
605df8af HS	49	int usb_uart_phy;
b74fe7c7 HS	50	};
b74fe7c7 HS	51
5fdbb97d HS	52	struct rockchip_usb_phy_base {
	53	struct device *dev;
	54	struct regmap *reg_base;
b74fe7c7	55	const struct rockchip_usb_phy_pdata *pdata;
5fdbb97d HS	56	};
5fdbb97d HS	57
64d11406	58	struct rockchip_usb_phy {
5fdbb97d	59	struct rockchip_usb_phy_base *base;
b74fe7c7	60	struct device_node *np;
64d11406	61	unsigned int reg_offset;
64d11406	62	struct clk *clk;
b74fe7c7 HS	63	struct clk *clk480m;
b74fe7c7 HS	64	struct clk_hw clk480m_hw;
64d11406	65	struct phy *phy;
605df8af	66	bool uart_enabled;
64d11406 YL	67	};
	68
	69	static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
	70	bool siddq)
	71	{
605df8af HS	72	u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ);
	73
	74	return regmap_write(phy->base->reg_base, phy->reg_offset, val);
64d11406 YL	75	}
64d11406 YL	76
b74fe7c7 HS	77	static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
b74fe7c7 HS	78	unsigned long parent_rate)
64d11406	79	{
b74fe7c7 HS	80	return 480000000;
	81	}
	82
	83	static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
	84	{
	85	struct rockchip_usb_phy *phy = container_of(hw,
	86	struct rockchip_usb_phy,
	87	clk480m_hw);
64d11406 YL	88
64d11406 YL	89	/* Power down usb phy analog blocks by set siddq 1 */
b74fe7c7 HS	90	rockchip_usb_phy_power(phy, 1);
	91	}
	92
	93	static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
	94	{
	95	struct rockchip_usb_phy *phy = container_of(hw,
	96	struct rockchip_usb_phy,
	97	clk480m_hw);
	98
	99	/* Power up usb phy analog blocks by set siddq 0 */
	100	return rockchip_usb_phy_power(phy, 0);
	101	}
	102
	103	static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
	104	{
	105	struct rockchip_usb_phy *phy = container_of(hw,
	106	struct rockchip_usb_phy,
	107	clk480m_hw);
	108	int ret;
	109	u32 val;
	110
	111	ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
	112	if (ret < 0)
64d11406 YL	113	return ret;
64d11406 YL	114
605df8af	115	return (val & UOC_CON0_SIDDQ) ? 0 : 1;
b74fe7c7 HS	116	}
	117
	118	static const struct clk_ops rockchip_usb_phy480m_ops = {
	119	.enable = rockchip_usb_phy480m_enable,
	120	.disable = rockchip_usb_phy480m_disable,
	121	.is_enabled = rockchip_usb_phy480m_is_enabled,
	122	.recalc_rate = rockchip_usb_phy480m_recalc_rate,
	123	};
	124
	125	static int rockchip_usb_phy_power_off(struct phy *_phy)
	126	{
	127	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
	128
605df8af HS	129	if (phy->uart_enabled)
	130	return -EBUSY;
	131
b74fe7c7	132	clk_disable_unprepare(phy->clk480m);
64d11406 YL	133
	134	return 0;
	135	}
	136
	137	static int rockchip_usb_phy_power_on(struct phy *_phy)
	138	{
	139	struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
64d11406	140
605df8af HS	141	if (phy->uart_enabled)
	142	return -EBUSY;
	143
b74fe7c7	144	return clk_prepare_enable(phy->clk480m);
64d11406 YL	145	}
64d11406 YL	146
4a9e5ca1	147	static const struct phy_ops ops = {
64d11406 YL	148	.power_on = rockchip_usb_phy_power_on,
	149	.power_off = rockchip_usb_phy_power_off,
	150	.owner = THIS_MODULE,
	151	};
	152
75d390fe HS	153	static void rockchip_usb_phy_action(void *data)
	154	{
	155	struct rockchip_usb_phy *rk_phy = data;
	156
605df8af HS	157	if (!rk_phy->uart_enabled) {
	158	of_clk_del_provider(rk_phy->np);
	159	clk_unregister(rk_phy->clk480m);
	160	}
b74fe7c7	161
75d390fe HS	162	if (rk_phy->clk)
	163	clk_put(rk_phy->clk);
	164	}
	165
97dd9101 HS	166	static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
	167	struct device_node *child)
	168	{
	169	struct rockchip_usb_phy *rk_phy;
	170	unsigned int reg_offset;
b74fe7c7 HS	171	const char *clk_name;
	172	struct clk_init_data init;
	173	int err, i;
97dd9101 HS	174
	175	rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
	176	if (!rk_phy)
	177	return -ENOMEM;
	178
	179	rk_phy->base = base;
b74fe7c7	180	rk_phy->np = child;
97dd9101 HS	181
	182	if (of_property_read_u32(child, "reg", &reg_offset)) {
	183	dev_err(base->dev, "missing reg property in node %s\n",
	184	child->name);
	185	return -EINVAL;
	186	}
	187
	188	rk_phy->reg_offset = reg_offset;
	189
97dd9101 HS	190	rk_phy->clk = of_clk_get_by_name(child, "phyclk");
	191	if (IS_ERR(rk_phy->clk))
	192	rk_phy->clk = NULL;
	193
b74fe7c7 HS	194	i = 0;
	195	init.name = NULL;
	196	while (base->pdata->phys[i].reg) {
	197	if (base->pdata->phys[i].reg == reg_offset) {
	198	init.name = base->pdata->phys[i].pll_name;
	199	break;
	200	}
	201	i++;
	202	}
	203
	204	if (!init.name) {
	205	dev_err(base->dev, "phy data not found\n");
	206	return -EINVAL;
	207	}
	208
605df8af HS	209	if (enable_usb_uart && base->pdata->usb_uart_phy == i) {
	210	dev_dbg(base->dev, "phy%d used as uart output\n", i);
	211	rk_phy->uart_enabled = true;
b74fe7c7	212	} else {
605df8af HS	213	if (rk_phy->clk) {
	214	clk_name = __clk_get_name(rk_phy->clk);
	215	init.flags = 0;
	216	init.parent_names = &clk_name;
	217	init.num_parents = 1;
	218	} else {
444525d4	219	init.flags = 0;
605df8af HS	220	init.parent_names = NULL;
	221	init.num_parents = 0;
	222	}
b74fe7c7	223
605df8af HS	224	init.ops = &rockchip_usb_phy480m_ops;
605df8af HS	225	rk_phy->clk480m_hw.init = &init;
b74fe7c7	226
605df8af HS	227	rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
	228	if (IS_ERR(rk_phy->clk480m)) {
	229	err = PTR_ERR(rk_phy->clk480m);
	230	goto err_clk;
	231	}
b74fe7c7	232
605df8af HS	233	err = of_clk_add_provider(child, of_clk_src_simple_get,
	234	rk_phy->clk480m);
	235	if (err < 0)
	236	goto err_clk_prov;
	237	}
b74fe7c7 HS	238
	239	err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
	240	if (err)
	241	goto err_devm_action;
	242
97dd9101 HS	243	rk_phy->phy = devm_phy_create(base->dev, child, &ops);
	244	if (IS_ERR(rk_phy->phy)) {
	245	dev_err(base->dev, "failed to create PHY\n");
	246	return PTR_ERR(rk_phy->phy);
	247	}
	248	phy_set_drvdata(rk_phy->phy, rk_phy);
	249
605df8af HS	250	/*
	251	* When acting as uart-pipe, just keep clock on otherwise
	252	* only power up usb phy when it use, so disable it when init
	253	*/
	254	if (rk_phy->uart_enabled)
	255	return clk_prepare_enable(rk_phy->clk);
	256	else
	257	return rockchip_usb_phy_power(rk_phy, 1);
b74fe7c7 HS	258
b74fe7c7 HS	259	err_devm_action:
605df8af HS	260	if (!rk_phy->uart_enabled)
605df8af HS	261	of_clk_del_provider(child);
b74fe7c7	262	err_clk_prov:
605df8af HS	263	if (!rk_phy->uart_enabled)
605df8af HS	264	clk_unregister(rk_phy->clk480m);
b74fe7c7 HS	265	err_clk:
	266	if (rk_phy->clk)
	267	clk_put(rk_phy->clk);
	268	return err;
97dd9101 HS	269	}
97dd9101 HS	270
b74fe7c7 HS	271	static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
	272	.phys = (struct rockchip_usb_phys[]){
	273	{ .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
	274	{ .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
	275	{ /* sentinel */ }
	276	},
	277	};
	278
	279	static const struct rockchip_usb_phy_pdata rk3188_pdata = {
	280	.phys = (struct rockchip_usb_phys[]){
	281	{ .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
	282	{ .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
	283	{ /* sentinel */ }
	284	},
	285	};
	286
605df8af HS	287	#define RK3288_UOC0_CON0 0x320
	288	#define RK3288_UOC0_CON0_COMMON_ON_N BIT(0)
	289	#define RK3288_UOC0_CON0_DISABLE BIT(4)
	290
	291	#define RK3288_UOC0_CON2 0x328
	292	#define RK3288_UOC0_CON2_SOFT_CON_SEL BIT(2)
	293
	294	#define RK3288_UOC0_CON3 0x32c
	295	#define RK3288_UOC0_CON3_UTMI_SUSPENDN BIT(0)
	296	#define RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING (1 << 1)
	297	#define RK3288_UOC0_CON3_UTMI_OPMODE_MASK (3 << 1)
	298	#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC (1 << 3)
	299	#define RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK (3 << 3)
	300	#define RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED BIT(5)
	301	#define RK3288_UOC0_CON3_BYPASSDMEN BIT(6)
	302	#define RK3288_UOC0_CON3_BYPASSSEL BIT(7)
	303
	304	/*
	305	* Enable the bypass of uart2 data through the otg usb phy.
	306	* Original description in the TRM.
	307	* 1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
	308	* 2. Disable the pull-up resistance on the D+ line by setting
	309	* OPMODE0[1:0] to 2’b01.
	310	* 3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
	311	* mode, set COMMONONN to 1’b1.
	312	* 4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
	313	* 5. Set BYPASSSEL0 to 1’b1.
	314	* 6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
	315	* To receive data, monitor FSVPLUS0.
	316	*
	317	* The actual code in the vendor kernel does some things differently.
	318	*/
	319	static int __init rk3288_init_usb_uart(struct regmap *grf)
	320	{
	321	u32 val;
	322	int ret;
	323
	324	/*
	325	* COMMON_ON and DISABLE settings are described in the TRM,
	326	* but were not present in the original code.
	327	* Also disable the analog phy components to save power.
	328	*/
	329	val = HIWORD_UPDATE(RK3288_UOC0_CON0_COMMON_ON_N
	330	\| RK3288_UOC0_CON0_DISABLE
	331	\| UOC_CON0_SIDDQ,
	332	RK3288_UOC0_CON0_COMMON_ON_N
	333	\| RK3288_UOC0_CON0_DISABLE
	334	\| UOC_CON0_SIDDQ);
	335	ret = regmap_write(grf, RK3288_UOC0_CON0, val);
	336	if (ret)
	337	return ret;
	338
	339	val = HIWORD_UPDATE(RK3288_UOC0_CON2_SOFT_CON_SEL,
	340	RK3288_UOC0_CON2_SOFT_CON_SEL);
	341	ret = regmap_write(grf, RK3288_UOC0_CON2, val);
	342	if (ret)
	343	return ret;
	344
	345	val = HIWORD_UPDATE(RK3288_UOC0_CON3_UTMI_OPMODE_NODRIVING
	346	\| RK3288_UOC0_CON3_UTMI_XCVRSEELCT_FSTRANSC
	347	\| RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED,
	348	RK3288_UOC0_CON3_UTMI_SUSPENDN
	349	\| RK3288_UOC0_CON3_UTMI_OPMODE_MASK
	350	\| RK3288_UOC0_CON3_UTMI_XCVRSEELCT_MASK
351	\| RK3288_UOC0_CON3_UTMI_TERMSEL_FULLSPEED);
352	ret = regmap_write(grf, RK3288_UOC0_CON3, val);
353	if (ret)
354	return ret;
355
356	val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL
357	\| RK3288_UOC0_CON3_BYPASSDMEN,
358	RK3288_UOC0_CON3_BYPASSSEL
359	\| RK3288_UOC0_CON3_BYPASSDMEN);
360	ret = regmap_write(grf, RK3288_UOC0_CON3, val);
361	if (ret)
362	return ret;
363
364	return 0;
365	}
366
b74fe7c7 HS	367	static const struct rockchip_usb_phy_pdata rk3288_pdata = {
	368	.phys = (struct rockchip_usb_phys[]){
	369	{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
	370	{ .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
	371	{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
	372	{ /* sentinel */ }
	373	},
605df8af HS	374	.init_usb_uart = rk3288_init_usb_uart,
605df8af HS	375	.usb_uart_phy = 0,
b74fe7c7 HS	376	};
b74fe7c7 HS	377
64d11406 YL	378	static int rockchip_usb_phy_probe(struct platform_device *pdev)
	379	{
	380	struct device *dev = &pdev->dev;
5fdbb97d	381	struct rockchip_usb_phy_base *phy_base;
64d11406	382	struct phy_provider *phy_provider;
b74fe7c7	383	const struct of_device_id *match;
64d11406	384	struct device_node *child;
08db7e5c	385	int err;
64d11406	386
5fdbb97d HS	387	phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
	388	if (!phy_base)
	389	return -ENOMEM;
	390
b74fe7c7 HS	391	match = of_match_device(dev->driver->of_match_table, dev);
	392	if (!match \|\| !match->data) {
	393	dev_err(dev, "missing phy data\n");
	394	return -EINVAL;
	395	}
	396
	397	phy_base->pdata = match->data;
	398
5fdbb97d HS	399	phy_base->dev = dev;
	400	phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
	401	"rockchip,grf");
	402	if (IS_ERR(phy_base->reg_base)) {
64d11406	403	dev_err(&pdev->dev, "Missing rockchip,grf property\n");
5fdbb97d	404	return PTR_ERR(phy_base->reg_base);
64d11406 YL	405	}
	406
	407	for_each_available_child_of_node(dev->of_node, child) {
97dd9101 HS	408	err = rockchip_usb_phy_init(phy_base, child);
	409	if (err) {
	410	of_node_put(child);
75d390fe	411	return err;
64d11406	412	}
64d11406 YL	413	}
	414
	415	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
	416	return PTR_ERR_OR_ZERO(phy_provider);
	417	}
	418
	419	static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
b74fe7c7 HS	420	{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
	421	{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
	422	{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
64d11406 YL	423	{}
	424	};
	425
	426	MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
	427
	428	static struct platform_driver rockchip_usb_driver = {
	429	.probe = rockchip_usb_phy_probe,
	430	.driver = {
	431	.name = "rockchip-usb-phy",
64d11406 YL	432	.of_match_table = rockchip_usb_phy_dt_ids,
	433	},
	434	};
	435
	436	module_platform_driver(rockchip_usb_driver);
	437
605df8af HS	438	#ifndef MODULE
	439	static int __init rockchip_init_usb_uart(void)
	440	{
	441	const struct of_device_id *match;
	442	const struct rockchip_usb_phy_pdata *data;
	443	struct device_node *np;
	444	struct regmap *grf;
	445	int ret;
	446
	447	if (!enable_usb_uart)
	448	return 0;
	449
	450	np = of_find_matching_node_and_match(NULL, rockchip_usb_phy_dt_ids,
	451	&match);
	452	if (!np) {
	453	pr_err("%s: failed to find usbphy node\n", __func__);
	454	return -ENOTSUPP;
	455	}
	456
	457	pr_debug("%s: using settings for %s\n", __func__, match->compatible);
	458	data = match->data;
	459
	460	if (!data->init_usb_uart) {
	461	pr_err("%s: usb-uart not available on %s\n",
	462	__func__, match->compatible);
	463	return -ENOTSUPP;
	464	}
	465
	466	grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	467	if (IS_ERR(grf)) {
	468	pr_err("%s: Missing rockchip,grf property, %lu\n",
	469	__func__, PTR_ERR(grf));
	470	return PTR_ERR(grf);
	471	}
	472
	473	ret = data->init_usb_uart(grf);
	474	if (ret) {
	475	pr_err("%s: could not init usb_uart, %d\n", __func__, ret);
	476	enable_usb_uart = 0;
	477	return ret;
	478	}
	479
	480	return 0;
	481	}
	482	early_initcall(rockchip_init_usb_uart);
	483
	484	static int __init rockchip_usb_uart(char *buf)
	485	{
	486	enable_usb_uart = true;
	487	return 0;
	488	}
	489	early_param("rockchip.usb_uart", rockchip_usb_uart);
	490	#endif
	491
64d11406 YL	492	MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
	493	MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
	494	MODULE_LICENSE("GPL v2");