[deliverable/linux.git] / drivers / phy / phy-ti-pipe3.c

/*
 * phy-ti-pipe3 - PIPE3 PHY driver.
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * Author: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/phy/phy.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
#include <linux/phy/omap_control_phy.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>

#define	PLL_STATUS		0x00000004
#define	PLL_GO			0x00000008
#define	PLL_CONFIGURATION1	0x0000000C
#define	PLL_CONFIGURATION2	0x00000010
#define	PLL_CONFIGURATION3	0x00000014
#define	PLL_CONFIGURATION4	0x00000020

#define	PLL_REGM_MASK		0x001FFE00
#define	PLL_REGM_SHIFT		0x9
#define	PLL_REGM_F_MASK		0x0003FFFF
#define	PLL_REGM_F_SHIFT	0x0
#define	PLL_REGN_MASK		0x000001FE
#define	PLL_REGN_SHIFT		0x1
#define	PLL_SELFREQDCO_MASK	0x0000000E
#define	PLL_SELFREQDCO_SHIFT	0x1
#define	PLL_SD_MASK		0x0003FC00
#define	PLL_SD_SHIFT		10
#define	SET_PLL_GO		0x1
#define PLL_LDOPWDN		BIT(15)
#define PLL_TICOPWDN		BIT(16)
#define	PLL_LOCK		0x2
#define	PLL_IDLE		0x1

/*
 * This is an Empirical value that works, need to confirm the actual
 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 */
#define PLL_IDLE_TIME	100	/* in milliseconds */
#define PLL_LOCK_TIME	100	/* in milliseconds */

struct pipe3_dpll_params {
	u16	m;
	u8	n;
	u8	freq:3;
	u8	sd;
	u32	mf;
};

struct pipe3_dpll_map {
	unsigned long rate;
	struct pipe3_dpll_params params;
};

struct ti_pipe3 {
	void __iomem		*pll_ctrl_base;
	struct device		*dev;
	struct device		*control_dev;
	struct clk		*wkupclk;
	struct clk		*sys_clk;
	struct clk		*refclk;
	struct clk		*div_clk;
	struct pipe3_dpll_map	*dpll_map;
	bool			enabled;
	spinlock_t		lock;	/* serialize clock enable/disable */
	/* the below flag is needed specifically for SATA */
	bool			refclk_enabled;
};

static struct pipe3_dpll_map dpll_map_usb[] = {
	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
	{ },					/* Terminator */
};

static struct pipe3_dpll_map dpll_map_sata[] = {
	{12000000, {1000, 7, 4, 6, 0} },	/* 12 MHz */
	{16800000, {714, 7, 4, 6, 0} },		/* 16.8 MHz */
	{19200000, {625, 7, 4, 6, 0} },		/* 19.2 MHz */
	{20000000, {600, 7, 4, 6, 0} },		/* 20 MHz */
	{26000000, {461, 7, 4, 6, 0} },		/* 26 MHz */
	{38400000, {312, 7, 4, 6, 0} },		/* 38.4 MHz */
	{ },					/* Terminator */
};

static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
{
	return __raw_readl(addr + offset);
}

static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	u32 data)
{
	__raw_writel(data, addr + offset);
}

static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
	unsigned long rate;
	struct pipe3_dpll_map *dpll_map = phy->dpll_map;

	rate = clk_get_rate(phy->sys_clk);

	for (; dpll_map->rate; dpll_map++) {
		if (rate == dpll_map->rate)
			return &dpll_map->params;
	}

	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);

	return NULL;
}

static int ti_pipe3_power_off(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 0);

	return 0;
}

static int ti_pipe3_power_on(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);

	omap_control_phy_power(phy->control_dev, 1);

	return 0;
}

static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
	u32		val;
	unsigned long	timeout;

	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if (val & PLL_LOCK)
			return 0;
	} while (!time_after(jiffies, timeout));

	dev_err(phy->dev, "DPLL failed to lock\n");
	return -EBUSY;
}

static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
	u32			val;
	struct pipe3_dpll_params *dpll_params;

	dpll_params = ti_pipe3_get_dpll_params(phy);
	if (!dpll_params)
		return -EINVAL;

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGN_MASK;
	val |= dpll_params->n << PLL_REGN_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val &= ~PLL_SELFREQDCO_MASK;
	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
	val &= ~PLL_REGM_MASK;
	val |= dpll_params->m << PLL_REGM_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
	val &= ~PLL_REGM_F_MASK;
	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);

	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
	val &= ~PLL_SD_MASK;
	val |= dpll_params->sd << PLL_SD_SHIFT;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);

	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);

	return ti_pipe3_dpll_wait_lock(phy);
}

static int ti_pipe3_init(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	int ret = 0;

	/*
	 * Set pcie_pcs register to 0x96 for proper functioning of phy
	 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
	 * 18-1804.
	 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
		omap_control_pcie_pcs(phy->control_dev, 0x96);
		return 0;
	}

	/* Bring it out of IDLE if it is IDLE */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	if (val & PLL_IDLE) {
		val &= ~PLL_IDLE;
		ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
		ret = ti_pipe3_dpll_wait_lock(phy);
	}

	/* Program the DPLL only if not locked */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	if (!(val & PLL_LOCK))
		if (ti_pipe3_dpll_program(phy))
			return -EINVAL;

	return ret;
}

static int ti_pipe3_exit(struct phy *x)
{
	struct ti_pipe3 *phy = phy_get_drvdata(x);
	u32 val;
	unsigned long timeout;

	/* SATA DPLL can't be powered down due to Errata i783 and PCIe
	 * does not have internal DPLL
	 */
	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") ||
	    of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
		return 0;

	/* Put DPLL in IDLE mode */
	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	val |= PLL_IDLE;
	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);

	/* wait for LDO and Oscillator to power down */
	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	do {
		cpu_relax();
		val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
			break;
	} while (!time_after(jiffies, timeout));

	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
		dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
			val);
		return -EBUSY;
	}

	return 0;
}
static struct phy_ops ops = {
	.init		= ti_pipe3_init,
	.exit		= ti_pipe3_exit,
	.power_on	= ti_pipe3_power_on,
	.power_off	= ti_pipe3_power_off,
	.owner		= THIS_MODULE,
};

#ifdef CONFIG_OF
static const struct of_device_id ti_pipe3_id_table[];
#endif

static int ti_pipe3_probe(struct platform_device *pdev)
{
	struct ti_pipe3 *phy;
	struct phy *generic_phy;
	struct phy_provider *phy_provider;
	struct resource *res;
	struct device_node *node = pdev->dev.of_node;
	struct device_node *control_node;
	struct platform_device *control_pdev;
	const struct of_device_id *match;
	struct clk *clk;

	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
	if (!phy)
		return -ENOMEM;

	phy->dev		= &pdev->dev;
	spin_lock_init(&phy->lock);

	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
		match = of_match_device(of_match_ptr(ti_pipe3_id_table),
					&pdev->dev);
		if (!match)
			return -EINVAL;

		phy->dpll_map = (struct pipe3_dpll_map *)match->data;
		if (!phy->dpll_map) {
			dev_err(&pdev->dev, "no DPLL data\n");
			return -EINVAL;
		}

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						   "pll_ctrl");
		phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
		if (IS_ERR(phy->pll_ctrl_base))
			return PTR_ERR(phy->pll_ctrl_base);

		phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
		if (IS_ERR(phy->sys_clk)) {
			dev_err(&pdev->dev, "unable to get sysclk\n");
			return -EINVAL;
		}
	}

	phy->refclk = devm_clk_get(phy->dev, "refclk");
	if (IS_ERR(phy->refclk)) {
		dev_err(&pdev->dev, "unable to get refclk\n");
		/* older DTBs have missing refclk in SATA PHY
		 * so don't bail out in case of SATA PHY.
		 */
		if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
			return PTR_ERR(phy->refclk);
	}

	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
		phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
		if (IS_ERR(phy->wkupclk)) {
			dev_err(&pdev->dev, "unable to get wkupclk\n");
			return PTR_ERR(phy->wkupclk);
		}
	} else {
		phy->wkupclk = ERR_PTR(-ENODEV);
	}

	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {

		clk = devm_clk_get(phy->dev, "dpll_ref");
		if (IS_ERR(clk)) {
			dev_err(&pdev->dev, "unable to get dpll ref clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 1500000000);

		clk = devm_clk_get(phy->dev, "dpll_ref_m2");
		if (IS_ERR(clk)) {
			dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 100000000);

		clk = devm_clk_get(phy->dev, "phy-div");
		if (IS_ERR(clk)) {
			dev_err(&pdev->dev, "unable to get phy-div clk\n");
			return PTR_ERR(clk);
		}
		clk_set_rate(clk, 100000000);

		phy->div_clk = devm_clk_get(phy->dev, "div-clk");
		if (IS_ERR(phy->div_clk)) {
			dev_err(&pdev->dev, "unable to get div-clk\n");
			return PTR_ERR(phy->div_clk);
		}
	} else {
		phy->div_clk = ERR_PTR(-ENODEV);
	}

	control_node = of_parse_phandle(node, "ctrl-module", 0);
	if (!control_node) {
		dev_err(&pdev->dev, "Failed to get control device phandle\n");
		return -EINVAL;
	}

	control_pdev = of_find_device_by_node(control_node);
	if (!control_pdev) {
		dev_err(&pdev->dev, "Failed to get control device\n");
		return -EINVAL;
	}

	phy->control_dev = &control_pdev->dev;

	omap_control_phy_power(phy->control_dev, 0);

	platform_set_drvdata(pdev, phy);
	pm_runtime_enable(phy->dev);

	generic_phy = devm_phy_create(phy->dev, NULL, &ops);
	if (IS_ERR(generic_phy))
		return PTR_ERR(generic_phy);

	phy_set_drvdata(generic_phy, phy);
	phy_provider = devm_of_phy_provider_register(phy->dev,
			of_phy_simple_xlate);
	if (IS_ERR(phy_provider))
		return PTR_ERR(phy_provider);

	pm_runtime_get(&pdev->dev);

	return 0;
}

static int ti_pipe3_remove(struct platform_device *pdev)
{
	if (!pm_runtime_suspended(&pdev->dev))
		pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return 0;
}

#ifdef CONFIG_PM
static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
{
	if (!IS_ERR(phy->refclk) && !phy->refclk_enabled) {
		int ret;

		ret = clk_prepare_enable(phy->refclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
			return ret;
		}
		phy->refclk_enabled = true;
	}

	return 0;
}

static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy)
{
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);

	phy->refclk_enabled = false;
}

static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
{
	int ret = 0;
	unsigned long flags;

	spin_lock_irqsave(&phy->lock, flags);
	if (phy->enabled)
		goto err1;

	ret = ti_pipe3_enable_refclk(phy);
	if (ret)
		goto err1;

	if (!IS_ERR(phy->wkupclk)) {
		ret = clk_prepare_enable(phy->wkupclk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
			goto err2;
		}
	}

	if (!IS_ERR(phy->div_clk)) {
		ret = clk_prepare_enable(phy->div_clk);
		if (ret) {
			dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
			goto err3;
		}
	}

	phy->enabled = true;
	spin_unlock_irqrestore(&phy->lock, flags);
	return 0;

err3:
	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);

err2:
	if (!IS_ERR(phy->refclk))
		clk_disable_unprepare(phy->refclk);

	ti_pipe3_disable_refclk(phy);
err1:
	spin_unlock_irqrestore(&phy->lock, flags);
	return ret;
}

static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
{
	unsigned long flags;

	spin_lock_irqsave(&phy->lock, flags);
	if (!phy->enabled) {
		spin_unlock_irqrestore(&phy->lock, flags);
		return;
	}

	if (!IS_ERR(phy->wkupclk))
		clk_disable_unprepare(phy->wkupclk);
	/* Don't disable refclk for SATA PHY due to Errata i783 */
	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
		ti_pipe3_disable_refclk(phy);
	if (!IS_ERR(phy->div_clk))
		clk_disable_unprepare(phy->div_clk);
	phy->enabled = false;
	spin_unlock_irqrestore(&phy->lock, flags);
}

static int ti_pipe3_runtime_suspend(struct device *dev)
{
	struct ti_pipe3	*phy = dev_get_drvdata(dev);

	ti_pipe3_disable_clocks(phy);
	return 0;
}

static int ti_pipe3_runtime_resume(struct device *dev)
{
	struct ti_pipe3	*phy = dev_get_drvdata(dev);
	int ret = 0;

	ret = ti_pipe3_enable_clocks(phy);
	return ret;
}

static int ti_pipe3_suspend(struct device *dev)
{
	struct ti_pipe3	*phy = dev_get_drvdata(dev);

	ti_pipe3_disable_clocks(phy);
	return 0;
}

static int ti_pipe3_resume(struct device *dev)
{
	struct ti_pipe3	*phy = dev_get_drvdata(dev);
	int ret;

	ret = ti_pipe3_enable_clocks(phy);
	if (ret)
		return ret;

	pm_runtime_disable(dev);
	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	return 0;
}
#endif

static const struct dev_pm_ops ti_pipe3_pm_ops = {
	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
			   ti_pipe3_runtime_resume, NULL)
	SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume)
};

#ifdef CONFIG_OF
static const struct of_device_id ti_pipe3_id_table[] = {
	{
		.compatible = "ti,phy-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,omap-usb3",
		.data = dpll_map_usb,
	},
	{
		.compatible = "ti,phy-pipe3-sata",
		.data = dpll_map_sata,
	},
	{
		.compatible = "ti,phy-pipe3-pcie",
	},
	{}
};
MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
#endif

static struct platform_driver ti_pipe3_driver = {
	.probe		= ti_pipe3_probe,
	.remove		= ti_pipe3_remove,
	.driver		= {
		.name	= "ti-pipe3",
		.pm	= &ti_pipe3_pm_ops,
		.of_match_table = of_match_ptr(ti_pipe3_id_table),
	},
};

module_platform_driver(ti_pipe3_driver);

MODULE_ALIAS("platform:ti_pipe3");
MODULE_AUTHOR("Texas Instruments Inc.");
MODULE_DESCRIPTION("TI PIPE3 phy driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
57f6ce07	1	/*
a70143bb	2	* phy-ti-pipe3 - PIPE3 PHY driver.
57f6ce07 KVA	3	*
	4	* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	* Author: Kishon Vijay Abraham I <kishon@ti.com>
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/module.h>
	20	#include <linux/platform_device.h>
	21	#include <linux/slab.h>
a70143bb	22	#include <linux/phy/phy.h>
57f6ce07 KVA	23	#include <linux/of.h>
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
a70143bb	26	#include <linux/io.h>
57f6ce07 KVA	27	#include <linux/pm_runtime.h>
57f6ce07 KVA	28	#include <linux/delay.h>
14da699b	29	#include <linux/phy/omap_control_phy.h>
918ee0d2	30	#include <linux/of_platform.h>
6e738432	31	#include <linux/spinlock.h>
57f6ce07	32
57f6ce07 KVA	33	#define PLL_STATUS 0x00000004
	34	#define PLL_GO 0x00000008
	35	#define PLL_CONFIGURATION1 0x0000000C
	36	#define PLL_CONFIGURATION2 0x00000010
	37	#define PLL_CONFIGURATION3 0x00000014
	38	#define PLL_CONFIGURATION4 0x00000020
	39
	40	#define PLL_REGM_MASK 0x001FFE00
	41	#define PLL_REGM_SHIFT 0x9
	42	#define PLL_REGM_F_MASK 0x0003FFFF
	43	#define PLL_REGM_F_SHIFT 0x0
	44	#define PLL_REGN_MASK 0x000001FE
	45	#define PLL_REGN_SHIFT 0x1
	46	#define PLL_SELFREQDCO_MASK 0x0000000E
	47	#define PLL_SELFREQDCO_SHIFT 0x1
	48	#define PLL_SD_MASK 0x0003FC00
1562864f	49	#define PLL_SD_SHIFT 10
57f6ce07	50	#define SET_PLL_GO 0x1
629138db RQ	51	#define PLL_LDOPWDN BIT(15)
629138db RQ	52	#define PLL_TICOPWDN BIT(16)
57f6ce07 KVA	53	#define PLL_LOCK 0x2
	54	#define PLL_IDLE 0x1
	55
	56	/*
	57	* This is an Empirical value that works, need to confirm the actual
a70143bb KVA	58	* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
a70143bb KVA	59	* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
57f6ce07	60	*/
629138db RQ	61	#define PLL_IDLE_TIME 100 /* in milliseconds */
629138db RQ	62	#define PLL_LOCK_TIME 100 /* in milliseconds */
57f6ce07	63
a70143bb KVA	64	struct pipe3_dpll_params {
	65	u16 m;
	66	u8 n;
	67	u8 freq:3;
	68	u8 sd;
	69	u32 mf;
	70	};
	71
61f54674 RQ	72	struct pipe3_dpll_map {
	73	unsigned long rate;
	74	struct pipe3_dpll_params params;
	75	};
	76
a70143bb KVA	77	struct ti_pipe3 {
	78	void __iomem *pll_ctrl_base;
	79	struct device *dev;
	80	struct device *control_dev;
	81	struct clk *wkupclk;
	82	struct clk *sys_clk;
1562864f	83	struct clk *refclk;
99bbd48c	84	struct clk *div_clk;
61f54674	85	struct pipe3_dpll_map *dpll_map;
6e738432 RQ	86	bool enabled;
6e738432 RQ	87	spinlock_t lock; /* serialize clock enable/disable */
7f33912d RQ	88	/* the below flag is needed specifically for SATA */
7f33912d RQ	89	bool refclk_enabled;
a70143bb KVA	90	};
a70143bb KVA	91
61f54674	92	static struct pipe3_dpll_map dpll_map_usb[] = {
519c6013 RQ	93	{12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
	94	{16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
	95	{19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
	96	{20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
	97	{26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
	98	{38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
61f54674 RQ	99	{ }, /* Terminator */
	100	};
	101
	102	static struct pipe3_dpll_map dpll_map_sata[] = {
	103	{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
	104	{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
	105	{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
	106	{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
	107	{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
	108	{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
	109	{ }, /* Terminator */
57f6ce07 KVA	110	};
57f6ce07 KVA	111
a70143bb KVA	112	static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
	113	{
	114	return __raw_readl(addr + offset);
	115	}
	116
	117	static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
	118	u32 data)
	119	{
	120	__raw_writel(data, addr + offset);
	121	}
	122
61f54674	123	static struct pipe3_dpll_params ti_pipe3_get_dpll_params(struct ti_pipe3 phy)
519c6013	124	{
61f54674 RQ	125	unsigned long rate;
61f54674 RQ	126	struct pipe3_dpll_map *dpll_map = phy->dpll_map;
519c6013	127
61f54674 RQ	128	rate = clk_get_rate(phy->sys_clk);
	129
	130	for (; dpll_map->rate; dpll_map++) {
	131	if (rate == dpll_map->rate)
	132	return &dpll_map->params;
519c6013 RQ	133	}
519c6013 RQ	134
61f54674 RQ	135	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
61f54674 RQ	136
1b97be8c	137	return NULL;
519c6013 RQ	138	}
519c6013 RQ	139
a70143bb KVA	140	static int ti_pipe3_power_off(struct phy *x)
	141	{
	142	struct ti_pipe3 *phy = phy_get_drvdata(x);
a70143bb	143
14da699b	144	omap_control_phy_power(phy->control_dev, 0);
a70143bb KVA	145
	146	return 0;
	147	}
	148
	149	static int ti_pipe3_power_on(struct phy *x)
57f6ce07	150	{
a70143bb	151	struct ti_pipe3 *phy = phy_get_drvdata(x);
57f6ce07	152
629138db	153	omap_control_phy_power(phy->control_dev, 1);
57f6ce07 KVA	154
	155	return 0;
	156	}
	157
629138db	158	static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
57f6ce07 KVA	159	{
	160	u32 val;
	161	unsigned long timeout;
	162
629138db	163	timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
57f6ce07	164	do {
629138db	165	cpu_relax();
a70143bb	166	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
57f6ce07	167	if (val & PLL_LOCK)
a5e5d3c0	168	return 0;
629138db RQ	169	} while (!time_after(jiffies, timeout));
629138db RQ	170
a5e5d3c0 AL	171	dev_err(phy->dev, "DPLL failed to lock\n");
a5e5d3c0 AL	172	return -EBUSY;
57f6ce07 KVA	173	}
57f6ce07 KVA	174
629138db	175	static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
57f6ce07 KVA	176	{
57f6ce07 KVA	177	u32 val;
a70143bb	178	struct pipe3_dpll_params *dpll_params;
57f6ce07	179
61f54674 RQ	180	dpll_params = ti_pipe3_get_dpll_params(phy);
61f54674 RQ	181	if (!dpll_params)
57f6ce07	182	return -EINVAL;
57f6ce07	183
a70143bb	184	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	185	val &= ~PLL_REGN_MASK;
519c6013	186	val \|= dpll_params->n << PLL_REGN_SHIFT;
a70143bb	187	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	188
a70143bb	189	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
57f6ce07	190	val &= ~PLL_SELFREQDCO_MASK;
519c6013	191	val \|= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
a70143bb	192	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
57f6ce07	193
a70143bb	194	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
57f6ce07	195	val &= ~PLL_REGM_MASK;
519c6013	196	val \|= dpll_params->m << PLL_REGM_SHIFT;
a70143bb	197	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
57f6ce07	198
a70143bb	199	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
57f6ce07	200	val &= ~PLL_REGM_F_MASK;
519c6013	201	val \|= dpll_params->mf << PLL_REGM_F_SHIFT;
a70143bb	202	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
57f6ce07	203
a70143bb	204	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
57f6ce07	205	val &= ~PLL_SD_MASK;
519c6013	206	val \|= dpll_params->sd << PLL_SD_SHIFT;
a70143bb	207	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
57f6ce07	208
629138db	209	ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
57f6ce07	210
629138db	211	return ti_pipe3_dpll_wait_lock(phy);
57f6ce07 KVA	212	}
57f6ce07 KVA	213
a70143bb	214	static int ti_pipe3_init(struct phy *x)
57f6ce07	215	{
a70143bb	216	struct ti_pipe3 *phy = phy_get_drvdata(x);
629138db RQ	217	u32 val;
629138db RQ	218	int ret = 0;
519c6013	219
0bc09f9c V	220	/*
	221	* Set pcie_pcs register to 0x96 for proper functioning of phy
	222	* as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
	223	* 18-1804.
	224	*/
f0e2cf7b	225	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
0bc09f9c	226	omap_control_pcie_pcs(phy->control_dev, 0x96);
99bbd48c	227	return 0;
f0e2cf7b	228	}
99bbd48c	229
629138db RQ	230	/* Bring it out of IDLE if it is IDLE */
	231	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	232	if (val & PLL_IDLE) {
	233	val &= ~PLL_IDLE;
	234	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	235	ret = ti_pipe3_dpll_wait_lock(phy);
	236	}
57f6ce07	237
629138db RQ	238	/* Program the DPLL only if not locked */
	239	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	240	if (!(val & PLL_LOCK))
	241	if (ti_pipe3_dpll_program(phy))
	242	return -EINVAL;
57f6ce07	243
629138db	244	return ret;
57f6ce07 KVA	245	}
57f6ce07 KVA	246
629138db RQ	247	static int ti_pipe3_exit(struct phy *x)
	248	{
	249	struct ti_pipe3 *phy = phy_get_drvdata(x);
	250	u32 val;
	251	unsigned long timeout;
	252
99bbd48c KVA	253	/* SATA DPLL can't be powered down due to Errata i783 and PCIe
	254	* does not have internal DPLL
	255	*/
	256	if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") \|\|
	257	of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie"))
56042e4e RQ	258	return 0;
56042e4e RQ	259
629138db RQ	260	/* Put DPLL in IDLE mode */
	261	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
	262	val \|= PLL_IDLE;
	263	ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
	264
	265	/* wait for LDO and Oscillator to power down */
	266	timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
	267	do {
	268	cpu_relax();
	269	val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
	270	if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
	271	break;
	272	} while (!time_after(jiffies, timeout));
	273
	274	if (!(val & PLL_TICOPWDN) \|\| !(val & PLL_LDOPWDN)) {
	275	dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
	276	val);
	277	return -EBUSY;
	278	}
	279
	280	return 0;
	281	}
a70143bb KVA	282	static struct phy_ops ops = {
a70143bb KVA	283	.init = ti_pipe3_init,
629138db	284	.exit = ti_pipe3_exit,
a70143bb KVA	285	.power_on = ti_pipe3_power_on,
	286	.power_off = ti_pipe3_power_off,
	287	.owner = THIS_MODULE,
	288	};
	289
61f54674 RQ	290	#ifdef CONFIG_OF
	291	static const struct of_device_id ti_pipe3_id_table[];
	292	#endif
	293
a70143bb	294	static int ti_pipe3_probe(struct platform_device *pdev)
57f6ce07	295	{
a70143bb KVA	296	struct ti_pipe3 *phy;
	297	struct phy *generic_phy;
	298	struct phy_provider *phy_provider;
918ee0d2 RQ	299	struct resource *res;
	300	struct device_node *node = pdev->dev.of_node;
	301	struct device_node *control_node;
	302	struct platform_device *control_pdev;
61f54674	303	const struct of_device_id *match;
99bbd48c	304	struct clk *clk;
57f6ce07 KVA	305
57f6ce07 KVA	306	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
3a4cfcbb	307	if (!phy)
57f6ce07	308	return -ENOMEM;
3a4cfcbb	309
99bbd48c	310	phy->dev = &pdev->dev;
6e738432	311	spin_lock_init(&phy->lock);
57f6ce07	312
99bbd48c KVA	313	if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
	314	match = of_match_device(of_match_ptr(ti_pipe3_id_table),
	315	&pdev->dev);
	316	if (!match)
	317	return -EINVAL;
61f54674	318
99bbd48c KVA	319	phy->dpll_map = (struct pipe3_dpll_map *)match->data;
	320	if (!phy->dpll_map) {
	321	dev_err(&pdev->dev, "no DPLL data\n");
	322	return -EINVAL;
	323	}
57f6ce07	324
99bbd48c KVA	325	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
	326	"pll_ctrl");
	327	phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
	328	if (IS_ERR(phy->pll_ctrl_base))
	329	return PTR_ERR(phy->pll_ctrl_base);
57f6ce07	330
99bbd48c KVA	331	phy->sys_clk = devm_clk_get(phy->dev, "sysclk");
	332	if (IS_ERR(phy->sys_clk)) {
	333	dev_err(&pdev->dev, "unable to get sysclk\n");
	334	return -EINVAL;
	335	}
	336	}
9c7f0443	337
7f33912d RQ	338	phy->refclk = devm_clk_get(phy->dev, "refclk");
	339	if (IS_ERR(phy->refclk)) {
	340	dev_err(&pdev->dev, "unable to get refclk\n");
	341	/* older DTBs have missing refclk in SATA PHY
	342	* so don't bail out in case of SATA PHY.
	343	*/
	344	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
	345	return PTR_ERR(phy->refclk);
	346	}
	347
99bbd48c	348	if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
9c7f0443 RQ	349	phy->wkupclk = devm_clk_get(phy->dev, "wkupclk");
	350	if (IS_ERR(phy->wkupclk)) {
	351	dev_err(&pdev->dev, "unable to get wkupclk\n");
	352	return PTR_ERR(phy->wkupclk);
	353	}
9c7f0443 RQ	354	} else {
9c7f0443 RQ	355	phy->wkupclk = ERR_PTR(-ENODEV);
57f6ce07	356	}
57f6ce07	357
99bbd48c	358	if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
99bbd48c KVA	359
	360	clk = devm_clk_get(phy->dev, "dpll_ref");
	361	if (IS_ERR(clk)) {
	362	dev_err(&pdev->dev, "unable to get dpll ref clk\n");
	363	return PTR_ERR(clk);
	364	}
	365	clk_set_rate(clk, 1500000000);
	366
	367	clk = devm_clk_get(phy->dev, "dpll_ref_m2");
	368	if (IS_ERR(clk)) {
	369	dev_err(&pdev->dev, "unable to get dpll ref m2 clk\n");
	370	return PTR_ERR(clk);
	371	}
	372	clk_set_rate(clk, 100000000);
	373
	374	clk = devm_clk_get(phy->dev, "phy-div");
	375	if (IS_ERR(clk)) {
	376	dev_err(&pdev->dev, "unable to get phy-div clk\n");
	377	return PTR_ERR(clk);
	378	}
	379	clk_set_rate(clk, 100000000);
	380
	381	phy->div_clk = devm_clk_get(phy->dev, "div-clk");
	382	if (IS_ERR(phy->div_clk)) {
	383	dev_err(&pdev->dev, "unable to get div-clk\n");
	384	return PTR_ERR(phy->div_clk);
	385	}
	386	} else {
	387	phy->div_clk = ERR_PTR(-ENODEV);
57f6ce07 KVA	388	}
57f6ce07 KVA	389
918ee0d2 RQ	390	control_node = of_parse_phandle(node, "ctrl-module", 0);
	391	if (!control_node) {
	392	dev_err(&pdev->dev, "Failed to get control device phandle\n");
	393	return -EINVAL;
57f6ce07	394	}
a70143bb	395
918ee0d2 RQ	396	control_pdev = of_find_device_by_node(control_node);
	397	if (!control_pdev) {
	398	dev_err(&pdev->dev, "Failed to get control device\n");
	399	return -EINVAL;
	400	}
	401
	402	phy->control_dev = &control_pdev->dev;
57f6ce07	403
14da699b	404	omap_control_phy_power(phy->control_dev, 0);
57f6ce07 KVA	405
57f6ce07 KVA	406	platform_set_drvdata(pdev, phy);
57f6ce07	407	pm_runtime_enable(phy->dev);
a70143bb	408
dbc98635	409	generic_phy = devm_phy_create(phy->dev, NULL, &ops);
a70143bb KVA	410	if (IS_ERR(generic_phy))
	411	return PTR_ERR(generic_phy);
	412
	413	phy_set_drvdata(generic_phy, phy);
	414	phy_provider = devm_of_phy_provider_register(phy->dev,
	415	of_phy_simple_xlate);
	416	if (IS_ERR(phy_provider))
	417	return PTR_ERR(phy_provider);
	418
57f6ce07 KVA	419	pm_runtime_get(&pdev->dev);
	420
	421	return 0;
	422	}
	423
a70143bb	424	static int ti_pipe3_remove(struct platform_device *pdev)
57f6ce07	425	{
57f6ce07 KVA	426	if (!pm_runtime_suspended(&pdev->dev))
	427	pm_runtime_put(&pdev->dev);
	428	pm_runtime_disable(&pdev->dev);
	429
	430	return 0;
	431	}
	432
7ba37053	433	#ifdef CONFIG_PM
7f33912d RQ	434	static int ti_pipe3_enable_refclk(struct ti_pipe3 *phy)
	435	{
	436	if (!IS_ERR(phy->refclk) && !phy->refclk_enabled) {
	437	int ret;
	438
	439	ret = clk_prepare_enable(phy->refclk);
	440	if (ret) {
	441	dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
	442	return ret;
	443	}
	444	phy->refclk_enabled = true;
	445	}
	446
	447	return 0;
	448	}
	449
	450	static void ti_pipe3_disable_refclk(struct ti_pipe3 *phy)
	451	{
	452	if (!IS_ERR(phy->refclk))
	453	clk_disable_unprepare(phy->refclk);
	454
	455	phy->refclk_enabled = false;
	456	}
57f6ce07	457
6e738432	458	static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
57f6ce07	459	{
6e738432 RQ	460	int ret = 0;
6e738432 RQ	461	unsigned long flags;
57f6ce07	462
6e738432 RQ	463	spin_lock_irqsave(&phy->lock, flags);
	464	if (phy->enabled)
	465	goto err1;
57f6ce07	466
7f33912d RQ	467	ret = ti_pipe3_enable_refclk(phy);
	468	if (ret)
	469	goto err1;
57f6ce07	470
1562864f RQ	471	if (!IS_ERR(phy->wkupclk)) {
	472	ret = clk_prepare_enable(phy->wkupclk);
	473	if (ret) {
	474	dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
	475	goto err2;
	476	}
57f6ce07 KVA	477	}
57f6ce07 KVA	478
99bbd48c KVA	479	if (!IS_ERR(phy->div_clk)) {
	480	ret = clk_prepare_enable(phy->div_clk);
	481	if (ret) {
	482	dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
	483	goto err3;
	484	}
	485	}
6e738432 RQ	486
	487	phy->enabled = true;
	488	spin_unlock_irqrestore(&phy->lock, flags);
57f6ce07 KVA	489	return 0;
57f6ce07 KVA	490
99bbd48c KVA	491	err3:
	492	if (!IS_ERR(phy->wkupclk))
	493	clk_disable_unprepare(phy->wkupclk);
	494
57f6ce07	495	err2:
1562864f RQ	496	if (!IS_ERR(phy->refclk))
1562864f RQ	497	clk_disable_unprepare(phy->refclk);
57f6ce07	498
7f33912d	499	ti_pipe3_disable_refclk(phy);
57f6ce07	500	err1:
6e738432 RQ	501	spin_unlock_irqrestore(&phy->lock, flags);
	502	return ret;
	503	}
	504
	505	static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
	506	{
	507	unsigned long flags;
	508
	509	spin_lock_irqsave(&phy->lock, flags);
	510	if (!phy->enabled) {
	511	spin_unlock_irqrestore(&phy->lock, flags);
	512	return;
	513	}
	514
	515	if (!IS_ERR(phy->wkupclk))
	516	clk_disable_unprepare(phy->wkupclk);
7f33912d RQ	517	/* Don't disable refclk for SATA PHY due to Errata i783 */
	518	if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata"))
	519	ti_pipe3_disable_refclk(phy);
6e738432 RQ	520	if (!IS_ERR(phy->div_clk))
	521	clk_disable_unprepare(phy->div_clk);
	522	phy->enabled = false;
	523	spin_unlock_irqrestore(&phy->lock, flags);
	524	}
	525
	526	static int ti_pipe3_runtime_suspend(struct device *dev)
	527	{
	528	struct ti_pipe3 *phy = dev_get_drvdata(dev);
	529
	530	ti_pipe3_disable_clocks(phy);
	531	return 0;
	532	}
	533
	534	static int ti_pipe3_runtime_resume(struct device *dev)
	535	{
	536	struct ti_pipe3 *phy = dev_get_drvdata(dev);
	537	int ret = 0;
	538
	539	ret = ti_pipe3_enable_clocks(phy);
57f6ce07 KVA	540	return ret;
	541	}
	542
6e738432 RQ	543	static int ti_pipe3_suspend(struct device *dev)
	544	{
	545	struct ti_pipe3 *phy = dev_get_drvdata(dev);
	546
	547	ti_pipe3_disable_clocks(phy);
	548	return 0;
	549	}
	550
	551	static int ti_pipe3_resume(struct device *dev)
	552	{
	553	struct ti_pipe3 *phy = dev_get_drvdata(dev);
	554	int ret;
	555
	556	ret = ti_pipe3_enable_clocks(phy);
	557	if (ret)
	558	return ret;
	559
	560	pm_runtime_disable(dev);
	561	pm_runtime_set_active(dev);
	562	pm_runtime_enable(dev);
	563	return 0;
	564	}
	565	#endif
	566
a70143bb KVA	567	static const struct dev_pm_ops ti_pipe3_pm_ops = {
	568	SET_RUNTIME_PM_OPS(ti_pipe3_runtime_suspend,
	569	ti_pipe3_runtime_resume, NULL)
6e738432	570	SET_SYSTEM_SLEEP_PM_OPS(ti_pipe3_suspend, ti_pipe3_resume)
57f6ce07 KVA	571	};
57f6ce07 KVA	572
57f6ce07	573	#ifdef CONFIG_OF
a70143bb	574	static const struct of_device_id ti_pipe3_id_table[] = {
61f54674 RQ	575	{
	576	.compatible = "ti,phy-usb3",
	577	.data = dpll_map_usb,
	578	},
	579	{
	580	.compatible = "ti,omap-usb3",
	581	.data = dpll_map_usb,
	582	},
	583	{
	584	.compatible = "ti,phy-pipe3-sata",
	585	.data = dpll_map_sata,
	586	},
99bbd48c KVA	587	{
	588	.compatible = "ti,phy-pipe3-pcie",
	589	},
57f6ce07 KVA	590	{}
57f6ce07 KVA	591	};
a70143bb	592	MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
57f6ce07 KVA	593	#endif
57f6ce07 KVA	594
a70143bb KVA	595	static struct platform_driver ti_pipe3_driver = {
	596	.probe = ti_pipe3_probe,
	597	.remove = ti_pipe3_remove,
57f6ce07	598	.driver = {
a70143bb	599	.name = "ti-pipe3",
6e738432	600	.pm = &ti_pipe3_pm_ops,
a70143bb	601	.of_match_table = of_match_ptr(ti_pipe3_id_table),
57f6ce07 KVA	602	},
	603	};
	604
a70143bb	605	module_platform_driver(ti_pipe3_driver);
57f6ce07	606
dd64ad38	607	MODULE_ALIAS("platform:ti_pipe3");
57f6ce07	608	MODULE_AUTHOR("Texas Instruments Inc.");
a70143bb	609	MODULE_DESCRIPTION("TI PIPE3 phy driver");
57f6ce07	610	MODULE_LICENSE("GPL v2");