Commit | Line | Data |
---|---|---|
9ebd9616 DB |
1 | /* |
2 | * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller | |
3 | * | |
4 | * Copyright (C) 2004-2007 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * Current status: | |
23 | * - HS USB ULPI mode works. | |
24 | * - 3-pin mode support may be added in future. | |
25 | */ | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/platform_device.h> | |
9ebd9616 DB |
31 | #include <linux/workqueue.h> |
32 | #include <linux/io.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/usb/otg.h> | |
6747caa7 | 35 | #include <linux/phy/phy.h> |
96be39ab | 36 | #include <linux/pm_runtime.h> |
c9721438 | 37 | #include <linux/usb/musb-omap.h> |
92a6e6b3 | 38 | #include <linux/usb/ulpi.h> |
b07682b6 | 39 | #include <linux/i2c/twl.h> |
66760169 JH |
40 | #include <linux/regulator/consumer.h> |
41 | #include <linux/err.h> | |
5a0e3ad6 | 42 | #include <linux/slab.h> |
9ebd9616 DB |
43 | |
44 | /* Register defines */ | |
45 | ||
9ebd9616 | 46 | #define MCPC_CTRL 0x30 |
9ebd9616 DB |
47 | #define MCPC_CTRL_RTSOL (1 << 7) |
48 | #define MCPC_CTRL_EXTSWR (1 << 6) | |
49 | #define MCPC_CTRL_EXTSWC (1 << 5) | |
50 | #define MCPC_CTRL_VOICESW (1 << 4) | |
51 | #define MCPC_CTRL_OUT64K (1 << 3) | |
52 | #define MCPC_CTRL_RTSCTSSW (1 << 2) | |
53 | #define MCPC_CTRL_HS_UART (1 << 0) | |
54 | ||
55 | #define MCPC_IO_CTRL 0x33 | |
9ebd9616 DB |
56 | #define MCPC_IO_CTRL_MICBIASEN (1 << 5) |
57 | #define MCPC_IO_CTRL_CTS_NPU (1 << 4) | |
58 | #define MCPC_IO_CTRL_RXD_PU (1 << 3) | |
59 | #define MCPC_IO_CTRL_TXDTYP (1 << 2) | |
60 | #define MCPC_IO_CTRL_CTSTYP (1 << 1) | |
61 | #define MCPC_IO_CTRL_RTSTYP (1 << 0) | |
62 | ||
63 | #define MCPC_CTRL2 0x36 | |
9ebd9616 DB |
64 | #define MCPC_CTRL2_MCPC_CK_EN (1 << 0) |
65 | ||
66 | #define OTHER_FUNC_CTRL 0x80 | |
9ebd9616 DB |
67 | #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4) |
68 | #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2) | |
69 | ||
70 | #define OTHER_IFC_CTRL 0x83 | |
9ebd9616 DB |
71 | #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6) |
72 | #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5) | |
73 | #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4) | |
74 | #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3) | |
75 | #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2) | |
76 | #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0) | |
77 | ||
78 | #define OTHER_INT_EN_RISE 0x86 | |
9ebd9616 | 79 | #define OTHER_INT_EN_FALL 0x89 |
9ebd9616 DB |
80 | #define OTHER_INT_STS 0x8C |
81 | #define OTHER_INT_LATCH 0x8D | |
82 | #define OTHER_INT_VB_SESS_VLD (1 << 7) | |
83 | #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */ | |
84 | #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */ | |
85 | #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */ | |
86 | #define OTHER_INT_MANU (1 << 1) | |
87 | #define OTHER_INT_ABNORMAL_STRESS (1 << 0) | |
88 | ||
89 | #define ID_STATUS 0x96 | |
90 | #define ID_RES_FLOAT (1 << 4) | |
91 | #define ID_RES_440K (1 << 3) | |
92 | #define ID_RES_200K (1 << 2) | |
93 | #define ID_RES_102K (1 << 1) | |
94 | #define ID_RES_GND (1 << 0) | |
95 | ||
96 | #define POWER_CTRL 0xAC | |
9ebd9616 DB |
97 | #define POWER_CTRL_OTG_ENAB (1 << 5) |
98 | ||
99 | #define OTHER_IFC_CTRL2 0xAF | |
9ebd9616 DB |
100 | #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4) |
101 | #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3) | |
102 | #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2) | |
103 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */ | |
104 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0) | |
105 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0) | |
106 | ||
107 | #define REG_CTRL_EN 0xB2 | |
9ebd9616 DB |
108 | #define REG_CTRL_ERROR 0xB5 |
109 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0) | |
110 | ||
111 | #define OTHER_FUNC_CTRL2 0xB8 | |
9ebd9616 DB |
112 | #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0) |
113 | ||
114 | /* following registers do not have separate _clr and _set registers */ | |
115 | #define VBUS_DEBOUNCE 0xC0 | |
116 | #define ID_DEBOUNCE 0xC1 | |
117 | #define VBAT_TIMER 0xD3 | |
118 | #define PHY_PWR_CTRL 0xFD | |
119 | #define PHY_PWR_PHYPWD (1 << 0) | |
120 | #define PHY_CLK_CTRL 0xFE | |
121 | #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2) | |
122 | #define PHY_CLK_CTRL_CLK32K_EN (1 << 1) | |
123 | #define REQ_PHY_DPLL_CLK (1 << 0) | |
124 | #define PHY_CLK_CTRL_STS 0xFF | |
125 | #define PHY_DPLL_CLK (1 << 0) | |
126 | ||
9d94e16b | 127 | /* In module TWL_MODULE_PM_MASTER */ |
def6f8b9 | 128 | #define STS_HW_CONDITIONS 0x0F |
9ebd9616 | 129 | |
9d94e16b | 130 | /* In module TWL_MODULE_PM_RECEIVER */ |
9ebd9616 DB |
131 | #define VUSB_DEDICATED1 0x7D |
132 | #define VUSB_DEDICATED2 0x7E | |
133 | #define VUSB1V5_DEV_GRP 0x71 | |
134 | #define VUSB1V5_TYPE 0x72 | |
135 | #define VUSB1V5_REMAP 0x73 | |
136 | #define VUSB1V8_DEV_GRP 0x74 | |
137 | #define VUSB1V8_TYPE 0x75 | |
138 | #define VUSB1V8_REMAP 0x76 | |
139 | #define VUSB3V1_DEV_GRP 0x77 | |
140 | #define VUSB3V1_TYPE 0x78 | |
141 | #define VUSB3V1_REMAP 0x79 | |
142 | ||
143 | /* In module TWL4030_MODULE_INTBR */ | |
144 | #define PMBR1 0x0D | |
145 | #define GPIO_USB_4PIN_ULPI_2430C (3 << 0) | |
146 | ||
9ebd9616 | 147 | struct twl4030_usb { |
74d4aa44 | 148 | struct usb_phy phy; |
9ebd9616 DB |
149 | struct device *dev; |
150 | ||
66760169 JH |
151 | /* TWL4030 internal USB regulator supplies */ |
152 | struct regulator *usb1v5; | |
153 | struct regulator *usb1v8; | |
154 | struct regulator *usb3v1; | |
155 | ||
9ebd9616 | 156 | /* for vbus reporting with irqs disabled */ |
dcc35b21 | 157 | struct mutex lock; |
9ebd9616 DB |
158 | |
159 | /* pin configuration */ | |
160 | enum twl4030_usb_mode usb_mode; | |
161 | ||
162 | int irq; | |
c9721438 | 163 | enum omap_musb_vbus_id_status linkstat; |
a87103a6 | 164 | bool vbus_supplied; |
249751f2 GI |
165 | |
166 | struct delayed_work id_workaround_work; | |
9ebd9616 DB |
167 | }; |
168 | ||
169 | /* internal define on top of container_of */ | |
74d4aa44 | 170 | #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy) |
9ebd9616 DB |
171 | |
172 | /*-------------------------------------------------------------------------*/ | |
173 | ||
174 | static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, | |
175 | u8 module, u8 data, u8 address) | |
176 | { | |
177 | u8 check; | |
178 | ||
fc7b92fc B |
179 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
180 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
181 | (check == data)) |
182 | return 0; | |
183 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
184 | 1, module, address, check, data); | |
185 | ||
186 | /* Failed once: Try again */ | |
fc7b92fc B |
187 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
188 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
189 | (check == data)) |
190 | return 0; | |
191 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
192 | 2, module, address, check, data); | |
193 | ||
194 | /* Failed again: Return error */ | |
195 | return -EBUSY; | |
196 | } | |
197 | ||
198 | #define twl4030_usb_write_verify(twl, address, data) \ | |
9d94e16b | 199 | twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address)) |
9ebd9616 DB |
200 | |
201 | static inline int twl4030_usb_write(struct twl4030_usb *twl, | |
202 | u8 address, u8 data) | |
203 | { | |
204 | int ret = 0; | |
205 | ||
9d94e16b | 206 | ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address); |
9ebd9616 DB |
207 | if (ret < 0) |
208 | dev_dbg(twl->dev, | |
209 | "TWL4030:USB:Write[0x%x] Error %d\n", address, ret); | |
210 | return ret; | |
211 | } | |
212 | ||
213 | static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address) | |
214 | { | |
215 | u8 data; | |
216 | int ret = 0; | |
217 | ||
fc7b92fc | 218 | ret = twl_i2c_read_u8(module, &data, address); |
9ebd9616 DB |
219 | if (ret >= 0) |
220 | ret = data; | |
221 | else | |
222 | dev_dbg(twl->dev, | |
223 | "TWL4030:readb[0x%x,0x%x] Error %d\n", | |
224 | module, address, ret); | |
225 | ||
226 | return ret; | |
227 | } | |
228 | ||
229 | static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address) | |
230 | { | |
9d94e16b | 231 | return twl4030_readb(twl, TWL_MODULE_USB, address); |
9ebd9616 DB |
232 | } |
233 | ||
234 | /*-------------------------------------------------------------------------*/ | |
235 | ||
236 | static inline int | |
237 | twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
238 | { | |
92a6e6b3 | 239 | return twl4030_usb_write(twl, ULPI_SET(reg), bits); |
9ebd9616 DB |
240 | } |
241 | ||
242 | static inline int | |
243 | twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
244 | { | |
92a6e6b3 | 245 | return twl4030_usb_write(twl, ULPI_CLR(reg), bits); |
9ebd9616 DB |
246 | } |
247 | ||
248 | /*-------------------------------------------------------------------------*/ | |
249 | ||
f65f4f40 GI |
250 | static bool twl4030_is_driving_vbus(struct twl4030_usb *twl) |
251 | { | |
252 | int ret; | |
253 | ||
254 | ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS); | |
255 | if (ret < 0 || !(ret & PHY_DPLL_CLK)) | |
256 | /* | |
257 | * if clocks are off, registers are not updated, | |
258 | * but we can assume we don't drive VBUS in this case | |
259 | */ | |
260 | return false; | |
261 | ||
262 | ret = twl4030_usb_read(twl, ULPI_OTG_CTRL); | |
263 | if (ret < 0) | |
264 | return false; | |
265 | ||
266 | return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false; | |
267 | } | |
268 | ||
c9721438 KVA |
269 | static enum omap_musb_vbus_id_status |
270 | twl4030_usb_linkstat(struct twl4030_usb *twl) | |
9ebd9616 DB |
271 | { |
272 | int status; | |
c9721438 | 273 | enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN; |
9ebd9616 | 274 | |
a87103a6 MK |
275 | twl->vbus_supplied = false; |
276 | ||
def6f8b9 DB |
277 | /* |
278 | * For ID/VBUS sensing, see manual section 15.4.8 ... | |
279 | * except when using only battery backup power, two | |
280 | * comparators produce VBUS_PRES and ID_PRES signals, | |
281 | * which don't match docs elsewhere. But ... BIT(7) | |
282 | * and BIT(2) of STS_HW_CONDITIONS, respectively, do | |
283 | * seem to match up. If either is true the USB_PRES | |
284 | * signal is active, the OTG module is activated, and | |
285 | * its interrupt may be raised (may wake the system). | |
286 | */ | |
9d94e16b | 287 | status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS); |
9ebd9616 DB |
288 | if (status < 0) |
289 | dev_err(twl->dev, "USB link status err %d\n", status); | |
def6f8b9 | 290 | else if (status & (BIT(7) | BIT(2))) { |
f65f4f40 GI |
291 | if (status & BIT(7)) { |
292 | if (twl4030_is_driving_vbus(twl)) | |
293 | status &= ~BIT(7); | |
294 | else | |
295 | twl->vbus_supplied = true; | |
296 | } | |
a87103a6 | 297 | |
def6f8b9 | 298 | if (status & BIT(2)) |
c9721438 | 299 | linkstat = OMAP_MUSB_ID_GROUND; |
f65f4f40 | 300 | else if (status & BIT(7)) |
c9721438 | 301 | linkstat = OMAP_MUSB_VBUS_VALID; |
f65f4f40 GI |
302 | else |
303 | linkstat = OMAP_MUSB_VBUS_OFF; | |
c9721438 KVA |
304 | } else { |
305 | if (twl->linkstat != OMAP_MUSB_UNKNOWN) | |
306 | linkstat = OMAP_MUSB_VBUS_OFF; | |
307 | } | |
9ebd9616 DB |
308 | |
309 | dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n", | |
310 | status, status, linkstat); | |
311 | ||
312 | /* REVISIT this assumes host and peripheral controllers | |
313 | * are registered, and that both are active... | |
314 | */ | |
315 | ||
9ebd9616 DB |
316 | return linkstat; |
317 | } | |
318 | ||
319 | static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode) | |
320 | { | |
321 | twl->usb_mode = mode; | |
322 | ||
323 | switch (mode) { | |
324 | case T2_USB_MODE_ULPI: | |
92a6e6b3 HK |
325 | twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL, |
326 | ULPI_IFC_CTRL_CARKITMODE); | |
9ebd9616 | 327 | twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); |
92a6e6b3 HK |
328 | twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL, |
329 | ULPI_FUNC_CTRL_XCVRSEL_MASK | | |
330 | ULPI_FUNC_CTRL_OPMODE_MASK); | |
9ebd9616 DB |
331 | break; |
332 | case -1: | |
333 | /* FIXME: power on defaults */ | |
334 | break; | |
335 | default: | |
336 | dev_err(twl->dev, "unsupported T2 transceiver mode %d\n", | |
337 | mode); | |
338 | break; | |
ed093e61 | 339 | } |
9ebd9616 DB |
340 | } |
341 | ||
342 | static void twl4030_i2c_access(struct twl4030_usb *twl, int on) | |
343 | { | |
344 | unsigned long timeout; | |
345 | int val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
346 | ||
347 | if (val >= 0) { | |
348 | if (on) { | |
349 | /* enable DPLL to access PHY registers over I2C */ | |
350 | val |= REQ_PHY_DPLL_CLK; | |
351 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
352 | (u8)val) < 0); | |
353 | ||
354 | timeout = jiffies + HZ; | |
355 | while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
356 | PHY_DPLL_CLK) | |
357 | && time_before(jiffies, timeout)) | |
358 | udelay(10); | |
359 | if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
360 | PHY_DPLL_CLK)) | |
361 | dev_err(twl->dev, "Timeout setting T2 HSUSB " | |
362 | "PHY DPLL clock\n"); | |
363 | } else { | |
364 | /* let ULPI control the DPLL clock */ | |
365 | val &= ~REQ_PHY_DPLL_CLK; | |
366 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
367 | (u8)val) < 0); | |
368 | } | |
369 | } | |
370 | } | |
371 | ||
fc8f2a76 | 372 | static void __twl4030_phy_power(struct twl4030_usb *twl, int on) |
9ebd9616 | 373 | { |
fc8f2a76 ML |
374 | u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); |
375 | ||
376 | if (on) | |
377 | pwr &= ~PHY_PWR_PHYPWD; | |
378 | else | |
379 | pwr |= PHY_PWR_PHYPWD; | |
9ebd9616 | 380 | |
fc8f2a76 ML |
381 | WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); |
382 | } | |
383 | ||
96be39ab | 384 | static int twl4030_usb_runtime_suspend(struct device *dev) |
9ebd9616 | 385 | { |
96be39ab | 386 | struct twl4030_usb *twl = dev_get_drvdata(dev); |
f1ddc24c | 387 | |
96be39ab | 388 | dev_dbg(twl->dev, "%s\n", __func__); |
48f48e17 | 389 | if (pm_runtime_suspended(dev)) |
f1ddc24c | 390 | return 0; |
9ebd9616 | 391 | |
bad8e335 TL |
392 | __twl4030_phy_power(twl, 0); |
393 | regulator_disable(twl->usb1v5); | |
394 | regulator_disable(twl->usb1v8); | |
395 | regulator_disable(twl->usb3v1); | |
96be39ab | 396 | |
6747caa7 KVA |
397 | return 0; |
398 | } | |
399 | ||
96be39ab | 400 | static int twl4030_usb_runtime_resume(struct device *dev) |
9ebd9616 | 401 | { |
96be39ab | 402 | struct twl4030_usb *twl = dev_get_drvdata(dev); |
bad8e335 | 403 | int res; |
96be39ab TL |
404 | |
405 | dev_dbg(twl->dev, "%s\n", __func__); | |
48f48e17 | 406 | if (pm_runtime_active(dev)) |
96be39ab TL |
407 | return 0; |
408 | ||
bad8e335 TL |
409 | res = regulator_enable(twl->usb3v1); |
410 | if (res) | |
411 | dev_err(twl->dev, "Failed to enable usb3v1\n"); | |
412 | ||
413 | res = regulator_enable(twl->usb1v8); | |
414 | if (res) | |
415 | dev_err(twl->dev, "Failed to enable usb1v8\n"); | |
416 | ||
417 | /* | |
418 | * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP | |
419 | * in twl4030) resets the VUSB_DEDICATED2 register. This reset | |
420 | * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to | |
421 | * SLEEP. We work around this by clearing the bit after usv3v1 | |
422 | * is re-activated. This ensures that VUSB3V1 is really active. | |
423 | */ | |
424 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); | |
425 | ||
426 | res = regulator_enable(twl->usb1v5); | |
427 | if (res) | |
428 | dev_err(twl->dev, "Failed to enable usb1v5\n"); | |
429 | ||
430 | __twl4030_phy_power(twl, 1); | |
431 | twl4030_usb_write(twl, PHY_CLK_CTRL, | |
432 | twl4030_usb_read(twl, PHY_CLK_CTRL) | | |
433 | (PHY_CLK_CTRL_CLOCKGATING_EN | | |
434 | PHY_CLK_CTRL_CLK32K_EN)); | |
96be39ab TL |
435 | |
436 | return 0; | |
437 | } | |
438 | ||
439 | static int twl4030_phy_power_off(struct phy *phy) | |
440 | { | |
441 | struct twl4030_usb *twl = phy_get_drvdata(phy); | |
442 | ||
443 | dev_dbg(twl->dev, "%s\n", __func__); | |
444 | pm_runtime_mark_last_busy(twl->dev); | |
445 | pm_runtime_put_autosuspend(twl->dev); | |
446 | ||
447 | return 0; | |
fc8f2a76 ML |
448 | } |
449 | ||
f1ddc24c | 450 | static int twl4030_phy_power_on(struct phy *phy) |
fc8f2a76 | 451 | { |
f1ddc24c KVA |
452 | struct twl4030_usb *twl = phy_get_drvdata(phy); |
453 | ||
fc8f2a76 | 454 | dev_dbg(twl->dev, "%s\n", __func__); |
96be39ab TL |
455 | pm_runtime_get_sync(twl->dev); |
456 | twl4030_i2c_access(twl, 1); | |
457 | twl4030_usb_set_mode(twl, twl->usb_mode); | |
458 | if (twl->usb_mode == T2_USB_MODE_ULPI) | |
459 | twl4030_i2c_access(twl, 0); | |
62dc5769 | 460 | schedule_delayed_work(&twl->id_workaround_work, 0); |
249751f2 | 461 | |
6747caa7 KVA |
462 | return 0; |
463 | } | |
464 | ||
66760169 | 465 | static int twl4030_usb_ldo_init(struct twl4030_usb *twl) |
9ebd9616 DB |
466 | { |
467 | /* Enable writing to power configuration registers */ | |
9d94e16b PU |
468 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, |
469 | TWL4030_PM_MASTER_PROTECT_KEY); | |
e7944d82 | 470 | |
9d94e16b PU |
471 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2, |
472 | TWL4030_PM_MASTER_PROTECT_KEY); | |
9ebd9616 | 473 | |
fc8f2a76 | 474 | /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/ |
9d94e16b | 475 | /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/ |
9ebd9616 DB |
476 | |
477 | /* input to VUSB3V1 LDO is from VBAT, not VBUS */ | |
9d94e16b | 478 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1); |
9ebd9616 | 479 | |
66760169 | 480 | /* Initialize 3.1V regulator */ |
9d94e16b | 481 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP); |
66760169 | 482 | |
9166902c | 483 | twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1"); |
66760169 JH |
484 | if (IS_ERR(twl->usb3v1)) |
485 | return -ENODEV; | |
486 | ||
9d94e16b | 487 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE); |
9ebd9616 | 488 | |
66760169 | 489 | /* Initialize 1.5V regulator */ |
9d94e16b | 490 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP); |
66760169 | 491 | |
9166902c | 492 | twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5"); |
66760169 | 493 | if (IS_ERR(twl->usb1v5)) |
9166902c | 494 | return -ENODEV; |
66760169 | 495 | |
9d94e16b | 496 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE); |
9ebd9616 | 497 | |
66760169 | 498 | /* Initialize 1.8V regulator */ |
9d94e16b | 499 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP); |
66760169 | 500 | |
9166902c | 501 | twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8"); |
66760169 | 502 | if (IS_ERR(twl->usb1v8)) |
9166902c | 503 | return -ENODEV; |
66760169 | 504 | |
9d94e16b | 505 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); |
9ebd9616 DB |
506 | |
507 | /* disable access to power configuration registers */ | |
9d94e16b PU |
508 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, |
509 | TWL4030_PM_MASTER_PROTECT_KEY); | |
66760169 JH |
510 | |
511 | return 0; | |
9ebd9616 DB |
512 | } |
513 | ||
514 | static ssize_t twl4030_usb_vbus_show(struct device *dev, | |
515 | struct device_attribute *attr, char *buf) | |
516 | { | |
517 | struct twl4030_usb *twl = dev_get_drvdata(dev); | |
9ebd9616 DB |
518 | int ret = -EINVAL; |
519 | ||
dcc35b21 | 520 | mutex_lock(&twl->lock); |
9ebd9616 | 521 | ret = sprintf(buf, "%s\n", |
a87103a6 | 522 | twl->vbus_supplied ? "on" : "off"); |
dcc35b21 | 523 | mutex_unlock(&twl->lock); |
9ebd9616 DB |
524 | |
525 | return ret; | |
526 | } | |
527 | static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL); | |
528 | ||
529 | static irqreturn_t twl4030_usb_irq(int irq, void *_twl) | |
530 | { | |
531 | struct twl4030_usb *twl = _twl; | |
c9721438 | 532 | enum omap_musb_vbus_id_status status; |
249751f2 | 533 | bool status_changed = false; |
9ebd9616 | 534 | |
9ebd9616 | 535 | status = twl4030_usb_linkstat(twl); |
249751f2 | 536 | |
dcc35b21 | 537 | mutex_lock(&twl->lock); |
249751f2 GI |
538 | if (status >= 0 && status != twl->linkstat) { |
539 | twl->linkstat = status; | |
540 | status_changed = true; | |
541 | } | |
dcc35b21 | 542 | mutex_unlock(&twl->lock); |
249751f2 GI |
543 | |
544 | if (status_changed) { | |
9ebd9616 DB |
545 | /* FIXME add a set_power() method so that B-devices can |
546 | * configure the charger appropriately. It's not always | |
547 | * correct to consume VBUS power, and how much current to | |
548 | * consume is a function of the USB configuration chosen | |
549 | * by the host. | |
550 | * | |
551 | * REVISIT usb_gadget_vbus_connect(...) as needed, ditto | |
552 | * its disconnect() sibling, when changing to/from the | |
553 | * USB_LINK_VBUS state. musb_hdrc won't care until it | |
554 | * starts to handle softconnect right. | |
555 | */ | |
96be39ab TL |
556 | if ((status == OMAP_MUSB_VBUS_VALID) || |
557 | (status == OMAP_MUSB_ID_GROUND)) { | |
48f48e17 | 558 | if (pm_runtime_suspended(twl->dev)) |
96be39ab TL |
559 | pm_runtime_get_sync(twl->dev); |
560 | } else { | |
48f48e17 | 561 | if (pm_runtime_active(twl->dev)) { |
96be39ab TL |
562 | pm_runtime_mark_last_busy(twl->dev); |
563 | pm_runtime_put_autosuspend(twl->dev); | |
564 | } | |
565 | } | |
249751f2 | 566 | omap_musb_mailbox(status); |
9ebd9616 | 567 | } |
85601b8d TL |
568 | |
569 | /* don't schedule during sleep - irq works right then */ | |
48f48e17 | 570 | if (status == OMAP_MUSB_ID_GROUND && pm_runtime_active(twl->dev)) { |
85601b8d TL |
571 | cancel_delayed_work(&twl->id_workaround_work); |
572 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
573 | } | |
574 | ||
575 | if (irq) | |
576 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); | |
9ebd9616 DB |
577 | |
578 | return IRQ_HANDLED; | |
579 | } | |
580 | ||
249751f2 | 581 | static void twl4030_id_workaround_work(struct work_struct *work) |
fc8f2a76 | 582 | { |
249751f2 GI |
583 | struct twl4030_usb *twl = container_of(work, struct twl4030_usb, |
584 | id_workaround_work.work); | |
249751f2 | 585 | |
85601b8d | 586 | twl4030_usb_irq(0, twl); |
249751f2 GI |
587 | } |
588 | ||
f1ddc24c | 589 | static int twl4030_phy_init(struct phy *phy) |
fc8f2a76 | 590 | { |
f1ddc24c | 591 | struct twl4030_usb *twl = phy_get_drvdata(phy); |
fc8f2a76 | 592 | |
96be39ab | 593 | pm_runtime_get_sync(twl->dev); |
62dc5769 | 594 | schedule_delayed_work(&twl->id_workaround_work, 0); |
96be39ab TL |
595 | pm_runtime_mark_last_busy(twl->dev); |
596 | pm_runtime_put_autosuspend(twl->dev); | |
597 | ||
817e5f33 | 598 | return 0; |
fc8f2a76 ML |
599 | } |
600 | ||
74d4aa44 HK |
601 | static int twl4030_set_peripheral(struct usb_otg *otg, |
602 | struct usb_gadget *gadget) | |
9ebd9616 | 603 | { |
74d4aa44 | 604 | if (!otg) |
9ebd9616 DB |
605 | return -ENODEV; |
606 | ||
74d4aa44 | 607 | otg->gadget = gadget; |
9ebd9616 | 608 | if (!gadget) |
8b9ca276 | 609 | otg->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
610 | |
611 | return 0; | |
612 | } | |
613 | ||
74d4aa44 | 614 | static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host) |
9ebd9616 | 615 | { |
74d4aa44 | 616 | if (!otg) |
9ebd9616 DB |
617 | return -ENODEV; |
618 | ||
74d4aa44 | 619 | otg->host = host; |
9ebd9616 | 620 | if (!host) |
8b9ca276 | 621 | otg->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
622 | |
623 | return 0; | |
624 | } | |
625 | ||
6747caa7 KVA |
626 | static const struct phy_ops ops = { |
627 | .init = twl4030_phy_init, | |
628 | .power_on = twl4030_phy_power_on, | |
629 | .power_off = twl4030_phy_power_off, | |
630 | .owner = THIS_MODULE, | |
631 | }; | |
632 | ||
96be39ab TL |
633 | static const struct dev_pm_ops twl4030_usb_pm_ops = { |
634 | SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend, | |
635 | twl4030_usb_runtime_resume, NULL) | |
636 | }; | |
637 | ||
41ac7b3a | 638 | static int twl4030_usb_probe(struct platform_device *pdev) |
9ebd9616 | 639 | { |
19f9e188 | 640 | struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev); |
9ebd9616 | 641 | struct twl4030_usb *twl; |
6747caa7 | 642 | struct phy *phy; |
66760169 | 643 | int status, err; |
74d4aa44 | 644 | struct usb_otg *otg; |
f8515f06 | 645 | struct device_node *np = pdev->dev.of_node; |
6747caa7 | 646 | struct phy_provider *phy_provider; |
9ebd9616 | 647 | |
b6d790f7 | 648 | twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL); |
9ebd9616 DB |
649 | if (!twl) |
650 | return -ENOMEM; | |
651 | ||
f8515f06 KVA |
652 | if (np) |
653 | of_property_read_u32(np, "usb_mode", | |
654 | (enum twl4030_usb_mode *)&twl->usb_mode); | |
6747caa7 | 655 | else if (pdata) { |
f8515f06 | 656 | twl->usb_mode = pdata->usb_mode; |
6747caa7 | 657 | } else { |
f8515f06 KVA |
658 | dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); |
659 | return -EINVAL; | |
660 | } | |
661 | ||
b6d790f7 | 662 | otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL); |
b8a3efa3 | 663 | if (!otg) |
74d4aa44 | 664 | return -ENOMEM; |
74d4aa44 | 665 | |
9ebd9616 DB |
666 | twl->dev = &pdev->dev; |
667 | twl->irq = platform_get_irq(pdev, 0); | |
a87103a6 | 668 | twl->vbus_supplied = false; |
c9721438 | 669 | twl->linkstat = OMAP_MUSB_UNKNOWN; |
74d4aa44 HK |
670 | |
671 | twl->phy.dev = twl->dev; | |
672 | twl->phy.label = "twl4030"; | |
673 | twl->phy.otg = otg; | |
c11747f6 | 674 | twl->phy.type = USB_PHY_TYPE_USB2; |
74d4aa44 | 675 | |
8b9ca276 | 676 | otg->usb_phy = &twl->phy; |
74d4aa44 HK |
677 | otg->set_host = twl4030_set_host; |
678 | otg->set_peripheral = twl4030_set_peripheral; | |
9ebd9616 | 679 | |
dbc98635 | 680 | phy = devm_phy_create(twl->dev, NULL, &ops); |
6747caa7 KVA |
681 | if (IS_ERR(phy)) { |
682 | dev_dbg(&pdev->dev, "Failed to create PHY\n"); | |
683 | return PTR_ERR(phy); | |
684 | } | |
685 | ||
686 | phy_set_drvdata(phy, twl); | |
687 | ||
64fe1891 KVA |
688 | phy_provider = devm_of_phy_provider_register(twl->dev, |
689 | of_phy_simple_xlate); | |
690 | if (IS_ERR(phy_provider)) | |
691 | return PTR_ERR(phy_provider); | |
692 | ||
dcc35b21 TL |
693 | /* init mutex for workqueue */ |
694 | mutex_init(&twl->lock); | |
9ebd9616 | 695 | |
249751f2 GI |
696 | INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work); |
697 | ||
66760169 JH |
698 | err = twl4030_usb_ldo_init(twl); |
699 | if (err) { | |
700 | dev_err(&pdev->dev, "ldo init failed\n"); | |
66760169 JH |
701 | return err; |
702 | } | |
c11747f6 | 703 | usb_add_phy_dev(&twl->phy); |
9ebd9616 DB |
704 | |
705 | platform_set_drvdata(pdev, twl); | |
706 | if (device_create_file(&pdev->dev, &dev_attr_vbus)) | |
707 | dev_warn(&pdev->dev, "could not create sysfs file\n"); | |
708 | ||
80d2e76c PR |
709 | ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier); |
710 | ||
96be39ab TL |
711 | pm_runtime_use_autosuspend(&pdev->dev); |
712 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
713 | pm_runtime_enable(&pdev->dev); | |
714 | pm_runtime_get_sync(&pdev->dev); | |
715 | ||
9ebd9616 DB |
716 | /* Our job is to use irqs and status from the power module |
717 | * to keep the transceiver disabled when nothing's connected. | |
718 | * | |
719 | * FIXME we actually shouldn't start enabling it until the | |
720 | * USB controller drivers have said they're ready, by calling | |
721 | * set_host() and/or set_peripheral() ... OTG_capable boards | |
722 | * need both handles, otherwise just one suffices. | |
723 | */ | |
9166902c KVA |
724 | status = devm_request_threaded_irq(twl->dev, twl->irq, NULL, |
725 | twl4030_usb_irq, IRQF_TRIGGER_FALLING | | |
726 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl); | |
9ebd9616 DB |
727 | if (status < 0) { |
728 | dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", | |
729 | twl->irq, status); | |
9ebd9616 DB |
730 | return status; |
731 | } | |
732 | ||
61211b1b HK |
733 | if (pdata) |
734 | err = phy_create_lookup(phy, "usb", "musb-hdrc.0"); | |
735 | if (err) | |
736 | return err; | |
737 | ||
96be39ab TL |
738 | pm_runtime_mark_last_busy(&pdev->dev); |
739 | pm_runtime_put_autosuspend(twl->dev); | |
740 | ||
9ebd9616 DB |
741 | dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); |
742 | return 0; | |
743 | } | |
744 | ||
39d35681 | 745 | static int twl4030_usb_remove(struct platform_device *pdev) |
9ebd9616 DB |
746 | { |
747 | struct twl4030_usb *twl = platform_get_drvdata(pdev); | |
748 | int val; | |
749 | ||
96be39ab | 750 | pm_runtime_get_sync(twl->dev); |
249751f2 | 751 | cancel_delayed_work(&twl->id_workaround_work); |
9ebd9616 DB |
752 | device_remove_file(twl->dev, &dev_attr_vbus); |
753 | ||
754 | /* set transceiver mode to power on defaults */ | |
755 | twl4030_usb_set_mode(twl, -1); | |
756 | ||
757 | /* autogate 60MHz ULPI clock, | |
758 | * clear dpll clock request for i2c access, | |
759 | * disable 32KHz | |
760 | */ | |
761 | val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
762 | if (val >= 0) { | |
763 | val |= PHY_CLK_CTRL_CLOCKGATING_EN; | |
764 | val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); | |
765 | twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); | |
766 | } | |
767 | ||
768 | /* disable complete OTG block */ | |
769 | twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); | |
96be39ab TL |
770 | pm_runtime_mark_last_busy(twl->dev); |
771 | pm_runtime_put(twl->dev); | |
9ebd9616 | 772 | |
9ebd9616 DB |
773 | return 0; |
774 | } | |
775 | ||
f8515f06 KVA |
776 | #ifdef CONFIG_OF |
777 | static const struct of_device_id twl4030_usb_id_table[] = { | |
778 | { .compatible = "ti,twl4030-usb" }, | |
779 | {} | |
780 | }; | |
781 | MODULE_DEVICE_TABLE(of, twl4030_usb_id_table); | |
782 | #endif | |
783 | ||
9ebd9616 DB |
784 | static struct platform_driver twl4030_usb_driver = { |
785 | .probe = twl4030_usb_probe, | |
39d35681 | 786 | .remove = twl4030_usb_remove, |
9ebd9616 DB |
787 | .driver = { |
788 | .name = "twl4030_usb", | |
96be39ab | 789 | .pm = &twl4030_usb_pm_ops, |
f8515f06 | 790 | .of_match_table = of_match_ptr(twl4030_usb_id_table), |
9ebd9616 DB |
791 | }, |
792 | }; | |
793 | ||
794 | static int __init twl4030_usb_init(void) | |
795 | { | |
796 | return platform_driver_register(&twl4030_usb_driver); | |
797 | } | |
798 | subsys_initcall(twl4030_usb_init); | |
799 | ||
800 | static void __exit twl4030_usb_exit(void) | |
801 | { | |
802 | platform_driver_unregister(&twl4030_usb_driver); | |
803 | } | |
804 | module_exit(twl4030_usb_exit); | |
805 | ||
806 | MODULE_ALIAS("platform:twl4030_usb"); | |
807 | MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation"); | |
808 | MODULE_DESCRIPTION("TWL4030 USB transceiver driver"); | |
809 | MODULE_LICENSE("GPL"); |