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9ebd9616 DB |
1 | /* |
2 | * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller | |
3 | * | |
4 | * Copyright (C) 2004-2007 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * Current status: | |
23 | * - HS USB ULPI mode works. | |
24 | * - 3-pin mode support may be added in future. | |
25 | */ | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/platform_device.h> | |
9ebd9616 DB |
31 | #include <linux/workqueue.h> |
32 | #include <linux/io.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/usb/otg.h> | |
6747caa7 | 35 | #include <linux/phy/phy.h> |
96be39ab | 36 | #include <linux/pm_runtime.h> |
8055555f | 37 | #include <linux/usb/musb.h> |
92a6e6b3 | 38 | #include <linux/usb/ulpi.h> |
b07682b6 | 39 | #include <linux/i2c/twl.h> |
66760169 JH |
40 | #include <linux/regulator/consumer.h> |
41 | #include <linux/err.h> | |
5a0e3ad6 | 42 | #include <linux/slab.h> |
9ebd9616 DB |
43 | |
44 | /* Register defines */ | |
45 | ||
9ebd9616 | 46 | #define MCPC_CTRL 0x30 |
9ebd9616 DB |
47 | #define MCPC_CTRL_RTSOL (1 << 7) |
48 | #define MCPC_CTRL_EXTSWR (1 << 6) | |
49 | #define MCPC_CTRL_EXTSWC (1 << 5) | |
50 | #define MCPC_CTRL_VOICESW (1 << 4) | |
51 | #define MCPC_CTRL_OUT64K (1 << 3) | |
52 | #define MCPC_CTRL_RTSCTSSW (1 << 2) | |
53 | #define MCPC_CTRL_HS_UART (1 << 0) | |
54 | ||
55 | #define MCPC_IO_CTRL 0x33 | |
9ebd9616 DB |
56 | #define MCPC_IO_CTRL_MICBIASEN (1 << 5) |
57 | #define MCPC_IO_CTRL_CTS_NPU (1 << 4) | |
58 | #define MCPC_IO_CTRL_RXD_PU (1 << 3) | |
59 | #define MCPC_IO_CTRL_TXDTYP (1 << 2) | |
60 | #define MCPC_IO_CTRL_CTSTYP (1 << 1) | |
61 | #define MCPC_IO_CTRL_RTSTYP (1 << 0) | |
62 | ||
63 | #define MCPC_CTRL2 0x36 | |
9ebd9616 DB |
64 | #define MCPC_CTRL2_MCPC_CK_EN (1 << 0) |
65 | ||
66 | #define OTHER_FUNC_CTRL 0x80 | |
9ebd9616 DB |
67 | #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4) |
68 | #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2) | |
69 | ||
70 | #define OTHER_IFC_CTRL 0x83 | |
9ebd9616 DB |
71 | #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6) |
72 | #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5) | |
73 | #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4) | |
74 | #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3) | |
75 | #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2) | |
76 | #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0) | |
77 | ||
78 | #define OTHER_INT_EN_RISE 0x86 | |
9ebd9616 | 79 | #define OTHER_INT_EN_FALL 0x89 |
9ebd9616 DB |
80 | #define OTHER_INT_STS 0x8C |
81 | #define OTHER_INT_LATCH 0x8D | |
82 | #define OTHER_INT_VB_SESS_VLD (1 << 7) | |
83 | #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */ | |
84 | #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */ | |
85 | #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */ | |
86 | #define OTHER_INT_MANU (1 << 1) | |
87 | #define OTHER_INT_ABNORMAL_STRESS (1 << 0) | |
88 | ||
89 | #define ID_STATUS 0x96 | |
90 | #define ID_RES_FLOAT (1 << 4) | |
91 | #define ID_RES_440K (1 << 3) | |
92 | #define ID_RES_200K (1 << 2) | |
93 | #define ID_RES_102K (1 << 1) | |
94 | #define ID_RES_GND (1 << 0) | |
95 | ||
96 | #define POWER_CTRL 0xAC | |
9ebd9616 DB |
97 | #define POWER_CTRL_OTG_ENAB (1 << 5) |
98 | ||
99 | #define OTHER_IFC_CTRL2 0xAF | |
9ebd9616 DB |
100 | #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4) |
101 | #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3) | |
102 | #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2) | |
103 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */ | |
104 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0) | |
105 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0) | |
106 | ||
107 | #define REG_CTRL_EN 0xB2 | |
9ebd9616 DB |
108 | #define REG_CTRL_ERROR 0xB5 |
109 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0) | |
110 | ||
111 | #define OTHER_FUNC_CTRL2 0xB8 | |
9ebd9616 DB |
112 | #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0) |
113 | ||
114 | /* following registers do not have separate _clr and _set registers */ | |
115 | #define VBUS_DEBOUNCE 0xC0 | |
116 | #define ID_DEBOUNCE 0xC1 | |
117 | #define VBAT_TIMER 0xD3 | |
118 | #define PHY_PWR_CTRL 0xFD | |
119 | #define PHY_PWR_PHYPWD (1 << 0) | |
120 | #define PHY_CLK_CTRL 0xFE | |
121 | #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2) | |
122 | #define PHY_CLK_CTRL_CLK32K_EN (1 << 1) | |
123 | #define REQ_PHY_DPLL_CLK (1 << 0) | |
124 | #define PHY_CLK_CTRL_STS 0xFF | |
125 | #define PHY_DPLL_CLK (1 << 0) | |
126 | ||
9d94e16b | 127 | /* In module TWL_MODULE_PM_MASTER */ |
def6f8b9 | 128 | #define STS_HW_CONDITIONS 0x0F |
9ebd9616 | 129 | |
9d94e16b | 130 | /* In module TWL_MODULE_PM_RECEIVER */ |
9ebd9616 DB |
131 | #define VUSB_DEDICATED1 0x7D |
132 | #define VUSB_DEDICATED2 0x7E | |
133 | #define VUSB1V5_DEV_GRP 0x71 | |
134 | #define VUSB1V5_TYPE 0x72 | |
135 | #define VUSB1V5_REMAP 0x73 | |
136 | #define VUSB1V8_DEV_GRP 0x74 | |
137 | #define VUSB1V8_TYPE 0x75 | |
138 | #define VUSB1V8_REMAP 0x76 | |
139 | #define VUSB3V1_DEV_GRP 0x77 | |
140 | #define VUSB3V1_TYPE 0x78 | |
141 | #define VUSB3V1_REMAP 0x79 | |
142 | ||
143 | /* In module TWL4030_MODULE_INTBR */ | |
144 | #define PMBR1 0x0D | |
145 | #define GPIO_USB_4PIN_ULPI_2430C (3 << 0) | |
146 | ||
56301df6 N |
147 | /* |
148 | * If VBUS is valid or ID is ground, then we know a | |
149 | * cable is present and we need to be runtime-enabled | |
150 | */ | |
8055555f | 151 | static inline bool cable_present(enum musb_vbus_id_status stat) |
56301df6 | 152 | { |
8055555f TL |
153 | return stat == MUSB_VBUS_VALID || |
154 | stat == MUSB_ID_GROUND; | |
56301df6 N |
155 | } |
156 | ||
9ebd9616 | 157 | struct twl4030_usb { |
74d4aa44 | 158 | struct usb_phy phy; |
9ebd9616 DB |
159 | struct device *dev; |
160 | ||
66760169 JH |
161 | /* TWL4030 internal USB regulator supplies */ |
162 | struct regulator *usb1v5; | |
163 | struct regulator *usb1v8; | |
164 | struct regulator *usb3v1; | |
165 | ||
9ebd9616 | 166 | /* for vbus reporting with irqs disabled */ |
dcc35b21 | 167 | struct mutex lock; |
9ebd9616 DB |
168 | |
169 | /* pin configuration */ | |
170 | enum twl4030_usb_mode usb_mode; | |
171 | ||
172 | int irq; | |
8055555f | 173 | enum musb_vbus_id_status linkstat; |
a87103a6 | 174 | bool vbus_supplied; |
249751f2 GI |
175 | |
176 | struct delayed_work id_workaround_work; | |
9ebd9616 DB |
177 | }; |
178 | ||
179 | /* internal define on top of container_of */ | |
74d4aa44 | 180 | #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy) |
9ebd9616 DB |
181 | |
182 | /*-------------------------------------------------------------------------*/ | |
183 | ||
184 | static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, | |
185 | u8 module, u8 data, u8 address) | |
186 | { | |
187 | u8 check; | |
188 | ||
fc7b92fc B |
189 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
190 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
191 | (check == data)) |
192 | return 0; | |
193 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
194 | 1, module, address, check, data); | |
195 | ||
196 | /* Failed once: Try again */ | |
fc7b92fc B |
197 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
198 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
199 | (check == data)) |
200 | return 0; | |
201 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
202 | 2, module, address, check, data); | |
203 | ||
204 | /* Failed again: Return error */ | |
205 | return -EBUSY; | |
206 | } | |
207 | ||
208 | #define twl4030_usb_write_verify(twl, address, data) \ | |
9d94e16b | 209 | twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address)) |
9ebd9616 DB |
210 | |
211 | static inline int twl4030_usb_write(struct twl4030_usb *twl, | |
212 | u8 address, u8 data) | |
213 | { | |
214 | int ret = 0; | |
215 | ||
9d94e16b | 216 | ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address); |
9ebd9616 DB |
217 | if (ret < 0) |
218 | dev_dbg(twl->dev, | |
219 | "TWL4030:USB:Write[0x%x] Error %d\n", address, ret); | |
220 | return ret; | |
221 | } | |
222 | ||
223 | static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address) | |
224 | { | |
225 | u8 data; | |
226 | int ret = 0; | |
227 | ||
fc7b92fc | 228 | ret = twl_i2c_read_u8(module, &data, address); |
9ebd9616 DB |
229 | if (ret >= 0) |
230 | ret = data; | |
231 | else | |
232 | dev_dbg(twl->dev, | |
233 | "TWL4030:readb[0x%x,0x%x] Error %d\n", | |
234 | module, address, ret); | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
239 | static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address) | |
240 | { | |
9d94e16b | 241 | return twl4030_readb(twl, TWL_MODULE_USB, address); |
9ebd9616 DB |
242 | } |
243 | ||
244 | /*-------------------------------------------------------------------------*/ | |
245 | ||
246 | static inline int | |
247 | twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
248 | { | |
92a6e6b3 | 249 | return twl4030_usb_write(twl, ULPI_SET(reg), bits); |
9ebd9616 DB |
250 | } |
251 | ||
252 | static inline int | |
253 | twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
254 | { | |
92a6e6b3 | 255 | return twl4030_usb_write(twl, ULPI_CLR(reg), bits); |
9ebd9616 DB |
256 | } |
257 | ||
258 | /*-------------------------------------------------------------------------*/ | |
259 | ||
f65f4f40 GI |
260 | static bool twl4030_is_driving_vbus(struct twl4030_usb *twl) |
261 | { | |
262 | int ret; | |
263 | ||
264 | ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS); | |
265 | if (ret < 0 || !(ret & PHY_DPLL_CLK)) | |
266 | /* | |
267 | * if clocks are off, registers are not updated, | |
268 | * but we can assume we don't drive VBUS in this case | |
269 | */ | |
270 | return false; | |
271 | ||
272 | ret = twl4030_usb_read(twl, ULPI_OTG_CTRL); | |
273 | if (ret < 0) | |
274 | return false; | |
275 | ||
276 | return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false; | |
277 | } | |
278 | ||
8055555f | 279 | static enum musb_vbus_id_status |
c9721438 | 280 | twl4030_usb_linkstat(struct twl4030_usb *twl) |
9ebd9616 DB |
281 | { |
282 | int status; | |
8055555f | 283 | enum musb_vbus_id_status linkstat = MUSB_UNKNOWN; |
9ebd9616 | 284 | |
a87103a6 MK |
285 | twl->vbus_supplied = false; |
286 | ||
def6f8b9 DB |
287 | /* |
288 | * For ID/VBUS sensing, see manual section 15.4.8 ... | |
289 | * except when using only battery backup power, two | |
290 | * comparators produce VBUS_PRES and ID_PRES signals, | |
291 | * which don't match docs elsewhere. But ... BIT(7) | |
292 | * and BIT(2) of STS_HW_CONDITIONS, respectively, do | |
293 | * seem to match up. If either is true the USB_PRES | |
294 | * signal is active, the OTG module is activated, and | |
295 | * its interrupt may be raised (may wake the system). | |
296 | */ | |
9d94e16b | 297 | status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS); |
9ebd9616 DB |
298 | if (status < 0) |
299 | dev_err(twl->dev, "USB link status err %d\n", status); | |
def6f8b9 | 300 | else if (status & (BIT(7) | BIT(2))) { |
f65f4f40 GI |
301 | if (status & BIT(7)) { |
302 | if (twl4030_is_driving_vbus(twl)) | |
303 | status &= ~BIT(7); | |
304 | else | |
305 | twl->vbus_supplied = true; | |
306 | } | |
a87103a6 | 307 | |
def6f8b9 | 308 | if (status & BIT(2)) |
8055555f | 309 | linkstat = MUSB_ID_GROUND; |
f65f4f40 | 310 | else if (status & BIT(7)) |
8055555f | 311 | linkstat = MUSB_VBUS_VALID; |
f65f4f40 | 312 | else |
8055555f | 313 | linkstat = MUSB_VBUS_OFF; |
c9721438 | 314 | } else { |
8055555f TL |
315 | if (twl->linkstat != MUSB_UNKNOWN) |
316 | linkstat = MUSB_VBUS_OFF; | |
c9721438 | 317 | } |
9ebd9616 DB |
318 | |
319 | dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n", | |
320 | status, status, linkstat); | |
321 | ||
322 | /* REVISIT this assumes host and peripheral controllers | |
323 | * are registered, and that both are active... | |
324 | */ | |
325 | ||
9ebd9616 DB |
326 | return linkstat; |
327 | } | |
328 | ||
329 | static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode) | |
330 | { | |
331 | twl->usb_mode = mode; | |
332 | ||
333 | switch (mode) { | |
334 | case T2_USB_MODE_ULPI: | |
92a6e6b3 HK |
335 | twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL, |
336 | ULPI_IFC_CTRL_CARKITMODE); | |
9ebd9616 | 337 | twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); |
92a6e6b3 HK |
338 | twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL, |
339 | ULPI_FUNC_CTRL_XCVRSEL_MASK | | |
340 | ULPI_FUNC_CTRL_OPMODE_MASK); | |
9ebd9616 DB |
341 | break; |
342 | case -1: | |
343 | /* FIXME: power on defaults */ | |
344 | break; | |
345 | default: | |
346 | dev_err(twl->dev, "unsupported T2 transceiver mode %d\n", | |
347 | mode); | |
348 | break; | |
ed093e61 | 349 | } |
9ebd9616 DB |
350 | } |
351 | ||
352 | static void twl4030_i2c_access(struct twl4030_usb *twl, int on) | |
353 | { | |
354 | unsigned long timeout; | |
355 | int val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
356 | ||
357 | if (val >= 0) { | |
358 | if (on) { | |
359 | /* enable DPLL to access PHY registers over I2C */ | |
360 | val |= REQ_PHY_DPLL_CLK; | |
361 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
362 | (u8)val) < 0); | |
363 | ||
364 | timeout = jiffies + HZ; | |
365 | while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
366 | PHY_DPLL_CLK) | |
367 | && time_before(jiffies, timeout)) | |
368 | udelay(10); | |
369 | if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
370 | PHY_DPLL_CLK)) | |
371 | dev_err(twl->dev, "Timeout setting T2 HSUSB " | |
372 | "PHY DPLL clock\n"); | |
373 | } else { | |
374 | /* let ULPI control the DPLL clock */ | |
375 | val &= ~REQ_PHY_DPLL_CLK; | |
376 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
377 | (u8)val) < 0); | |
378 | } | |
379 | } | |
380 | } | |
381 | ||
fc8f2a76 | 382 | static void __twl4030_phy_power(struct twl4030_usb *twl, int on) |
9ebd9616 | 383 | { |
fc8f2a76 ML |
384 | u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); |
385 | ||
386 | if (on) | |
387 | pwr &= ~PHY_PWR_PHYPWD; | |
388 | else | |
389 | pwr |= PHY_PWR_PHYPWD; | |
9ebd9616 | 390 | |
fc8f2a76 ML |
391 | WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); |
392 | } | |
393 | ||
8073fb82 | 394 | static int __maybe_unused twl4030_usb_runtime_suspend(struct device *dev) |
9ebd9616 | 395 | { |
96be39ab | 396 | struct twl4030_usb *twl = dev_get_drvdata(dev); |
f1ddc24c | 397 | |
96be39ab | 398 | dev_dbg(twl->dev, "%s\n", __func__); |
9ebd9616 | 399 | |
bad8e335 TL |
400 | __twl4030_phy_power(twl, 0); |
401 | regulator_disable(twl->usb1v5); | |
402 | regulator_disable(twl->usb1v8); | |
403 | regulator_disable(twl->usb3v1); | |
96be39ab | 404 | |
6747caa7 KVA |
405 | return 0; |
406 | } | |
407 | ||
8073fb82 | 408 | static int __maybe_unused twl4030_usb_runtime_resume(struct device *dev) |
9ebd9616 | 409 | { |
96be39ab | 410 | struct twl4030_usb *twl = dev_get_drvdata(dev); |
bad8e335 | 411 | int res; |
96be39ab TL |
412 | |
413 | dev_dbg(twl->dev, "%s\n", __func__); | |
96be39ab | 414 | |
bad8e335 TL |
415 | res = regulator_enable(twl->usb3v1); |
416 | if (res) | |
417 | dev_err(twl->dev, "Failed to enable usb3v1\n"); | |
418 | ||
419 | res = regulator_enable(twl->usb1v8); | |
420 | if (res) | |
421 | dev_err(twl->dev, "Failed to enable usb1v8\n"); | |
422 | ||
423 | /* | |
424 | * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP | |
425 | * in twl4030) resets the VUSB_DEDICATED2 register. This reset | |
426 | * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to | |
427 | * SLEEP. We work around this by clearing the bit after usv3v1 | |
428 | * is re-activated. This ensures that VUSB3V1 is really active. | |
429 | */ | |
430 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); | |
431 | ||
432 | res = regulator_enable(twl->usb1v5); | |
433 | if (res) | |
434 | dev_err(twl->dev, "Failed to enable usb1v5\n"); | |
435 | ||
436 | __twl4030_phy_power(twl, 1); | |
437 | twl4030_usb_write(twl, PHY_CLK_CTRL, | |
438 | twl4030_usb_read(twl, PHY_CLK_CTRL) | | |
439 | (PHY_CLK_CTRL_CLOCKGATING_EN | | |
440 | PHY_CLK_CTRL_CLK32K_EN)); | |
96be39ab TL |
441 | |
442 | return 0; | |
443 | } | |
444 | ||
445 | static int twl4030_phy_power_off(struct phy *phy) | |
446 | { | |
447 | struct twl4030_usb *twl = phy_get_drvdata(phy); | |
448 | ||
449 | dev_dbg(twl->dev, "%s\n", __func__); | |
450 | pm_runtime_mark_last_busy(twl->dev); | |
451 | pm_runtime_put_autosuspend(twl->dev); | |
452 | ||
453 | return 0; | |
fc8f2a76 ML |
454 | } |
455 | ||
f1ddc24c | 456 | static int twl4030_phy_power_on(struct phy *phy) |
fc8f2a76 | 457 | { |
f1ddc24c KVA |
458 | struct twl4030_usb *twl = phy_get_drvdata(phy); |
459 | ||
fc8f2a76 | 460 | dev_dbg(twl->dev, "%s\n", __func__); |
96be39ab TL |
461 | pm_runtime_get_sync(twl->dev); |
462 | twl4030_i2c_access(twl, 1); | |
463 | twl4030_usb_set_mode(twl, twl->usb_mode); | |
464 | if (twl->usb_mode == T2_USB_MODE_ULPI) | |
465 | twl4030_i2c_access(twl, 0); | |
12b7db2b TL |
466 | twl->linkstat = MUSB_UNKNOWN; |
467 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
249751f2 | 468 | |
6747caa7 KVA |
469 | return 0; |
470 | } | |
471 | ||
66760169 | 472 | static int twl4030_usb_ldo_init(struct twl4030_usb *twl) |
9ebd9616 DB |
473 | { |
474 | /* Enable writing to power configuration registers */ | |
9d94e16b PU |
475 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, |
476 | TWL4030_PM_MASTER_PROTECT_KEY); | |
e7944d82 | 477 | |
9d94e16b PU |
478 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2, |
479 | TWL4030_PM_MASTER_PROTECT_KEY); | |
9ebd9616 | 480 | |
fc8f2a76 | 481 | /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/ |
9d94e16b | 482 | /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/ |
9ebd9616 DB |
483 | |
484 | /* input to VUSB3V1 LDO is from VBAT, not VBUS */ | |
9d94e16b | 485 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1); |
9ebd9616 | 486 | |
66760169 | 487 | /* Initialize 3.1V regulator */ |
9d94e16b | 488 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP); |
66760169 | 489 | |
9166902c | 490 | twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1"); |
66760169 JH |
491 | if (IS_ERR(twl->usb3v1)) |
492 | return -ENODEV; | |
493 | ||
9d94e16b | 494 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE); |
9ebd9616 | 495 | |
66760169 | 496 | /* Initialize 1.5V regulator */ |
9d94e16b | 497 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP); |
66760169 | 498 | |
9166902c | 499 | twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5"); |
66760169 | 500 | if (IS_ERR(twl->usb1v5)) |
9166902c | 501 | return -ENODEV; |
66760169 | 502 | |
9d94e16b | 503 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE); |
9ebd9616 | 504 | |
66760169 | 505 | /* Initialize 1.8V regulator */ |
9d94e16b | 506 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP); |
66760169 | 507 | |
9166902c | 508 | twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8"); |
66760169 | 509 | if (IS_ERR(twl->usb1v8)) |
9166902c | 510 | return -ENODEV; |
66760169 | 511 | |
9d94e16b | 512 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); |
9ebd9616 DB |
513 | |
514 | /* disable access to power configuration registers */ | |
9d94e16b PU |
515 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, |
516 | TWL4030_PM_MASTER_PROTECT_KEY); | |
66760169 JH |
517 | |
518 | return 0; | |
9ebd9616 DB |
519 | } |
520 | ||
521 | static ssize_t twl4030_usb_vbus_show(struct device *dev, | |
522 | struct device_attribute *attr, char *buf) | |
523 | { | |
524 | struct twl4030_usb *twl = dev_get_drvdata(dev); | |
9ebd9616 DB |
525 | int ret = -EINVAL; |
526 | ||
dcc35b21 | 527 | mutex_lock(&twl->lock); |
9ebd9616 | 528 | ret = sprintf(buf, "%s\n", |
a87103a6 | 529 | twl->vbus_supplied ? "on" : "off"); |
dcc35b21 | 530 | mutex_unlock(&twl->lock); |
9ebd9616 DB |
531 | |
532 | return ret; | |
533 | } | |
534 | static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL); | |
535 | ||
536 | static irqreturn_t twl4030_usb_irq(int irq, void *_twl) | |
537 | { | |
538 | struct twl4030_usb *twl = _twl; | |
8055555f | 539 | enum musb_vbus_id_status status; |
249751f2 | 540 | bool status_changed = false; |
12b7db2b | 541 | int err; |
9ebd9616 | 542 | |
9ebd9616 | 543 | status = twl4030_usb_linkstat(twl); |
249751f2 | 544 | |
dcc35b21 | 545 | mutex_lock(&twl->lock); |
249751f2 | 546 | if (status >= 0 && status != twl->linkstat) { |
56301df6 N |
547 | status_changed = |
548 | cable_present(twl->linkstat) != | |
549 | cable_present(status); | |
249751f2 | 550 | twl->linkstat = status; |
249751f2 | 551 | } |
dcc35b21 | 552 | mutex_unlock(&twl->lock); |
249751f2 GI |
553 | |
554 | if (status_changed) { | |
9ebd9616 DB |
555 | /* FIXME add a set_power() method so that B-devices can |
556 | * configure the charger appropriately. It's not always | |
557 | * correct to consume VBUS power, and how much current to | |
558 | * consume is a function of the USB configuration chosen | |
559 | * by the host. | |
560 | * | |
561 | * REVISIT usb_gadget_vbus_connect(...) as needed, ditto | |
562 | * its disconnect() sibling, when changing to/from the | |
563 | * USB_LINK_VBUS state. musb_hdrc won't care until it | |
564 | * starts to handle softconnect right. | |
565 | */ | |
56301df6 N |
566 | if (cable_present(status)) { |
567 | pm_runtime_get_sync(twl->dev); | |
96be39ab | 568 | } else { |
56301df6 N |
569 | pm_runtime_mark_last_busy(twl->dev); |
570 | pm_runtime_put_autosuspend(twl->dev); | |
96be39ab | 571 | } |
12b7db2b TL |
572 | err = musb_mailbox(status); |
573 | if (err) | |
574 | twl->linkstat = MUSB_UNKNOWN; | |
9ebd9616 | 575 | } |
85601b8d TL |
576 | |
577 | /* don't schedule during sleep - irq works right then */ | |
8055555f | 578 | if (status == MUSB_ID_GROUND && pm_runtime_active(twl->dev)) { |
85601b8d TL |
579 | cancel_delayed_work(&twl->id_workaround_work); |
580 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
581 | } | |
582 | ||
583 | if (irq) | |
584 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); | |
9ebd9616 DB |
585 | |
586 | return IRQ_HANDLED; | |
587 | } | |
588 | ||
249751f2 | 589 | static void twl4030_id_workaround_work(struct work_struct *work) |
fc8f2a76 | 590 | { |
249751f2 GI |
591 | struct twl4030_usb *twl = container_of(work, struct twl4030_usb, |
592 | id_workaround_work.work); | |
249751f2 | 593 | |
85601b8d | 594 | twl4030_usb_irq(0, twl); |
249751f2 GI |
595 | } |
596 | ||
f1ddc24c | 597 | static int twl4030_phy_init(struct phy *phy) |
fc8f2a76 | 598 | { |
f1ddc24c | 599 | struct twl4030_usb *twl = phy_get_drvdata(phy); |
fc8f2a76 | 600 | |
96be39ab | 601 | pm_runtime_get_sync(twl->dev); |
12b7db2b TL |
602 | twl->linkstat = MUSB_UNKNOWN; |
603 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
96be39ab TL |
604 | pm_runtime_mark_last_busy(twl->dev); |
605 | pm_runtime_put_autosuspend(twl->dev); | |
606 | ||
817e5f33 | 607 | return 0; |
fc8f2a76 ML |
608 | } |
609 | ||
74d4aa44 HK |
610 | static int twl4030_set_peripheral(struct usb_otg *otg, |
611 | struct usb_gadget *gadget) | |
9ebd9616 | 612 | { |
74d4aa44 | 613 | if (!otg) |
9ebd9616 DB |
614 | return -ENODEV; |
615 | ||
74d4aa44 | 616 | otg->gadget = gadget; |
9ebd9616 | 617 | if (!gadget) |
8b9ca276 | 618 | otg->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
619 | |
620 | return 0; | |
621 | } | |
622 | ||
74d4aa44 | 623 | static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host) |
9ebd9616 | 624 | { |
74d4aa44 | 625 | if (!otg) |
9ebd9616 DB |
626 | return -ENODEV; |
627 | ||
74d4aa44 | 628 | otg->host = host; |
9ebd9616 | 629 | if (!host) |
8b9ca276 | 630 | otg->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
6747caa7 KVA |
635 | static const struct phy_ops ops = { |
636 | .init = twl4030_phy_init, | |
637 | .power_on = twl4030_phy_power_on, | |
638 | .power_off = twl4030_phy_power_off, | |
639 | .owner = THIS_MODULE, | |
640 | }; | |
641 | ||
96be39ab TL |
642 | static const struct dev_pm_ops twl4030_usb_pm_ops = { |
643 | SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend, | |
644 | twl4030_usb_runtime_resume, NULL) | |
645 | }; | |
646 | ||
41ac7b3a | 647 | static int twl4030_usb_probe(struct platform_device *pdev) |
9ebd9616 | 648 | { |
19f9e188 | 649 | struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev); |
9ebd9616 | 650 | struct twl4030_usb *twl; |
6747caa7 | 651 | struct phy *phy; |
66760169 | 652 | int status, err; |
74d4aa44 | 653 | struct usb_otg *otg; |
f8515f06 | 654 | struct device_node *np = pdev->dev.of_node; |
6747caa7 | 655 | struct phy_provider *phy_provider; |
9ebd9616 | 656 | |
b6d790f7 | 657 | twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL); |
9ebd9616 DB |
658 | if (!twl) |
659 | return -ENOMEM; | |
660 | ||
f8515f06 KVA |
661 | if (np) |
662 | of_property_read_u32(np, "usb_mode", | |
663 | (enum twl4030_usb_mode *)&twl->usb_mode); | |
6747caa7 | 664 | else if (pdata) { |
f8515f06 | 665 | twl->usb_mode = pdata->usb_mode; |
6747caa7 | 666 | } else { |
f8515f06 KVA |
667 | dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); |
668 | return -EINVAL; | |
669 | } | |
670 | ||
b6d790f7 | 671 | otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL); |
b8a3efa3 | 672 | if (!otg) |
74d4aa44 | 673 | return -ENOMEM; |
74d4aa44 | 674 | |
9ebd9616 DB |
675 | twl->dev = &pdev->dev; |
676 | twl->irq = platform_get_irq(pdev, 0); | |
a87103a6 | 677 | twl->vbus_supplied = false; |
8055555f | 678 | twl->linkstat = MUSB_UNKNOWN; |
74d4aa44 HK |
679 | |
680 | twl->phy.dev = twl->dev; | |
681 | twl->phy.label = "twl4030"; | |
682 | twl->phy.otg = otg; | |
c11747f6 | 683 | twl->phy.type = USB_PHY_TYPE_USB2; |
74d4aa44 | 684 | |
8b9ca276 | 685 | otg->usb_phy = &twl->phy; |
74d4aa44 HK |
686 | otg->set_host = twl4030_set_host; |
687 | otg->set_peripheral = twl4030_set_peripheral; | |
9ebd9616 | 688 | |
dbc98635 | 689 | phy = devm_phy_create(twl->dev, NULL, &ops); |
6747caa7 KVA |
690 | if (IS_ERR(phy)) { |
691 | dev_dbg(&pdev->dev, "Failed to create PHY\n"); | |
692 | return PTR_ERR(phy); | |
693 | } | |
694 | ||
695 | phy_set_drvdata(phy, twl); | |
696 | ||
64fe1891 KVA |
697 | phy_provider = devm_of_phy_provider_register(twl->dev, |
698 | of_phy_simple_xlate); | |
699 | if (IS_ERR(phy_provider)) | |
700 | return PTR_ERR(phy_provider); | |
701 | ||
dcc35b21 TL |
702 | /* init mutex for workqueue */ |
703 | mutex_init(&twl->lock); | |
9ebd9616 | 704 | |
249751f2 GI |
705 | INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work); |
706 | ||
66760169 JH |
707 | err = twl4030_usb_ldo_init(twl); |
708 | if (err) { | |
709 | dev_err(&pdev->dev, "ldo init failed\n"); | |
66760169 JH |
710 | return err; |
711 | } | |
c11747f6 | 712 | usb_add_phy_dev(&twl->phy); |
9ebd9616 DB |
713 | |
714 | platform_set_drvdata(pdev, twl); | |
715 | if (device_create_file(&pdev->dev, &dev_attr_vbus)) | |
716 | dev_warn(&pdev->dev, "could not create sysfs file\n"); | |
717 | ||
80d2e76c PR |
718 | ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier); |
719 | ||
96be39ab TL |
720 | pm_runtime_use_autosuspend(&pdev->dev); |
721 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
722 | pm_runtime_enable(&pdev->dev); | |
58a66dba | 723 | pm_runtime_get_sync(&pdev->dev); |
96be39ab | 724 | |
9ebd9616 DB |
725 | /* Our job is to use irqs and status from the power module |
726 | * to keep the transceiver disabled when nothing's connected. | |
727 | * | |
728 | * FIXME we actually shouldn't start enabling it until the | |
729 | * USB controller drivers have said they're ready, by calling | |
730 | * set_host() and/or set_peripheral() ... OTG_capable boards | |
731 | * need both handles, otherwise just one suffices. | |
732 | */ | |
9166902c KVA |
733 | status = devm_request_threaded_irq(twl->dev, twl->irq, NULL, |
734 | twl4030_usb_irq, IRQF_TRIGGER_FALLING | | |
735 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl); | |
9ebd9616 DB |
736 | if (status < 0) { |
737 | dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", | |
738 | twl->irq, status); | |
9ebd9616 DB |
739 | return status; |
740 | } | |
741 | ||
61211b1b HK |
742 | if (pdata) |
743 | err = phy_create_lookup(phy, "usb", "musb-hdrc.0"); | |
744 | if (err) | |
745 | return err; | |
746 | ||
96be39ab TL |
747 | pm_runtime_mark_last_busy(&pdev->dev); |
748 | pm_runtime_put_autosuspend(twl->dev); | |
749 | ||
9ebd9616 DB |
750 | dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); |
751 | return 0; | |
752 | } | |
753 | ||
39d35681 | 754 | static int twl4030_usb_remove(struct platform_device *pdev) |
9ebd9616 DB |
755 | { |
756 | struct twl4030_usb *twl = platform_get_drvdata(pdev); | |
757 | int val; | |
758 | ||
b241d31e | 759 | usb_remove_phy(&twl->phy); |
96be39ab | 760 | pm_runtime_get_sync(twl->dev); |
249751f2 | 761 | cancel_delayed_work(&twl->id_workaround_work); |
9ebd9616 DB |
762 | device_remove_file(twl->dev, &dev_attr_vbus); |
763 | ||
764 | /* set transceiver mode to power on defaults */ | |
765 | twl4030_usb_set_mode(twl, -1); | |
766 | ||
58a66dba TL |
767 | /* idle ulpi before powering off */ |
768 | if (cable_present(twl->linkstat)) | |
769 | pm_runtime_put_noidle(twl->dev); | |
770 | pm_runtime_mark_last_busy(twl->dev); | |
12b7db2b TL |
771 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
772 | pm_runtime_put_sync(twl->dev); | |
58a66dba TL |
773 | pm_runtime_disable(twl->dev); |
774 | ||
9ebd9616 DB |
775 | /* autogate 60MHz ULPI clock, |
776 | * clear dpll clock request for i2c access, | |
777 | * disable 32KHz | |
778 | */ | |
779 | val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
780 | if (val >= 0) { | |
781 | val |= PHY_CLK_CTRL_CLOCKGATING_EN; | |
782 | val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); | |
783 | twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); | |
784 | } | |
785 | ||
786 | /* disable complete OTG block */ | |
787 | twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); | |
56301df6 | 788 | |
9ebd9616 DB |
789 | return 0; |
790 | } | |
791 | ||
f8515f06 KVA |
792 | #ifdef CONFIG_OF |
793 | static const struct of_device_id twl4030_usb_id_table[] = { | |
794 | { .compatible = "ti,twl4030-usb" }, | |
795 | {} | |
796 | }; | |
797 | MODULE_DEVICE_TABLE(of, twl4030_usb_id_table); | |
798 | #endif | |
799 | ||
9ebd9616 DB |
800 | static struct platform_driver twl4030_usb_driver = { |
801 | .probe = twl4030_usb_probe, | |
39d35681 | 802 | .remove = twl4030_usb_remove, |
9ebd9616 DB |
803 | .driver = { |
804 | .name = "twl4030_usb", | |
96be39ab | 805 | .pm = &twl4030_usb_pm_ops, |
f8515f06 | 806 | .of_match_table = of_match_ptr(twl4030_usb_id_table), |
9ebd9616 DB |
807 | }, |
808 | }; | |
809 | ||
810 | static int __init twl4030_usb_init(void) | |
811 | { | |
812 | return platform_driver_register(&twl4030_usb_driver); | |
813 | } | |
814 | subsys_initcall(twl4030_usb_init); | |
815 | ||
816 | static void __exit twl4030_usb_exit(void) | |
817 | { | |
818 | platform_driver_unregister(&twl4030_usb_driver); | |
819 | } | |
820 | module_exit(twl4030_usb_exit); | |
821 | ||
822 | MODULE_ALIAS("platform:twl4030_usb"); | |
823 | MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation"); | |
824 | MODULE_DESCRIPTION("TWL4030 USB transceiver driver"); | |
825 | MODULE_LICENSE("GPL"); |