Commit | Line | Data |
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9ebd9616 DB |
1 | /* |
2 | * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller | |
3 | * | |
4 | * Copyright (C) 2004-2007 Texas Instruments | |
5 | * Copyright (C) 2008 Nokia Corporation | |
6 | * Contact: Felipe Balbi <felipe.balbi@nokia.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | * Current status: | |
23 | * - HS USB ULPI mode works. | |
24 | * - 3-pin mode support may be added in future. | |
25 | */ | |
26 | ||
27 | #include <linux/module.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/spinlock.h> | |
32 | #include <linux/workqueue.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/usb/otg.h> | |
6747caa7 | 36 | #include <linux/phy/phy.h> |
96be39ab | 37 | #include <linux/pm_runtime.h> |
c9721438 | 38 | #include <linux/usb/musb-omap.h> |
92a6e6b3 | 39 | #include <linux/usb/ulpi.h> |
b07682b6 | 40 | #include <linux/i2c/twl.h> |
66760169 JH |
41 | #include <linux/regulator/consumer.h> |
42 | #include <linux/err.h> | |
5a0e3ad6 | 43 | #include <linux/slab.h> |
9ebd9616 DB |
44 | |
45 | /* Register defines */ | |
46 | ||
9ebd9616 | 47 | #define MCPC_CTRL 0x30 |
9ebd9616 DB |
48 | #define MCPC_CTRL_RTSOL (1 << 7) |
49 | #define MCPC_CTRL_EXTSWR (1 << 6) | |
50 | #define MCPC_CTRL_EXTSWC (1 << 5) | |
51 | #define MCPC_CTRL_VOICESW (1 << 4) | |
52 | #define MCPC_CTRL_OUT64K (1 << 3) | |
53 | #define MCPC_CTRL_RTSCTSSW (1 << 2) | |
54 | #define MCPC_CTRL_HS_UART (1 << 0) | |
55 | ||
56 | #define MCPC_IO_CTRL 0x33 | |
9ebd9616 DB |
57 | #define MCPC_IO_CTRL_MICBIASEN (1 << 5) |
58 | #define MCPC_IO_CTRL_CTS_NPU (1 << 4) | |
59 | #define MCPC_IO_CTRL_RXD_PU (1 << 3) | |
60 | #define MCPC_IO_CTRL_TXDTYP (1 << 2) | |
61 | #define MCPC_IO_CTRL_CTSTYP (1 << 1) | |
62 | #define MCPC_IO_CTRL_RTSTYP (1 << 0) | |
63 | ||
64 | #define MCPC_CTRL2 0x36 | |
9ebd9616 DB |
65 | #define MCPC_CTRL2_MCPC_CK_EN (1 << 0) |
66 | ||
67 | #define OTHER_FUNC_CTRL 0x80 | |
9ebd9616 DB |
68 | #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4) |
69 | #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2) | |
70 | ||
71 | #define OTHER_IFC_CTRL 0x83 | |
9ebd9616 DB |
72 | #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6) |
73 | #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5) | |
74 | #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4) | |
75 | #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3) | |
76 | #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2) | |
77 | #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0) | |
78 | ||
79 | #define OTHER_INT_EN_RISE 0x86 | |
9ebd9616 | 80 | #define OTHER_INT_EN_FALL 0x89 |
9ebd9616 DB |
81 | #define OTHER_INT_STS 0x8C |
82 | #define OTHER_INT_LATCH 0x8D | |
83 | #define OTHER_INT_VB_SESS_VLD (1 << 7) | |
84 | #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */ | |
85 | #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */ | |
86 | #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */ | |
87 | #define OTHER_INT_MANU (1 << 1) | |
88 | #define OTHER_INT_ABNORMAL_STRESS (1 << 0) | |
89 | ||
90 | #define ID_STATUS 0x96 | |
91 | #define ID_RES_FLOAT (1 << 4) | |
92 | #define ID_RES_440K (1 << 3) | |
93 | #define ID_RES_200K (1 << 2) | |
94 | #define ID_RES_102K (1 << 1) | |
95 | #define ID_RES_GND (1 << 0) | |
96 | ||
97 | #define POWER_CTRL 0xAC | |
9ebd9616 DB |
98 | #define POWER_CTRL_OTG_ENAB (1 << 5) |
99 | ||
100 | #define OTHER_IFC_CTRL2 0xAF | |
9ebd9616 DB |
101 | #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4) |
102 | #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3) | |
103 | #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2) | |
104 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */ | |
105 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0) | |
106 | #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0) | |
107 | ||
108 | #define REG_CTRL_EN 0xB2 | |
9ebd9616 DB |
109 | #define REG_CTRL_ERROR 0xB5 |
110 | #define ULPI_I2C_CONFLICT_INTEN (1 << 0) | |
111 | ||
112 | #define OTHER_FUNC_CTRL2 0xB8 | |
9ebd9616 DB |
113 | #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0) |
114 | ||
115 | /* following registers do not have separate _clr and _set registers */ | |
116 | #define VBUS_DEBOUNCE 0xC0 | |
117 | #define ID_DEBOUNCE 0xC1 | |
118 | #define VBAT_TIMER 0xD3 | |
119 | #define PHY_PWR_CTRL 0xFD | |
120 | #define PHY_PWR_PHYPWD (1 << 0) | |
121 | #define PHY_CLK_CTRL 0xFE | |
122 | #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2) | |
123 | #define PHY_CLK_CTRL_CLK32K_EN (1 << 1) | |
124 | #define REQ_PHY_DPLL_CLK (1 << 0) | |
125 | #define PHY_CLK_CTRL_STS 0xFF | |
126 | #define PHY_DPLL_CLK (1 << 0) | |
127 | ||
9d94e16b | 128 | /* In module TWL_MODULE_PM_MASTER */ |
def6f8b9 | 129 | #define STS_HW_CONDITIONS 0x0F |
9ebd9616 | 130 | |
9d94e16b | 131 | /* In module TWL_MODULE_PM_RECEIVER */ |
9ebd9616 DB |
132 | #define VUSB_DEDICATED1 0x7D |
133 | #define VUSB_DEDICATED2 0x7E | |
134 | #define VUSB1V5_DEV_GRP 0x71 | |
135 | #define VUSB1V5_TYPE 0x72 | |
136 | #define VUSB1V5_REMAP 0x73 | |
137 | #define VUSB1V8_DEV_GRP 0x74 | |
138 | #define VUSB1V8_TYPE 0x75 | |
139 | #define VUSB1V8_REMAP 0x76 | |
140 | #define VUSB3V1_DEV_GRP 0x77 | |
141 | #define VUSB3V1_TYPE 0x78 | |
142 | #define VUSB3V1_REMAP 0x79 | |
143 | ||
144 | /* In module TWL4030_MODULE_INTBR */ | |
145 | #define PMBR1 0x0D | |
146 | #define GPIO_USB_4PIN_ULPI_2430C (3 << 0) | |
147 | ||
9ebd9616 | 148 | struct twl4030_usb { |
74d4aa44 | 149 | struct usb_phy phy; |
9ebd9616 DB |
150 | struct device *dev; |
151 | ||
66760169 JH |
152 | /* TWL4030 internal USB regulator supplies */ |
153 | struct regulator *usb1v5; | |
154 | struct regulator *usb1v8; | |
155 | struct regulator *usb3v1; | |
156 | ||
9ebd9616 DB |
157 | /* for vbus reporting with irqs disabled */ |
158 | spinlock_t lock; | |
159 | ||
160 | /* pin configuration */ | |
161 | enum twl4030_usb_mode usb_mode; | |
162 | ||
163 | int irq; | |
c9721438 | 164 | enum omap_musb_vbus_id_status linkstat; |
a87103a6 | 165 | bool vbus_supplied; |
9ebd9616 | 166 | u8 asleep; |
249751f2 GI |
167 | |
168 | struct delayed_work id_workaround_work; | |
9ebd9616 DB |
169 | }; |
170 | ||
171 | /* internal define on top of container_of */ | |
74d4aa44 | 172 | #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy) |
9ebd9616 DB |
173 | |
174 | /*-------------------------------------------------------------------------*/ | |
175 | ||
176 | static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl, | |
177 | u8 module, u8 data, u8 address) | |
178 | { | |
179 | u8 check; | |
180 | ||
fc7b92fc B |
181 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
182 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
183 | (check == data)) |
184 | return 0; | |
185 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
186 | 1, module, address, check, data); | |
187 | ||
188 | /* Failed once: Try again */ | |
fc7b92fc B |
189 | if ((twl_i2c_write_u8(module, data, address) >= 0) && |
190 | (twl_i2c_read_u8(module, &check, address) >= 0) && | |
9ebd9616 DB |
191 | (check == data)) |
192 | return 0; | |
193 | dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n", | |
194 | 2, module, address, check, data); | |
195 | ||
196 | /* Failed again: Return error */ | |
197 | return -EBUSY; | |
198 | } | |
199 | ||
200 | #define twl4030_usb_write_verify(twl, address, data) \ | |
9d94e16b | 201 | twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address)) |
9ebd9616 DB |
202 | |
203 | static inline int twl4030_usb_write(struct twl4030_usb *twl, | |
204 | u8 address, u8 data) | |
205 | { | |
206 | int ret = 0; | |
207 | ||
9d94e16b | 208 | ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address); |
9ebd9616 DB |
209 | if (ret < 0) |
210 | dev_dbg(twl->dev, | |
211 | "TWL4030:USB:Write[0x%x] Error %d\n", address, ret); | |
212 | return ret; | |
213 | } | |
214 | ||
215 | static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address) | |
216 | { | |
217 | u8 data; | |
218 | int ret = 0; | |
219 | ||
fc7b92fc | 220 | ret = twl_i2c_read_u8(module, &data, address); |
9ebd9616 DB |
221 | if (ret >= 0) |
222 | ret = data; | |
223 | else | |
224 | dev_dbg(twl->dev, | |
225 | "TWL4030:readb[0x%x,0x%x] Error %d\n", | |
226 | module, address, ret); | |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
231 | static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address) | |
232 | { | |
9d94e16b | 233 | return twl4030_readb(twl, TWL_MODULE_USB, address); |
9ebd9616 DB |
234 | } |
235 | ||
236 | /*-------------------------------------------------------------------------*/ | |
237 | ||
238 | static inline int | |
239 | twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
240 | { | |
92a6e6b3 | 241 | return twl4030_usb_write(twl, ULPI_SET(reg), bits); |
9ebd9616 DB |
242 | } |
243 | ||
244 | static inline int | |
245 | twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits) | |
246 | { | |
92a6e6b3 | 247 | return twl4030_usb_write(twl, ULPI_CLR(reg), bits); |
9ebd9616 DB |
248 | } |
249 | ||
250 | /*-------------------------------------------------------------------------*/ | |
251 | ||
f65f4f40 GI |
252 | static bool twl4030_is_driving_vbus(struct twl4030_usb *twl) |
253 | { | |
254 | int ret; | |
255 | ||
256 | ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS); | |
257 | if (ret < 0 || !(ret & PHY_DPLL_CLK)) | |
258 | /* | |
259 | * if clocks are off, registers are not updated, | |
260 | * but we can assume we don't drive VBUS in this case | |
261 | */ | |
262 | return false; | |
263 | ||
264 | ret = twl4030_usb_read(twl, ULPI_OTG_CTRL); | |
265 | if (ret < 0) | |
266 | return false; | |
267 | ||
268 | return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false; | |
269 | } | |
270 | ||
c9721438 KVA |
271 | static enum omap_musb_vbus_id_status |
272 | twl4030_usb_linkstat(struct twl4030_usb *twl) | |
9ebd9616 DB |
273 | { |
274 | int status; | |
c9721438 | 275 | enum omap_musb_vbus_id_status linkstat = OMAP_MUSB_UNKNOWN; |
9ebd9616 | 276 | |
a87103a6 MK |
277 | twl->vbus_supplied = false; |
278 | ||
def6f8b9 DB |
279 | /* |
280 | * For ID/VBUS sensing, see manual section 15.4.8 ... | |
281 | * except when using only battery backup power, two | |
282 | * comparators produce VBUS_PRES and ID_PRES signals, | |
283 | * which don't match docs elsewhere. But ... BIT(7) | |
284 | * and BIT(2) of STS_HW_CONDITIONS, respectively, do | |
285 | * seem to match up. If either is true the USB_PRES | |
286 | * signal is active, the OTG module is activated, and | |
287 | * its interrupt may be raised (may wake the system). | |
288 | */ | |
9d94e16b | 289 | status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS); |
9ebd9616 DB |
290 | if (status < 0) |
291 | dev_err(twl->dev, "USB link status err %d\n", status); | |
def6f8b9 | 292 | else if (status & (BIT(7) | BIT(2))) { |
f65f4f40 GI |
293 | if (status & BIT(7)) { |
294 | if (twl4030_is_driving_vbus(twl)) | |
295 | status &= ~BIT(7); | |
296 | else | |
297 | twl->vbus_supplied = true; | |
298 | } | |
a87103a6 | 299 | |
def6f8b9 | 300 | if (status & BIT(2)) |
c9721438 | 301 | linkstat = OMAP_MUSB_ID_GROUND; |
f65f4f40 | 302 | else if (status & BIT(7)) |
c9721438 | 303 | linkstat = OMAP_MUSB_VBUS_VALID; |
f65f4f40 GI |
304 | else |
305 | linkstat = OMAP_MUSB_VBUS_OFF; | |
c9721438 KVA |
306 | } else { |
307 | if (twl->linkstat != OMAP_MUSB_UNKNOWN) | |
308 | linkstat = OMAP_MUSB_VBUS_OFF; | |
309 | } | |
9ebd9616 DB |
310 | |
311 | dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n", | |
312 | status, status, linkstat); | |
313 | ||
314 | /* REVISIT this assumes host and peripheral controllers | |
315 | * are registered, and that both are active... | |
316 | */ | |
317 | ||
9ebd9616 DB |
318 | return linkstat; |
319 | } | |
320 | ||
321 | static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode) | |
322 | { | |
323 | twl->usb_mode = mode; | |
324 | ||
325 | switch (mode) { | |
326 | case T2_USB_MODE_ULPI: | |
92a6e6b3 HK |
327 | twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL, |
328 | ULPI_IFC_CTRL_CARKITMODE); | |
9ebd9616 | 329 | twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); |
92a6e6b3 HK |
330 | twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL, |
331 | ULPI_FUNC_CTRL_XCVRSEL_MASK | | |
332 | ULPI_FUNC_CTRL_OPMODE_MASK); | |
9ebd9616 DB |
333 | break; |
334 | case -1: | |
335 | /* FIXME: power on defaults */ | |
336 | break; | |
337 | default: | |
338 | dev_err(twl->dev, "unsupported T2 transceiver mode %d\n", | |
339 | mode); | |
340 | break; | |
ed093e61 | 341 | } |
9ebd9616 DB |
342 | } |
343 | ||
344 | static void twl4030_i2c_access(struct twl4030_usb *twl, int on) | |
345 | { | |
346 | unsigned long timeout; | |
347 | int val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
348 | ||
349 | if (val >= 0) { | |
350 | if (on) { | |
351 | /* enable DPLL to access PHY registers over I2C */ | |
352 | val |= REQ_PHY_DPLL_CLK; | |
353 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
354 | (u8)val) < 0); | |
355 | ||
356 | timeout = jiffies + HZ; | |
357 | while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
358 | PHY_DPLL_CLK) | |
359 | && time_before(jiffies, timeout)) | |
360 | udelay(10); | |
361 | if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & | |
362 | PHY_DPLL_CLK)) | |
363 | dev_err(twl->dev, "Timeout setting T2 HSUSB " | |
364 | "PHY DPLL clock\n"); | |
365 | } else { | |
366 | /* let ULPI control the DPLL clock */ | |
367 | val &= ~REQ_PHY_DPLL_CLK; | |
368 | WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, | |
369 | (u8)val) < 0); | |
370 | } | |
371 | } | |
372 | } | |
373 | ||
fc8f2a76 | 374 | static void __twl4030_phy_power(struct twl4030_usb *twl, int on) |
9ebd9616 | 375 | { |
fc8f2a76 ML |
376 | u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); |
377 | ||
378 | if (on) | |
379 | pwr &= ~PHY_PWR_PHYPWD; | |
380 | else | |
381 | pwr |= PHY_PWR_PHYPWD; | |
9ebd9616 | 382 | |
fc8f2a76 ML |
383 | WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); |
384 | } | |
385 | ||
386 | static void twl4030_phy_power(struct twl4030_usb *twl, int on) | |
387 | { | |
9ec602ec FB |
388 | int ret; |
389 | ||
9ebd9616 | 390 | if (on) { |
9ec602ec FB |
391 | ret = regulator_enable(twl->usb3v1); |
392 | if (ret) | |
393 | dev_err(twl->dev, "Failed to enable usb3v1\n"); | |
394 | ||
395 | ret = regulator_enable(twl->usb1v8); | |
396 | if (ret) | |
397 | dev_err(twl->dev, "Failed to enable usb1v8\n"); | |
398 | ||
66760169 JH |
399 | /* |
400 | * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP | |
401 | * in twl4030) resets the VUSB_DEDICATED2 register. This reset | |
402 | * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to | |
403 | * SLEEP. We work around this by clearing the bit after usv3v1 | |
404 | * is re-activated. This ensures that VUSB3V1 is really active. | |
405 | */ | |
9d94e16b | 406 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); |
9ec602ec FB |
407 | |
408 | ret = regulator_enable(twl->usb1v5); | |
409 | if (ret) | |
410 | dev_err(twl->dev, "Failed to enable usb1v5\n"); | |
411 | ||
fc8f2a76 | 412 | __twl4030_phy_power(twl, 1); |
9ebd9616 DB |
413 | twl4030_usb_write(twl, PHY_CLK_CTRL, |
414 | twl4030_usb_read(twl, PHY_CLK_CTRL) | | |
415 | (PHY_CLK_CTRL_CLOCKGATING_EN | | |
416 | PHY_CLK_CTRL_CLK32K_EN)); | |
fc8f2a76 ML |
417 | } else { |
418 | __twl4030_phy_power(twl, 0); | |
66760169 JH |
419 | regulator_disable(twl->usb1v5); |
420 | regulator_disable(twl->usb1v8); | |
421 | regulator_disable(twl->usb3v1); | |
9ebd9616 DB |
422 | } |
423 | } | |
424 | ||
96be39ab | 425 | static int twl4030_usb_runtime_suspend(struct device *dev) |
9ebd9616 | 426 | { |
96be39ab | 427 | struct twl4030_usb *twl = dev_get_drvdata(dev); |
f1ddc24c | 428 | |
96be39ab | 429 | dev_dbg(twl->dev, "%s\n", __func__); |
9ebd9616 | 430 | if (twl->asleep) |
f1ddc24c | 431 | return 0; |
9ebd9616 DB |
432 | |
433 | twl4030_phy_power(twl, 0); | |
434 | twl->asleep = 1; | |
96be39ab | 435 | |
6747caa7 KVA |
436 | return 0; |
437 | } | |
438 | ||
96be39ab | 439 | static int twl4030_usb_runtime_resume(struct device *dev) |
9ebd9616 | 440 | { |
96be39ab TL |
441 | struct twl4030_usb *twl = dev_get_drvdata(dev); |
442 | ||
443 | dev_dbg(twl->dev, "%s\n", __func__); | |
444 | if (!twl->asleep) | |
445 | return 0; | |
446 | ||
9ebd9616 | 447 | twl4030_phy_power(twl, 1); |
96be39ab TL |
448 | twl->asleep = 0; |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static int twl4030_phy_power_off(struct phy *phy) | |
454 | { | |
455 | struct twl4030_usb *twl = phy_get_drvdata(phy); | |
456 | ||
457 | dev_dbg(twl->dev, "%s\n", __func__); | |
458 | pm_runtime_mark_last_busy(twl->dev); | |
459 | pm_runtime_put_autosuspend(twl->dev); | |
460 | ||
461 | return 0; | |
fc8f2a76 ML |
462 | } |
463 | ||
f1ddc24c | 464 | static int twl4030_phy_power_on(struct phy *phy) |
fc8f2a76 | 465 | { |
f1ddc24c KVA |
466 | struct twl4030_usb *twl = phy_get_drvdata(phy); |
467 | ||
fc8f2a76 | 468 | dev_dbg(twl->dev, "%s\n", __func__); |
96be39ab TL |
469 | pm_runtime_get_sync(twl->dev); |
470 | twl4030_i2c_access(twl, 1); | |
471 | twl4030_usb_set_mode(twl, twl->usb_mode); | |
472 | if (twl->usb_mode == T2_USB_MODE_ULPI) | |
473 | twl4030_i2c_access(twl, 0); | |
249751f2 GI |
474 | |
475 | /* | |
476 | * XXX When VBUS gets driven after musb goes to A mode, | |
477 | * ID_PRES related interrupts no longer arrive, why? | |
478 | * Register itself is updated fine though, so we must poll. | |
479 | */ | |
480 | if (twl->linkstat == OMAP_MUSB_ID_GROUND) { | |
481 | cancel_delayed_work(&twl->id_workaround_work); | |
482 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
483 | } | |
6747caa7 KVA |
484 | return 0; |
485 | } | |
486 | ||
66760169 | 487 | static int twl4030_usb_ldo_init(struct twl4030_usb *twl) |
9ebd9616 DB |
488 | { |
489 | /* Enable writing to power configuration registers */ | |
9d94e16b PU |
490 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1, |
491 | TWL4030_PM_MASTER_PROTECT_KEY); | |
e7944d82 | 492 | |
9d94e16b PU |
493 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2, |
494 | TWL4030_PM_MASTER_PROTECT_KEY); | |
9ebd9616 | 495 | |
fc8f2a76 | 496 | /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/ |
9d94e16b | 497 | /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/ |
9ebd9616 DB |
498 | |
499 | /* input to VUSB3V1 LDO is from VBAT, not VBUS */ | |
9d94e16b | 500 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1); |
9ebd9616 | 501 | |
66760169 | 502 | /* Initialize 3.1V regulator */ |
9d94e16b | 503 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP); |
66760169 | 504 | |
9166902c | 505 | twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1"); |
66760169 JH |
506 | if (IS_ERR(twl->usb3v1)) |
507 | return -ENODEV; | |
508 | ||
9d94e16b | 509 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE); |
9ebd9616 | 510 | |
66760169 | 511 | /* Initialize 1.5V regulator */ |
9d94e16b | 512 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP); |
66760169 | 513 | |
9166902c | 514 | twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5"); |
66760169 | 515 | if (IS_ERR(twl->usb1v5)) |
9166902c | 516 | return -ENODEV; |
66760169 | 517 | |
9d94e16b | 518 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE); |
9ebd9616 | 519 | |
66760169 | 520 | /* Initialize 1.8V regulator */ |
9d94e16b | 521 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP); |
66760169 | 522 | |
9166902c | 523 | twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8"); |
66760169 | 524 | if (IS_ERR(twl->usb1v8)) |
9166902c | 525 | return -ENODEV; |
66760169 | 526 | |
9d94e16b | 527 | twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE); |
9ebd9616 DB |
528 | |
529 | /* disable access to power configuration registers */ | |
9d94e16b PU |
530 | twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0, |
531 | TWL4030_PM_MASTER_PROTECT_KEY); | |
66760169 JH |
532 | |
533 | return 0; | |
9ebd9616 DB |
534 | } |
535 | ||
536 | static ssize_t twl4030_usb_vbus_show(struct device *dev, | |
537 | struct device_attribute *attr, char *buf) | |
538 | { | |
539 | struct twl4030_usb *twl = dev_get_drvdata(dev); | |
540 | unsigned long flags; | |
541 | int ret = -EINVAL; | |
542 | ||
543 | spin_lock_irqsave(&twl->lock, flags); | |
544 | ret = sprintf(buf, "%s\n", | |
a87103a6 | 545 | twl->vbus_supplied ? "on" : "off"); |
9ebd9616 DB |
546 | spin_unlock_irqrestore(&twl->lock, flags); |
547 | ||
548 | return ret; | |
549 | } | |
550 | static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL); | |
551 | ||
552 | static irqreturn_t twl4030_usb_irq(int irq, void *_twl) | |
553 | { | |
554 | struct twl4030_usb *twl = _twl; | |
c9721438 | 555 | enum omap_musb_vbus_id_status status; |
249751f2 | 556 | bool status_changed = false; |
9ebd9616 | 557 | |
9ebd9616 | 558 | status = twl4030_usb_linkstat(twl); |
249751f2 GI |
559 | |
560 | spin_lock_irq(&twl->lock); | |
561 | if (status >= 0 && status != twl->linkstat) { | |
562 | twl->linkstat = status; | |
563 | status_changed = true; | |
564 | } | |
565 | spin_unlock_irq(&twl->lock); | |
566 | ||
567 | if (status_changed) { | |
9ebd9616 DB |
568 | /* FIXME add a set_power() method so that B-devices can |
569 | * configure the charger appropriately. It's not always | |
570 | * correct to consume VBUS power, and how much current to | |
571 | * consume is a function of the USB configuration chosen | |
572 | * by the host. | |
573 | * | |
574 | * REVISIT usb_gadget_vbus_connect(...) as needed, ditto | |
575 | * its disconnect() sibling, when changing to/from the | |
576 | * USB_LINK_VBUS state. musb_hdrc won't care until it | |
577 | * starts to handle softconnect right. | |
578 | */ | |
96be39ab TL |
579 | if ((status == OMAP_MUSB_VBUS_VALID) || |
580 | (status == OMAP_MUSB_ID_GROUND)) { | |
581 | if (twl->asleep) | |
582 | pm_runtime_get_sync(twl->dev); | |
583 | } else { | |
584 | if (!twl->asleep) { | |
585 | pm_runtime_mark_last_busy(twl->dev); | |
586 | pm_runtime_put_autosuspend(twl->dev); | |
587 | } | |
588 | } | |
249751f2 | 589 | omap_musb_mailbox(status); |
9ebd9616 | 590 | } |
85601b8d TL |
591 | |
592 | /* don't schedule during sleep - irq works right then */ | |
593 | if (status == OMAP_MUSB_ID_GROUND && !twl->asleep) { | |
594 | cancel_delayed_work(&twl->id_workaround_work); | |
595 | schedule_delayed_work(&twl->id_workaround_work, HZ); | |
596 | } | |
597 | ||
598 | if (irq) | |
599 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); | |
9ebd9616 DB |
600 | |
601 | return IRQ_HANDLED; | |
602 | } | |
603 | ||
249751f2 | 604 | static void twl4030_id_workaround_work(struct work_struct *work) |
fc8f2a76 | 605 | { |
249751f2 GI |
606 | struct twl4030_usb *twl = container_of(work, struct twl4030_usb, |
607 | id_workaround_work.work); | |
249751f2 | 608 | |
85601b8d | 609 | twl4030_usb_irq(0, twl); |
249751f2 GI |
610 | } |
611 | ||
f1ddc24c | 612 | static int twl4030_phy_init(struct phy *phy) |
fc8f2a76 | 613 | { |
f1ddc24c | 614 | struct twl4030_usb *twl = phy_get_drvdata(phy); |
c9721438 | 615 | enum omap_musb_vbus_id_status status; |
fc8f2a76 | 616 | |
96be39ab | 617 | pm_runtime_get_sync(twl->dev); |
44a50d08 | 618 | status = twl4030_usb_linkstat(twl); |
249751f2 GI |
619 | twl->linkstat = status; |
620 | ||
96be39ab | 621 | if (status == OMAP_MUSB_ID_GROUND || status == OMAP_MUSB_VBUS_VALID) |
c9721438 | 622 | omap_musb_mailbox(twl->linkstat); |
44a50d08 | 623 | |
fc8f2a76 | 624 | sysfs_notify(&twl->dev->kobj, NULL, "vbus"); |
96be39ab TL |
625 | pm_runtime_mark_last_busy(twl->dev); |
626 | pm_runtime_put_autosuspend(twl->dev); | |
627 | ||
817e5f33 | 628 | return 0; |
fc8f2a76 ML |
629 | } |
630 | ||
74d4aa44 HK |
631 | static int twl4030_set_peripheral(struct usb_otg *otg, |
632 | struct usb_gadget *gadget) | |
9ebd9616 | 633 | { |
74d4aa44 | 634 | if (!otg) |
9ebd9616 DB |
635 | return -ENODEV; |
636 | ||
74d4aa44 | 637 | otg->gadget = gadget; |
9ebd9616 | 638 | if (!gadget) |
74d4aa44 | 639 | otg->phy->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
640 | |
641 | return 0; | |
642 | } | |
643 | ||
74d4aa44 | 644 | static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host) |
9ebd9616 | 645 | { |
74d4aa44 | 646 | if (!otg) |
9ebd9616 DB |
647 | return -ENODEV; |
648 | ||
74d4aa44 | 649 | otg->host = host; |
9ebd9616 | 650 | if (!host) |
74d4aa44 | 651 | otg->phy->state = OTG_STATE_UNDEFINED; |
9ebd9616 DB |
652 | |
653 | return 0; | |
654 | } | |
655 | ||
6747caa7 KVA |
656 | static const struct phy_ops ops = { |
657 | .init = twl4030_phy_init, | |
658 | .power_on = twl4030_phy_power_on, | |
659 | .power_off = twl4030_phy_power_off, | |
660 | .owner = THIS_MODULE, | |
661 | }; | |
662 | ||
96be39ab TL |
663 | static const struct dev_pm_ops twl4030_usb_pm_ops = { |
664 | SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend, | |
665 | twl4030_usb_runtime_resume, NULL) | |
666 | }; | |
667 | ||
41ac7b3a | 668 | static int twl4030_usb_probe(struct platform_device *pdev) |
9ebd9616 | 669 | { |
19f9e188 | 670 | struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev); |
9ebd9616 | 671 | struct twl4030_usb *twl; |
6747caa7 | 672 | struct phy *phy; |
66760169 | 673 | int status, err; |
74d4aa44 | 674 | struct usb_otg *otg; |
f8515f06 | 675 | struct device_node *np = pdev->dev.of_node; |
6747caa7 KVA |
676 | struct phy_provider *phy_provider; |
677 | struct phy_init_data *init_data = NULL; | |
9ebd9616 | 678 | |
b6d790f7 | 679 | twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL); |
9ebd9616 DB |
680 | if (!twl) |
681 | return -ENOMEM; | |
682 | ||
f8515f06 KVA |
683 | if (np) |
684 | of_property_read_u32(np, "usb_mode", | |
685 | (enum twl4030_usb_mode *)&twl->usb_mode); | |
6747caa7 | 686 | else if (pdata) { |
f8515f06 | 687 | twl->usb_mode = pdata->usb_mode; |
6747caa7 KVA |
688 | init_data = pdata->init_data; |
689 | } else { | |
f8515f06 KVA |
690 | dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); |
691 | return -EINVAL; | |
692 | } | |
693 | ||
b6d790f7 | 694 | otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL); |
b8a3efa3 | 695 | if (!otg) |
74d4aa44 | 696 | return -ENOMEM; |
74d4aa44 | 697 | |
9ebd9616 DB |
698 | twl->dev = &pdev->dev; |
699 | twl->irq = platform_get_irq(pdev, 0); | |
a87103a6 | 700 | twl->vbus_supplied = false; |
74d4aa44 | 701 | twl->asleep = 1; |
c9721438 | 702 | twl->linkstat = OMAP_MUSB_UNKNOWN; |
74d4aa44 HK |
703 | |
704 | twl->phy.dev = twl->dev; | |
705 | twl->phy.label = "twl4030"; | |
706 | twl->phy.otg = otg; | |
c11747f6 | 707 | twl->phy.type = USB_PHY_TYPE_USB2; |
74d4aa44 HK |
708 | |
709 | otg->phy = &twl->phy; | |
710 | otg->set_host = twl4030_set_host; | |
711 | otg->set_peripheral = twl4030_set_peripheral; | |
9ebd9616 | 712 | |
f0ed8176 | 713 | phy = devm_phy_create(twl->dev, NULL, &ops, init_data); |
6747caa7 KVA |
714 | if (IS_ERR(phy)) { |
715 | dev_dbg(&pdev->dev, "Failed to create PHY\n"); | |
716 | return PTR_ERR(phy); | |
717 | } | |
718 | ||
719 | phy_set_drvdata(phy, twl); | |
720 | ||
64fe1891 KVA |
721 | phy_provider = devm_of_phy_provider_register(twl->dev, |
722 | of_phy_simple_xlate); | |
723 | if (IS_ERR(phy_provider)) | |
724 | return PTR_ERR(phy_provider); | |
725 | ||
9ebd9616 DB |
726 | /* init spinlock for workqueue */ |
727 | spin_lock_init(&twl->lock); | |
728 | ||
249751f2 GI |
729 | INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work); |
730 | ||
66760169 JH |
731 | err = twl4030_usb_ldo_init(twl); |
732 | if (err) { | |
733 | dev_err(&pdev->dev, "ldo init failed\n"); | |
66760169 JH |
734 | return err; |
735 | } | |
c11747f6 | 736 | usb_add_phy_dev(&twl->phy); |
9ebd9616 DB |
737 | |
738 | platform_set_drvdata(pdev, twl); | |
739 | if (device_create_file(&pdev->dev, &dev_attr_vbus)) | |
740 | dev_warn(&pdev->dev, "could not create sysfs file\n"); | |
741 | ||
80d2e76c PR |
742 | ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier); |
743 | ||
96be39ab TL |
744 | pm_runtime_use_autosuspend(&pdev->dev); |
745 | pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); | |
746 | pm_runtime_enable(&pdev->dev); | |
747 | pm_runtime_get_sync(&pdev->dev); | |
748 | ||
9ebd9616 DB |
749 | /* Our job is to use irqs and status from the power module |
750 | * to keep the transceiver disabled when nothing's connected. | |
751 | * | |
752 | * FIXME we actually shouldn't start enabling it until the | |
753 | * USB controller drivers have said they're ready, by calling | |
754 | * set_host() and/or set_peripheral() ... OTG_capable boards | |
755 | * need both handles, otherwise just one suffices. | |
756 | */ | |
9166902c KVA |
757 | status = devm_request_threaded_irq(twl->dev, twl->irq, NULL, |
758 | twl4030_usb_irq, IRQF_TRIGGER_FALLING | | |
759 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl); | |
9ebd9616 DB |
760 | if (status < 0) { |
761 | dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n", | |
762 | twl->irq, status); | |
9ebd9616 DB |
763 | return status; |
764 | } | |
765 | ||
96be39ab TL |
766 | pm_runtime_mark_last_busy(&pdev->dev); |
767 | pm_runtime_put_autosuspend(twl->dev); | |
768 | ||
9ebd9616 DB |
769 | dev_info(&pdev->dev, "Initialized TWL4030 USB module\n"); |
770 | return 0; | |
771 | } | |
772 | ||
39d35681 | 773 | static int twl4030_usb_remove(struct platform_device *pdev) |
9ebd9616 DB |
774 | { |
775 | struct twl4030_usb *twl = platform_get_drvdata(pdev); | |
776 | int val; | |
777 | ||
96be39ab | 778 | pm_runtime_get_sync(twl->dev); |
249751f2 | 779 | cancel_delayed_work(&twl->id_workaround_work); |
9ebd9616 DB |
780 | device_remove_file(twl->dev, &dev_attr_vbus); |
781 | ||
782 | /* set transceiver mode to power on defaults */ | |
783 | twl4030_usb_set_mode(twl, -1); | |
784 | ||
785 | /* autogate 60MHz ULPI clock, | |
786 | * clear dpll clock request for i2c access, | |
787 | * disable 32KHz | |
788 | */ | |
789 | val = twl4030_usb_read(twl, PHY_CLK_CTRL); | |
790 | if (val >= 0) { | |
791 | val |= PHY_CLK_CTRL_CLOCKGATING_EN; | |
792 | val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK); | |
793 | twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val); | |
794 | } | |
795 | ||
796 | /* disable complete OTG block */ | |
797 | twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB); | |
96be39ab TL |
798 | pm_runtime_mark_last_busy(twl->dev); |
799 | pm_runtime_put(twl->dev); | |
9ebd9616 | 800 | |
9ebd9616 DB |
801 | return 0; |
802 | } | |
803 | ||
f8515f06 KVA |
804 | #ifdef CONFIG_OF |
805 | static const struct of_device_id twl4030_usb_id_table[] = { | |
806 | { .compatible = "ti,twl4030-usb" }, | |
807 | {} | |
808 | }; | |
809 | MODULE_DEVICE_TABLE(of, twl4030_usb_id_table); | |
810 | #endif | |
811 | ||
9ebd9616 DB |
812 | static struct platform_driver twl4030_usb_driver = { |
813 | .probe = twl4030_usb_probe, | |
39d35681 | 814 | .remove = twl4030_usb_remove, |
9ebd9616 DB |
815 | .driver = { |
816 | .name = "twl4030_usb", | |
96be39ab | 817 | .pm = &twl4030_usb_pm_ops, |
9ebd9616 | 818 | .owner = THIS_MODULE, |
f8515f06 | 819 | .of_match_table = of_match_ptr(twl4030_usb_id_table), |
9ebd9616 DB |
820 | }, |
821 | }; | |
822 | ||
823 | static int __init twl4030_usb_init(void) | |
824 | { | |
825 | return platform_driver_register(&twl4030_usb_driver); | |
826 | } | |
827 | subsys_initcall(twl4030_usb_init); | |
828 | ||
829 | static void __exit twl4030_usb_exit(void) | |
830 | { | |
831 | platform_driver_unregister(&twl4030_usb_driver); | |
832 | } | |
833 | module_exit(twl4030_usb_exit); | |
834 | ||
835 | MODULE_ALIAS("platform:twl4030_usb"); | |
836 | MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation"); | |
837 | MODULE_DESCRIPTION("TWL4030 USB transceiver driver"); | |
838 | MODULE_LICENSE("GPL"); |