[deliverable/linux.git] / drivers / pinctrl / intel / Kconfig

#
# Intel pin control drivers
#

config PINCTRL_BAYTRAIL
	bool "Intel Baytrail GPIO pin control"
	depends on GPIOLIB && ACPI
	select GPIOLIB_IRQCHIP
	help
	  driver for memory mapped GPIO functionality on Intel Baytrail
	  platforms. Supports 3 banks with 102, 28 and 44 gpios.
	  Most pins are usually muxed to some other functionality by firmware,
	  so only a small amount is available for gpio use.

	  Requires ACPI device enumeration code to set up a platform device.

config PINCTRL_CHERRYVIEW
	tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
	depends on ACPI
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	select GPIOLIB
	select GPIOLIB_IRQCHIP
	help
	  Cherryview/Braswell pinctrl driver provides an interface that
	  allows configuring of SoC pins and using them as GPIOs.

config PINCTRL_INTEL
	tristate
	select PINMUX
	select PINCONF
	select GENERIC_PINCONF
	select GPIOLIB
	select GPIOLIB_IRQCHIP

config PINCTRL_BROXTON
	tristate "Intel Broxton pinctrl and GPIO driver"
	depends on ACPI
	select PINCTRL_INTEL
	help
	  Broxton pinctrl driver provides an interface that allows
	  configuring of SoC pins and using them as GPIOs.

config PINCTRL_SUNRISEPOINT
	tristate "Intel Sunrisepoint pinctrl and GPIO driver"
	depends on ACPI
	select PINCTRL_INTEL
	help
	  Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
	  provides an interface that allows configuring of PCH pins and
	  using them as GPIOs.
Commit	Line	Data
5fae8b86 MW	1	#
	2	# Intel pin control drivers
	3	#
	4
	5	config PINCTRL_BAYTRAIL
	6	bool "Intel Baytrail GPIO pin control"
	7	depends on GPIOLIB && ACPI
	8	select GPIOLIB_IRQCHIP
	9	help
	10	driver for memory mapped GPIO functionality on Intel Baytrail
	11	platforms. Supports 3 banks with 102, 28 and 44 gpios.
	12	Most pins are usually muxed to some other functionality by firmware,
	13	so only a small amount is available for gpio use.
	14
	15	Requires ACPI device enumeration code to set up a platform device.
6e08d6bb MW	16
	17	config PINCTRL_CHERRYVIEW
	18	tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
	19	depends on ACPI
	20	select PINMUX
	21	select PINCONF
	22	select GENERIC_PINCONF
	23	select GPIOLIB
	24	select GPIOLIB_IRQCHIP
	25	help
	26	Cherryview/Braswell pinctrl driver provides an interface that
	27	allows configuring of SoC pins and using them as GPIOs.
7981c001 MW	28
	29	config PINCTRL_INTEL
	30	tristate
	31	select PINMUX
	32	select PINCONF
	33	select GENERIC_PINCONF
	34	select GPIOLIB
	35	select GPIOLIB_IRQCHIP
	36
ee1a6ca4 MW	37	config PINCTRL_BROXTON
	38	tristate "Intel Broxton pinctrl and GPIO driver"
	39	depends on ACPI
	40	select PINCTRL_INTEL
	41	help
	42	Broxton pinctrl driver provides an interface that allows
	43	configuring of SoC pins and using them as GPIOs.
	44
7981c001 MW	45	config PINCTRL_SUNRISEPOINT
	46	tristate "Intel Sunrisepoint pinctrl and GPIO driver"
	47	depends on ACPI
	48	select PINCTRL_INTEL
	49	help
	50	Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
	51	provides an interface that allows configuring of PCH pins and
	52	using them as GPIOs.