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Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
[deliverable/linux.git] / drivers / pinctrl / intel / pinctrl-baytrail.c
CommitLineData
a5d811bb
MN		 1/*
2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
a5d811bb
MN		 15 */
16
17#include <linux/kernel.h>
a5d811bb
MN		 18#include <linux/init.h>
19#include <linux/types.h>
20#include <linux/bitops.h>
21#include <linux/interrupt.h>
86e3ef81 22#include <linux/gpio.h>
bf9a5c96 23#include <linux/gpio/driver.h>
a5d811bb 24#include <linux/acpi.h>
a5d811bb
MN		 25#include <linux/platform_device.h>
26#include <linux/seq_file.h>
27#include <linux/io.h>
28#include <linux/pm_runtime.h>
29#include <linux/pinctrl/pinctrl.h>
c501d0b1
CC		 30#include <linux/pinctrl/pinmux.h>
31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinconf-generic.h>
a5d811bb
MN		 33
34/* memory mapped register offsets */
35#define BYT_CONF0_REG 0x000
36#define BYT_CONF1_REG 0x004
37#define BYT_VAL_REG 0x008
38#define BYT_DFT_REG 0x00c
39#define BYT_INT_STAT_REG 0x800
658b476c 40#define BYT_DEBOUNCE_REG 0x9d0
a5d811bb
MN		 41
42/* BYT_CONF0_REG register bits */
3ff95885 43#define BYT_IODEN BIT(31)
ff998356 44#define BYT_DIRECT_IRQ_EN BIT(27)
a5d811bb
MN		 45#define BYT_TRIG_NEG BIT(26)
46#define BYT_TRIG_POS BIT(25)
47#define BYT_TRIG_LVL BIT(24)
658b476c 48#define BYT_DEBOUNCE_EN BIT(20)
3ff95885
MW		 49#define BYT_PULL_STR_SHIFT 9
50#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
51#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
52#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
53#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
54#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
55#define BYT_PULL_ASSIGN_SHIFT 7
56#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
57#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
58#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
a5d811bb
MN		 59#define BYT_PIN_MUX 0x07
60
61/* BYT_VAL_REG register bits */
62#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
63#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
64#define BYT_LEVEL BIT(0)
65
66#define BYT_DIR_MASK (BIT(1) | BIT(2))
67#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
68
fcc18deb
MW		 69#define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
70 BYT_PIN_MUX)
71#define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
72
658b476c
CC		 73/* BYT_DEBOUNCE_REG bits */
74#define BYT_DEBOUNCE_PULSE_MASK 0x7
75#define BYT_DEBOUNCE_PULSE_375US 1
76#define BYT_DEBOUNCE_PULSE_750US 2
77#define BYT_DEBOUNCE_PULSE_1500US 3
78#define BYT_DEBOUNCE_PULSE_3MS 4
79#define BYT_DEBOUNCE_PULSE_6MS 5
80#define BYT_DEBOUNCE_PULSE_12MS 6
81#define BYT_DEBOUNCE_PULSE_24MS 7
82
a5d811bb
MN		 83#define BYT_NGPIO_SCORE 102
84#define BYT_NGPIO_NCORE 28
85#define BYT_NGPIO_SUS 44
86
42bd0070
CKH		 87#define BYT_SCORE_ACPI_UID "1"
88#define BYT_NCORE_ACPI_UID "2"
89#define BYT_SUS_ACPI_UID "3"
90
c501d0b1
CC		 91/*
92 * This is the function value most pins have for GPIO muxing. If the value
93 * differs from the default one, it must be explicitly mentioned. Otherwise, the
94 * pin control implementation will set the muxing value to default GPIO if it
95 * does not find a match for the requested function.
96 */
97#define BYT_DEFAULT_GPIO_MUX 0
98
c8f5c4c7
CC		 99struct byt_gpio_pin_context {
100 u32 conf0;
101 u32 val;
102};
103
104struct byt_simple_func_mux {
105 const char *name;
106 unsigned short func;
107};
108
109struct byt_mixed_func_mux {
110 const char *name;
111 const unsigned short *func_values;
112};
113
114struct byt_pingroup {
115 const char *name;
116 const unsigned int *pins;
117 size_t npins;
118 unsigned short has_simple_funcs;
119 union {
120 const struct byt_simple_func_mux *simple_funcs;
121 const struct byt_mixed_func_mux *mixed_funcs;
122 };
123 size_t nfuncs;
124};
125
126struct byt_function {
127 const char *name;
128 const char * const *groups;
129 size_t ngroups;
130};
131
132struct byt_community {
133 unsigned int pin_base;
134 size_t npins;
135 const unsigned int *pad_map;
136 void __iomem *reg_base;
137};
138
139#define SIMPLE_FUNC(n, f) \
140 { \
141 .name = (n), \
142 .func = (f), \
143 }
144#define MIXED_FUNC(n, f) \
145 { \
146 .name = (n), \
147 .func_values = (f), \
148 }
149
150#define PIN_GROUP_SIMPLE(n, p, f) \
151 { \
152 .name = (n), \
153 .pins = (p), \
154 .npins = ARRAY_SIZE((p)), \
bbccb9c7
AM		 155 .has_simple_funcs = 1, \
156 { \
157 .simple_funcs = (f), \
158 }, \
c8f5c4c7
CC		 159 .nfuncs = ARRAY_SIZE((f)), \
160 }
161#define PIN_GROUP_MIXED(n, p, f) \
162 { \
163 .name = (n), \
164 .pins = (p), \
165 .npins = ARRAY_SIZE((p)), \
166 .has_simple_funcs = 0, \
bbccb9c7
AM		 167 { \
168 .mixed_funcs = (f), \
169 }, \
c8f5c4c7
CC		 170 .nfuncs = ARRAY_SIZE((f)), \
171 }
172
173#define FUNCTION(n, g) \
174 { \
175 .name = (n), \
176 .groups = (g), \
177 .ngroups = ARRAY_SIZE((g)), \
178 }
179
180#define COMMUNITY(p, n, map) \
181 { \
182 .pin_base = (p), \
183 .npins = (n), \
184 .pad_map = (map),\
185 }
a5d811bb 186
c8f5c4c7
CC		 187struct byt_pinctrl_soc_data {
188 const char *uid;
189 const struct pinctrl_pin_desc *pins;
190 size_t npins;
191 const struct byt_pingroup *groups;
192 size_t ngroups;
193 const struct byt_function *functions;
194 size_t nfunctions;
195 const struct byt_community *communities;
196 size_t ncommunities;
197};
198
71e6ca61
CC		 199struct byt_gpio {
200 struct gpio_chip chip;
201 struct platform_device *pdev;
202 struct pinctrl_dev *pctl_dev;
203 struct pinctrl_desc pctl_desc;
204 raw_spinlock_t lock;
205 const struct byt_pinctrl_soc_data *soc_data;
206 struct byt_community *communities_copy;
207 struct byt_gpio_pin_context *saved_context;
208};
209
c8f5c4c7
CC		 210/* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
211static const struct pinctrl_pin_desc byt_score_pins[] = {
212 PINCTRL_PIN(0, "SATA_GP0"),
213 PINCTRL_PIN(1, "SATA_GP1"),
214 PINCTRL_PIN(2, "SATA_LED#"),
215 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
216 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
217 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
218 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
219 PINCTRL_PIN(7, "SD3_WP"),
220 PINCTRL_PIN(8, "HDA_RST"),
221 PINCTRL_PIN(9, "HDA_SYNC"),
222 PINCTRL_PIN(10, "HDA_CLK"),
223 PINCTRL_PIN(11, "HDA_SDO"),
224 PINCTRL_PIN(12, "HDA_SDI0"),
225 PINCTRL_PIN(13, "HDA_SDI1"),
226 PINCTRL_PIN(14, "GPIO_S0_SC14"),
227 PINCTRL_PIN(15, "GPIO_S0_SC15"),
228 PINCTRL_PIN(16, "MMC1_CLK"),
229 PINCTRL_PIN(17, "MMC1_D0"),
230 PINCTRL_PIN(18, "MMC1_D1"),
231 PINCTRL_PIN(19, "MMC1_D2"),
232 PINCTRL_PIN(20, "MMC1_D3"),
233 PINCTRL_PIN(21, "MMC1_D4"),
234 PINCTRL_PIN(22, "MMC1_D5"),
235 PINCTRL_PIN(23, "MMC1_D6"),
236 PINCTRL_PIN(24, "MMC1_D7"),
237 PINCTRL_PIN(25, "MMC1_CMD"),
238 PINCTRL_PIN(26, "MMC1_RST"),
239 PINCTRL_PIN(27, "SD2_CLK"),
240 PINCTRL_PIN(28, "SD2_D0"),
241 PINCTRL_PIN(29, "SD2_D1"),
242 PINCTRL_PIN(30, "SD2_D2"),
243 PINCTRL_PIN(31, "SD2_D3_CD"),
244 PINCTRL_PIN(32, "SD2_CMD"),
245 PINCTRL_PIN(33, "SD3_CLK"),
246 PINCTRL_PIN(34, "SD3_D0"),
247 PINCTRL_PIN(35, "SD3_D1"),
248 PINCTRL_PIN(36, "SD3_D2"),
249 PINCTRL_PIN(37, "SD3_D3"),
250 PINCTRL_PIN(38, "SD3_CD"),
251 PINCTRL_PIN(39, "SD3_CMD"),
252 PINCTRL_PIN(40, "SD3_1P8EN"),
253 PINCTRL_PIN(41, "SD3_PWREN#"),
254 PINCTRL_PIN(42, "ILB_LPC_AD0"),
255 PINCTRL_PIN(43, "ILB_LPC_AD1"),
256 PINCTRL_PIN(44, "ILB_LPC_AD2"),
257 PINCTRL_PIN(45, "ILB_LPC_AD3"),
258 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
259 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
260 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
261 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
262 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
263 PINCTRL_PIN(51, "PCU_SMB_DATA"),
264 PINCTRL_PIN(52, "PCU_SMB_CLK"),
265 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
266 PINCTRL_PIN(54, "ILB_8254_SPKR"),
267 PINCTRL_PIN(55, "GPIO_S0_SC55"),
268 PINCTRL_PIN(56, "GPIO_S0_SC56"),
269 PINCTRL_PIN(57, "GPIO_S0_SC57"),
270 PINCTRL_PIN(58, "GPIO_S0_SC58"),
271 PINCTRL_PIN(59, "GPIO_S0_SC59"),
272 PINCTRL_PIN(60, "GPIO_S0_SC60"),
273 PINCTRL_PIN(61, "GPIO_S0_SC61"),
274 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
275 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
276 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
277 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
278 PINCTRL_PIN(66, "SIO_SPI_CS"),
279 PINCTRL_PIN(67, "SIO_SPI_MISO"),
280 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
281 PINCTRL_PIN(69, "SIO_SPI_CLK"),
282 PINCTRL_PIN(70, "SIO_UART1_RXD"),
283 PINCTRL_PIN(71, "SIO_UART1_TXD"),
284 PINCTRL_PIN(72, "SIO_UART1_RTS"),
285 PINCTRL_PIN(73, "SIO_UART1_CTS"),
286 PINCTRL_PIN(74, "SIO_UART2_RXD"),
287 PINCTRL_PIN(75, "SIO_UART2_TXD"),
288 PINCTRL_PIN(76, "SIO_UART2_RTS"),
289 PINCTRL_PIN(77, "SIO_UART2_CTS"),
290 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
291 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
292 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
293 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
294 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
295 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
296 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
297 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
298 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
299 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
300 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
301 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
302 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
303 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
304 PINCTRL_PIN(92, "GPIO_S0_SC92"),
305 PINCTRL_PIN(93, "GPIO_S0_SC93"),
306 PINCTRL_PIN(94, "SIO_PWM0"),
307 PINCTRL_PIN(95, "SIO_PWM1"),
308 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
309 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
310 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
311 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
312 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
313 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
314};
a5d811bb 315
c8f5c4c7
CC		 316static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
317 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
318 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
319 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
320 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
321 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
322 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
323 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
324 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
325 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
326 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
327 97, 100,
328};
329
330/* SCORE groups */
331static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
332static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
333static const struct byt_simple_func_mux byt_score_uart_mux[] = {
334 SIMPLE_FUNC("uart", 1),
335};
336
337static const unsigned int byt_score_pwm0_pins[] = { 94 };
338static const unsigned int byt_score_pwm1_pins[] = { 95 };
339static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
340 SIMPLE_FUNC("pwm", 1),
341};
342
343static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
344static const struct byt_simple_func_mux byt_score_spi_mux[] = {
345 SIMPLE_FUNC("spi", 1),
346};
347
348static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
349static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
350static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
351static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
352static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
353static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
354static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
355static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
356 SIMPLE_FUNC("i2c", 1),
357};
358
359static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
360static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
361static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
362static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
363 SIMPLE_FUNC("ssp", 1),
364};
365
366static const unsigned int byt_score_sdcard_pins[] = {
367 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
368};
369static const unsigned short byt_score_sdcard_mux_values[] = {
370 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
371};
372static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
373 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
374};
375
376static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
377static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
378 SIMPLE_FUNC("sdio", 1),
379};
380
381static const unsigned int byt_score_emmc_pins[] = {
382 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
383};
384static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
385 SIMPLE_FUNC("emmc", 1),
386};
387
388static const unsigned int byt_score_ilb_lpc_pins[] = {
389 42, 43, 44, 45, 46, 47, 48, 49, 50,
390};
391static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
392 SIMPLE_FUNC("lpc", 1),
393};
394
395static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
396static const struct byt_simple_func_mux byt_score_sata_mux[] = {
397 SIMPLE_FUNC("sata", 1),
398};
399
400static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
401static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
402static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
b41aa4f8
CC		 403static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
404static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
405static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
c8f5c4c7
CC		 406static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
407 SIMPLE_FUNC("plt_clk", 1),
a5d811bb
MN		 408};
409
c8f5c4c7
CC		 410static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
411static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
412 SIMPLE_FUNC("smbus", 1),
413};
414
415static const struct byt_pingroup byt_score_groups[] = {
416 PIN_GROUP_SIMPLE("uart1_grp",
417 byt_score_uart1_pins, byt_score_uart_mux),
418 PIN_GROUP_SIMPLE("uart2_grp",
419 byt_score_uart2_pins, byt_score_uart_mux),
420 PIN_GROUP_SIMPLE("pwm0_grp",
421 byt_score_pwm0_pins, byt_score_pwm_mux),
422 PIN_GROUP_SIMPLE("pwm1_grp",
423 byt_score_pwm1_pins, byt_score_pwm_mux),
424 PIN_GROUP_SIMPLE("ssp2_grp",
425 byt_score_ssp2_pins, byt_score_pwm_mux),
426 PIN_GROUP_SIMPLE("sio_spi_grp",
427 byt_score_sio_spi_pins, byt_score_spi_mux),
428 PIN_GROUP_SIMPLE("i2c5_grp",
429 byt_score_i2c5_pins, byt_score_i2c_mux),
430 PIN_GROUP_SIMPLE("i2c6_grp",
431 byt_score_i2c6_pins, byt_score_i2c_mux),
432 PIN_GROUP_SIMPLE("i2c4_grp",
433 byt_score_i2c4_pins, byt_score_i2c_mux),
434 PIN_GROUP_SIMPLE("i2c3_grp",
435 byt_score_i2c3_pins, byt_score_i2c_mux),
436 PIN_GROUP_SIMPLE("i2c2_grp",
437 byt_score_i2c2_pins, byt_score_i2c_mux),
438 PIN_GROUP_SIMPLE("i2c1_grp",
439 byt_score_i2c1_pins, byt_score_i2c_mux),
440 PIN_GROUP_SIMPLE("i2c0_grp",
441 byt_score_i2c0_pins, byt_score_i2c_mux),
442 PIN_GROUP_SIMPLE("ssp0_grp",
443 byt_score_ssp0_pins, byt_score_ssp_mux),
444 PIN_GROUP_SIMPLE("ssp1_grp",
445 byt_score_ssp1_pins, byt_score_ssp_mux),
446 PIN_GROUP_MIXED("sdcard_grp",
447 byt_score_sdcard_pins, byt_score_sdcard_mux),
448 PIN_GROUP_SIMPLE("sdio_grp",
449 byt_score_sdio_pins, byt_score_sdio_mux),
450 PIN_GROUP_SIMPLE("emmc_grp",
451 byt_score_emmc_pins, byt_score_emmc_mux),
452 PIN_GROUP_SIMPLE("lpc_grp",
453 byt_score_ilb_lpc_pins, byt_score_lpc_mux),
454 PIN_GROUP_SIMPLE("sata_grp",
455 byt_score_sata_pins, byt_score_sata_mux),
456 PIN_GROUP_SIMPLE("plt_clk0_grp",
457 byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
458 PIN_GROUP_SIMPLE("plt_clk1_grp",
459 byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
460 PIN_GROUP_SIMPLE("plt_clk2_grp",
461 byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
462 PIN_GROUP_SIMPLE("plt_clk3_grp",
463 byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
464 PIN_GROUP_SIMPLE("plt_clk4_grp",
465 byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
466 PIN_GROUP_SIMPLE("plt_clk5_grp",
467 byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
468 PIN_GROUP_SIMPLE("smbus_grp",
469 byt_score_smbus_pins, byt_score_smbus_mux),
470};
471
472static const char * const byt_score_uart_groups[] = {
473 "uart1_grp", "uart2_grp",
474};
475static const char * const byt_score_pwm_groups[] = {
476 "pwm0_grp", "pwm1_grp",
477};
478static const char * const byt_score_ssp_groups[] = {
479 "ssp0_grp", "ssp1_grp", "ssp2_grp",
480};
481static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
482static const char * const byt_score_i2c_groups[] = {
483 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
484 "i2c6_grp",
485};
486static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
487static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
488static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
489static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
490static const char * const byt_score_sata_groups[] = { "sata_grp" };
491static const char * const byt_score_plt_clk_groups[] = {
492 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
493 "plt_clk4_grp", "plt_clk5_grp",
494};
495static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
496static const char * const byt_score_gpio_groups[] = {
497 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
498 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
499 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
500 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
501 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
502 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
503
504};
505
506static const struct byt_function byt_score_functions[] = {
507 FUNCTION("uart", byt_score_uart_groups),
508 FUNCTION("pwm", byt_score_pwm_groups),
509 FUNCTION("ssp", byt_score_ssp_groups),
510 FUNCTION("spi", byt_score_spi_groups),
511 FUNCTION("i2c", byt_score_i2c_groups),
512 FUNCTION("sdcard", byt_score_sdcard_groups),
513 FUNCTION("sdio", byt_score_sdio_groups),
514 FUNCTION("emmc", byt_score_emmc_groups),
515 FUNCTION("lpc", byt_score_lpc_groups),
516 FUNCTION("sata", byt_score_sata_groups),
517 FUNCTION("plt_clk", byt_score_plt_clk_groups),
518 FUNCTION("smbus", byt_score_smbus_groups),
519 FUNCTION("gpio", byt_score_gpio_groups),
520};
521
522static const struct byt_community byt_score_communities[] = {
523 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
524};
525
526static const struct byt_pinctrl_soc_data byt_score_soc_data = {
527 .uid = BYT_SCORE_ACPI_UID,
528 .pins = byt_score_pins,
529 .npins = ARRAY_SIZE(byt_score_pins),
530 .groups = byt_score_groups,
531 .ngroups = ARRAY_SIZE(byt_score_groups),
532 .functions = byt_score_functions,
533 .nfunctions = ARRAY_SIZE(byt_score_functions),
534 .communities = byt_score_communities,
535 .ncommunities = ARRAY_SIZE(byt_score_communities),
536};
537
538/* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
539static const struct pinctrl_pin_desc byt_sus_pins[] = {
540 PINCTRL_PIN(0, "GPIO_S50"),
541 PINCTRL_PIN(1, "GPIO_S51"),
542 PINCTRL_PIN(2, "GPIO_S52"),
543 PINCTRL_PIN(3, "GPIO_S53"),
544 PINCTRL_PIN(4, "GPIO_S54"),
545 PINCTRL_PIN(5, "GPIO_S55"),
546 PINCTRL_PIN(6, "GPIO_S56"),
547 PINCTRL_PIN(7, "GPIO_S57"),
548 PINCTRL_PIN(8, "GPIO_S58"),
549 PINCTRL_PIN(9, "GPIO_S59"),
550 PINCTRL_PIN(10, "GPIO_S510"),
551 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
552 PINCTRL_PIN(12, "PMC_SUSCLK0"),
553 PINCTRL_PIN(13, "GPIO_S513"),
554 PINCTRL_PIN(14, "USB_ULPI_RST"),
555 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
556 PINCTRL_PIN(16, "PMC_PWRBTN"),
557 PINCTRL_PIN(17, "GPIO_S517"),
558 PINCTRL_PIN(18, "PMC_SUS_STAT"),
559 PINCTRL_PIN(19, "USB_OC0"),
560 PINCTRL_PIN(20, "USB_OC1"),
561 PINCTRL_PIN(21, "PCU_SPI_CS1"),
562 PINCTRL_PIN(22, "GPIO_S522"),
563 PINCTRL_PIN(23, "GPIO_S523"),
564 PINCTRL_PIN(24, "GPIO_S524"),
565 PINCTRL_PIN(25, "GPIO_S525"),
566 PINCTRL_PIN(26, "GPIO_S526"),
567 PINCTRL_PIN(27, "GPIO_S527"),
568 PINCTRL_PIN(28, "GPIO_S528"),
569 PINCTRL_PIN(29, "GPIO_S529"),
570 PINCTRL_PIN(30, "GPIO_S530"),
571 PINCTRL_PIN(31, "USB_ULPI_CLK"),
572 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
573 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
574 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
575 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
576 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
577 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
578 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
579 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
580 PINCTRL_PIN(40, "USB_ULPI_DIR"),
581 PINCTRL_PIN(41, "USB_ULPI_NXT"),
582 PINCTRL_PIN(42, "USB_ULPI_STP"),
583 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
584};
585
c8f5c4c7 586static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
a5d811bb
MN		 587 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
588 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
589 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
590 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
591 52, 53, 59, 40,
592};
593
c8f5c4c7
CC		 594static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
595static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
596 SIMPLE_FUNC("usb", 0),
597 SIMPLE_FUNC("gpio", 1),
598};
599
600static const unsigned int byt_sus_usb_ulpi_pins[] = {
601 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
602};
603static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
604 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
605};
606static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
607 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
608};
609static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
610 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
611 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
612};
613
614static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
615static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
616 SIMPLE_FUNC("spi", 0),
617 SIMPLE_FUNC("gpio", 1),
618};
619
620static const struct byt_pingroup byt_sus_groups[] = {
621 PIN_GROUP_SIMPLE("usb_oc_grp",
622 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
623 PIN_GROUP_MIXED("usb_ulpi_grp",
624 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
625 PIN_GROUP_SIMPLE("pcu_spi_grp",
626 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
627};
628
629static const char * const byt_sus_usb_groups[] = {
630 "usb_oc_grp", "usb_ulpi_grp",
631};
632static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
633static const char * const byt_sus_gpio_groups[] = {
634 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
635};
636
637static const struct byt_function byt_sus_functions[] = {
638 FUNCTION("usb", byt_sus_usb_groups),
639 FUNCTION("spi", byt_sus_spi_groups),
640 FUNCTION("gpio", byt_sus_gpio_groups),
641};
642
643static const struct byt_community byt_sus_communities[] = {
644 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
645};
646
647static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
648 .uid = BYT_SUS_ACPI_UID,
649 .pins = byt_sus_pins,
650 .npins = ARRAY_SIZE(byt_sus_pins),
651 .groups = byt_sus_groups,
652 .ngroups = ARRAY_SIZE(byt_sus_groups),
653 .functions = byt_sus_functions,
654 .nfunctions = ARRAY_SIZE(byt_sus_functions),
655 .communities = byt_sus_communities,
656 .ncommunities = ARRAY_SIZE(byt_sus_communities),
657};
658
659static const struct pinctrl_pin_desc byt_ncore_pins[] = {
660 PINCTRL_PIN(0, "GPIO_NCORE0"),
661 PINCTRL_PIN(1, "GPIO_NCORE1"),
662 PINCTRL_PIN(2, "GPIO_NCORE2"),
663 PINCTRL_PIN(3, "GPIO_NCORE3"),
664 PINCTRL_PIN(4, "GPIO_NCORE4"),
665 PINCTRL_PIN(5, "GPIO_NCORE5"),
666 PINCTRL_PIN(6, "GPIO_NCORE6"),
667 PINCTRL_PIN(7, "GPIO_NCORE7"),
668 PINCTRL_PIN(8, "GPIO_NCORE8"),
669 PINCTRL_PIN(9, "GPIO_NCORE9"),
670 PINCTRL_PIN(10, "GPIO_NCORE10"),
671 PINCTRL_PIN(11, "GPIO_NCORE11"),
672 PINCTRL_PIN(12, "GPIO_NCORE12"),
673 PINCTRL_PIN(13, "GPIO_NCORE13"),
674 PINCTRL_PIN(14, "GPIO_NCORE14"),
675 PINCTRL_PIN(15, "GPIO_NCORE15"),
676 PINCTRL_PIN(16, "GPIO_NCORE16"),
677 PINCTRL_PIN(17, "GPIO_NCORE17"),
678 PINCTRL_PIN(18, "GPIO_NCORE18"),
679 PINCTRL_PIN(19, "GPIO_NCORE19"),
680 PINCTRL_PIN(20, "GPIO_NCORE20"),
681 PINCTRL_PIN(21, "GPIO_NCORE21"),
682 PINCTRL_PIN(22, "GPIO_NCORE22"),
683 PINCTRL_PIN(23, "GPIO_NCORE23"),
684 PINCTRL_PIN(24, "GPIO_NCORE24"),
685 PINCTRL_PIN(25, "GPIO_NCORE25"),
686 PINCTRL_PIN(26, "GPIO_NCORE26"),
687 PINCTRL_PIN(27, "GPIO_NCORE27"),
688};
689
690static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
691 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
692 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
693 3, 6, 10, 13, 2, 5, 9, 7,
694};
695
696static const struct byt_community byt_ncore_communities[] = {
697 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
698};
699
700static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
701 .uid = BYT_NCORE_ACPI_UID,
702 .pins = byt_ncore_pins,
703 .npins = ARRAY_SIZE(byt_ncore_pins),
704 .communities = byt_ncore_communities,
705 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
706};
707
c8f5c4c7
CC		 708static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
709 &byt_score_soc_data,
710 &byt_sus_soc_data,
711 &byt_ncore_soc_data,
712 NULL,
713};
714
c501d0b1
CC		 715static struct byt_community *byt_get_community(struct byt_gpio *vg,
716 unsigned int pin)
a5d811bb 717{
c501d0b1
CC		 718 struct byt_community *comm;
719 int i;
720
721 for (i = 0; i < vg->soc_data->ncommunities; i++) {
722 comm = vg->communities_copy + i;
723 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
724 return comm;
725 }
a5d811bb 726
c501d0b1
CC		 727 return NULL;
728}
729
730static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
731 int reg)
732{
733 struct byt_community *comm = byt_get_community(vg, offset);
734 u32 reg_offset = 0;
735
736 if (!comm)
737 return NULL;
738
739 offset -= comm->pin_base;
a5d811bb
MN		 740 if (reg == BYT_INT_STAT_REG)
741 reg_offset = (offset / 32) * 4;
742 else
c501d0b1
CC		 743 reg_offset = comm->pad_map[offset] * 16;
744
745 return comm->reg_base + reg_offset + reg;
746}
747
748static int byt_get_groups_count(struct pinctrl_dev *pctldev)
749{
750 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
751
752 return vg->soc_data->ngroups;
753}
754
755static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
756 unsigned int selector)
757{
758 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
759
760 return vg->soc_data->groups[selector].name;
761}
762
763static int byt_get_group_pins(struct pinctrl_dev *pctldev,
764 unsigned int selector,
765 const unsigned int **pins,
766 unsigned int *num_pins)
767{
768 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
769
770 *pins = vg->soc_data->groups[selector].pins;
771 *num_pins = vg->soc_data->groups[selector].npins;
772
773 return 0;
774}
775
776static const struct pinctrl_ops byt_pinctrl_ops = {
777 .get_groups_count = byt_get_groups_count,
778 .get_group_name = byt_get_group_name,
779 .get_group_pins = byt_get_group_pins,
780};
781
782static int byt_get_functions_count(struct pinctrl_dev *pctldev)
783{
784 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
785
786 return vg->soc_data->nfunctions;
787}
788
789static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
790 unsigned int selector)
791{
792 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
793
794 return vg->soc_data->functions[selector].name;
795}
796
797static int byt_get_function_groups(struct pinctrl_dev *pctldev,
798 unsigned int selector,
799 const char * const **groups,
800 unsigned int *num_groups)
801{
802 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
803
804 *groups = vg->soc_data->functions[selector].groups;
805 *num_groups = vg->soc_data->functions[selector].ngroups;
806
807 return 0;
808}
809
810static int byt_get_group_simple_mux(const struct byt_pingroup group,
811 const char *func_name,
812 unsigned short *func)
813{
814 int i;
815
816 for (i = 0; i < group.nfuncs; i++) {
817 if (!strcmp(group.simple_funcs[i].name, func_name)) {
818 *func = group.simple_funcs[i].func;
819 return 0;
820 }
821 }
822
823 return 1;
824}
825
826static int byt_get_group_mixed_mux(const struct byt_pingroup group,
827 const char *func_name,
828 const unsigned short **func)
829{
830 int i;
831
832 for (i = 0; i < group.nfuncs; i++) {
833 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
834 *func = group.mixed_funcs[i].func_values;
835 return 0;
836 }
837 }
a5d811bb 838
c501d0b1 839 return 1;
a5d811bb
MN		 840}
841
c501d0b1
CC		 842static void byt_set_group_simple_mux(struct byt_gpio *vg,
843 const struct byt_pingroup group,
844 unsigned short func)
95f0972c 845{
95f0972c 846 unsigned long flags;
c501d0b1 847 int i;
95f0972c 848
78e1c896 849 raw_spin_lock_irqsave(&vg->lock, flags);
c501d0b1
CC		 850
851 for (i = 0; i < group.npins; i++) {
852 void __iomem *padcfg0;
853 u32 value;
854
855 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
856 if (!padcfg0) {
857 dev_warn(&vg->pdev->dev,
858 "Group %s, pin %i not muxed (no padcfg0)\n",
859 group.name, i);
860 continue;
861 }
862
863 value = readl(padcfg0);
864 value &= ~BYT_PIN_MUX;
865 value |= func;
866 writel(value, padcfg0);
867 }
868
78e1c896 869 raw_spin_unlock_irqrestore(&vg->lock, flags);
95f0972c
MW		 870}
871
c501d0b1
CC		 872static void byt_set_group_mixed_mux(struct byt_gpio *vg,
873 const struct byt_pingroup group,
874 const unsigned short *func)
875{
876 unsigned long flags;
877 int i;
878
879 raw_spin_lock_irqsave(&vg->lock, flags);
880
881 for (i = 0; i < group.npins; i++) {
882 void __iomem *padcfg0;
883 u32 value;
884
885 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
886 if (!padcfg0) {
887 dev_warn(&vg->pdev->dev,
888 "Group %s, pin %i not muxed (no padcfg0)\n",
889 group.name, i);
890 continue;
891 }
892
893 value = readl(padcfg0);
894 value &= ~BYT_PIN_MUX;
895 value |= func[i];
896 writel(value, padcfg0);
897 }
898
899 raw_spin_unlock_irqrestore(&vg->lock, flags);
900}
901
902static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
903 unsigned int group_selector)
904{
905 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
906 const struct byt_function func = vg->soc_data->functions[func_selector];
907 const struct byt_pingroup group = vg->soc_data->groups[group_selector];
908 const unsigned short *mixed_func;
909 unsigned short simple_func;
910 int ret = 1;
911
912 if (group.has_simple_funcs)
913 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
914 else
915 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
916
917 if (ret)
918 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
919 else if (group.has_simple_funcs)
920 byt_set_group_simple_mux(vg, group, simple_func);
921 else
922 byt_set_group_mixed_mux(vg, group, mixed_func);
923
924 return 0;
925}
926
f8323b6b 927static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
42bd0070
CKH		 928{
929 /* SCORE pin 92-93 */
c501d0b1
CC		 930 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
931 offset >= 92 && offset <= 93)
f8323b6b 932 return 1;
42bd0070
CKH		 933
934 /* SUS pin 11-21 */
c501d0b1
CC		 935 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
936 offset >= 11 && offset <= 21)
f8323b6b 937 return 1;
42bd0070 938
f8323b6b 939 return 0;
42bd0070
CKH		 940}
941
c501d0b1 942static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
a5d811bb 943{
c501d0b1
CC		 944 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
945 unsigned long flags;
946 u32 value;
947
948 raw_spin_lock_irqsave(&vg->lock, flags);
949 value = readl(reg);
950 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
951 writel(value, reg);
952 raw_spin_unlock_irqrestore(&vg->lock, flags);
953}
954
955static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
956 struct pinctrl_gpio_range *range,
957 unsigned int offset)
958{
959 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
960 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
f8323b6b 961 u32 value, gpio_mux;
39ce8150
MW		 962 unsigned long flags;
963
78e1c896 964 raw_spin_lock_irqsave(&vg->lock, flags);
42bd0070
CKH		 965
966 /*
967 * In most cases, func pin mux 000 means GPIO function.
968 * But, some pins may have func pin mux 001 represents
f8323b6b
MW		 969 * GPIO function.
970 *
971 * Because there are devices out there where some pins were not
972 * configured correctly we allow changing the mux value from
973 * request (but print out warning about that).
42bd0070
CKH		 974 */
975 value = readl(reg) & BYT_PIN_MUX;
f8323b6b
MW		 976 gpio_mux = byt_get_gpio_mux(vg, offset);
977 if (WARN_ON(gpio_mux != value)) {
f8323b6b
MW		 978 value = readl(reg) & ~BYT_PIN_MUX;
979 value |= gpio_mux;
980 writel(value, reg);
f8323b6b
MW		 981
982 dev_warn(&vg->pdev->dev,
983 "pin %u forcibly re-configured as GPIO\n", offset);
42bd0070 984 }
a5d811bb 985
78e1c896 986 raw_spin_unlock_irqrestore(&vg->lock, flags);
39ce8150 987
a5d811bb
MN		 988 pm_runtime_get(&vg->pdev->dev);
989
990 return 0;
991}
992
c501d0b1
CC		 993static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
994 struct pinctrl_gpio_range *range,
995 unsigned int offset)
996{
997 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
998
999 byt_gpio_clear_triggering(vg, offset);
1000 pm_runtime_put(&vg->pdev->dev);
1001}
1002
1003static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1004 struct pinctrl_gpio_range *range,
1005 unsigned int offset,
1006 bool input)
1007{
1008 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1009 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1010 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1011 unsigned long flags;
1012 u32 value;
1013
1014 raw_spin_lock_irqsave(&vg->lock, flags);
1015
1016 value = readl(val_reg);
1017 value &= ~BYT_DIR_MASK;
1018 if (input)
1019 value |= BYT_OUTPUT_EN;
1020 else
1021 /*
1022 * Before making any direction modifications, do a check if gpio
1023 * is set for direct IRQ. On baytrail, setting GPIO to output
1024 * does not make sense, so let's at least warn the caller before
1025 * they shoot themselves in the foot.
1026 */
1027 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
1028 "Potential Error: Setting GPIO with direct_irq_en to output");
1029 writel(value, val_reg);
1030
1031 raw_spin_unlock_irqrestore(&vg->lock, flags);
1032
1033 return 0;
1034}
1035
1036static const struct pinmux_ops byt_pinmux_ops = {
1037 .get_functions_count = byt_get_functions_count,
1038 .get_function_name = byt_get_function_name,
1039 .get_function_groups = byt_get_function_groups,
1040 .set_mux = byt_set_mux,
1041 .gpio_request_enable = byt_gpio_request_enable,
1042 .gpio_disable_free = byt_gpio_disable_free,
1043 .gpio_set_direction = byt_gpio_set_direction,
1044};
1045
c501d0b1
CC		 1046static void byt_get_pull_strength(u32 reg, u16 *strength)
1047{
1048 switch (reg & BYT_PULL_STR_MASK) {
1049 case BYT_PULL_STR_2K:
1050 *strength = 2000;
1051 break;
1052 case BYT_PULL_STR_10K:
1053 *strength = 10000;
1054 break;
1055 case BYT_PULL_STR_20K:
1056 *strength = 20000;
1057 break;
1058 case BYT_PULL_STR_40K:
1059 *strength = 40000;
1060 break;
1061 }
1062}
1063
1064static int byt_set_pull_strength(u32 *reg, u16 strength)
1065{
1066 *reg &= ~BYT_PULL_STR_MASK;
1067
1068 switch (strength) {
1069 case 2000:
1070 *reg |= BYT_PULL_STR_2K;
1071 break;
1072 case 10000:
1073 *reg |= BYT_PULL_STR_10K;
1074 break;
1075 case 20000:
1076 *reg |= BYT_PULL_STR_20K;
1077 break;
1078 case 40000:
1079 *reg |= BYT_PULL_STR_40K;
1080 break;
1081 default:
1082 return -EINVAL;
1083 }
1084
1085 return 0;
1086}
1087
1088static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1089 unsigned long *config)
1090{
1091 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1092 enum pin_config_param param = pinconf_to_config_param(*config);
1093 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1094 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1095 unsigned long flags;
658b476c 1096 u32 conf, pull, val, debounce;
c501d0b1
CC		 1097 u16 arg = 0;
1098
1099 raw_spin_lock_irqsave(&vg->lock, flags);
1100 conf = readl(conf_reg);
1101 pull = conf & BYT_PULL_ASSIGN_MASK;
1102 val = readl(val_reg);
1103 raw_spin_unlock_irqrestore(&vg->lock, flags);
1104
1105 switch (param) {
1106 case PIN_CONFIG_BIAS_DISABLE:
1107 if (pull)
1108 return -EINVAL;
1109 break;
1110 case PIN_CONFIG_BIAS_PULL_DOWN:
1111 /* Pull assignment is only applicable in input mode */
1112 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1113 return -EINVAL;
1114
1115 byt_get_pull_strength(conf, &arg);
1116
1117 break;
1118 case PIN_CONFIG_BIAS_PULL_UP:
1119 /* Pull assignment is only applicable in input mode */
1120 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1121 return -EINVAL;
1122
1123 byt_get_pull_strength(conf, &arg);
1124
658b476c
CC		 1125 break;
1126 case PIN_CONFIG_INPUT_DEBOUNCE:
1127 if (!(conf & BYT_DEBOUNCE_EN))
1128 return -EINVAL;
1129
1130 raw_spin_lock_irqsave(&vg->lock, flags);
1131 debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
1132 raw_spin_unlock_irqrestore(&vg->lock, flags);
1133
1134 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1135 case BYT_DEBOUNCE_PULSE_375US:
1136 arg = 375;
1137 break;
1138 case BYT_DEBOUNCE_PULSE_750US:
1139 arg = 750;
1140 break;
1141 case BYT_DEBOUNCE_PULSE_1500US:
1142 arg = 1500;
1143 break;
1144 case BYT_DEBOUNCE_PULSE_3MS:
1145 arg = 3000;
1146 break;
1147 case BYT_DEBOUNCE_PULSE_6MS:
1148 arg = 6000;
1149 break;
1150 case BYT_DEBOUNCE_PULSE_12MS:
1151 arg = 12000;
1152 break;
1153 case BYT_DEBOUNCE_PULSE_24MS:
1154 arg = 24000;
1155 break;
1156 default:
1157 return -EINVAL;
1158 }
1159
c501d0b1
CC		 1160 break;
1161 default:
1162 return -ENOTSUPP;
1163 }
1164
1165 *config = pinconf_to_config_packed(param, arg);
1166
1167 return 0;
1168}
1169
1170static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1171 unsigned int offset,
1172 unsigned long *configs,
1173 unsigned int num_configs)
1174{
1175 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1176 unsigned int param, arg;
1177 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1178 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1179 unsigned long flags;
658b476c 1180 u32 conf, val, debounce;
c501d0b1
CC		 1181 int i, ret = 0;
1182
1183 raw_spin_lock_irqsave(&vg->lock, flags);
1184
1185 conf = readl(conf_reg);
1186 val = readl(val_reg);
1187
1188 for (i = 0; i < num_configs; i++) {
1189 param = pinconf_to_config_param(configs[i]);
1190 arg = pinconf_to_config_argument(configs[i]);
1191
1192 switch (param) {
1193 case PIN_CONFIG_BIAS_DISABLE:
1194 conf &= ~BYT_PULL_ASSIGN_MASK;
1195 break;
1196 case PIN_CONFIG_BIAS_PULL_DOWN:
1197 /* Set default strength value in case none is given */
1198 if (arg == 1)
1199 arg = 2000;
1200
1201 /*
1202 * Pull assignment is only applicable in input mode. If
1203 * chip is not in input mode, set it and warn about it.
1204 */
1205 if (val & BYT_INPUT_EN) {
1206 val &= ~BYT_INPUT_EN;
1207 writel(val, val_reg);
1208 dev_warn(&vg->pdev->dev,
1209 "pin %u forcibly set to input mode\n",
1210 offset);
1211 }
1212
1213 conf &= ~BYT_PULL_ASSIGN_MASK;
1214 conf |= BYT_PULL_ASSIGN_DOWN;
1215 ret = byt_set_pull_strength(&conf, arg);
1216
1217 break;
1218 case PIN_CONFIG_BIAS_PULL_UP:
1219 /* Set default strength value in case none is given */
1220 if (arg == 1)
1221 arg = 2000;
1222
1223 /*
1224 * Pull assignment is only applicable in input mode. If
1225 * chip is not in input mode, set it and warn about it.
1226 */
1227 if (val & BYT_INPUT_EN) {
1228 val &= ~BYT_INPUT_EN;
1229 writel(val, val_reg);
1230 dev_warn(&vg->pdev->dev,
1231 "pin %u forcibly set to input mode\n",
1232 offset);
1233 }
1234
1235 conf &= ~BYT_PULL_ASSIGN_MASK;
1236 conf |= BYT_PULL_ASSIGN_UP;
1237 ret = byt_set_pull_strength(&conf, arg);
1238
658b476c
CC		 1239 break;
1240 case PIN_CONFIG_INPUT_DEBOUNCE:
1241 debounce = readl(byt_gpio_reg(vg, offset,
1242 BYT_DEBOUNCE_REG));
1243 conf &= ~BYT_DEBOUNCE_PULSE_MASK;
1244
1245 switch (arg) {
1246 case 375:
1247 conf |= BYT_DEBOUNCE_PULSE_375US;
1248 break;
1249 case 750:
1250 conf |= BYT_DEBOUNCE_PULSE_750US;
1251 break;
1252 case 1500:
1253 conf |= BYT_DEBOUNCE_PULSE_1500US;
1254 break;
1255 case 3000:
1256 conf |= BYT_DEBOUNCE_PULSE_3MS;
1257 break;
1258 case 6000:
1259 conf |= BYT_DEBOUNCE_PULSE_6MS;
1260 break;
1261 case 12000:
1262 conf |= BYT_DEBOUNCE_PULSE_12MS;
1263 break;
1264 case 24000:
1265 conf |= BYT_DEBOUNCE_PULSE_24MS;
1266 break;
1267 default:
1268 ret = -EINVAL;
1269 }
1270
c501d0b1
CC		 1271 break;
1272 default:
1273 ret = -ENOTSUPP;
1274 }
1275
1276 if (ret)
1277 break;
1278 }
1279
1280 if (!ret)
1281 writel(conf, conf_reg);
1282
1283 raw_spin_unlock_irqrestore(&vg->lock, flags);
1284
1285 return ret;
1286}
1287
1288static const struct pinconf_ops byt_pinconf_ops = {
1289 .is_generic = true,
1290 .pin_config_get = byt_pin_config_get,
1291 .pin_config_set = byt_pin_config_set,
1292};
1293
1294static const struct pinctrl_desc byt_pinctrl_desc = {
1295 .pctlops = &byt_pinctrl_ops,
1296 .pmxops = &byt_pinmux_ops,
1297 .confops = &byt_pinconf_ops,
1298 .owner = THIS_MODULE,
1299};
1300
a5d811bb
MN		 1301static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1302{
bf9a5c96 1303 struct byt_gpio *vg = gpiochip_get_data(chip);
c501d0b1 1304 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
39ce8150
MW		 1305 unsigned long flags;
1306 u32 val;
1307
78e1c896 1308 raw_spin_lock_irqsave(&vg->lock, flags);
39ce8150 1309 val = readl(reg);
78e1c896 1310 raw_spin_unlock_irqrestore(&vg->lock, flags);
39ce8150 1311
3bde8771 1312 return !!(val & BYT_LEVEL);
a5d811bb
MN		 1313}
1314
1315static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1316{
bf9a5c96 1317 struct byt_gpio *vg = gpiochip_get_data(chip);
c501d0b1 1318 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
a5d811bb
MN		 1319 unsigned long flags;
1320 u32 old_val;
1321
86e3ef81
CC		 1322 if (!reg)
1323 return;
a5d811bb 1324
86e3ef81 1325 raw_spin_lock_irqsave(&vg->lock, flags);
a5d811bb 1326 old_val = readl(reg);
a5d811bb
MN		 1327 if (value)
1328 writel(old_val | BYT_LEVEL, reg);
1329 else
1330 writel(old_val & ~BYT_LEVEL, reg);
78e1c896 1331 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb
MN		 1332}
1333
86e3ef81 1334static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
a5d811bb 1335{
bf9a5c96 1336 struct byt_gpio *vg = gpiochip_get_data(chip);
c501d0b1 1337 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
a5d811bb
MN		 1338 unsigned long flags;
1339 u32 value;
1340
86e3ef81
CC		 1341 if (!reg)
1342 return -EINVAL;
a5d811bb 1343
86e3ef81
CC		 1344 raw_spin_lock_irqsave(&vg->lock, flags);
1345 value = readl(reg);
78e1c896 1346 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb 1347
86e3ef81
CC		 1348 if (!(value & BYT_OUTPUT_EN))
1349 return GPIOF_DIR_OUT;
1350 if (!(value & BYT_INPUT_EN))
1351 return GPIOF_DIR_IN;
1352
1353 return -EINVAL;
a5d811bb
MN		 1354}
1355
86e3ef81 1356static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
a5d811bb 1357{
86e3ef81
CC		 1358 return pinctrl_gpio_direction_input(chip->base + offset);
1359}
1360
1361static int byt_gpio_direction_output(struct gpio_chip *chip,
1362 unsigned int offset, int value)
1363{
1364 int ret = pinctrl_gpio_direction_output(chip->base + offset);
496940c1 1365
86e3ef81
CC		 1366 if (ret)
1367 return ret;
a5d811bb 1368
86e3ef81 1369 byt_gpio_set(chip, offset, value);
a5d811bb
MN		 1370
1371 return 0;
1372}
1373
1374static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1375{
bf9a5c96 1376 struct byt_gpio *vg = gpiochip_get_data(chip);
a5d811bb 1377 int i;
86e3ef81 1378 u32 conf0, val;
a5d811bb 1379
86e3ef81
CC		 1380 for (i = 0; i < vg->soc_data->npins; i++) {
1381 const struct byt_community *comm;
3ff95885
MW		 1382 const char *pull_str = NULL;
1383 const char *pull = NULL;
86e3ef81 1384 void __iomem *reg;
78e1c896 1385 unsigned long flags;
a4d8d6da 1386 const char *label;
86e3ef81 1387 unsigned int pin;
78e1c896
MW		 1388
1389 raw_spin_lock_irqsave(&vg->lock, flags);
86e3ef81
CC		 1390 pin = vg->soc_data->pins[i].number;
1391 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1392 if (!reg) {
1393 seq_printf(s,
1394 "Could not retrieve pin %i conf0 reg\n",
1395 pin);
22bbd21b 1396 raw_spin_unlock_irqrestore(&vg->lock, flags);
86e3ef81
CC		 1397 continue;
1398 }
1399 conf0 = readl(reg);
1400
1401 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1402 if (!reg) {
1403 seq_printf(s,
1404 "Could not retrieve pin %i val reg\n", pin);
22bbd21b
DC		 1405 raw_spin_unlock_irqrestore(&vg->lock, flags);
1406 continue;
86e3ef81
CC		 1407 }
1408 val = readl(reg);
78e1c896 1409 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb 1410
86e3ef81
CC		 1411 comm = byt_get_community(vg, pin);
1412 if (!comm) {
1413 seq_printf(s,
1414 "Could not get community for pin %i\n", pin);
1415 continue;
1416 }
a4d8d6da
MN		 1417 label = gpiochip_is_requested(chip, i);
1418 if (!label)
1419 label = "Unrequested";
1420
3ff95885
MW		 1421 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1422 case BYT_PULL_ASSIGN_UP:
1423 pull = "up";
1424 break;
1425 case BYT_PULL_ASSIGN_DOWN:
1426 pull = "down";
1427 break;
1428 }
1429
1430 switch (conf0 & BYT_PULL_STR_MASK) {
1431 case BYT_PULL_STR_2K:
1432 pull_str = "2k";
1433 break;
1434 case BYT_PULL_STR_10K:
1435 pull_str = "10k";
1436 break;
1437 case BYT_PULL_STR_20K:
1438 pull_str = "20k";
1439 break;
1440 case BYT_PULL_STR_40K:
1441 pull_str = "40k";
1442 break;
1443 }
1444
a5d811bb 1445 seq_printf(s,
3ff95885 1446 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
86e3ef81 1447 pin,
a4d8d6da 1448 label,
a5d811bb
MN		 1449 val & BYT_INPUT_EN ? " " : "in",
1450 val & BYT_OUTPUT_EN ? " " : "out",
1451 val & BYT_LEVEL ? "hi" : "lo",
86e3ef81 1452 comm->pad_map[i], comm->pad_map[i] * 32,
a5d811bb 1453 conf0 & 0x7,
3ff95885
MW		 1454 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1455 conf0 & BYT_TRIG_POS ? " rise" : " ",
1456 conf0 & BYT_TRIG_LVL ? " level" : " ");
1457
1458 if (pull && pull_str)
1459 seq_printf(s, " %-4s %-3s", pull, pull_str);
1460 else
1461 seq_puts(s, " ");
1462
1463 if (conf0 & BYT_IODEN)
1464 seq_puts(s, " open-drain");
1465
1466 seq_puts(s, "\n");
a5d811bb 1467 }
a5d811bb
MN		 1468}
1469
86e3ef81
CC		 1470static const struct gpio_chip byt_gpio_chip = {
1471 .owner = THIS_MODULE,
1472 .request = gpiochip_generic_request,
1473 .free = gpiochip_generic_free,
1474 .get_direction = byt_gpio_get_direction,
1475 .direction_input = byt_gpio_direction_input,
1476 .direction_output = byt_gpio_direction_output,
1477 .get = byt_gpio_get,
1478 .set = byt_gpio_set,
1479 .dbg_show = byt_gpio_dbg_show,
1480};
1481
31e4329f
MW		 1482static void byt_irq_ack(struct irq_data *d)
1483{
1484 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
bf9a5c96 1485 struct byt_gpio *vg = gpiochip_get_data(gc);
31e4329f
MW		 1486 unsigned offset = irqd_to_hwirq(d);
1487 void __iomem *reg;
1488
c501d0b1 1489 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
9f573b98
CC		 1490 if (!reg)
1491 return;
1492
1493 raw_spin_lock(&vg->lock);
31e4329f 1494 writel(BIT(offset % 32), reg);
78e1c896 1495 raw_spin_unlock(&vg->lock);
31e4329f
MW		 1496}
1497
9f573b98
CC		 1498static void byt_irq_mask(struct irq_data *d)
1499{
1500 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1501 struct byt_gpio *vg = gpiochip_get_data(gc);
1502
1503 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1504}
1505
a5d811bb
MN		 1506static void byt_irq_unmask(struct irq_data *d)
1507{
31e4329f 1508 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
bf9a5c96 1509 struct byt_gpio *vg = gpiochip_get_data(gc);
31e4329f
MW		 1510 unsigned offset = irqd_to_hwirq(d);
1511 unsigned long flags;
1512 void __iomem *reg;
1513 u32 value;
1514
c501d0b1 1515 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
9f573b98
CC		 1516 if (!reg)
1517 return;
78e1c896
MW		 1518
1519 raw_spin_lock_irqsave(&vg->lock, flags);
31e4329f
MW		 1520 value = readl(reg);
1521
1522 switch (irqd_get_trigger_type(d)) {
1523 case IRQ_TYPE_LEVEL_HIGH:
1524 value |= BYT_TRIG_LVL;
1525 case IRQ_TYPE_EDGE_RISING:
1526 value |= BYT_TRIG_POS;
1527 break;
1528 case IRQ_TYPE_LEVEL_LOW:
1529 value |= BYT_TRIG_LVL;
1530 case IRQ_TYPE_EDGE_FALLING:
1531 value |= BYT_TRIG_NEG;
1532 break;
1533 case IRQ_TYPE_EDGE_BOTH:
1534 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1535 break;
1536 }
1537
1538 writel(value, reg);
1539
78e1c896 1540 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb
MN		 1541}
1542
9f573b98 1543static int byt_irq_type(struct irq_data *d, unsigned int type)
a5d811bb 1544{
9f573b98
CC		 1545 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1546 u32 offset = irqd_to_hwirq(d);
1547 u32 value;
1548 unsigned long flags;
1549 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
31e4329f 1550
9f573b98
CC		 1551 if (!reg || offset >= vg->chip.ngpio)
1552 return -EINVAL;
1553
1554 raw_spin_lock_irqsave(&vg->lock, flags);
1555 value = readl(reg);
1556
1557 WARN(value & BYT_DIRECT_IRQ_EN,
1558 "Bad pad config for io mode, force direct_irq_en bit clearing");
1559
1560 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1561 * are used to indicate high and low level triggering
1562 */
1563 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1564 BYT_TRIG_LVL);
1565
1566 writel(value, reg);
1567
1568 if (type & IRQ_TYPE_EDGE_BOTH)
1569 irq_set_handler_locked(d, handle_edge_irq);
1570 else if (type & IRQ_TYPE_LEVEL_MASK)
1571 irq_set_handler_locked(d, handle_level_irq);
1572
1573 raw_spin_unlock_irqrestore(&vg->lock, flags);
1574
1575 return 0;
a5d811bb
MN		 1576}
1577
1578static struct irq_chip byt_irqchip = {
9f573b98
CC		 1579 .name = "BYT-GPIO",
1580 .irq_ack = byt_irq_ack,
1581 .irq_mask = byt_irq_mask,
1582 .irq_unmask = byt_irq_unmask,
1583 .irq_set_type = byt_irq_type,
1584 .flags = IRQCHIP_SKIP_SET_WAKE,
a5d811bb
MN		 1585};
1586
71e6ca61
CC		 1587static void byt_gpio_irq_handler(struct irq_desc *desc)
1588{
1589 struct irq_data *data = irq_desc_get_irq_data(desc);
1590 struct byt_gpio *vg = gpiochip_get_data(
1591 irq_desc_get_handler_data(desc));
1592 struct irq_chip *chip = irq_data_get_irq_chip(data);
1593 u32 base, pin;
1594 void __iomem *reg;
1595 unsigned long pending;
1596 unsigned int virq;
1597
1598 /* check from GPIO controller which pin triggered the interrupt */
1599 for (base = 0; base < vg->chip.ngpio; base += 32) {
1600 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1601
1602 if (!reg) {
1603 dev_warn(&vg->pdev->dev,
1604 "Pin %i: could not retrieve interrupt status register\n",
1605 base);
1606 continue;
1607 }
1608
1609 pending = readl(reg);
1610 for_each_set_bit(pin, &pending, 32) {
1611 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
1612 generic_handle_irq(virq);
1613 }
1614 }
1615 chip->irq_eoi(data);
1616}
1617
a5d811bb
MN		 1618static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1619{
1620 void __iomem *reg;
1621 u32 base, value;
95f0972c
MW		 1622 int i;
1623
1624 /*
1625 * Clear interrupt triggers for all pins that are GPIOs and
1626 * do not use direct IRQ mode. This will prevent spurious
1627 * interrupts from misconfigured pins.
1628 */
71e6ca61
CC		 1629 for (i = 0; i < vg->soc_data->npins; i++) {
1630 unsigned int pin = vg->soc_data->pins[i].number;
1631
1632 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1633 if (!reg) {
1634 dev_warn(&vg->pdev->dev,
1635 "Pin %i: could not retrieve conf0 register\n",
1636 i);
1637 continue;
1638 }
1639
1640 value = readl(reg);
95f0972c
MW		 1641 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
1642 !(value & BYT_DIRECT_IRQ_EN)) {
1643 byt_gpio_clear_triggering(vg, i);
1644 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
1645 }
1646 }
a5d811bb
MN		 1647
1648 /* clear interrupt status trigger registers */
71e6ca61 1649 for (base = 0; base < vg->soc_data->npins; base += 32) {
c501d0b1 1650 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
71e6ca61
CC		 1651
1652 if (!reg) {
1653 dev_warn(&vg->pdev->dev,
1654 "Pin %i: could not retrieve irq status reg\n",
1655 base);
1656 continue;
1657 }
1658
a5d811bb
MN		 1659 writel(0xffffffff, reg);
1660 /* make sure trigger bits are cleared, if not then a pin
1661 might be misconfigured in bios */
1662 value = readl(reg);
1663 if (value)
1664 dev_err(&vg->pdev->dev,
1665 "GPIO interrupt error, pins misconfigured\n");
1666 }
1667}
1668
71e6ca61 1669static int byt_gpio_probe(struct byt_gpio *vg)
a5d811bb 1670{
a5d811bb 1671 struct gpio_chip *gc;
71e6ca61 1672 struct resource *irq_rc;
a5d811bb
MN		 1673 int ret;
1674
71e6ca61
CC		 1675 /* Set up gpio chip */
1676 vg->chip = byt_gpio_chip;
1677 gc = &vg->chip;
1678 gc->label = dev_name(&vg->pdev->dev);
1679 gc->base = -1;
1680 gc->can_sleep = false;
1681 gc->parent = &vg->pdev->dev;
1682 gc->ngpio = vg->soc_data->npins;
a5d811bb 1683
fcc18deb 1684#ifdef CONFIG_PM_SLEEP
71e6ca61 1685 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
fcc18deb
MW		 1686 sizeof(*vg->saved_context), GFP_KERNEL);
1687#endif
bf9a5c96 1688 ret = gpiochip_add_data(gc, vg);
e1ee5c57 1689 if (ret) {
71e6ca61 1690 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
e1ee5c57
MW		 1691 return ret;
1692 }
1693
71e6ca61
CC		 1694 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1695 0, 0, vg->soc_data->npins);
1696 if (ret) {
1697 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1698 goto fail;
1699 }
1700
a5d811bb 1701 /* set up interrupts */
71e6ca61 1702 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
a5d811bb 1703 if (irq_rc && irq_rc->start) {
a5d811bb 1704 byt_gpio_irq_init_hw(vg);
e1ee5c57
MW		 1705 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1706 handle_simple_irq, IRQ_TYPE_NONE);
1707 if (ret) {
71e6ca61
CC		 1708 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1709 goto fail;
e1ee5c57 1710 }
a5d811bb 1711
e1ee5c57
MW		 1712 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1713 (unsigned)irq_rc->start,
1714 byt_gpio_irq_handler);
605a7bca
JY		 1715 }
1716
71e6ca61
CC		 1717 return ret;
1718
1719fail:
1720 gpiochip_remove(&vg->chip);
1721
1722 return ret;
1723}
1724
1725static int byt_set_soc_data(struct byt_gpio *vg,
1726 const struct byt_pinctrl_soc_data *soc_data)
1727{
1728 int i;
1729
1730 vg->soc_data = soc_data;
1731 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1732 soc_data->ncommunities,
1733 sizeof(*vg->communities_copy),
1734 GFP_KERNEL);
1735 if (!vg->communities_copy)
1736 return -ENOMEM;
1737
1738 for (i = 0; i < soc_data->ncommunities; i++) {
1739 struct byt_community *comm = vg->communities_copy + i;
1740 struct resource *mem_rc;
1741
1742 *comm = vg->soc_data->communities[i];
1743
1744 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1745 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1746 if (IS_ERR(comm->reg_base))
1747 return PTR_ERR(comm->reg_base);
1748 }
1749
1750 return 0;
1751}
1752
1753static const struct acpi_device_id byt_gpio_acpi_match[] = {
1754 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1755 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1756 { }
1757};
1758MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1759
1760static int byt_pinctrl_probe(struct platform_device *pdev)
1761{
1762 const struct byt_pinctrl_soc_data *soc_data = NULL;
1763 const struct byt_pinctrl_soc_data **soc_table;
1764 const struct acpi_device_id *acpi_id;
1765 struct acpi_device *acpi_dev;
1766 struct byt_gpio *vg;
1767 int i, ret;
1768
1769 acpi_dev = ACPI_COMPANION(&pdev->dev);
1770 if (!acpi_dev)
1771 return -ENODEV;
1772
1773 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1774 if (!acpi_id)
1775 return -ENODEV;
1776
1777 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1778
1779 for (i = 0; soc_table[i]; i++) {
1780 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1781 soc_data = soc_table[i];
1782 break;
1783 }
1784 }
1785
1786 if (!soc_data)
1787 return -ENODEV;
1788
1789 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1790 if (!vg)
1791 return -ENOMEM;
1792
1793 vg->pdev = pdev;
1794 ret = byt_set_soc_data(vg, soc_data);
1795 if (ret) {
1796 dev_err(&pdev->dev, "failed to set soc data\n");
1797 return ret;
1798 }
1799
1800 vg->pctl_desc = byt_pinctrl_desc;
1801 vg->pctl_desc.name = dev_name(&pdev->dev);
1802 vg->pctl_desc.pins = vg->soc_data->pins;
1803 vg->pctl_desc.npins = vg->soc_data->npins;
1804
1805 vg->pctl_dev = pinctrl_register(&vg->pctl_desc, &pdev->dev, vg);
1806 if (IS_ERR(vg->pctl_dev)) {
1807 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1808 return PTR_ERR(vg->pctl_dev);
1809 }
1810
1811 ret = byt_gpio_probe(vg);
1812 if (ret) {
1813 pinctrl_unregister(vg->pctl_dev);
1814 return ret;
1815 }
1816
1817 platform_set_drvdata(pdev, vg);
1818 raw_spin_lock_init(&vg->lock);
1819 pm_runtime_enable(&pdev->dev);
1820
1821 return 0;
1822}
1823
fcc18deb
MW		 1824#ifdef CONFIG_PM_SLEEP
1825static int byt_gpio_suspend(struct device *dev)
1826{
1827 struct platform_device *pdev = to_platform_device(dev);
1828 struct byt_gpio *vg = platform_get_drvdata(pdev);
1829 int i;
1830
71e6ca61 1831 for (i = 0; i < vg->soc_data->npins; i++) {
fcc18deb
MW		 1832 void __iomem *reg;
1833 u32 value;
71e6ca61 1834 unsigned int pin = vg->soc_data->pins[i].number;
fcc18deb 1835
71e6ca61
CC		 1836 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1837 if (!reg) {
1838 dev_warn(&vg->pdev->dev,
1839 "Pin %i: could not retrieve conf0 register\n",
1840 i);
1841 continue;
1842 }
fcc18deb
MW		 1843 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1844 vg->saved_context[i].conf0 = value;
1845
71e6ca61 1846 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
fcc18deb
MW		 1847 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1848 vg->saved_context[i].val = value;
1849 }
1850
1851 return 0;
1852}
1853
1854static int byt_gpio_resume(struct device *dev)
1855{
1856 struct platform_device *pdev = to_platform_device(dev);
1857 struct byt_gpio *vg = platform_get_drvdata(pdev);
1858 int i;
1859
71e6ca61 1860 for (i = 0; i < vg->soc_data->npins; i++) {
fcc18deb
MW		 1861 void __iomem *reg;
1862 u32 value;
71e6ca61 1863 unsigned int pin = vg->soc_data->pins[i].number;
fcc18deb 1864
71e6ca61
CC		 1865 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1866 if (!reg) {
1867 dev_warn(&vg->pdev->dev,
1868 "Pin %i: could not retrieve conf0 register\n",
1869 i);
1870 continue;
1871 }
fcc18deb
MW		 1872 value = readl(reg);
1873 if ((value & BYT_CONF0_RESTORE_MASK) !=
1874 vg->saved_context[i].conf0) {
1875 value &= ~BYT_CONF0_RESTORE_MASK;
1876 value |= vg->saved_context[i].conf0;
1877 writel(value, reg);
1878 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1879 }
1880
71e6ca61 1881 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
fcc18deb
MW		 1882 value = readl(reg);
1883 if ((value & BYT_VAL_RESTORE_MASK) !=
1884 vg->saved_context[i].val) {
1885 u32 v;
1886
1887 v = value & ~BYT_VAL_RESTORE_MASK;
1888 v |= vg->saved_context[i].val;
1889 if (v != value) {
1890 writel(v, reg);
1891 dev_dbg(dev, "restored pin %d val %#08x\n",
1892 i, v);
1893 }
1894 }
1895 }
1896
1897 return 0;
1898}
1899#endif
1900
ec879f12 1901#ifdef CONFIG_PM
a5d811bb
MN		 1902static int byt_gpio_runtime_suspend(struct device *dev)
1903{
1904 return 0;
1905}
1906
1907static int byt_gpio_runtime_resume(struct device *dev)
1908{
1909 return 0;
1910}
ec879f12 1911#endif
a5d811bb
MN		 1912
1913static const struct dev_pm_ops byt_gpio_pm_ops = {
fcc18deb
MW		 1914 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1915 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1916 NULL)
a5d811bb
MN		 1917};
1918
a5d811bb 1919static struct platform_driver byt_gpio_driver = {
71e6ca61 1920 .probe = byt_pinctrl_probe,
a5d811bb 1921 .driver = {
360943a8
PG		 1922 .name = "byt_gpio",
1923 .pm = &byt_gpio_pm_ops,
1924 .suppress_bind_attrs = true,
1925
a5d811bb
MN		 1926 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1927 },
1928};
1929
1930static int __init byt_gpio_init(void)
1931{
1932 return platform_driver_register(&byt_gpio_driver);
1933}
a5d811bb 1934subsys_initcall(byt_gpio_init);
Linux kernel - Deliverables
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