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1 | /* |
2 | * Cherryview/Braswell pinctrl driver | |
3 | * | |
4 | * Copyright (C) 2014, Intel Corporation | |
5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | |
6 | * | |
7 | * This driver is based on the original Cherryview GPIO driver by | |
8 | * Ning Li <ning.li@intel.com> | |
9 | * Alan Cox <alan@linux.intel.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/gpio.h> | |
21 | #include <linux/gpio/driver.h> | |
22 | #include <linux/acpi.h> | |
23 | #include <linux/pinctrl/pinctrl.h> | |
24 | #include <linux/pinctrl/pinmux.h> | |
25 | #include <linux/pinctrl/pinconf.h> | |
26 | #include <linux/pinctrl/pinconf-generic.h> | |
27 | #include <linux/platform_device.h> | |
28 | ||
29 | #define CHV_INTSTAT 0x300 | |
30 | #define CHV_INTMASK 0x380 | |
31 | ||
32 | #define FAMILY_PAD_REGS_OFF 0x4400 | |
33 | #define FAMILY_PAD_REGS_SIZE 0x400 | |
34 | #define MAX_FAMILY_PAD_GPIO_NO 15 | |
35 | #define GPIO_REGS_SIZE 8 | |
36 | ||
37 | #define CHV_PADCTRL0 0x000 | |
38 | #define CHV_PADCTRL0_INTSEL_SHIFT 28 | |
39 | #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) | |
40 | #define CHV_PADCTRL0_TERM_UP BIT(23) | |
41 | #define CHV_PADCTRL0_TERM_SHIFT 20 | |
42 | #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) | |
43 | #define CHV_PADCTRL0_TERM_20K 1 | |
44 | #define CHV_PADCTRL0_TERM_5K 2 | |
45 | #define CHV_PADCTRL0_TERM_1K 4 | |
46 | #define CHV_PADCTRL0_PMODE_SHIFT 16 | |
47 | #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) | |
48 | #define CHV_PADCTRL0_GPIOEN BIT(15) | |
49 | #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 | |
50 | #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) | |
51 | #define CHV_PADCTRL0_GPIOCFG_GPIO 0 | |
52 | #define CHV_PADCTRL0_GPIOCFG_GPO 1 | |
53 | #define CHV_PADCTRL0_GPIOCFG_GPI 2 | |
54 | #define CHV_PADCTRL0_GPIOCFG_HIZ 3 | |
55 | #define CHV_PADCTRL0_GPIOTXSTATE BIT(1) | |
56 | #define CHV_PADCTRL0_GPIORXSTATE BIT(0) | |
57 | ||
58 | #define CHV_PADCTRL1 0x004 | |
59 | #define CHV_PADCTRL1_CFGLOCK BIT(31) | |
60 | #define CHV_PADCTRL1_INVRXTX_SHIFT 4 | |
61 | #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) | |
62 | #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) | |
63 | #define CHV_PADCTRL1_ODEN BIT(3) | |
64 | #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) | |
65 | #define CHV_PADCTRL1_INTWAKECFG_MASK 7 | |
66 | #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 | |
67 | #define CHV_PADCTRL1_INTWAKECFG_RISING 2 | |
68 | #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 | |
69 | #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 | |
70 | ||
71 | /** | |
72 | * struct chv_alternate_function - A per group or per pin alternate function | |
73 | * @pin: Pin number (only used in per pin configs) | |
74 | * @mode: Mode the pin should be set in | |
75 | * @invert_oe: Invert OE for this pin | |
76 | */ | |
77 | struct chv_alternate_function { | |
78 | unsigned pin; | |
79 | u8 mode; | |
80 | bool invert_oe; | |
81 | }; | |
82 | ||
83 | /** | |
84 | * struct chv_pincgroup - describes a CHV pin group | |
85 | * @name: Name of the group | |
86 | * @pins: An array of pins in this group | |
87 | * @npins: Number of pins in this group | |
88 | * @altfunc: Alternate function applied to all pins in this group | |
89 | * @overrides: Alternate function override per pin or %NULL if not used | |
90 | * @noverrides: Number of per pin alternate function overrides if | |
91 | * @overrides != NULL. | |
92 | */ | |
93 | struct chv_pingroup { | |
94 | const char *name; | |
95 | const unsigned *pins; | |
96 | size_t npins; | |
97 | struct chv_alternate_function altfunc; | |
98 | const struct chv_alternate_function *overrides; | |
99 | size_t noverrides; | |
100 | }; | |
101 | ||
102 | /** | |
103 | * struct chv_function - A CHV pinmux function | |
104 | * @name: Name of the function | |
105 | * @groups: An array of groups for this function | |
106 | * @ngroups: Number of groups in @groups | |
107 | */ | |
108 | struct chv_function { | |
109 | const char *name; | |
110 | const char * const *groups; | |
111 | size_t ngroups; | |
112 | }; | |
113 | ||
114 | /** | |
115 | * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs | |
116 | * @base: Start pin number | |
117 | * @npins: Number of pins in this range | |
118 | */ | |
119 | struct chv_gpio_pinrange { | |
120 | unsigned base; | |
121 | unsigned npins; | |
122 | }; | |
123 | ||
124 | /** | |
125 | * struct chv_community - A community specific configuration | |
126 | * @uid: ACPI _UID used to match the community | |
127 | * @pins: All pins in this community | |
128 | * @npins: Number of pins | |
129 | * @groups: All groups in this community | |
130 | * @ngroups: Number of groups | |
131 | * @functions: All functions in this community | |
132 | * @nfunctions: Number of functions | |
133 | * @ngpios: Number of GPIOs in this community | |
134 | * @gpio_ranges: An array of GPIO ranges in this community | |
135 | * @ngpio_ranges: Number of GPIO ranges | |
136 | * @ngpios: Total number of GPIOs in this community | |
137 | */ | |
138 | struct chv_community { | |
139 | const char *uid; | |
140 | const struct pinctrl_pin_desc *pins; | |
141 | size_t npins; | |
142 | const struct chv_pingroup *groups; | |
143 | size_t ngroups; | |
144 | const struct chv_function *functions; | |
145 | size_t nfunctions; | |
146 | const struct chv_gpio_pinrange *gpio_ranges; | |
147 | size_t ngpio_ranges; | |
148 | size_t ngpios; | |
149 | }; | |
150 | ||
9eb457b5 MW |
151 | struct chv_pin_context { |
152 | u32 padctrl0; | |
153 | u32 padctrl1; | |
154 | }; | |
155 | ||
6e08d6bb MW |
156 | /** |
157 | * struct chv_pinctrl - CHV pinctrl private structure | |
158 | * @dev: Pointer to the parent device | |
159 | * @pctldesc: Pin controller description | |
160 | * @pctldev: Pointer to the pin controller device | |
161 | * @chip: GPIO chip in this pin controller | |
162 | * @regs: MMIO registers | |
6e08d6bb MW |
163 | * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO |
164 | * offset (in GPIO number space) | |
165 | * @community: Community this pinctrl instance represents | |
166 | * | |
167 | * The first group in @groups is expected to contain all pins that can be | |
168 | * used as GPIOs. | |
169 | */ | |
170 | struct chv_pinctrl { | |
171 | struct device *dev; | |
172 | struct pinctrl_desc pctldesc; | |
173 | struct pinctrl_dev *pctldev; | |
174 | struct gpio_chip chip; | |
175 | void __iomem *regs; | |
6e08d6bb MW |
176 | unsigned intr_lines[16]; |
177 | const struct chv_community *community; | |
9eb457b5 MW |
178 | u32 saved_intmask; |
179 | struct chv_pin_context *saved_pin_context; | |
6e08d6bb MW |
180 | }; |
181 | ||
6e08d6bb MW |
182 | #define ALTERNATE_FUNCTION(p, m, i) \ |
183 | { \ | |
184 | .pin = (p), \ | |
185 | .mode = (m), \ | |
186 | .invert_oe = (i), \ | |
187 | } | |
188 | ||
189 | #define PIN_GROUP(n, p, m, i) \ | |
190 | { \ | |
191 | .name = (n), \ | |
192 | .pins = (p), \ | |
193 | .npins = ARRAY_SIZE((p)), \ | |
194 | .altfunc.mode = (m), \ | |
195 | .altfunc.invert_oe = (i), \ | |
196 | } | |
197 | ||
198 | #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ | |
199 | { \ | |
200 | .name = (n), \ | |
201 | .pins = (p), \ | |
202 | .npins = ARRAY_SIZE((p)), \ | |
203 | .altfunc.mode = (m), \ | |
204 | .altfunc.invert_oe = (i), \ | |
205 | .overrides = (o), \ | |
206 | .noverrides = ARRAY_SIZE((o)), \ | |
207 | } | |
208 | ||
209 | #define FUNCTION(n, g) \ | |
210 | { \ | |
211 | .name = (n), \ | |
212 | .groups = (g), \ | |
213 | .ngroups = ARRAY_SIZE((g)), \ | |
214 | } | |
215 | ||
216 | #define GPIO_PINRANGE(start, end) \ | |
217 | { \ | |
218 | .base = (start), \ | |
219 | .npins = (end) - (start) + 1, \ | |
220 | } | |
221 | ||
222 | static const struct pinctrl_pin_desc southwest_pins[] = { | |
223 | PINCTRL_PIN(0, "FST_SPI_D2"), | |
224 | PINCTRL_PIN(1, "FST_SPI_D0"), | |
225 | PINCTRL_PIN(2, "FST_SPI_CLK"), | |
226 | PINCTRL_PIN(3, "FST_SPI_D3"), | |
227 | PINCTRL_PIN(4, "FST_SPI_CS1_B"), | |
228 | PINCTRL_PIN(5, "FST_SPI_D1"), | |
229 | PINCTRL_PIN(6, "FST_SPI_CS0_B"), | |
230 | PINCTRL_PIN(7, "FST_SPI_CS2_B"), | |
231 | ||
232 | PINCTRL_PIN(15, "UART1_RTS_B"), | |
233 | PINCTRL_PIN(16, "UART1_RXD"), | |
234 | PINCTRL_PIN(17, "UART2_RXD"), | |
235 | PINCTRL_PIN(18, "UART1_CTS_B"), | |
236 | PINCTRL_PIN(19, "UART2_RTS_B"), | |
237 | PINCTRL_PIN(20, "UART1_TXD"), | |
238 | PINCTRL_PIN(21, "UART2_TXD"), | |
239 | PINCTRL_PIN(22, "UART2_CTS_B"), | |
240 | ||
241 | PINCTRL_PIN(30, "MF_HDA_CLK"), | |
242 | PINCTRL_PIN(31, "MF_HDA_RSTB"), | |
243 | PINCTRL_PIN(32, "MF_HDA_SDIO"), | |
244 | PINCTRL_PIN(33, "MF_HDA_SDO"), | |
245 | PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), | |
246 | PINCTRL_PIN(35, "MF_HDA_SYNC"), | |
247 | PINCTRL_PIN(36, "MF_HDA_SDI1"), | |
248 | PINCTRL_PIN(37, "MF_HDA_DOCKENB"), | |
249 | ||
250 | PINCTRL_PIN(45, "I2C5_SDA"), | |
251 | PINCTRL_PIN(46, "I2C4_SDA"), | |
252 | PINCTRL_PIN(47, "I2C6_SDA"), | |
253 | PINCTRL_PIN(48, "I2C5_SCL"), | |
254 | PINCTRL_PIN(49, "I2C_NFC_SDA"), | |
255 | PINCTRL_PIN(50, "I2C4_SCL"), | |
256 | PINCTRL_PIN(51, "I2C6_SCL"), | |
257 | PINCTRL_PIN(52, "I2C_NFC_SCL"), | |
258 | ||
259 | PINCTRL_PIN(60, "I2C1_SDA"), | |
260 | PINCTRL_PIN(61, "I2C0_SDA"), | |
261 | PINCTRL_PIN(62, "I2C2_SDA"), | |
262 | PINCTRL_PIN(63, "I2C1_SCL"), | |
263 | PINCTRL_PIN(64, "I2C3_SDA"), | |
264 | PINCTRL_PIN(65, "I2C0_SCL"), | |
265 | PINCTRL_PIN(66, "I2C2_SCL"), | |
266 | PINCTRL_PIN(67, "I2C3_SCL"), | |
267 | ||
268 | PINCTRL_PIN(75, "SATA_GP0"), | |
269 | PINCTRL_PIN(76, "SATA_GP1"), | |
270 | PINCTRL_PIN(77, "SATA_LEDN"), | |
271 | PINCTRL_PIN(78, "SATA_GP2"), | |
272 | PINCTRL_PIN(79, "MF_SMB_ALERTB"), | |
273 | PINCTRL_PIN(80, "SATA_GP3"), | |
274 | PINCTRL_PIN(81, "MF_SMB_CLK"), | |
275 | PINCTRL_PIN(82, "MF_SMB_DATA"), | |
276 | ||
277 | PINCTRL_PIN(90, "PCIE_CLKREQ0B"), | |
278 | PINCTRL_PIN(91, "PCIE_CLKREQ1B"), | |
279 | PINCTRL_PIN(92, "GP_SSP_2_CLK"), | |
280 | PINCTRL_PIN(93, "PCIE_CLKREQ2B"), | |
281 | PINCTRL_PIN(94, "GP_SSP_2_RXD"), | |
282 | PINCTRL_PIN(95, "PCIE_CLKREQ3B"), | |
283 | PINCTRL_PIN(96, "GP_SSP_2_FS"), | |
284 | PINCTRL_PIN(97, "GP_SSP_2_TXD"), | |
285 | }; | |
286 | ||
287 | static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; | |
288 | static const unsigned southwest_uart0_pins[] = { 16, 20 }; | |
289 | static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; | |
290 | static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; | |
291 | static const unsigned southwest_i2c0_pins[] = { 61, 65 }; | |
292 | static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; | |
293 | static const unsigned southwest_lpe_pins[] = { | |
294 | 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, | |
295 | }; | |
296 | static const unsigned southwest_i2c1_pins[] = { 60, 63 }; | |
297 | static const unsigned southwest_i2c2_pins[] = { 62, 66 }; | |
298 | static const unsigned southwest_i2c3_pins[] = { 64, 67 }; | |
299 | static const unsigned southwest_i2c4_pins[] = { 46, 50 }; | |
300 | static const unsigned southwest_i2c5_pins[] = { 45, 48 }; | |
301 | static const unsigned southwest_i2c6_pins[] = { 47, 51 }; | |
302 | static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; | |
303 | static const unsigned southwest_smbus_pins[] = { 79, 81, 82 }; | |
304 | static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; | |
305 | ||
306 | /* LPE I2S TXD pins need to have invert_oe set */ | |
307 | static const struct chv_alternate_function southwest_lpe_altfuncs[] = { | |
308 | ALTERNATE_FUNCTION(30, 1, true), | |
309 | ALTERNATE_FUNCTION(34, 1, true), | |
310 | ALTERNATE_FUNCTION(97, 1, true), | |
311 | }; | |
312 | ||
313 | /* | |
314 | * Two spi3 chipselects are available in different mode than the main spi3 | |
315 | * functionality, which is using mode 1. | |
316 | */ | |
317 | static const struct chv_alternate_function southwest_spi3_altfuncs[] = { | |
318 | ALTERNATE_FUNCTION(76, 3, false), | |
319 | ALTERNATE_FUNCTION(80, 3, false), | |
320 | }; | |
321 | ||
322 | static const struct chv_pingroup southwest_groups[] = { | |
323 | PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false), | |
324 | PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false), | |
325 | PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false), | |
326 | PIN_GROUP("hda_grp", southwest_hda_pins, 2, false), | |
327 | PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true), | |
328 | PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true), | |
329 | PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true), | |
330 | PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true), | |
331 | PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true), | |
332 | PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true), | |
333 | PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true), | |
334 | PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), | |
335 | ||
336 | PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, | |
337 | southwest_lpe_altfuncs), | |
338 | PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, | |
339 | southwest_spi3_altfuncs), | |
340 | }; | |
341 | ||
342 | static const char * const southwest_uart0_groups[] = { "uart0_grp" }; | |
343 | static const char * const southwest_uart1_groups[] = { "uart1_grp" }; | |
344 | static const char * const southwest_uart2_groups[] = { "uart2_grp" }; | |
345 | static const char * const southwest_hda_groups[] = { "hda_grp" }; | |
346 | static const char * const southwest_lpe_groups[] = { "lpe_grp" }; | |
347 | static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; | |
348 | static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; | |
349 | static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; | |
350 | static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; | |
351 | static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; | |
352 | static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; | |
353 | static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; | |
354 | static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; | |
355 | static const char * const southwest_spi3_groups[] = { "spi3_grp" }; | |
356 | ||
357 | /* | |
358 | * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are | |
359 | * enabled only as GPIOs. | |
360 | */ | |
361 | static const struct chv_function southwest_functions[] = { | |
362 | FUNCTION("uart0", southwest_uart0_groups), | |
363 | FUNCTION("uart1", southwest_uart1_groups), | |
364 | FUNCTION("uart2", southwest_uart2_groups), | |
365 | FUNCTION("hda", southwest_hda_groups), | |
366 | FUNCTION("lpe", southwest_lpe_groups), | |
367 | FUNCTION("i2c0", southwest_i2c0_groups), | |
368 | FUNCTION("i2c1", southwest_i2c1_groups), | |
369 | FUNCTION("i2c2", southwest_i2c2_groups), | |
370 | FUNCTION("i2c3", southwest_i2c3_groups), | |
371 | FUNCTION("i2c4", southwest_i2c4_groups), | |
372 | FUNCTION("i2c5", southwest_i2c5_groups), | |
373 | FUNCTION("i2c6", southwest_i2c6_groups), | |
374 | FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), | |
375 | FUNCTION("spi3", southwest_spi3_groups), | |
376 | }; | |
377 | ||
378 | static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { | |
379 | GPIO_PINRANGE(0, 7), | |
380 | GPIO_PINRANGE(15, 22), | |
381 | GPIO_PINRANGE(30, 37), | |
382 | GPIO_PINRANGE(45, 52), | |
383 | GPIO_PINRANGE(60, 67), | |
384 | GPIO_PINRANGE(75, 82), | |
385 | GPIO_PINRANGE(90, 97), | |
386 | }; | |
387 | ||
388 | static const struct chv_community southwest_community = { | |
389 | .uid = "1", | |
390 | .pins = southwest_pins, | |
391 | .npins = ARRAY_SIZE(southwest_pins), | |
392 | .groups = southwest_groups, | |
393 | .ngroups = ARRAY_SIZE(southwest_groups), | |
394 | .functions = southwest_functions, | |
395 | .nfunctions = ARRAY_SIZE(southwest_functions), | |
396 | .gpio_ranges = southwest_gpio_ranges, | |
397 | .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), | |
398 | .ngpios = ARRAY_SIZE(southwest_pins), | |
399 | }; | |
400 | ||
401 | static const struct pinctrl_pin_desc north_pins[] = { | |
402 | PINCTRL_PIN(0, "GPIO_DFX_0"), | |
403 | PINCTRL_PIN(1, "GPIO_DFX_3"), | |
404 | PINCTRL_PIN(2, "GPIO_DFX_7"), | |
405 | PINCTRL_PIN(3, "GPIO_DFX_1"), | |
406 | PINCTRL_PIN(4, "GPIO_DFX_5"), | |
407 | PINCTRL_PIN(5, "GPIO_DFX_4"), | |
408 | PINCTRL_PIN(6, "GPIO_DFX_8"), | |
409 | PINCTRL_PIN(7, "GPIO_DFX_2"), | |
410 | PINCTRL_PIN(8, "GPIO_DFX_6"), | |
411 | ||
412 | PINCTRL_PIN(15, "GPIO_SUS0"), | |
413 | PINCTRL_PIN(16, "SEC_GPIO_SUS10"), | |
414 | PINCTRL_PIN(17, "GPIO_SUS3"), | |
415 | PINCTRL_PIN(18, "GPIO_SUS7"), | |
416 | PINCTRL_PIN(19, "GPIO_SUS1"), | |
417 | PINCTRL_PIN(20, "GPIO_SUS5"), | |
418 | PINCTRL_PIN(21, "SEC_GPIO_SUS11"), | |
419 | PINCTRL_PIN(22, "GPIO_SUS4"), | |
420 | PINCTRL_PIN(23, "SEC_GPIO_SUS8"), | |
421 | PINCTRL_PIN(24, "GPIO_SUS2"), | |
422 | PINCTRL_PIN(25, "GPIO_SUS6"), | |
423 | PINCTRL_PIN(26, "CX_PREQ_B"), | |
424 | PINCTRL_PIN(27, "SEC_GPIO_SUS9"), | |
425 | ||
426 | PINCTRL_PIN(30, "TRST_B"), | |
427 | PINCTRL_PIN(31, "TCK"), | |
428 | PINCTRL_PIN(32, "PROCHOT_B"), | |
429 | PINCTRL_PIN(33, "SVIDO_DATA"), | |
430 | PINCTRL_PIN(34, "TMS"), | |
431 | PINCTRL_PIN(35, "CX_PRDY_B_2"), | |
432 | PINCTRL_PIN(36, "TDO_2"), | |
433 | PINCTRL_PIN(37, "CX_PRDY_B"), | |
434 | PINCTRL_PIN(38, "SVIDO_ALERT_B"), | |
435 | PINCTRL_PIN(39, "TDO"), | |
436 | PINCTRL_PIN(40, "SVIDO_CLK"), | |
437 | PINCTRL_PIN(41, "TDI"), | |
438 | ||
439 | PINCTRL_PIN(45, "GP_CAMERASB_05"), | |
440 | PINCTRL_PIN(46, "GP_CAMERASB_02"), | |
441 | PINCTRL_PIN(47, "GP_CAMERASB_08"), | |
442 | PINCTRL_PIN(48, "GP_CAMERASB_00"), | |
443 | PINCTRL_PIN(49, "GP_CAMERASB_06"), | |
444 | PINCTRL_PIN(50, "GP_CAMERASB_10"), | |
445 | PINCTRL_PIN(51, "GP_CAMERASB_03"), | |
446 | PINCTRL_PIN(52, "GP_CAMERASB_09"), | |
447 | PINCTRL_PIN(53, "GP_CAMERASB_01"), | |
448 | PINCTRL_PIN(54, "GP_CAMERASB_07"), | |
449 | PINCTRL_PIN(55, "GP_CAMERASB_11"), | |
450 | PINCTRL_PIN(56, "GP_CAMERASB_04"), | |
451 | ||
452 | PINCTRL_PIN(60, "PANEL0_BKLTEN"), | |
453 | PINCTRL_PIN(61, "HV_DDI0_HPD"), | |
454 | PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), | |
455 | PINCTRL_PIN(63, "PANEL1_BKLTCTL"), | |
456 | PINCTRL_PIN(64, "HV_DDI1_HPD"), | |
457 | PINCTRL_PIN(65, "PANEL0_BKLTCTL"), | |
458 | PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), | |
459 | PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), | |
460 | PINCTRL_PIN(68, "HV_DDI2_HPD"), | |
461 | PINCTRL_PIN(69, "PANEL1_VDDEN"), | |
462 | PINCTRL_PIN(70, "PANEL1_BKLTEN"), | |
463 | PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), | |
464 | PINCTRL_PIN(72, "PANEL0_VDDEN"), | |
465 | }; | |
466 | ||
467 | static const struct chv_gpio_pinrange north_gpio_ranges[] = { | |
468 | GPIO_PINRANGE(0, 8), | |
469 | GPIO_PINRANGE(15, 27), | |
470 | GPIO_PINRANGE(30, 41), | |
471 | GPIO_PINRANGE(45, 56), | |
472 | GPIO_PINRANGE(60, 72), | |
473 | }; | |
474 | ||
475 | static const struct chv_community north_community = { | |
476 | .uid = "2", | |
477 | .pins = north_pins, | |
478 | .npins = ARRAY_SIZE(north_pins), | |
479 | .gpio_ranges = north_gpio_ranges, | |
480 | .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), | |
481 | .ngpios = ARRAY_SIZE(north_pins), | |
482 | }; | |
483 | ||
484 | static const struct pinctrl_pin_desc east_pins[] = { | |
485 | PINCTRL_PIN(0, "PMU_SLP_S3_B"), | |
486 | PINCTRL_PIN(1, "PMU_BATLOW_B"), | |
487 | PINCTRL_PIN(2, "SUS_STAT_B"), | |
488 | PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), | |
489 | PINCTRL_PIN(4, "PMU_AC_PRESENT"), | |
490 | PINCTRL_PIN(5, "PMU_PLTRST_B"), | |
491 | PINCTRL_PIN(6, "PMU_SUSCLK"), | |
492 | PINCTRL_PIN(7, "PMU_SLP_LAN_B"), | |
493 | PINCTRL_PIN(8, "PMU_PWRBTN_B"), | |
494 | PINCTRL_PIN(9, "PMU_SLP_S4_B"), | |
495 | PINCTRL_PIN(10, "PMU_WAKE_B"), | |
496 | PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), | |
497 | ||
498 | PINCTRL_PIN(15, "MF_ISH_GPIO_3"), | |
499 | PINCTRL_PIN(16, "MF_ISH_GPIO_7"), | |
500 | PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), | |
501 | PINCTRL_PIN(18, "MF_ISH_GPIO_1"), | |
502 | PINCTRL_PIN(19, "MF_ISH_GPIO_5"), | |
503 | PINCTRL_PIN(20, "MF_ISH_GPIO_9"), | |
504 | PINCTRL_PIN(21, "MF_ISH_GPIO_0"), | |
505 | PINCTRL_PIN(22, "MF_ISH_GPIO_4"), | |
506 | PINCTRL_PIN(23, "MF_ISH_GPIO_8"), | |
507 | PINCTRL_PIN(24, "MF_ISH_GPIO_2"), | |
508 | PINCTRL_PIN(25, "MF_ISH_GPIO_6"), | |
509 | PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), | |
510 | }; | |
511 | ||
512 | static const struct chv_gpio_pinrange east_gpio_ranges[] = { | |
513 | GPIO_PINRANGE(0, 11), | |
514 | GPIO_PINRANGE(15, 26), | |
515 | }; | |
516 | ||
517 | static const struct chv_community east_community = { | |
518 | .uid = "3", | |
519 | .pins = east_pins, | |
520 | .npins = ARRAY_SIZE(east_pins), | |
521 | .gpio_ranges = east_gpio_ranges, | |
522 | .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), | |
523 | .ngpios = ARRAY_SIZE(east_pins), | |
524 | }; | |
525 | ||
526 | static const struct pinctrl_pin_desc southeast_pins[] = { | |
527 | PINCTRL_PIN(0, "MF_PLT_CLK0"), | |
528 | PINCTRL_PIN(1, "PWM1"), | |
529 | PINCTRL_PIN(2, "MF_PLT_CLK1"), | |
530 | PINCTRL_PIN(3, "MF_PLT_CLK4"), | |
531 | PINCTRL_PIN(4, "MF_PLT_CLK3"), | |
532 | PINCTRL_PIN(5, "PWM0"), | |
533 | PINCTRL_PIN(6, "MF_PLT_CLK5"), | |
534 | PINCTRL_PIN(7, "MF_PLT_CLK2"), | |
535 | ||
536 | PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), | |
537 | PINCTRL_PIN(16, "SDMMC1_CLK"), | |
538 | PINCTRL_PIN(17, "SDMMC1_D0"), | |
539 | PINCTRL_PIN(18, "SDMMC2_D1"), | |
540 | PINCTRL_PIN(19, "SDMMC2_CLK"), | |
541 | PINCTRL_PIN(20, "SDMMC1_D2"), | |
542 | PINCTRL_PIN(21, "SDMMC2_D2"), | |
543 | PINCTRL_PIN(22, "SDMMC2_CMD"), | |
544 | PINCTRL_PIN(23, "SDMMC1_CMD"), | |
545 | PINCTRL_PIN(24, "SDMMC1_D1"), | |
546 | PINCTRL_PIN(25, "SDMMC2_D0"), | |
547 | PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), | |
548 | ||
549 | PINCTRL_PIN(30, "SDMMC3_D1"), | |
550 | PINCTRL_PIN(31, "SDMMC3_CLK"), | |
551 | PINCTRL_PIN(32, "SDMMC3_D3"), | |
552 | PINCTRL_PIN(33, "SDMMC3_D2"), | |
553 | PINCTRL_PIN(34, "SDMMC3_CMD"), | |
554 | PINCTRL_PIN(35, "SDMMC3_D0"), | |
555 | ||
556 | PINCTRL_PIN(45, "MF_LPC_AD2"), | |
557 | PINCTRL_PIN(46, "LPC_CLKRUNB"), | |
558 | PINCTRL_PIN(47, "MF_LPC_AD0"), | |
559 | PINCTRL_PIN(48, "LPC_FRAMEB"), | |
560 | PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), | |
561 | PINCTRL_PIN(50, "MF_LPC_AD3"), | |
562 | PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), | |
563 | PINCTRL_PIN(52, "MF_LPC_AD1"), | |
564 | ||
565 | PINCTRL_PIN(60, "SPI1_MISO"), | |
566 | PINCTRL_PIN(61, "SPI1_CSO_B"), | |
567 | PINCTRL_PIN(62, "SPI1_CLK"), | |
568 | PINCTRL_PIN(63, "MMC1_D6"), | |
569 | PINCTRL_PIN(64, "SPI1_MOSI"), | |
570 | PINCTRL_PIN(65, "MMC1_D5"), | |
571 | PINCTRL_PIN(66, "SPI1_CS1_B"), | |
572 | PINCTRL_PIN(67, "MMC1_D4_SD_WE"), | |
573 | PINCTRL_PIN(68, "MMC1_D7"), | |
574 | PINCTRL_PIN(69, "MMC1_RCLK"), | |
575 | ||
576 | PINCTRL_PIN(75, "USB_OC1_B"), | |
577 | PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), | |
578 | PINCTRL_PIN(77, "GPIO_ALERT"), | |
579 | PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), | |
580 | PINCTRL_PIN(79, "ILB_SERIRQ"), | |
581 | PINCTRL_PIN(80, "USB_OC0_B"), | |
582 | PINCTRL_PIN(81, "SDMMC3_CD_B"), | |
583 | PINCTRL_PIN(82, "SPKR"), | |
584 | PINCTRL_PIN(83, "SUSPWRDNACK"), | |
585 | PINCTRL_PIN(84, "SPARE_PIN"), | |
586 | PINCTRL_PIN(85, "SDMMC3_1P8_EN"), | |
587 | }; | |
588 | ||
589 | static const unsigned southeast_pwm0_pins[] = { 5 }; | |
590 | static const unsigned southeast_pwm1_pins[] = { 1 }; | |
591 | static const unsigned southeast_sdmmc1_pins[] = { | |
592 | 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, | |
593 | }; | |
594 | static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; | |
595 | static const unsigned southeast_sdmmc3_pins[] = { | |
596 | 30, 31, 32, 33, 34, 35, 78, 81, 85, | |
597 | }; | |
598 | static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; | |
599 | static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; | |
600 | ||
601 | static const struct chv_pingroup southeast_groups[] = { | |
602 | PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false), | |
603 | PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false), | |
604 | PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), | |
605 | PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), | |
606 | PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), | |
607 | PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false), | |
608 | PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false), | |
609 | }; | |
610 | ||
611 | static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; | |
612 | static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; | |
613 | static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; | |
614 | static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; | |
615 | static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; | |
616 | static const char * const southeast_spi1_groups[] = { "spi1_grp" }; | |
617 | static const char * const southeast_spi2_groups[] = { "spi2_grp" }; | |
618 | ||
619 | static const struct chv_function southeast_functions[] = { | |
620 | FUNCTION("pwm0", southeast_pwm0_groups), | |
621 | FUNCTION("pwm1", southeast_pwm1_groups), | |
622 | FUNCTION("sdmmc1", southeast_sdmmc1_groups), | |
623 | FUNCTION("sdmmc2", southeast_sdmmc2_groups), | |
624 | FUNCTION("sdmmc3", southeast_sdmmc3_groups), | |
625 | FUNCTION("spi1", southeast_spi1_groups), | |
626 | FUNCTION("spi2", southeast_spi2_groups), | |
627 | }; | |
628 | ||
629 | static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { | |
630 | GPIO_PINRANGE(0, 7), | |
631 | GPIO_PINRANGE(15, 26), | |
632 | GPIO_PINRANGE(30, 35), | |
633 | GPIO_PINRANGE(45, 52), | |
634 | GPIO_PINRANGE(60, 69), | |
635 | GPIO_PINRANGE(75, 85), | |
636 | }; | |
637 | ||
638 | static const struct chv_community southeast_community = { | |
639 | .uid = "4", | |
640 | .pins = southeast_pins, | |
641 | .npins = ARRAY_SIZE(southeast_pins), | |
642 | .groups = southeast_groups, | |
643 | .ngroups = ARRAY_SIZE(southeast_groups), | |
644 | .functions = southeast_functions, | |
645 | .nfunctions = ARRAY_SIZE(southeast_functions), | |
646 | .gpio_ranges = southeast_gpio_ranges, | |
647 | .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), | |
648 | .ngpios = ARRAY_SIZE(southeast_pins), | |
649 | }; | |
650 | ||
651 | static const struct chv_community *chv_communities[] = { | |
652 | &southwest_community, | |
653 | &north_community, | |
654 | &east_community, | |
655 | &southeast_community, | |
656 | }; | |
657 | ||
0bd50d71 DD |
658 | /* |
659 | * Lock to serialize register accesses | |
660 | * | |
661 | * Due to a silicon issue, a shared lock must be used to prevent | |
662 | * concurrent accesses across the 4 GPIO controllers. | |
663 | * | |
664 | * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), | |
665 | * errata #CHT34, for further information. | |
666 | */ | |
667 | static DEFINE_RAW_SPINLOCK(chv_lock); | |
668 | ||
6e08d6bb MW |
669 | static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset, |
670 | unsigned reg) | |
671 | { | |
672 | unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO; | |
673 | unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; | |
674 | ||
675 | offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no + | |
676 | GPIO_REGS_SIZE * pad_no; | |
677 | ||
678 | return pctrl->regs + offset + reg; | |
679 | } | |
680 | ||
681 | static void chv_writel(u32 value, void __iomem *reg) | |
682 | { | |
683 | writel(value, reg); | |
684 | /* simple readback to confirm the bus transferring done */ | |
685 | readl(reg); | |
686 | } | |
687 | ||
688 | /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ | |
689 | static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset) | |
690 | { | |
691 | void __iomem *reg; | |
692 | ||
693 | reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); | |
694 | return readl(reg) & CHV_PADCTRL1_CFGLOCK; | |
695 | } | |
696 | ||
697 | static int chv_get_groups_count(struct pinctrl_dev *pctldev) | |
698 | { | |
699 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
700 | ||
701 | return pctrl->community->ngroups; | |
702 | } | |
703 | ||
704 | static const char *chv_get_group_name(struct pinctrl_dev *pctldev, | |
705 | unsigned group) | |
706 | { | |
707 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
708 | ||
709 | return pctrl->community->groups[group].name; | |
710 | } | |
711 | ||
712 | static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, | |
713 | const unsigned **pins, unsigned *npins) | |
714 | { | |
715 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
716 | ||
717 | *pins = pctrl->community->groups[group].pins; | |
718 | *npins = pctrl->community->groups[group].npins; | |
719 | return 0; | |
720 | } | |
721 | ||
722 | static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
723 | unsigned offset) | |
724 | { | |
725 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
726 | unsigned long flags; | |
727 | u32 ctrl0, ctrl1; | |
728 | bool locked; | |
729 | ||
0bd50d71 | 730 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
731 | |
732 | ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); | |
733 | ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1)); | |
734 | locked = chv_pad_locked(pctrl, offset); | |
735 | ||
0bd50d71 | 736 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
737 | |
738 | if (ctrl0 & CHV_PADCTRL0_GPIOEN) { | |
739 | seq_puts(s, "GPIO "); | |
740 | } else { | |
741 | u32 mode; | |
742 | ||
743 | mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; | |
744 | mode >>= CHV_PADCTRL0_PMODE_SHIFT; | |
745 | ||
746 | seq_printf(s, "mode %d ", mode); | |
747 | } | |
748 | ||
749 | seq_printf(s, "ctrl0 0x%08x ctrl1 0x%08x", ctrl0, ctrl1); | |
750 | ||
751 | if (locked) | |
752 | seq_puts(s, " [LOCKED]"); | |
753 | } | |
754 | ||
755 | static const struct pinctrl_ops chv_pinctrl_ops = { | |
756 | .get_groups_count = chv_get_groups_count, | |
757 | .get_group_name = chv_get_group_name, | |
758 | .get_group_pins = chv_get_group_pins, | |
759 | .pin_dbg_show = chv_pin_dbg_show, | |
760 | }; | |
761 | ||
762 | static int chv_get_functions_count(struct pinctrl_dev *pctldev) | |
763 | { | |
764 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
765 | ||
766 | return pctrl->community->nfunctions; | |
767 | } | |
768 | ||
769 | static const char *chv_get_function_name(struct pinctrl_dev *pctldev, | |
770 | unsigned function) | |
771 | { | |
772 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
773 | ||
774 | return pctrl->community->functions[function].name; | |
775 | } | |
776 | ||
777 | static int chv_get_function_groups(struct pinctrl_dev *pctldev, | |
778 | unsigned function, | |
779 | const char * const **groups, | |
780 | unsigned * const ngroups) | |
781 | { | |
782 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
783 | ||
784 | *groups = pctrl->community->functions[function].groups; | |
785 | *ngroups = pctrl->community->functions[function].ngroups; | |
786 | return 0; | |
787 | } | |
788 | ||
789 | static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, | |
790 | unsigned group) | |
791 | { | |
792 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
793 | const struct chv_pingroup *grp; | |
794 | unsigned long flags; | |
795 | int i; | |
796 | ||
797 | grp = &pctrl->community->groups[group]; | |
798 | ||
0bd50d71 | 799 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
800 | |
801 | /* Check first that the pad is not locked */ | |
802 | for (i = 0; i < grp->npins; i++) { | |
803 | if (chv_pad_locked(pctrl, grp->pins[i])) { | |
804 | dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n", | |
805 | grp->pins[i]); | |
0bd50d71 | 806 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
807 | return -EBUSY; |
808 | } | |
809 | } | |
810 | ||
811 | for (i = 0; i < grp->npins; i++) { | |
812 | const struct chv_alternate_function *altfunc = &grp->altfunc; | |
813 | int pin = grp->pins[i]; | |
814 | void __iomem *reg; | |
815 | u32 value; | |
816 | ||
817 | /* Check if there is pin-specific config */ | |
818 | if (grp->overrides) { | |
819 | int j; | |
820 | ||
821 | for (j = 0; j < grp->noverrides; j++) { | |
822 | if (grp->overrides[j].pin == pin) { | |
823 | altfunc = &grp->overrides[j]; | |
824 | break; | |
825 | } | |
826 | } | |
827 | } | |
828 | ||
829 | reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); | |
830 | value = readl(reg); | |
831 | /* Disable GPIO mode */ | |
832 | value &= ~CHV_PADCTRL0_GPIOEN; | |
833 | /* Set to desired mode */ | |
834 | value &= ~CHV_PADCTRL0_PMODE_MASK; | |
835 | value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; | |
836 | chv_writel(value, reg); | |
837 | ||
838 | /* Update for invert_oe */ | |
839 | reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); | |
840 | value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; | |
841 | if (altfunc->invert_oe) | |
842 | value |= CHV_PADCTRL1_INVRXTX_TXENABLE; | |
843 | chv_writel(value, reg); | |
844 | ||
845 | dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", | |
846 | pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); | |
847 | } | |
848 | ||
0bd50d71 | 849 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
850 | |
851 | return 0; | |
852 | } | |
853 | ||
854 | static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, | |
855 | struct pinctrl_gpio_range *range, | |
856 | unsigned offset) | |
857 | { | |
858 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
859 | unsigned long flags; | |
860 | void __iomem *reg; | |
861 | u32 value; | |
862 | ||
0bd50d71 | 863 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
864 | |
865 | if (chv_pad_locked(pctrl, offset)) { | |
866 | value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0)); | |
867 | if (!(value & CHV_PADCTRL0_GPIOEN)) { | |
868 | /* Locked so cannot enable */ | |
0bd50d71 | 869 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
870 | return -EBUSY; |
871 | } | |
872 | } else { | |
873 | int i; | |
874 | ||
875 | /* Reset the interrupt mapping */ | |
876 | for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { | |
877 | if (pctrl->intr_lines[i] == offset) { | |
878 | pctrl->intr_lines[i] = 0; | |
879 | break; | |
880 | } | |
881 | } | |
882 | ||
883 | /* Disable interrupt generation */ | |
884 | reg = chv_padreg(pctrl, offset, CHV_PADCTRL1); | |
885 | value = readl(reg); | |
886 | value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; | |
887 | value &= ~CHV_PADCTRL1_INVRXTX_MASK; | |
888 | chv_writel(value, reg); | |
889 | ||
6e08d6bb | 890 | reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); |
2479c730 MW |
891 | value = readl(reg); |
892 | ||
893 | /* | |
894 | * If the pin is in HiZ mode (both TX and RX buffers are | |
895 | * disabled) we turn it to be input now. | |
896 | */ | |
897 | if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == | |
898 | (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { | |
899 | value &= ~CHV_PADCTRL0_GPIOCFG_MASK; | |
900 | value |= CHV_PADCTRL0_GPIOCFG_GPI << | |
901 | CHV_PADCTRL0_GPIOCFG_SHIFT; | |
902 | } | |
903 | ||
904 | /* Switch to a GPIO mode */ | |
905 | value |= CHV_PADCTRL0_GPIOEN; | |
6e08d6bb MW |
906 | chv_writel(value, reg); |
907 | } | |
908 | ||
0bd50d71 | 909 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
910 | |
911 | return 0; | |
912 | } | |
913 | ||
914 | static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, | |
915 | struct pinctrl_gpio_range *range, | |
916 | unsigned offset) | |
917 | { | |
918 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
919 | unsigned long flags; | |
920 | void __iomem *reg; | |
921 | u32 value; | |
922 | ||
0bd50d71 | 923 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
924 | |
925 | reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); | |
926 | value = readl(reg) & ~CHV_PADCTRL0_GPIOEN; | |
927 | chv_writel(value, reg); | |
928 | ||
0bd50d71 | 929 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
930 | } |
931 | ||
932 | static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, | |
933 | struct pinctrl_gpio_range *range, | |
934 | unsigned offset, bool input) | |
935 | { | |
936 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
937 | void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0); | |
938 | unsigned long flags; | |
939 | u32 ctrl0; | |
940 | ||
0bd50d71 | 941 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
942 | |
943 | ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK; | |
944 | if (input) | |
945 | ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; | |
946 | else | |
947 | ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; | |
948 | chv_writel(ctrl0, reg); | |
949 | ||
0bd50d71 | 950 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
951 | |
952 | return 0; | |
953 | } | |
954 | ||
955 | static const struct pinmux_ops chv_pinmux_ops = { | |
956 | .get_functions_count = chv_get_functions_count, | |
957 | .get_function_name = chv_get_function_name, | |
958 | .get_function_groups = chv_get_function_groups, | |
959 | .set_mux = chv_pinmux_set_mux, | |
960 | .gpio_request_enable = chv_gpio_request_enable, | |
961 | .gpio_disable_free = chv_gpio_disable_free, | |
962 | .gpio_set_direction = chv_gpio_set_direction, | |
963 | }; | |
964 | ||
965 | static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, | |
966 | unsigned long *config) | |
967 | { | |
968 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
969 | enum pin_config_param param = pinconf_to_config_param(*config); | |
970 | unsigned long flags; | |
971 | u32 ctrl0, ctrl1; | |
972 | u16 arg = 0; | |
973 | u32 term; | |
974 | ||
0bd50d71 | 975 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
976 | ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); |
977 | ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); | |
0bd50d71 | 978 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
979 | |
980 | term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; | |
981 | ||
982 | switch (param) { | |
983 | case PIN_CONFIG_BIAS_DISABLE: | |
984 | if (term) | |
985 | return -EINVAL; | |
986 | break; | |
987 | ||
988 | case PIN_CONFIG_BIAS_PULL_UP: | |
989 | if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) | |
990 | return -EINVAL; | |
991 | ||
992 | switch (term) { | |
993 | case CHV_PADCTRL0_TERM_20K: | |
994 | arg = 20000; | |
995 | break; | |
996 | case CHV_PADCTRL0_TERM_5K: | |
997 | arg = 5000; | |
998 | break; | |
999 | case CHV_PADCTRL0_TERM_1K: | |
1000 | arg = 1000; | |
1001 | break; | |
1002 | } | |
1003 | ||
1004 | break; | |
1005 | ||
1006 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1007 | if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | switch (term) { | |
1011 | case CHV_PADCTRL0_TERM_20K: | |
1012 | arg = 20000; | |
1013 | break; | |
1014 | case CHV_PADCTRL0_TERM_5K: | |
1015 | arg = 5000; | |
1016 | break; | |
1017 | } | |
1018 | ||
1019 | break; | |
1020 | ||
1021 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
1022 | if (!(ctrl1 & CHV_PADCTRL1_ODEN)) | |
1023 | return -EINVAL; | |
1024 | break; | |
1025 | ||
1026 | case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { | |
1027 | u32 cfg; | |
1028 | ||
1029 | cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; | |
1030 | cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; | |
1031 | if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) | |
1032 | return -EINVAL; | |
1033 | ||
1034 | break; | |
1035 | } | |
1036 | ||
1037 | default: | |
1038 | return -ENOTSUPP; | |
1039 | } | |
1040 | ||
1041 | *config = pinconf_to_config_packed(param, arg); | |
1042 | return 0; | |
1043 | } | |
1044 | ||
1045 | static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin, | |
1046 | enum pin_config_param param, u16 arg) | |
1047 | { | |
1048 | void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); | |
1049 | unsigned long flags; | |
1050 | u32 ctrl0, pull; | |
1051 | ||
0bd50d71 | 1052 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
1053 | ctrl0 = readl(reg); |
1054 | ||
1055 | switch (param) { | |
1056 | case PIN_CONFIG_BIAS_DISABLE: | |
1057 | ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); | |
1058 | break; | |
1059 | ||
1060 | case PIN_CONFIG_BIAS_PULL_UP: | |
1061 | ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); | |
1062 | ||
1063 | switch (arg) { | |
1064 | case 1000: | |
1065 | /* For 1k there is only pull up */ | |
1066 | pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; | |
1067 | break; | |
1068 | case 5000: | |
1069 | pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; | |
1070 | break; | |
1071 | case 20000: | |
1072 | pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; | |
1073 | break; | |
1074 | default: | |
0bd50d71 | 1075 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1076 | return -EINVAL; |
1077 | } | |
1078 | ||
1079 | ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; | |
1080 | break; | |
1081 | ||
1082 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1083 | ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); | |
1084 | ||
1085 | switch (arg) { | |
1086 | case 5000: | |
1087 | pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; | |
1088 | break; | |
1089 | case 20000: | |
1090 | pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; | |
1091 | break; | |
1092 | default: | |
0bd50d71 | 1093 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1094 | return -EINVAL; |
1095 | } | |
1096 | ||
1097 | ctrl0 |= pull; | |
1098 | break; | |
1099 | ||
1100 | default: | |
0bd50d71 | 1101 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1102 | return -EINVAL; |
1103 | } | |
1104 | ||
1105 | chv_writel(ctrl0, reg); | |
0bd50d71 | 1106 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1107 | |
1108 | return 0; | |
1109 | } | |
1110 | ||
ccdf81d0 DD |
1111 | static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, |
1112 | bool enable) | |
1113 | { | |
1114 | void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); | |
1115 | unsigned long flags; | |
1116 | u32 ctrl1; | |
1117 | ||
1118 | raw_spin_lock_irqsave(&chv_lock, flags); | |
1119 | ctrl1 = readl(reg); | |
1120 | ||
1121 | if (enable) | |
1122 | ctrl1 |= CHV_PADCTRL1_ODEN; | |
1123 | else | |
1124 | ctrl1 &= ~CHV_PADCTRL1_ODEN; | |
1125 | ||
1126 | chv_writel(ctrl1, reg); | |
1127 | raw_spin_unlock_irqrestore(&chv_lock, flags); | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
6e08d6bb MW |
1132 | static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin, |
1133 | unsigned long *configs, unsigned nconfigs) | |
1134 | { | |
1135 | struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
1136 | enum pin_config_param param; | |
1137 | int i, ret; | |
1138 | u16 arg; | |
1139 | ||
1140 | if (chv_pad_locked(pctrl, pin)) | |
1141 | return -EBUSY; | |
1142 | ||
1143 | for (i = 0; i < nconfigs; i++) { | |
1144 | param = pinconf_to_config_param(configs[i]); | |
1145 | arg = pinconf_to_config_argument(configs[i]); | |
1146 | ||
1147 | switch (param) { | |
1148 | case PIN_CONFIG_BIAS_DISABLE: | |
1149 | case PIN_CONFIG_BIAS_PULL_UP: | |
1150 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
1151 | ret = chv_config_set_pull(pctrl, pin, param, arg); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | break; | |
1155 | ||
ccdf81d0 DD |
1156 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
1157 | ret = chv_config_set_oden(pctrl, pin, false); | |
1158 | if (ret) | |
1159 | return ret; | |
1160 | break; | |
1161 | ||
1162 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
1163 | ret = chv_config_set_oden(pctrl, pin, true); | |
1164 | if (ret) | |
1165 | return ret; | |
1166 | break; | |
1167 | ||
6e08d6bb MW |
1168 | default: |
1169 | return -ENOTSUPP; | |
1170 | } | |
1171 | ||
1172 | dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin, | |
1173 | param, arg); | |
1174 | } | |
1175 | ||
1176 | return 0; | |
1177 | } | |
1178 | ||
77401d7f DD |
1179 | static int chv_config_group_get(struct pinctrl_dev *pctldev, |
1180 | unsigned int group, | |
1181 | unsigned long *config) | |
1182 | { | |
1183 | const unsigned int *pins; | |
1184 | unsigned int npins; | |
1185 | int ret; | |
1186 | ||
1187 | ret = chv_get_group_pins(pctldev, group, &pins, &npins); | |
1188 | if (ret) | |
1189 | return ret; | |
1190 | ||
1191 | ret = chv_config_get(pctldev, pins[0], config); | |
1192 | if (ret) | |
1193 | return ret; | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | static int chv_config_group_set(struct pinctrl_dev *pctldev, | |
1199 | unsigned int group, unsigned long *configs, | |
1200 | unsigned int num_configs) | |
1201 | { | |
1202 | const unsigned int *pins; | |
1203 | unsigned int npins; | |
1204 | int i, ret; | |
1205 | ||
1206 | ret = chv_get_group_pins(pctldev, group, &pins, &npins); | |
1207 | if (ret) | |
1208 | return ret; | |
1209 | ||
1210 | for (i = 0; i < npins; i++) { | |
1211 | ret = chv_config_set(pctldev, pins[i], configs, num_configs); | |
1212 | if (ret) | |
1213 | return ret; | |
1214 | } | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
6e08d6bb MW |
1219 | static const struct pinconf_ops chv_pinconf_ops = { |
1220 | .is_generic = true, | |
1221 | .pin_config_set = chv_config_set, | |
1222 | .pin_config_get = chv_config_get, | |
77401d7f DD |
1223 | .pin_config_group_get = chv_config_group_get, |
1224 | .pin_config_group_set = chv_config_group_set, | |
6e08d6bb MW |
1225 | }; |
1226 | ||
1227 | static struct pinctrl_desc chv_pinctrl_desc = { | |
1228 | .pctlops = &chv_pinctrl_ops, | |
1229 | .pmxops = &chv_pinmux_ops, | |
1230 | .confops = &chv_pinconf_ops, | |
1231 | .owner = THIS_MODULE, | |
1232 | }; | |
1233 | ||
6e08d6bb MW |
1234 | static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, |
1235 | unsigned offset) | |
1236 | { | |
1237 | return pctrl->community->pins[offset].number; | |
1238 | } | |
1239 | ||
1240 | static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1241 | { | |
0587d3db | 1242 | struct chv_pinctrl *pctrl = gpiochip_get_data(chip); |
6e08d6bb | 1243 | int pin = chv_gpio_offset_to_pin(pctrl, offset); |
4585b000 | 1244 | unsigned long flags; |
6e08d6bb MW |
1245 | u32 ctrl0, cfg; |
1246 | ||
0bd50d71 | 1247 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb | 1248 | ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); |
0bd50d71 | 1249 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1250 | |
1251 | cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; | |
1252 | cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; | |
1253 | ||
1254 | if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) | |
1255 | return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); | |
1256 | return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); | |
1257 | } | |
1258 | ||
1259 | static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1260 | { | |
0587d3db | 1261 | struct chv_pinctrl *pctrl = gpiochip_get_data(chip); |
6e08d6bb MW |
1262 | unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); |
1263 | unsigned long flags; | |
1264 | void __iomem *reg; | |
1265 | u32 ctrl0; | |
1266 | ||
0bd50d71 | 1267 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
1268 | |
1269 | reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); | |
1270 | ctrl0 = readl(reg); | |
1271 | ||
1272 | if (value) | |
1273 | ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; | |
1274 | else | |
1275 | ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; | |
1276 | ||
1277 | chv_writel(ctrl0, reg); | |
1278 | ||
0bd50d71 | 1279 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1280 | } |
1281 | ||
1282 | static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) | |
1283 | { | |
0587d3db | 1284 | struct chv_pinctrl *pctrl = gpiochip_get_data(chip); |
6e08d6bb MW |
1285 | unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); |
1286 | u32 ctrl0, direction; | |
4585b000 | 1287 | unsigned long flags; |
6e08d6bb | 1288 | |
0bd50d71 | 1289 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb | 1290 | ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); |
0bd50d71 | 1291 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1292 | |
1293 | direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; | |
1294 | direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; | |
1295 | ||
1296 | return direction != CHV_PADCTRL0_GPIOCFG_GPO; | |
1297 | } | |
1298 | ||
1299 | static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
1300 | { | |
1301 | return pinctrl_gpio_direction_input(chip->base + offset); | |
1302 | } | |
1303 | ||
1304 | static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
1305 | int value) | |
1306 | { | |
549e783f | 1307 | chv_gpio_set(chip, offset, value); |
6e08d6bb MW |
1308 | return pinctrl_gpio_direction_output(chip->base + offset); |
1309 | } | |
1310 | ||
1311 | static const struct gpio_chip chv_gpio_chip = { | |
1312 | .owner = THIS_MODULE, | |
98c85d58 JG |
1313 | .request = gpiochip_generic_request, |
1314 | .free = gpiochip_generic_free, | |
6e08d6bb MW |
1315 | .get_direction = chv_gpio_get_direction, |
1316 | .direction_input = chv_gpio_direction_input, | |
1317 | .direction_output = chv_gpio_direction_output, | |
1318 | .get = chv_gpio_get, | |
1319 | .set = chv_gpio_set, | |
1320 | }; | |
1321 | ||
1322 | static void chv_gpio_irq_ack(struct irq_data *d) | |
1323 | { | |
1324 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
0587d3db | 1325 | struct chv_pinctrl *pctrl = gpiochip_get_data(gc); |
6e08d6bb MW |
1326 | int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); |
1327 | u32 intr_line; | |
1328 | ||
0bd50d71 | 1329 | raw_spin_lock(&chv_lock); |
6e08d6bb MW |
1330 | |
1331 | intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); | |
1332 | intr_line &= CHV_PADCTRL0_INTSEL_MASK; | |
1333 | intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; | |
1334 | chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT); | |
1335 | ||
0bd50d71 | 1336 | raw_spin_unlock(&chv_lock); |
6e08d6bb MW |
1337 | } |
1338 | ||
1339 | static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) | |
1340 | { | |
1341 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
0587d3db | 1342 | struct chv_pinctrl *pctrl = gpiochip_get_data(gc); |
6e08d6bb MW |
1343 | int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); |
1344 | u32 value, intr_line; | |
1345 | unsigned long flags; | |
1346 | ||
0bd50d71 | 1347 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
1348 | |
1349 | intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); | |
1350 | intr_line &= CHV_PADCTRL0_INTSEL_MASK; | |
1351 | intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; | |
1352 | ||
1353 | value = readl(pctrl->regs + CHV_INTMASK); | |
1354 | if (mask) | |
1355 | value &= ~BIT(intr_line); | |
1356 | else | |
1357 | value |= BIT(intr_line); | |
1358 | chv_writel(value, pctrl->regs + CHV_INTMASK); | |
1359 | ||
0bd50d71 | 1360 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1361 | } |
1362 | ||
1363 | static void chv_gpio_irq_mask(struct irq_data *d) | |
1364 | { | |
1365 | chv_gpio_irq_mask_unmask(d, true); | |
1366 | } | |
1367 | ||
1368 | static void chv_gpio_irq_unmask(struct irq_data *d) | |
1369 | { | |
1370 | chv_gpio_irq_mask_unmask(d, false); | |
1371 | } | |
1372 | ||
e6c906de MW |
1373 | static unsigned chv_gpio_irq_startup(struct irq_data *d) |
1374 | { | |
1375 | /* | |
1376 | * Check if the interrupt has been requested with 0 as triggering | |
1377 | * type. In that case it is assumed that the current values | |
1378 | * programmed to the hardware are used (e.g BIOS configured | |
1379 | * defaults). | |
1380 | * | |
1381 | * In that case ->irq_set_type() will never be called so we need to | |
1382 | * read back the values from hardware now, set correct flow handler | |
1383 | * and update mappings before the interrupt is being used. | |
1384 | */ | |
1385 | if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { | |
1386 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
0587d3db | 1387 | struct chv_pinctrl *pctrl = gpiochip_get_data(gc); |
e6c906de MW |
1388 | unsigned offset = irqd_to_hwirq(d); |
1389 | int pin = chv_gpio_offset_to_pin(pctrl, offset); | |
1390 | irq_flow_handler_t handler; | |
1391 | unsigned long flags; | |
1392 | u32 intsel, value; | |
1393 | ||
0bd50d71 | 1394 | raw_spin_lock_irqsave(&chv_lock, flags); |
e6c906de MW |
1395 | intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); |
1396 | intsel &= CHV_PADCTRL0_INTSEL_MASK; | |
1397 | intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; | |
1398 | ||
1399 | value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1)); | |
1400 | if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) | |
1401 | handler = handle_level_irq; | |
1402 | else | |
1403 | handler = handle_edge_irq; | |
1404 | ||
e6c906de | 1405 | if (!pctrl->intr_lines[intsel]) { |
a4e3f783 | 1406 | irq_set_handler_locked(d, handler); |
e6c906de MW |
1407 | pctrl->intr_lines[intsel] = offset; |
1408 | } | |
0bd50d71 | 1409 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
e6c906de MW |
1410 | } |
1411 | ||
1412 | chv_gpio_irq_unmask(d); | |
1413 | return 0; | |
1414 | } | |
1415 | ||
6e08d6bb MW |
1416 | static int chv_gpio_irq_type(struct irq_data *d, unsigned type) |
1417 | { | |
1418 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
0587d3db | 1419 | struct chv_pinctrl *pctrl = gpiochip_get_data(gc); |
6e08d6bb MW |
1420 | unsigned offset = irqd_to_hwirq(d); |
1421 | int pin = chv_gpio_offset_to_pin(pctrl, offset); | |
1422 | unsigned long flags; | |
1423 | u32 value; | |
1424 | ||
0bd50d71 | 1425 | raw_spin_lock_irqsave(&chv_lock, flags); |
6e08d6bb MW |
1426 | |
1427 | /* | |
1428 | * Pins which can be used as shared interrupt are configured in | |
1429 | * BIOS. Driver trusts BIOS configurations and assigns different | |
1430 | * handler according to the irq type. | |
1431 | * | |
1432 | * Driver needs to save the mapping between each pin and | |
1433 | * its interrupt line. | |
1434 | * 1. If the pin cfg is locked in BIOS: | |
1435 | * Trust BIOS has programmed IntWakeCfg bits correctly, | |
1436 | * driver just needs to save the mapping. | |
1437 | * 2. If the pin cfg is not locked in BIOS: | |
1438 | * Driver programs the IntWakeCfg bits and save the mapping. | |
1439 | */ | |
1440 | if (!chv_pad_locked(pctrl, pin)) { | |
1441 | void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); | |
1442 | ||
1443 | value = readl(reg); | |
1444 | value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; | |
1445 | value &= ~CHV_PADCTRL1_INVRXTX_MASK; | |
1446 | ||
1447 | if (type & IRQ_TYPE_EDGE_BOTH) { | |
1448 | if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | |
1449 | value |= CHV_PADCTRL1_INTWAKECFG_BOTH; | |
1450 | else if (type & IRQ_TYPE_EDGE_RISING) | |
1451 | value |= CHV_PADCTRL1_INTWAKECFG_RISING; | |
1452 | else if (type & IRQ_TYPE_EDGE_FALLING) | |
1453 | value |= CHV_PADCTRL1_INTWAKECFG_FALLING; | |
1454 | } else if (type & IRQ_TYPE_LEVEL_MASK) { | |
1455 | value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; | |
1456 | if (type & IRQ_TYPE_LEVEL_LOW) | |
1457 | value |= CHV_PADCTRL1_INVRXTX_RXDATA; | |
1458 | } | |
1459 | ||
1460 | chv_writel(value, reg); | |
1461 | } | |
1462 | ||
1463 | value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); | |
1464 | value &= CHV_PADCTRL0_INTSEL_MASK; | |
1465 | value >>= CHV_PADCTRL0_INTSEL_SHIFT; | |
1466 | ||
1467 | pctrl->intr_lines[value] = offset; | |
1468 | ||
1469 | if (type & IRQ_TYPE_EDGE_BOTH) | |
a4e3f783 | 1470 | irq_set_handler_locked(d, handle_edge_irq); |
6e08d6bb | 1471 | else if (type & IRQ_TYPE_LEVEL_MASK) |
a4e3f783 | 1472 | irq_set_handler_locked(d, handle_level_irq); |
6e08d6bb | 1473 | |
0bd50d71 | 1474 | raw_spin_unlock_irqrestore(&chv_lock, flags); |
6e08d6bb MW |
1475 | |
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | static struct irq_chip chv_gpio_irqchip = { | |
1480 | .name = "chv-gpio", | |
e6c906de | 1481 | .irq_startup = chv_gpio_irq_startup, |
6e08d6bb MW |
1482 | .irq_ack = chv_gpio_irq_ack, |
1483 | .irq_mask = chv_gpio_irq_mask, | |
1484 | .irq_unmask = chv_gpio_irq_unmask, | |
1485 | .irq_set_type = chv_gpio_irq_type, | |
1486 | .flags = IRQCHIP_SKIP_SET_WAKE, | |
1487 | }; | |
1488 | ||
bd0b9ac4 | 1489 | static void chv_gpio_irq_handler(struct irq_desc *desc) |
6e08d6bb MW |
1490 | { |
1491 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); | |
0587d3db | 1492 | struct chv_pinctrl *pctrl = gpiochip_get_data(gc); |
5663bb27 | 1493 | struct irq_chip *chip = irq_desc_get_chip(desc); |
6e08d6bb MW |
1494 | unsigned long pending; |
1495 | u32 intr_line; | |
1496 | ||
1497 | chained_irq_enter(chip, desc); | |
1498 | ||
1499 | pending = readl(pctrl->regs + CHV_INTSTAT); | |
1500 | for_each_set_bit(intr_line, &pending, 16) { | |
1501 | unsigned irq, offset; | |
1502 | ||
1503 | offset = pctrl->intr_lines[intr_line]; | |
1504 | irq = irq_find_mapping(gc->irqdomain, offset); | |
1505 | generic_handle_irq(irq); | |
1506 | } | |
1507 | ||
1508 | chained_irq_exit(chip, desc); | |
1509 | } | |
1510 | ||
1511 | static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) | |
1512 | { | |
1513 | const struct chv_gpio_pinrange *range; | |
1514 | struct gpio_chip *chip = &pctrl->chip; | |
1515 | int ret, i, offset; | |
1516 | ||
1517 | *chip = chv_gpio_chip; | |
1518 | ||
1519 | chip->ngpio = pctrl->community->ngpios; | |
1520 | chip->label = dev_name(pctrl->dev); | |
58383c78 | 1521 | chip->parent = pctrl->dev; |
6e08d6bb MW |
1522 | chip->base = -1; |
1523 | ||
0587d3db | 1524 | ret = gpiochip_add_data(chip, pctrl); |
6e08d6bb MW |
1525 | if (ret) { |
1526 | dev_err(pctrl->dev, "Failed to register gpiochip\n"); | |
1527 | return ret; | |
1528 | } | |
1529 | ||
1530 | for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) { | |
1531 | range = &pctrl->community->gpio_ranges[i]; | |
1532 | ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset, | |
1533 | range->base, range->npins); | |
1534 | if (ret) { | |
1535 | dev_err(pctrl->dev, "failed to add GPIO pin range\n"); | |
1536 | goto fail; | |
1537 | } | |
1538 | ||
1539 | offset += range->npins; | |
1540 | } | |
1541 | ||
bcb48cca | 1542 | /* Clear all interrupts */ |
6e08d6bb MW |
1543 | chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); |
1544 | ||
1545 | ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, | |
bcb48cca | 1546 | handle_bad_irq, IRQ_TYPE_NONE); |
6e08d6bb MW |
1547 | if (ret) { |
1548 | dev_err(pctrl->dev, "failed to add IRQ chip\n"); | |
1549 | goto fail; | |
1550 | } | |
1551 | ||
1552 | gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, | |
1553 | chv_gpio_irq_handler); | |
1554 | return 0; | |
1555 | ||
1556 | fail: | |
1557 | gpiochip_remove(chip); | |
1558 | ||
1559 | return ret; | |
1560 | } | |
1561 | ||
1562 | static int chv_pinctrl_probe(struct platform_device *pdev) | |
1563 | { | |
1564 | struct chv_pinctrl *pctrl; | |
1565 | struct acpi_device *adev; | |
1566 | struct resource *res; | |
1567 | int ret, irq, i; | |
1568 | ||
1569 | adev = ACPI_COMPANION(&pdev->dev); | |
1570 | if (!adev) | |
1571 | return -ENODEV; | |
1572 | ||
1573 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
1574 | if (!pctrl) | |
1575 | return -ENOMEM; | |
1576 | ||
1577 | for (i = 0; i < ARRAY_SIZE(chv_communities); i++) | |
1578 | if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) { | |
1579 | pctrl->community = chv_communities[i]; | |
1580 | break; | |
1581 | } | |
1582 | if (i == ARRAY_SIZE(chv_communities)) | |
1583 | return -ENODEV; | |
1584 | ||
6e08d6bb MW |
1585 | pctrl->dev = &pdev->dev; |
1586 | ||
9eb457b5 MW |
1587 | #ifdef CONFIG_PM_SLEEP |
1588 | pctrl->saved_pin_context = devm_kcalloc(pctrl->dev, | |
1589 | pctrl->community->npins, sizeof(*pctrl->saved_pin_context), | |
1590 | GFP_KERNEL); | |
1591 | if (!pctrl->saved_pin_context) | |
1592 | return -ENOMEM; | |
1593 | #endif | |
1594 | ||
6e08d6bb MW |
1595 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1596 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
1597 | if (IS_ERR(pctrl->regs)) | |
1598 | return PTR_ERR(pctrl->regs); | |
1599 | ||
1600 | irq = platform_get_irq(pdev, 0); | |
1601 | if (irq < 0) { | |
1602 | dev_err(&pdev->dev, "failed to get interrupt number\n"); | |
1603 | return irq; | |
1604 | } | |
1605 | ||
1606 | pctrl->pctldesc = chv_pinctrl_desc; | |
1607 | pctrl->pctldesc.name = dev_name(&pdev->dev); | |
1608 | pctrl->pctldesc.pins = pctrl->community->pins; | |
1609 | pctrl->pctldesc.npins = pctrl->community->npins; | |
1610 | ||
7cf061fa LD |
1611 | pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, |
1612 | pctrl); | |
323de9ef | 1613 | if (IS_ERR(pctrl->pctldev)) { |
6e08d6bb | 1614 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); |
323de9ef | 1615 | return PTR_ERR(pctrl->pctldev); |
6e08d6bb MW |
1616 | } |
1617 | ||
1618 | ret = chv_gpio_probe(pctrl, irq); | |
7cf061fa | 1619 | if (ret) |
6e08d6bb | 1620 | return ret; |
6e08d6bb MW |
1621 | |
1622 | platform_set_drvdata(pdev, pctrl); | |
1623 | ||
1624 | return 0; | |
1625 | } | |
1626 | ||
1627 | static int chv_pinctrl_remove(struct platform_device *pdev) | |
1628 | { | |
1629 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1630 | ||
1631 | gpiochip_remove(&pctrl->chip); | |
6e08d6bb MW |
1632 | |
1633 | return 0; | |
1634 | } | |
1635 | ||
9eb457b5 MW |
1636 | #ifdef CONFIG_PM_SLEEP |
1637 | static int chv_pinctrl_suspend(struct device *dev) | |
1638 | { | |
1639 | struct platform_device *pdev = to_platform_device(dev); | |
1640 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1641 | int i; | |
1642 | ||
1643 | pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK); | |
1644 | ||
1645 | for (i = 0; i < pctrl->community->npins; i++) { | |
1646 | const struct pinctrl_pin_desc *desc; | |
1647 | struct chv_pin_context *ctx; | |
1648 | void __iomem *reg; | |
1649 | ||
1650 | desc = &pctrl->community->pins[i]; | |
1651 | if (chv_pad_locked(pctrl, desc->number)) | |
1652 | continue; | |
1653 | ||
1654 | ctx = &pctrl->saved_pin_context[i]; | |
1655 | ||
1656 | reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); | |
1657 | ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; | |
1658 | ||
1659 | reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); | |
1660 | ctx->padctrl1 = readl(reg); | |
1661 | } | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | static int chv_pinctrl_resume(struct device *dev) | |
1667 | { | |
1668 | struct platform_device *pdev = to_platform_device(dev); | |
1669 | struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); | |
1670 | int i; | |
1671 | ||
1672 | /* | |
1673 | * Mask all interrupts before restoring per-pin configuration | |
1674 | * registers because we don't know in which state BIOS left them | |
1675 | * upon exiting suspend. | |
1676 | */ | |
1677 | chv_writel(0, pctrl->regs + CHV_INTMASK); | |
1678 | ||
1679 | for (i = 0; i < pctrl->community->npins; i++) { | |
1680 | const struct pinctrl_pin_desc *desc; | |
1681 | const struct chv_pin_context *ctx; | |
1682 | void __iomem *reg; | |
1683 | u32 val; | |
1684 | ||
1685 | desc = &pctrl->community->pins[i]; | |
1686 | if (chv_pad_locked(pctrl, desc->number)) | |
1687 | continue; | |
1688 | ||
1689 | ctx = &pctrl->saved_pin_context[i]; | |
1690 | ||
1691 | /* Only restore if our saved state differs from the current */ | |
1692 | reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0); | |
1693 | val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE; | |
1694 | if (ctx->padctrl0 != val) { | |
1695 | chv_writel(ctx->padctrl0, reg); | |
1696 | dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n", | |
1697 | desc->number, readl(reg)); | |
1698 | } | |
1699 | ||
1700 | reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1); | |
1701 | val = readl(reg); | |
1702 | if (ctx->padctrl1 != val) { | |
1703 | chv_writel(ctx->padctrl1, reg); | |
1704 | dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n", | |
1705 | desc->number, readl(reg)); | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | /* | |
1710 | * Now that all pins are restored to known state, we can restore | |
1711 | * the interrupt mask register as well. | |
1712 | */ | |
1713 | chv_writel(0xffff, pctrl->regs + CHV_INTSTAT); | |
1714 | chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK); | |
1715 | ||
1716 | return 0; | |
1717 | } | |
1718 | #endif | |
1719 | ||
1720 | static const struct dev_pm_ops chv_pinctrl_pm_ops = { | |
1721 | SET_LATE_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend, chv_pinctrl_resume) | |
1722 | }; | |
1723 | ||
6e08d6bb MW |
1724 | static const struct acpi_device_id chv_pinctrl_acpi_match[] = { |
1725 | { "INT33FF" }, | |
1726 | { } | |
1727 | }; | |
1728 | MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); | |
1729 | ||
1730 | static struct platform_driver chv_pinctrl_driver = { | |
1731 | .probe = chv_pinctrl_probe, | |
1732 | .remove = chv_pinctrl_remove, | |
1733 | .driver = { | |
1734 | .name = "cherryview-pinctrl", | |
9eb457b5 | 1735 | .pm = &chv_pinctrl_pm_ops, |
6e08d6bb MW |
1736 | .acpi_match_table = chv_pinctrl_acpi_match, |
1737 | }, | |
1738 | }; | |
1739 | ||
1740 | static int __init chv_pinctrl_init(void) | |
1741 | { | |
1742 | return platform_driver_register(&chv_pinctrl_driver); | |
1743 | } | |
1744 | subsys_initcall(chv_pinctrl_init); | |
1745 | ||
1746 | static void __exit chv_pinctrl_exit(void) | |
1747 | { | |
1748 | platform_driver_unregister(&chv_pinctrl_driver); | |
1749 | } | |
1750 | module_exit(chv_pinctrl_exit); | |
1751 | ||
1752 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); | |
1753 | MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); | |
1754 | MODULE_LICENSE("GPL v2"); |