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Merge remote-tracking branches 'spi/fix/lock', 'spi/fix/maintainers', 'spi/fix/put...
[deliverable/linux.git] / drivers / pinctrl / intel / pinctrl-intel.c
CommitLineData
7981c001
MW		 1/*
2 * Intel pinctrl/GPIO core driver.
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
193b40c8 14#include <linux/interrupt.h>
7981c001
MW		 15#include <linux/gpio/driver.h>
16#include <linux/platform_device.h>
7981c001
MW		 17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21
22#include "pinctrl-intel.h"
23
7981c001
MW		 24/* Offset from regs */
25#define PADBAR 0x00c
26#define GPI_IS 0x100
27#define GPI_GPE_STS 0x140
28#define GPI_GPE_EN 0x160
29
30#define PADOWN_BITS 4
31#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
32#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
99a735b3 33#define PADOWN_GPP(p) ((p) / 8)
7981c001
MW		 34
35/* Offset from pad_regs */
36#define PADCFG0 0x000
37#define PADCFG0_RXEVCFG_SHIFT 25
38#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
39#define PADCFG0_RXEVCFG_LEVEL 0
40#define PADCFG0_RXEVCFG_EDGE 1
41#define PADCFG0_RXEVCFG_DISABLED 2
42#define PADCFG0_RXEVCFG_EDGE_BOTH 3
43#define PADCFG0_RXINV BIT(23)
44#define PADCFG0_GPIROUTIOXAPIC BIT(20)
45#define PADCFG0_GPIROUTSCI BIT(19)
46#define PADCFG0_GPIROUTSMI BIT(18)
47#define PADCFG0_GPIROUTNMI BIT(17)
48#define PADCFG0_PMODE_SHIFT 10
49#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
50#define PADCFG0_GPIORXDIS BIT(9)
51#define PADCFG0_GPIOTXDIS BIT(8)
52#define PADCFG0_GPIORXSTATE BIT(1)
53#define PADCFG0_GPIOTXSTATE BIT(0)
54
55#define PADCFG1 0x004
56#define PADCFG1_TERM_UP BIT(13)
57#define PADCFG1_TERM_SHIFT 10
58#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
59#define PADCFG1_TERM_20K 4
60#define PADCFG1_TERM_2K 3
61#define PADCFG1_TERM_5K 2
62#define PADCFG1_TERM_1K 1
63
64struct intel_pad_context {
65 u32 padcfg0;
66 u32 padcfg1;
67};
68
69struct intel_community_context {
70 u32 *intmask;
71};
72
73struct intel_pinctrl_context {
74 struct intel_pad_context *pads;
75 struct intel_community_context *communities;
76};
77
78/**
79 * struct intel_pinctrl - Intel pinctrl private structure
80 * @dev: Pointer to the device structure
81 * @lock: Lock to serialize register access
82 * @pctldesc: Pin controller description
83 * @pctldev: Pointer to the pin controller device
84 * @chip: GPIO chip in this pin controller
85 * @soc: SoC/PCH specific pin configuration data
86 * @communities: All communities in this pin controller
87 * @ncommunities: Number of communities in this pin controller
88 * @context: Configuration saved over system sleep
89 */
90struct intel_pinctrl {
91 struct device *dev;
27d9098c 92 raw_spinlock_t lock;
7981c001
MW		 93 struct pinctrl_desc pctldesc;
94 struct pinctrl_dev *pctldev;
95 struct gpio_chip chip;
96 const struct intel_pinctrl_soc_data *soc;
97 struct intel_community *communities;
98 size_t ncommunities;
99 struct intel_pinctrl_context context;
100};
101
7981c001
MW		 102#define pin_to_padno(c, p) ((p) - (c)->pin_base)
103
104static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
105 unsigned pin)
106{
107 struct intel_community *community;
108 int i;
109
110 for (i = 0; i < pctrl->ncommunities; i++) {
111 community = &pctrl->communities[i];
112 if (pin >= community->pin_base &&
113 pin < community->pin_base + community->npins)
114 return community;
115 }
116
117 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
118 return NULL;
119}
120
121static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
122 unsigned reg)
123{
124 const struct intel_community *community;
125 unsigned padno;
126
127 community = intel_get_community(pctrl, pin);
128 if (!community)
129 return NULL;
130
131 padno = pin_to_padno(community, pin);
132 return community->pad_regs + reg + padno * 8;
133}
134
135static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
136{
137 const struct intel_community *community;
99a735b3 138 unsigned padno, gpp, offset, group;
7981c001
MW		 139 void __iomem *padown;
140
141 community = intel_get_community(pctrl, pin);
142 if (!community)
143 return false;
144 if (!community->padown_offset)
145 return true;
146
147 padno = pin_to_padno(community, pin);
99a735b3
QZ		 148 group = padno / community->gpp_size;
149 gpp = PADOWN_GPP(padno % community->gpp_size);
150 offset = community->padown_offset + 0x10 * group + gpp * 4;
7981c001
MW		 151 padown = community->regs + offset;
152
153 return !(readl(padown) & PADOWN_MASK(padno));
154}
155
4341e8a5 156static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
7981c001
MW		 157{
158 const struct intel_community *community;
159 unsigned padno, gpp, offset;
160 void __iomem *hostown;
161
162 community = intel_get_community(pctrl, pin);
163 if (!community)
164 return true;
165 if (!community->hostown_offset)
166 return false;
167
168 padno = pin_to_padno(community, pin);
618a919b 169 gpp = padno / community->gpp_size;
7981c001
MW		 170 offset = community->hostown_offset + gpp * 4;
171 hostown = community->regs + offset;
172
618a919b 173 return !(readl(hostown) & BIT(padno % community->gpp_size));
7981c001
MW		 174}
175
176static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
177{
178 struct intel_community *community;
179 unsigned padno, gpp, offset;
180 u32 value;
181
182 community = intel_get_community(pctrl, pin);
183 if (!community)
184 return true;
185 if (!community->padcfglock_offset)
186 return false;
187
188 padno = pin_to_padno(community, pin);
618a919b 189 gpp = padno / community->gpp_size;
7981c001
MW		 190
191 /*
192 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
193 * the pad is considered unlocked. Any other case means that it is
194 * either fully or partially locked and we don't touch it.
195 */
196 offset = community->padcfglock_offset + gpp * 8;
197 value = readl(community->regs + offset);
618a919b 198 if (value & BIT(pin % community->gpp_size))
7981c001
MW		 199 return true;
200
201 offset = community->padcfglock_offset + 4 + gpp * 8;
202 value = readl(community->regs + offset);
618a919b 203 if (value & BIT(pin % community->gpp_size))
7981c001
MW		 204 return true;
205
206 return false;
207}
208
209static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
210{
211 return intel_pad_owned_by_host(pctrl, pin) &&
7981c001
MW		 212 !intel_pad_locked(pctrl, pin);
213}
214
215static int intel_get_groups_count(struct pinctrl_dev *pctldev)
216{
217 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
218
219 return pctrl->soc->ngroups;
220}
221
222static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
223 unsigned group)
224{
225 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
226
227 return pctrl->soc->groups[group].name;
228}
229
230static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
231 const unsigned **pins, unsigned *npins)
232{
233 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
234
235 *pins = pctrl->soc->groups[group].pins;
236 *npins = pctrl->soc->groups[group].npins;
237 return 0;
238}
239
240static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
241 unsigned pin)
242{
243 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
244 u32 cfg0, cfg1, mode;
245 bool locked, acpi;
246
247 if (!intel_pad_owned_by_host(pctrl, pin)) {
248 seq_puts(s, "not available");
249 return;
250 }
251
252 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
253 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
254
255 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
256 if (!mode)
257 seq_puts(s, "GPIO ");
258 else
259 seq_printf(s, "mode %d ", mode);
260
261 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
262
263 locked = intel_pad_locked(pctrl, pin);
4341e8a5 264 acpi = intel_pad_acpi_mode(pctrl, pin);
7981c001
MW		 265
266 if (locked || acpi) {
267 seq_puts(s, " [");
268 if (locked) {
269 seq_puts(s, "LOCKED");
270 if (acpi)
271 seq_puts(s, ", ");
272 }
273 if (acpi)
274 seq_puts(s, "ACPI");
275 seq_puts(s, "]");
276 }
277}
278
279static const struct pinctrl_ops intel_pinctrl_ops = {
280 .get_groups_count = intel_get_groups_count,
281 .get_group_name = intel_get_group_name,
282 .get_group_pins = intel_get_group_pins,
283 .pin_dbg_show = intel_pin_dbg_show,
284};
285
286static int intel_get_functions_count(struct pinctrl_dev *pctldev)
287{
288 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
289
290 return pctrl->soc->nfunctions;
291}
292
293static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
294 unsigned function)
295{
296 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
297
298 return pctrl->soc->functions[function].name;
299}
300
301static int intel_get_function_groups(struct pinctrl_dev *pctldev,
302 unsigned function,
303 const char * const **groups,
304 unsigned * const ngroups)
305{
306 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
307
308 *groups = pctrl->soc->functions[function].groups;
309 *ngroups = pctrl->soc->functions[function].ngroups;
310 return 0;
311}
312
313static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
314 unsigned group)
315{
316 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
317 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
318 unsigned long flags;
319 int i;
320
27d9098c 321 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 322
323 /*
324 * All pins in the groups needs to be accessible and writable
325 * before we can enable the mux for this group.
326 */
327 for (i = 0; i < grp->npins; i++) {
328 if (!intel_pad_usable(pctrl, grp->pins[i])) {
27d9098c 329 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 330 return -EBUSY;
331 }
332 }
333
334 /* Now enable the mux setting for each pin in the group */
335 for (i = 0; i < grp->npins; i++) {
336 void __iomem *padcfg0;
337 u32 value;
338
339 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
340 value = readl(padcfg0);
341
342 value &= ~PADCFG0_PMODE_MASK;
343 value |= grp->mode << PADCFG0_PMODE_SHIFT;
344
345 writel(value, padcfg0);
346 }
347
27d9098c 348 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 349
350 return 0;
351}
352
353static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
354 struct pinctrl_gpio_range *range,
355 unsigned pin)
356{
357 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
358 void __iomem *padcfg0;
359 unsigned long flags;
360 u32 value;
361
27d9098c 362 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 363
364 if (!intel_pad_usable(pctrl, pin)) {
27d9098c 365 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 366 return -EBUSY;
367 }
368
369 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
370 /* Put the pad into GPIO mode */
371 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
372 /* Disable SCI/SMI/NMI generation */
373 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
374 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
375 /* Disable TX buffer and enable RX (this will be input) */
376 value &= ~PADCFG0_GPIORXDIS;
377 value |= PADCFG0_GPIOTXDIS;
378 writel(value, padcfg0);
379
27d9098c 380 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 381
382 return 0;
383}
384
385static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
386 struct pinctrl_gpio_range *range,
387 unsigned pin, bool input)
388{
389 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
390 void __iomem *padcfg0;
391 unsigned long flags;
392 u32 value;
393
27d9098c 394 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 395
396 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
397
398 value = readl(padcfg0);
399 if (input)
400 value |= PADCFG0_GPIOTXDIS;
401 else
402 value &= ~PADCFG0_GPIOTXDIS;
403 writel(value, padcfg0);
404
27d9098c 405 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 406
407 return 0;
408}
409
410static const struct pinmux_ops intel_pinmux_ops = {
411 .get_functions_count = intel_get_functions_count,
412 .get_function_name = intel_get_function_name,
413 .get_function_groups = intel_get_function_groups,
414 .set_mux = intel_pinmux_set_mux,
415 .gpio_request_enable = intel_gpio_request_enable,
416 .gpio_set_direction = intel_gpio_set_direction,
417};
418
419static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
420 unsigned long *config)
421{
422 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
423 enum pin_config_param param = pinconf_to_config_param(*config);
424 u32 value, term;
425 u16 arg = 0;
426
427 if (!intel_pad_owned_by_host(pctrl, pin))
428 return -ENOTSUPP;
429
430 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
431 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
432
433 switch (param) {
434 case PIN_CONFIG_BIAS_DISABLE:
435 if (term)
436 return -EINVAL;
437 break;
438
439 case PIN_CONFIG_BIAS_PULL_UP:
440 if (!term || !(value & PADCFG1_TERM_UP))
441 return -EINVAL;
442
443 switch (term) {
444 case PADCFG1_TERM_1K:
445 arg = 1000;
446 break;
447 case PADCFG1_TERM_2K:
448 arg = 2000;
449 break;
450 case PADCFG1_TERM_5K:
451 arg = 5000;
452 break;
453 case PADCFG1_TERM_20K:
454 arg = 20000;
455 break;
456 }
457
458 break;
459
460 case PIN_CONFIG_BIAS_PULL_DOWN:
461 if (!term || value & PADCFG1_TERM_UP)
462 return -EINVAL;
463
464 switch (term) {
465 case PADCFG1_TERM_5K:
466 arg = 5000;
467 break;
468 case PADCFG1_TERM_20K:
469 arg = 20000;
470 break;
471 }
472
473 break;
474
475 default:
476 return -ENOTSUPP;
477 }
478
479 *config = pinconf_to_config_packed(param, arg);
480 return 0;
481}
482
483static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
484 unsigned long config)
485{
486 unsigned param = pinconf_to_config_param(config);
487 unsigned arg = pinconf_to_config_argument(config);
488 void __iomem *padcfg1;
489 unsigned long flags;
490 int ret = 0;
491 u32 value;
492
27d9098c 493 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 494
495 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
496 value = readl(padcfg1);
497
498 switch (param) {
499 case PIN_CONFIG_BIAS_DISABLE:
500 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
501 break;
502
503 case PIN_CONFIG_BIAS_PULL_UP:
504 value &= ~PADCFG1_TERM_MASK;
505
506 value |= PADCFG1_TERM_UP;
507
508 switch (arg) {
509 case 20000:
510 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
511 break;
512 case 5000:
513 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
514 break;
515 case 2000:
516 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
517 break;
518 case 1000:
519 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
520 break;
521 default:
522 ret = -EINVAL;
523 }
524
525 break;
526
527 case PIN_CONFIG_BIAS_PULL_DOWN:
528 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
529
530 switch (arg) {
531 case 20000:
532 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
533 break;
534 case 5000:
535 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
536 break;
537 default:
538 ret = -EINVAL;
539 }
540
541 break;
542 }
543
544 if (!ret)
545 writel(value, padcfg1);
546
27d9098c 547 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 548
549 return ret;
550}
551
552static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
553 unsigned long *configs, unsigned nconfigs)
554{
555 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
556 int i, ret;
557
558 if (!intel_pad_usable(pctrl, pin))
559 return -ENOTSUPP;
560
561 for (i = 0; i < nconfigs; i++) {
562 switch (pinconf_to_config_param(configs[i])) {
563 case PIN_CONFIG_BIAS_DISABLE:
564 case PIN_CONFIG_BIAS_PULL_UP:
565 case PIN_CONFIG_BIAS_PULL_DOWN:
566 ret = intel_config_set_pull(pctrl, pin, configs[i]);
567 if (ret)
568 return ret;
569 break;
570
571 default:
572 return -ENOTSUPP;
573 }
574 }
575
576 return 0;
577}
578
579static const struct pinconf_ops intel_pinconf_ops = {
580 .is_generic = true,
581 .pin_config_get = intel_config_get,
582 .pin_config_set = intel_config_set,
583};
584
585static const struct pinctrl_desc intel_pinctrl_desc = {
586 .pctlops = &intel_pinctrl_ops,
587 .pmxops = &intel_pinmux_ops,
588 .confops = &intel_pinconf_ops,
589 .owner = THIS_MODULE,
590};
591
7981c001
MW		 592static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
593{
acfd4c63 594 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
7981c001
MW		 595 void __iomem *reg;
596
597 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
598 if (!reg)
599 return -EINVAL;
600
601 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
602}
603
604static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
605{
acfd4c63 606 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
7981c001
MW		 607 void __iomem *reg;
608
609 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
610 if (reg) {
611 unsigned long flags;
612 u32 padcfg0;
613
27d9098c 614 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 615 padcfg0 = readl(reg);
616 if (value)
617 padcfg0 |= PADCFG0_GPIOTXSTATE;
618 else
619 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
620 writel(padcfg0, reg);
27d9098c 621 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 622 }
623}
624
625static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
626{
627 return pinctrl_gpio_direction_input(chip->base + offset);
628}
629
630static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
631 int value)
632{
633 intel_gpio_set(chip, offset, value);
634 return pinctrl_gpio_direction_output(chip->base + offset);
635}
636
637static const struct gpio_chip intel_gpio_chip = {
638 .owner = THIS_MODULE,
98c85d58
JG		 639 .request = gpiochip_generic_request,
640 .free = gpiochip_generic_free,
7981c001
MW		 641 .direction_input = intel_gpio_direction_input,
642 .direction_output = intel_gpio_direction_output,
643 .get = intel_gpio_get,
644 .set = intel_gpio_set,
645};
646
647static void intel_gpio_irq_ack(struct irq_data *d)
648{
649 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
acfd4c63 650 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
7981c001
MW		 651 const struct intel_community *community;
652 unsigned pin = irqd_to_hwirq(d);
653
27d9098c 654 raw_spin_lock(&pctrl->lock);
7981c001
MW		 655
656 community = intel_get_community(pctrl, pin);
657 if (community) {
658 unsigned padno = pin_to_padno(community, pin);
618a919b
QZ		 659 unsigned gpp_offset = padno % community->gpp_size;
660 unsigned gpp = padno / community->gpp_size;
7981c001
MW		 661
662 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
663 }
664
27d9098c 665 raw_spin_unlock(&pctrl->lock);
7981c001
MW		 666}
667
a939bb57
QZ		 668static void intel_gpio_irq_enable(struct irq_data *d)
669{
670 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
671 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
672 const struct intel_community *community;
673 unsigned pin = irqd_to_hwirq(d);
674 unsigned long flags;
675
27d9098c 676 raw_spin_lock_irqsave(&pctrl->lock, flags);
a939bb57
QZ		 677
678 community = intel_get_community(pctrl, pin);
679 if (community) {
680 unsigned padno = pin_to_padno(community, pin);
681 unsigned gpp_size = community->gpp_size;
682 unsigned gpp_offset = padno % gpp_size;
683 unsigned gpp = padno / gpp_size;
684 u32 value;
685
686 /* Clear interrupt status first to avoid unexpected interrupt */
687 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
688
689 value = readl(community->regs + community->ie_offset + gpp * 4);
690 value |= BIT(gpp_offset);
691 writel(value, community->regs + community->ie_offset + gpp * 4);
692 }
693
27d9098c 694 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
a939bb57
QZ		 695}
696
7981c001
MW		 697static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
698{
699 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
acfd4c63 700 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
7981c001
MW		 701 const struct intel_community *community;
702 unsigned pin = irqd_to_hwirq(d);
703 unsigned long flags;
704
27d9098c 705 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 706
707 community = intel_get_community(pctrl, pin);
708 if (community) {
709 unsigned padno = pin_to_padno(community, pin);
618a919b
QZ		 710 unsigned gpp_offset = padno % community->gpp_size;
711 unsigned gpp = padno / community->gpp_size;
7981c001
MW		 712 void __iomem *reg;
713 u32 value;
714
715 reg = community->regs + community->ie_offset + gpp * 4;
716 value = readl(reg);
717 if (mask)
718 value &= ~BIT(gpp_offset);
719 else
720 value |= BIT(gpp_offset);
721 writel(value, reg);
722 }
723
27d9098c 724 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 725}
726
727static void intel_gpio_irq_mask(struct irq_data *d)
728{
729 intel_gpio_irq_mask_unmask(d, true);
730}
731
732static void intel_gpio_irq_unmask(struct irq_data *d)
733{
734 intel_gpio_irq_mask_unmask(d, false);
735}
736
737static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
738{
739 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
acfd4c63 740 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
7981c001
MW		 741 unsigned pin = irqd_to_hwirq(d);
742 unsigned long flags;
743 void __iomem *reg;
744 u32 value;
745
746 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
747 if (!reg)
748 return -EINVAL;
749
4341e8a5
MW		 750 /*
751 * If the pin is in ACPI mode it is still usable as a GPIO but it
752 * cannot be used as IRQ because GPI_IS status bit will not be
753 * updated by the host controller hardware.
754 */
755 if (intel_pad_acpi_mode(pctrl, pin)) {
756 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
757 return -EPERM;
758 }
759
27d9098c 760 raw_spin_lock_irqsave(&pctrl->lock, flags);
7981c001
MW		 761
762 value = readl(reg);
763
764 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
765
766 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
767 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
768 } else if (type & IRQ_TYPE_EDGE_FALLING) {
769 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
770 value |= PADCFG0_RXINV;
771 } else if (type & IRQ_TYPE_EDGE_RISING) {
772 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
bf380cfa
QZ		 773 } else if (type & IRQ_TYPE_LEVEL_MASK) {
774 if (type & IRQ_TYPE_LEVEL_LOW)
775 value |= PADCFG0_RXINV;
7981c001
MW		 776 } else {
777 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
778 }
779
780 writel(value, reg);
781
782 if (type & IRQ_TYPE_EDGE_BOTH)
fc756bcd 783 irq_set_handler_locked(d, handle_edge_irq);
7981c001 784 else if (type & IRQ_TYPE_LEVEL_MASK)
fc756bcd 785 irq_set_handler_locked(d, handle_level_irq);
7981c001 786
27d9098c 787 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
7981c001
MW		 788
789 return 0;
790}
791
792static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
793{
794 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
acfd4c63 795 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
7981c001
MW		 796 const struct intel_community *community;
797 unsigned pin = irqd_to_hwirq(d);
798 unsigned padno, gpp, gpp_offset;
9a520fd9 799 unsigned long flags;
7981c001
MW		 800 u32 gpe_en;
801
802 community = intel_get_community(pctrl, pin);
803 if (!community)
804 return -EINVAL;
805
9a520fd9
AS		 806 raw_spin_lock_irqsave(&pctrl->lock, flags);
807
7981c001 808 padno = pin_to_padno(community, pin);
618a919b
QZ		 809 gpp = padno / community->gpp_size;
810 gpp_offset = padno % community->gpp_size;
7981c001
MW		 811
812 /* Clear the existing wake status */
813 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
814
815 /*
816 * The controller will generate wake when GPE of the corresponding
817 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
818 * set).
819 */
820 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
821 if (on)
822 gpe_en |= BIT(gpp_offset);
823 else
824 gpe_en &= ~BIT(gpp_offset);
825 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
826
9a520fd9
AS		 827 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
828
7981c001
MW		 829 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
830 return 0;
831}
832
193b40c8 833static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
7981c001
MW		 834 const struct intel_community *community)
835{
193b40c8
MW		 836 struct gpio_chip *gc = &pctrl->chip;
837 irqreturn_t ret = IRQ_NONE;
7981c001
MW		 838 int gpp;
839
840 for (gpp = 0; gpp < community->ngpps; gpp++) {
841 unsigned long pending, enabled, gpp_offset;
842
843 pending = readl(community->regs + GPI_IS + gpp * 4);
844 enabled = readl(community->regs + community->ie_offset +
845 gpp * 4);
846
847 /* Only interrupts that are enabled */
848 pending &= enabled;
849
618a919b 850 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
7981c001
MW		 851 unsigned padno, irq;
852
853 /*
854 * The last group in community can have less pins
855 * than NPADS_IN_GPP.
856 */
618a919b 857 padno = gpp_offset + gpp * community->gpp_size;
7981c001
MW		 858 if (padno >= community->npins)
859 break;
860
861 irq = irq_find_mapping(gc->irqdomain,
862 community->pin_base + padno);
863 generic_handle_irq(irq);
193b40c8
MW		 864
865 ret |= IRQ_HANDLED;
7981c001
MW		 866 }
867 }
193b40c8
MW		 868
869 return ret;
7981c001
MW		 870}
871
193b40c8 872static irqreturn_t intel_gpio_irq(int irq, void *data)
7981c001 873{
193b40c8
MW		 874 const struct intel_community *community;
875 struct intel_pinctrl *pctrl = data;
876 irqreturn_t ret = IRQ_NONE;
7981c001
MW		 877 int i;
878
7981c001 879 /* Need to check all communities for pending interrupts */
193b40c8
MW		 880 for (i = 0; i < pctrl->ncommunities; i++) {
881 community = &pctrl->communities[i];
882 ret |= intel_gpio_community_irq_handler(pctrl, community);
883 }
7981c001 884
193b40c8 885 return ret;
7981c001
MW		 886}
887
888static struct irq_chip intel_gpio_irqchip = {
889 .name = "intel-gpio",
a939bb57 890 .irq_enable = intel_gpio_irq_enable,
7981c001
MW		 891 .irq_ack = intel_gpio_irq_ack,
892 .irq_mask = intel_gpio_irq_mask,
893 .irq_unmask = intel_gpio_irq_unmask,
894 .irq_set_type = intel_gpio_irq_type,
895 .irq_set_wake = intel_gpio_irq_wake,
896};
897
7981c001
MW		 898static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
899{
900 int ret;
901
902 pctrl->chip = intel_gpio_chip;
903
904 pctrl->chip.ngpio = pctrl->soc->npins;
905 pctrl->chip.label = dev_name(pctrl->dev);
58383c78 906 pctrl->chip.parent = pctrl->dev;
7981c001
MW		 907 pctrl->chip.base = -1;
908
acfd4c63 909 ret = gpiochip_add_data(&pctrl->chip, pctrl);
7981c001
MW		 910 if (ret) {
911 dev_err(pctrl->dev, "failed to register gpiochip\n");
912 return ret;
913 }
914
915 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
916 0, 0, pctrl->soc->npins);
917 if (ret) {
918 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
193b40c8
MW		 919 goto fail;
920 }
921
922 /*
923 * We need to request the interrupt here (instead of providing chip
924 * to the irq directly) because on some platforms several GPIO
925 * controllers share the same interrupt line.
926 */
1a7d1cb8
MW		 927 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
928 IRQF_SHARED | IRQF_NO_THREAD,
193b40c8
MW		 929 dev_name(pctrl->dev), pctrl);
930 if (ret) {
931 dev_err(pctrl->dev, "failed to request interrupt\n");
932 goto fail;
7981c001
MW		 933 }
934
935 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
936 handle_simple_irq, IRQ_TYPE_NONE);
937 if (ret) {
938 dev_err(pctrl->dev, "failed to add irqchip\n");
193b40c8 939 goto fail;
7981c001
MW		 940 }
941
942 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
193b40c8 943 NULL);
7981c001 944 return 0;
193b40c8
MW		 945
946fail:
947 gpiochip_remove(&pctrl->chip);
948
949 return ret;
7981c001
MW		 950}
951
952static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
953{
954#ifdef CONFIG_PM_SLEEP
955 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
956 struct intel_community_context *communities;
957 struct intel_pad_context *pads;
958 int i;
959
960 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
961 if (!pads)
962 return -ENOMEM;
963
964 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
965 sizeof(*communities), GFP_KERNEL);
966 if (!communities)
967 return -ENOMEM;
968
969
970 for (i = 0; i < pctrl->ncommunities; i++) {
971 struct intel_community *community = &pctrl->communities[i];
972 u32 *intmask;
973
974 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
975 sizeof(*intmask), GFP_KERNEL);
976 if (!intmask)
977 return -ENOMEM;
978
979 communities[i].intmask = intmask;
980 }
981
982 pctrl->context.pads = pads;
983 pctrl->context.communities = communities;
984#endif
985
986 return 0;
987}
988
989int intel_pinctrl_probe(struct platform_device *pdev,
990 const struct intel_pinctrl_soc_data *soc_data)
991{
992 struct intel_pinctrl *pctrl;
993 int i, ret, irq;
994
995 if (!soc_data)
996 return -EINVAL;
997
998 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
999 if (!pctrl)
1000 return -ENOMEM;
1001
1002 pctrl->dev = &pdev->dev;
1003 pctrl->soc = soc_data;
27d9098c 1004 raw_spin_lock_init(&pctrl->lock);
7981c001
MW		 1005
1006 /*
1007 * Make a copy of the communities which we can use to hold pointers
1008 * to the registers.
1009 */
1010 pctrl->ncommunities = pctrl->soc->ncommunities;
1011 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1012 sizeof(*pctrl->communities), GFP_KERNEL);
1013 if (!pctrl->communities)
1014 return -ENOMEM;
1015
1016 for (i = 0; i < pctrl->ncommunities; i++) {
1017 struct intel_community *community = &pctrl->communities[i];
1018 struct resource *res;
1019 void __iomem *regs;
1020 u32 padbar;
1021
1022 *community = pctrl->soc->communities[i];
1023
1024 res = platform_get_resource(pdev, IORESOURCE_MEM,
1025 community->barno);
1026 regs = devm_ioremap_resource(&pdev->dev, res);
1027 if (IS_ERR(regs))
1028 return PTR_ERR(regs);
1029
1030 /* Read offset of the pad configuration registers */
1031 padbar = readl(regs + PADBAR);
1032
1033 community->regs = regs;
1034 community->pad_regs = regs + padbar;
618a919b
QZ		 1035 community->ngpps = DIV_ROUND_UP(community->npins,
1036 community->gpp_size);
7981c001
MW		 1037 }
1038
1039 irq = platform_get_irq(pdev, 0);
1040 if (irq < 0) {
1041 dev_err(&pdev->dev, "failed to get interrupt number\n");
1042 return irq;
1043 }
1044
1045 ret = intel_pinctrl_pm_init(pctrl);
1046 if (ret)
1047 return ret;
1048
1049 pctrl->pctldesc = intel_pinctrl_desc;
1050 pctrl->pctldesc.name = dev_name(&pdev->dev);
1051 pctrl->pctldesc.pins = pctrl->soc->pins;
1052 pctrl->pctldesc.npins = pctrl->soc->npins;
1053
54d46cd7
LD		 1054 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1055 pctrl);
323de9ef 1056 if (IS_ERR(pctrl->pctldev)) {
7981c001 1057 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
323de9ef 1058 return PTR_ERR(pctrl->pctldev);
7981c001
MW		 1059 }
1060
1061 ret = intel_gpio_probe(pctrl, irq);
54d46cd7 1062 if (ret)
7981c001 1063 return ret;
7981c001
MW		 1064
1065 platform_set_drvdata(pdev, pctrl);
1066
1067 return 0;
1068}
1069EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1070
1071int intel_pinctrl_remove(struct platform_device *pdev)
1072{
1073 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1074
1075 gpiochip_remove(&pctrl->chip);
7981c001
MW		 1076
1077 return 0;
1078}
1079EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1080
1081#ifdef CONFIG_PM_SLEEP
1082int intel_pinctrl_suspend(struct device *dev)
1083{
1084 struct platform_device *pdev = to_platform_device(dev);
1085 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1086 struct intel_community_context *communities;
1087 struct intel_pad_context *pads;
1088 int i;
1089
1090 pads = pctrl->context.pads;
1091 for (i = 0; i < pctrl->soc->npins; i++) {
1092 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1093 u32 val;
1094
1095 if (!intel_pad_usable(pctrl, desc->number))
1096 continue;
1097
1098 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1099 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1100 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1101 pads[i].padcfg1 = val;
1102 }
1103
1104 communities = pctrl->context.communities;
1105 for (i = 0; i < pctrl->ncommunities; i++) {
1106 struct intel_community *community = &pctrl->communities[i];
1107 void __iomem *base;
1108 unsigned gpp;
1109
1110 base = community->regs + community->ie_offset;
1111 for (gpp = 0; gpp < community->ngpps; gpp++)
1112 communities[i].intmask[gpp] = readl(base + gpp * 4);
1113 }
1114
1115 return 0;
1116}
1117EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1118
f487bbf3
MW		 1119static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1120{
1121 size_t i;
1122
1123 for (i = 0; i < pctrl->ncommunities; i++) {
1124 const struct intel_community *community;
1125 void __iomem *base;
1126 unsigned gpp;
1127
1128 community = &pctrl->communities[i];
1129 base = community->regs;
1130
1131 for (gpp = 0; gpp < community->ngpps; gpp++) {
1132 /* Mask and clear all interrupts */
1133 writel(0, base + community->ie_offset + gpp * 4);
1134 writel(0xffff, base + GPI_IS + gpp * 4);
1135 }
1136 }
1137}
1138
7981c001
MW		 1139int intel_pinctrl_resume(struct device *dev)
1140{
1141 struct platform_device *pdev = to_platform_device(dev);
1142 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1143 const struct intel_community_context *communities;
1144 const struct intel_pad_context *pads;
1145 int i;
1146
1147 /* Mask all interrupts */
1148 intel_gpio_irq_init(pctrl);
1149
1150 pads = pctrl->context.pads;
1151 for (i = 0; i < pctrl->soc->npins; i++) {
1152 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1153 void __iomem *padcfg;
1154 u32 val;
1155
1156 if (!intel_pad_usable(pctrl, desc->number))
1157 continue;
1158
1159 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1160 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1161 if (val != pads[i].padcfg0) {
1162 writel(pads[i].padcfg0, padcfg);
1163 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1164 desc->number, readl(padcfg));
1165 }
1166
1167 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1168 val = readl(padcfg);
1169 if (val != pads[i].padcfg1) {
1170 writel(pads[i].padcfg1, padcfg);
1171 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1172 desc->number, readl(padcfg));
1173 }
1174 }
1175
1176 communities = pctrl->context.communities;
1177 for (i = 0; i < pctrl->ncommunities; i++) {
1178 struct intel_community *community = &pctrl->communities[i];
1179 void __iomem *base;
1180 unsigned gpp;
1181
1182 base = community->regs + community->ie_offset;
1183 for (gpp = 0; gpp < community->ngpps; gpp++) {
1184 writel(communities[i].intmask[gpp], base + gpp * 4);
1185 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1186 readl(base + gpp * 4));
1187 }
1188 }
1189
1190 return 0;
1191}
1192EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1193#endif
1194
1195MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1196MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1197MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1198MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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