projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pinctrl: mediatek: Add Pinctrl/GPIO/EINT driver for mt2701
[deliverable/linux.git] / drivers / pinctrl / mediatek / pinctrl-mtk-common.c
CommitLineData
a6df410d
HY		 1/*
2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/io.h>
11aa679a 17#include <linux/gpio/driver.h>
a6df410d
HY		 18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include <linux/regmap.h>
33#include <linux/mfd/syscon.h>
d9819eb9 34#include <linux/delay.h>
30f010f5 35#include <linux/interrupt.h>
58a5e1b6 36#include <linux/pm.h>
a6df410d
HY		 37#include <dt-bindings/pinctrl/mt65xx.h>
38
39#include "../core.h"
40#include "../pinconf.h"
41#include "../pinctrl-utils.h"
42#include "pinctrl-mtk-common.h"
43
44#define MAX_GPIO_MODE_PER_REG 5
45#define GPIO_MODE_BITS 3
46
47static const char * const mtk_gpio_functions[] = {
48 "func0", "func1", "func2", "func3",
49 "func4", "func5", "func6", "func7",
148b95ee
BH		 50 "func8", "func9", "func10", "func11",
51 "func12", "func13", "func14", "func15",
a6df410d
HY		 52};
53
54/*
55 * There are two base address for pull related configuration
56 * in mt8135, and different GPIO pins use different base address.
57 * When pin number greater than type1_start and less than type1_end,
58 * should use the second base address.
59 */
60static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
61 unsigned long pin)
62{
63 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
64 return pctl->regmap2;
65 return pctl->regmap1;
66}
67
68static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
69{
70 /* Different SoC has different mask and port shift. */
71 return ((pin >> 4) & pctl->devdata->port_mask)
72 << pctl->devdata->port_shf;
73}
74
75static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
76 struct pinctrl_gpio_range *range, unsigned offset,
77 bool input)
78{
79 unsigned int reg_addr;
80 unsigned int bit;
81 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
82
83 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
84 bit = BIT(offset & 0xf);
85
148b95ee
BH		 86 if (pctl->devdata->spec_dir_set)
87 pctl->devdata->spec_dir_set(&reg_addr, offset);
88
a6df410d
HY		 89 if (input)
90 /* Different SoC has different alignment offset. */
91 reg_addr = CLR_ADDR(reg_addr, pctl);
92 else
93 reg_addr = SET_ADDR(reg_addr, pctl);
94
95 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
96 return 0;
97}
98
99static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
100{
101 unsigned int reg_addr;
102 unsigned int bit;
11aa679a 103 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 104
105 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
106 bit = BIT(offset & 0xf);
107
108 if (value)
109 reg_addr = SET_ADDR(reg_addr, pctl);
110 else
111 reg_addr = CLR_ADDR(reg_addr, pctl);
112
113 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
114}
115
25d76b21
HY		 116static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
117 int value, enum pin_config_param arg)
a6df410d
HY		 118{
119 unsigned int reg_addr, offset;
120 unsigned int bit;
25d76b21
HY		 121
122 /**
123 * Due to some soc are not support ies/smt config, add this special
124 * control to handle it.
125 */
126 if (!pctl->devdata->spec_ies_smt_set &&
127 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
128 arg == PIN_CONFIG_INPUT_ENABLE)
129 return -EINVAL;
130
131 if (!pctl->devdata->spec_ies_smt_set &&
132 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
133 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
134 return -EINVAL;
30f010f5
HY		 135
136 /*
137 * Due to some pins are irregular, their input enable and smt
25d76b21 138 * control register are discontinuous, so we need this special handle.
30f010f5
HY		 139 */
140 if (pctl->devdata->spec_ies_smt_set) {
25d76b21
HY		 141 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
142 pin, pctl->devdata->port_align, value, arg);
30f010f5 143 }
a6df410d
HY		 144
145 bit = BIT(pin & 0xf);
146
25d76b21 147 if (arg == PIN_CONFIG_INPUT_ENABLE)
a6df410d
HY		 148 offset = pctl->devdata->ies_offset;
149 else
150 offset = pctl->devdata->smt_offset;
151
152 if (value)
153 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
154 else
155 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
156
157 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
25d76b21
HY		 158 return 0;
159}
160
161int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
162 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
163 unsigned int pin, unsigned char align, int value)
164{
165 unsigned int i, reg_addr, bit;
166
167 for (i = 0; i < info_num; i++) {
168 if (pin >= ies_smt_infos[i].start &&
169 pin <= ies_smt_infos[i].end) {
170 break;
171 }
172 }
173
174 if (i == info_num)
175 return -EINVAL;
176
177 if (value)
178 reg_addr = ies_smt_infos[i].offset + align;
179 else
180 reg_addr = ies_smt_infos[i].offset + (align << 1);
181
182 bit = BIT(ies_smt_infos[i].bit);
183 regmap_write(regmap, reg_addr, bit);
184 return 0;
a6df410d
HY		 185}
186
187static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
188 struct mtk_pinctrl *pctl, unsigned long pin) {
189 int i;
190
191 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
192 const struct mtk_pin_drv_grp *pin_drv =
193 pctl->devdata->pin_drv_grp + i;
194 if (pin == pin_drv->pin)
195 return pin_drv;
196 }
197
198 return NULL;
199}
200
201static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
202 unsigned int pin, unsigned char driving)
203{
204 const struct mtk_pin_drv_grp *pin_drv;
205 unsigned int val;
206 unsigned int bits, mask, shift;
207 const struct mtk_drv_group_desc *drv_grp;
208
209 if (pin >= pctl->devdata->npins)
210 return -EINVAL;
211
212 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
213 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
214 return -EINVAL;
215
216 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
217 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
218 && !(driving % drv_grp->step)) {
219 val = driving / drv_grp->step - 1;
220 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
221 mask = BIT(bits) - 1;
222 shift = pin_drv->bit + drv_grp->low_bit;
223 mask <<= shift;
224 val <<= shift;
225 return regmap_update_bits(mtk_get_regmap(pctl, pin),
226 pin_drv->offset, mask, val);
227 }
228
229 return -EINVAL;
230}
231
e73fe271
YC		 232int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
233 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
234 unsigned int info_num, unsigned int pin,
235 unsigned char align, bool isup, unsigned int r1r0)
236{
237 unsigned int i;
238 unsigned int reg_pupd, reg_set, reg_rst;
239 unsigned int bit_pupd, bit_r0, bit_r1;
240 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
241 bool find = false;
242
243 for (i = 0; i < info_num; i++) {
244 if (pin == pupd_infos[i].pin) {
245 find = true;
246 break;
247 }
248 }
249
250 if (!find)
251 return -EINVAL;
252
253 spec_pupd_pin = pupd_infos + i;
254 reg_set = spec_pupd_pin->offset + align;
255 reg_rst = spec_pupd_pin->offset + (align << 1);
256
257 if (isup)
258 reg_pupd = reg_rst;
259 else
260 reg_pupd = reg_set;
261
262 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
263 regmap_write(regmap, reg_pupd, bit_pupd);
264
265 bit_r0 = BIT(spec_pupd_pin->r0_bit);
266 bit_r1 = BIT(spec_pupd_pin->r1_bit);
267
268 switch (r1r0) {
269 case MTK_PUPD_SET_R1R0_00:
270 regmap_write(regmap, reg_rst, bit_r0);
271 regmap_write(regmap, reg_rst, bit_r1);
272 break;
273 case MTK_PUPD_SET_R1R0_01:
274 regmap_write(regmap, reg_set, bit_r0);
275 regmap_write(regmap, reg_rst, bit_r1);
276 break;
277 case MTK_PUPD_SET_R1R0_10:
278 regmap_write(regmap, reg_rst, bit_r0);
279 regmap_write(regmap, reg_set, bit_r1);
280 break;
281 case MTK_PUPD_SET_R1R0_11:
282 regmap_write(regmap, reg_set, bit_r0);
283 regmap_write(regmap, reg_set, bit_r1);
284 break;
285 default:
286 return -EINVAL;
287 }
288
289 return 0;
290}
291
a6df410d
HY		 292static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
293 unsigned int pin, bool enable, bool isup, unsigned int arg)
294{
295 unsigned int bit;
296 unsigned int reg_pullen, reg_pullsel;
297 int ret;
298
299 /* Some pins' pull setting are very different,
300 * they have separate pull up/down bit, R0 and R1
301 * resistor bit, so we need this special handle.
302 */
303 if (pctl->devdata->spec_pull_set) {
304 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
305 pin, pctl->devdata->port_align, isup, arg);
306 if (!ret)
307 return 0;
308 }
309
310 /* For generic pull config, default arg value should be 0 or 1. */
311 if (arg != 0 && arg != 1) {
312 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
313 arg, pin);
314 return -EINVAL;
315 }
316
317 bit = BIT(pin & 0xf);
318 if (enable)
319 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
320 pctl->devdata->pullen_offset, pctl);
321 else
322 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
323 pctl->devdata->pullen_offset, pctl);
324
325 if (isup)
326 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
327 pctl->devdata->pullsel_offset, pctl);
328 else
329 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
330 pctl->devdata->pullsel_offset, pctl);
331
332 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
333 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
334 return 0;
335}
336
337static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
338 unsigned int pin, enum pin_config_param param,
339 enum pin_config_param arg)
340{
25d76b21 341 int ret = 0;
a6df410d
HY		 342 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
343
344 switch (param) {
345 case PIN_CONFIG_BIAS_DISABLE:
25d76b21 346 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
a6df410d
HY		 347 break;
348 case PIN_CONFIG_BIAS_PULL_UP:
25d76b21 349 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
a6df410d
HY		 350 break;
351 case PIN_CONFIG_BIAS_PULL_DOWN:
25d76b21 352 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
a6df410d
HY		 353 break;
354 case PIN_CONFIG_INPUT_ENABLE:
25d76b21 355 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 356 break;
357 case PIN_CONFIG_OUTPUT:
358 mtk_gpio_set(pctl->chip, pin, arg);
25d76b21 359 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
a6df410d
HY		 360 break;
361 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
25d76b21 362 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
a6df410d
HY		 363 break;
364 case PIN_CONFIG_DRIVE_STRENGTH:
25d76b21 365 ret = mtk_pconf_set_driving(pctl, pin, arg);
a6df410d
HY		 366 break;
367 default:
25d76b21 368 ret = -EINVAL;
a6df410d
HY		 369 }
370
25d76b21 371 return ret;
a6df410d
HY		 372}
373
374static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
375 unsigned group,
376 unsigned long *config)
377{
378 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
379
380 *config = pctl->groups[group].config;
381
382 return 0;
383}
384
385static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
386 unsigned long *configs, unsigned num_configs)
387{
388 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
389 struct mtk_pinctrl_group *g = &pctl->groups[group];
25d76b21 390 int i, ret;
a6df410d
HY		 391
392 for (i = 0; i < num_configs; i++) {
25d76b21 393 ret = mtk_pconf_parse_conf(pctldev, g->pin,
a6df410d
HY		 394 pinconf_to_config_param(configs[i]),
395 pinconf_to_config_argument(configs[i]));
25d76b21
HY		 396 if (ret < 0)
397 return ret;
a6df410d
HY		 398
399 g->config = configs[i];
400 }
401
402 return 0;
403}
404
405static const struct pinconf_ops mtk_pconf_ops = {
406 .pin_config_group_get = mtk_pconf_group_get,
407 .pin_config_group_set = mtk_pconf_group_set,
408};
409
410static struct mtk_pinctrl_group *
411mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
412{
413 int i;
414
415 for (i = 0; i < pctl->ngroups; i++) {
416 struct mtk_pinctrl_group *grp = pctl->groups + i;
417
418 if (grp->pin == pin)
419 return grp;
420 }
421
422 return NULL;
423}
424
425static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
426 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
427{
428 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
429 const struct mtk_desc_function *func = pin->functions;
430
431 while (func && func->name) {
432 if (func->muxval == fnum)
433 return func;
434 func++;
435 }
436
437 return NULL;
438}
439
440static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
441 u32 pin_num, u32 fnum)
442{
443 int i;
444
445 for (i = 0; i < pctl->devdata->npins; i++) {
446 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
447
448 if (pin->pin.number == pin_num) {
449 const struct mtk_desc_function *func =
450 pin->functions;
451
452 while (func && func->name) {
453 if (func->muxval == fnum)
454 return true;
455 func++;
456 }
457
458 break;
459 }
460 }
461
462 return false;
463}
464
465static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
466 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
467 struct pinctrl_map **map, unsigned *reserved_maps,
468 unsigned *num_maps)
469{
470 bool ret;
471
472 if (*num_maps == *reserved_maps)
473 return -ENOSPC;
474
475 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
476 (*map)[*num_maps].data.mux.group = grp->name;
477
478 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
479 if (!ret) {
480 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
481 fnum, pin);
482 return -EINVAL;
483 }
484
485 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
486 (*num_maps)++;
487
488 return 0;
489}
490
491static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
492 struct device_node *node,
493 struct pinctrl_map **map,
494 unsigned *reserved_maps,
495 unsigned *num_maps)
496{
497 struct property *pins;
498 u32 pinfunc, pin, func;
499 int num_pins, num_funcs, maps_per_pin;
500 unsigned long *configs;
501 unsigned int num_configs;
502 bool has_config = 0;
503 int i, err;
504 unsigned reserve = 0;
505 struct mtk_pinctrl_group *grp;
506 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
507
508 pins = of_find_property(node, "pinmux", NULL);
509 if (!pins) {
510 dev_err(pctl->dev, "missing pins property in node %s .\n",
511 node->name);
512 return -EINVAL;
513 }
514
c445cac3
HY		 515 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
516 &num_configs);
b04a23b0
HY		 517 if (err)
518 return err;
519
a6df410d
HY		 520 if (num_configs)
521 has_config = 1;
522
523 num_pins = pins->length / sizeof(u32);
524 num_funcs = num_pins;
525 maps_per_pin = 0;
526 if (num_funcs)
527 maps_per_pin++;
528 if (has_config && num_pins >= 1)
529 maps_per_pin++;
530
b04a23b0
HY		 531 if (!num_pins || !maps_per_pin) {
532 err = -EINVAL;
533 goto exit;
534 }
a6df410d
HY		 535
536 reserve = num_pins * maps_per_pin;
537
538 err = pinctrl_utils_reserve_map(pctldev, map,
539 reserved_maps, num_maps, reserve);
540 if (err < 0)
b04a23b0 541 goto exit;
a6df410d
HY		 542
543 for (i = 0; i < num_pins; i++) {
544 err = of_property_read_u32_index(node, "pinmux",
545 i, &pinfunc);
546 if (err)
b04a23b0 547 goto exit;
a6df410d
HY		 548
549 pin = MTK_GET_PIN_NO(pinfunc);
550 func = MTK_GET_PIN_FUNC(pinfunc);
551
552 if (pin >= pctl->devdata->npins ||
553 func >= ARRAY_SIZE(mtk_gpio_functions)) {
554 dev_err(pctl->dev, "invalid pins value.\n");
555 err = -EINVAL;
b04a23b0 556 goto exit;
a6df410d
HY		 557 }
558
559 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
560 if (!grp) {
561 dev_err(pctl->dev, "unable to match pin %d to group\n",
562 pin);
b04a23b0
HY		 563 err = -EINVAL;
564 goto exit;
a6df410d
HY		 565 }
566
567 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
568 reserved_maps, num_maps);
569 if (err < 0)
b04a23b0 570 goto exit;
a6df410d
HY		 571
572 if (has_config) {
573 err = pinctrl_utils_add_map_configs(pctldev, map,
574 reserved_maps, num_maps, grp->name,
575 configs, num_configs,
576 PIN_MAP_TYPE_CONFIGS_GROUP);
577 if (err < 0)
b04a23b0 578 goto exit;
a6df410d
HY		 579 }
580 }
581
b04a23b0 582 err = 0;
a6df410d 583
b04a23b0
HY		 584exit:
585 kfree(configs);
a6df410d
HY		 586 return err;
587}
588
589static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
590 struct device_node *np_config,
591 struct pinctrl_map **map, unsigned *num_maps)
592{
593 struct device_node *np;
594 unsigned reserved_maps;
595 int ret;
596
597 *map = NULL;
598 *num_maps = 0;
599 reserved_maps = 0;
600
601 for_each_child_of_node(np_config, np) {
602 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
603 &reserved_maps, num_maps);
604 if (ret < 0) {
605 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
4fc8a4b2 606 of_node_put(np);
a6df410d
HY		 607 return ret;
608 }
609 }
610
611 return 0;
612}
613
614static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
615{
616 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
617
618 return pctl->ngroups;
619}
620
621static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
622 unsigned group)
623{
624 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
625
626 return pctl->groups[group].name;
627}
628
629static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
630 unsigned group,
631 const unsigned **pins,
632 unsigned *num_pins)
633{
634 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
635
636 *pins = (unsigned *)&pctl->groups[group].pin;
637 *num_pins = 1;
638
639 return 0;
640}
641
642static const struct pinctrl_ops mtk_pctrl_ops = {
643 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
644 .dt_free_map = pinctrl_utils_dt_free_map,
645 .get_groups_count = mtk_pctrl_get_groups_count,
646 .get_group_name = mtk_pctrl_get_group_name,
647 .get_group_pins = mtk_pctrl_get_group_pins,
648};
649
650static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
651{
652 return ARRAY_SIZE(mtk_gpio_functions);
653}
654
655static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
656 unsigned selector)
657{
658 return mtk_gpio_functions[selector];
659}
660
661static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
662 unsigned function,
663 const char * const **groups,
664 unsigned * const num_groups)
665{
666 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
667
668 *groups = pctl->grp_names;
669 *num_groups = pctl->ngroups;
670
671 return 0;
672}
673
674static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
675 unsigned long pin, unsigned long mode)
676{
677 unsigned int reg_addr;
678 unsigned char bit;
679 unsigned int val;
680 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
681 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
682
148b95ee
BH		 683 if (pctl->devdata->spec_pinmux_set)
684 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
685 pin, mode);
686
a6df410d
HY		 687 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
688 + pctl->devdata->pinmux_offset;
689
148b95ee 690 mode &= mask;
a6df410d
HY		 691 bit = pin % MAX_GPIO_MODE_PER_REG;
692 mask <<= (GPIO_MODE_BITS * bit);
693 val = (mode << (GPIO_MODE_BITS * bit));
694 return regmap_update_bits(mtk_get_regmap(pctl, pin),
695 reg_addr, mask, val);
696}
697
d9819eb9
MM		 698static const struct mtk_desc_pin *
699mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
700{
701 int i;
702 const struct mtk_desc_pin *pin;
703
704 for (i = 0; i < pctl->devdata->npins; i++) {
705 pin = pctl->devdata->pins + i;
706 if (pin->eint.eintnum == eint_num)
707 return pin;
708 }
709
710 return NULL;
711}
712
a6df410d
HY		 713static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
714 unsigned function,
715 unsigned group)
716{
717 bool ret;
718 const struct mtk_desc_function *desc;
719 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
720 struct mtk_pinctrl_group *g = pctl->groups + group;
721
722 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
723 if (!ret) {
c70336cc 724 dev_err(pctl->dev, "invalid function %d on group %d .\n",
a6df410d
HY		 725 function, group);
726 return -EINVAL;
727 }
728
729 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
730 if (!desc)
731 return -EINVAL;
732 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
733 return 0;
734}
735
736static const struct pinmux_ops mtk_pmx_ops = {
737 .get_functions_count = mtk_pmx_get_funcs_cnt,
738 .get_function_name = mtk_pmx_get_func_name,
739 .get_function_groups = mtk_pmx_get_func_groups,
740 .set_mux = mtk_pmx_set_mux,
741 .gpio_set_direction = mtk_pmx_gpio_set_direction,
742};
743
a6df410d
HY		 744static int mtk_gpio_direction_input(struct gpio_chip *chip,
745 unsigned offset)
746{
747 return pinctrl_gpio_direction_input(chip->base + offset);
748}
749
750static int mtk_gpio_direction_output(struct gpio_chip *chip,
751 unsigned offset, int value)
752{
753 mtk_gpio_set(chip, offset, value);
754 return pinctrl_gpio_direction_output(chip->base + offset);
755}
756
757static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
758{
759 unsigned int reg_addr;
760 unsigned int bit;
761 unsigned int read_val = 0;
762
11aa679a 763 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d
HY		 764
765 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
766 bit = BIT(offset & 0xf);
148b95ee
BH		 767
768 if (pctl->devdata->spec_dir_set)
769 pctl->devdata->spec_dir_set(&reg_addr, offset);
770
a6df410d 771 regmap_read(pctl->regmap1, reg_addr, &read_val);
f97c2309 772 return !(read_val & bit);
a6df410d
HY		 773}
774
775static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
776{
777 unsigned int reg_addr;
778 unsigned int bit;
779 unsigned int read_val = 0;
11aa679a 780 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
a6df410d 781
f97c2309
HY		 782 reg_addr = mtk_get_port(pctl, offset) +
783 pctl->devdata->din_offset;
a6df410d
HY		 784
785 bit = BIT(offset & 0xf);
786 regmap_read(pctl->regmap1, reg_addr, &read_val);
787 return !!(read_val & bit);
788}
789
d9819eb9
MM		 790static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
791{
792 const struct mtk_desc_pin *pin;
11aa679a 793 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
d9819eb9
MM		 794 int irq;
795
796 pin = pctl->devdata->pins + offset;
797 if (pin->eint.eintnum == NO_EINT_SUPPORT)
798 return -EINVAL;
799
800 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
801 if (!irq)
802 return -EINVAL;
803
804 return irq;
805}
806
807static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
808{
809 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
810 const struct mtk_desc_pin *pin;
811 int ret;
812
813 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
814
815 if (!pin) {
816 dev_err(pctl->dev, "Can not find pin\n");
817 return -EINVAL;
818 }
819
820 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
821 if (ret) {
822 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
823 irqd_to_hwirq(d));
824 return ret;
825 }
826
827 /* set mux to INT mode */
828 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
829
830 return 0;
831}
832
833static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
834{
835 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
836 const struct mtk_desc_pin *pin;
837
838 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
839
840 if (!pin) {
841 dev_err(pctl->dev, "Can not find pin\n");
842 return;
843 }
844
845 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
846}
847
848static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
849 unsigned int eint_num, unsigned int offset)
850{
851 unsigned int eint_base = 0;
852 void __iomem *reg;
853
854 if (eint_num >= pctl->devdata->ap_num)
855 eint_base = pctl->devdata->ap_num;
856
857 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
858
859 return reg;
860}
861
862/*
863 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
864 * @eint_num: the EINT number to setmtk_pinctrl
865 */
866static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
867 unsigned int eint_num)
868{
869 unsigned int sens;
870 unsigned int bit = BIT(eint_num % 32);
871 const struct mtk_eint_offsets *eint_offsets =
872 &pctl->devdata->eint_offsets;
873
874 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
875 eint_offsets->sens);
876
877 if (readl(reg) & bit)
878 sens = MT_LEVEL_SENSITIVE;
879 else
880 sens = MT_EDGE_SENSITIVE;
881
882 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
883 return 1;
884 else
885 return 0;
886}
887
888/*
889 * mtk_eint_get_mask: To get the eint mask
890 * @eint_num: the EINT number to get
891 */
892static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
893 unsigned int eint_num)
894{
895 unsigned int bit = BIT(eint_num % 32);
896 const struct mtk_eint_offsets *eint_offsets =
897 &pctl->devdata->eint_offsets;
898
899 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
900 eint_offsets->mask);
901
902 return !!(readl(reg) & bit);
903}
904
3221f40b
YC		 905static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
906{
907 int start_level, curr_level;
908 unsigned int reg_offset;
909 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
b4b05b9a 910 u32 mask = BIT(hwirq & 0x1f);
3221f40b
YC		 911 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
912 void __iomem *reg = pctl->eint_reg_base + (port << 2);
913 const struct mtk_desc_pin *pin;
914
915 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
916 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
917 do {
918 start_level = curr_level;
919 if (start_level)
920 reg_offset = eint_offsets->pol_clr;
921 else
922 reg_offset = eint_offsets->pol_set;
923 writel(mask, reg + reg_offset);
924
925 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
926 } while (start_level != curr_level);
927
928 return start_level;
929}
930
d9819eb9
MM		 931static void mtk_eint_mask(struct irq_data *d)
932{
933 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
934 const struct mtk_eint_offsets *eint_offsets =
935 &pctl->devdata->eint_offsets;
936 u32 mask = BIT(d->hwirq & 0x1f);
937 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
938 eint_offsets->mask_set);
939
940 writel(mask, reg);
941}
942
943static void mtk_eint_unmask(struct irq_data *d)
944{
945 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
946 const struct mtk_eint_offsets *eint_offsets =
947 &pctl->devdata->eint_offsets;
948 u32 mask = BIT(d->hwirq & 0x1f);
949 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
950 eint_offsets->mask_clr);
951
952 writel(mask, reg);
3221f40b
YC		 953
954 if (pctl->eint_dual_edges[d->hwirq])
955 mtk_eint_flip_edge(pctl, d->hwirq);
d9819eb9
MM		 956}
957
958static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
959 unsigned debounce)
960{
58383c78 961 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
d9819eb9
MM		 962 int eint_num, virq, eint_offset;
963 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
964 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
965 const struct mtk_desc_pin *pin;
966 struct irq_data *d;
967
968 pin = pctl->devdata->pins + offset;
969 if (pin->eint.eintnum == NO_EINT_SUPPORT)
970 return -EINVAL;
971
972 eint_num = pin->eint.eintnum;
973 virq = irq_find_mapping(pctl->domain, eint_num);
974 eint_offset = (eint_num % 4) * 8;
975 d = irq_get_irq_data(virq);
976
977 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
978 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
979 if (!mtk_eint_can_en_debounce(pctl, eint_num))
980 return -ENOSYS;
981
982 dbnc = ARRAY_SIZE(dbnc_arr);
983 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
984 if (debounce <= dbnc_arr[i]) {
985 dbnc = i;
986 break;
987 }
988 }
989
990 if (!mtk_eint_get_mask(pctl, eint_num)) {
991 mtk_eint_mask(d);
992 unmask = 1;
74d77e50
CIK		 993 } else {
994 unmask = 0;
d9819eb9
MM		 995 }
996
997 clr_bit = 0xff << eint_offset;
998 writel(clr_bit, pctl->eint_reg_base + clr_offset);
999
1000 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
1001 eint_offset;
1002 rst = EINT_DBNC_RST_BIT << eint_offset;
1003 writel(rst | bit, pctl->eint_reg_base + set_offset);
1004
1005 /* Delay a while (more than 2T) to wait for hw debounce counter reset
1006 work correctly */
1007 udelay(1);
1008 if (unmask == 1)
1009 mtk_eint_unmask(d);
1010
1011 return 0;
1012}
1013
a6df410d
HY		 1014static struct gpio_chip mtk_gpio_chip = {
1015 .owner = THIS_MODULE,
98c85d58
JG		 1016 .request = gpiochip_generic_request,
1017 .free = gpiochip_generic_free,
f97c2309 1018 .get_direction = mtk_gpio_get_direction,
a6df410d
HY		 1019 .direction_input = mtk_gpio_direction_input,
1020 .direction_output = mtk_gpio_direction_output,
1021 .get = mtk_gpio_get,
1022 .set = mtk_gpio_set,
d9819eb9
MM		 1023 .to_irq = mtk_gpio_to_irq,
1024 .set_debounce = mtk_gpio_set_debounce,
a6df410d
HY		 1025 .of_gpio_n_cells = 2,
1026};
1027
d9819eb9
MM		 1028static int mtk_eint_set_type(struct irq_data *d,
1029 unsigned int type)
1030{
1031 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1032 const struct mtk_eint_offsets *eint_offsets =
1033 &pctl->devdata->eint_offsets;
1034 u32 mask = BIT(d->hwirq & 0x1f);
1035 void __iomem *reg;
1036
1037 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
d9819eb9
MM		 1038 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1039 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1040 d->irq, d->hwirq, type);
1041 return -EINVAL;
1042 }
1043
3221f40b
YC		 1044 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1045 pctl->eint_dual_edges[d->hwirq] = 1;
1046 else
1047 pctl->eint_dual_edges[d->hwirq] = 0;
1048
d9819eb9
MM		 1049 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1050 reg = mtk_eint_get_offset(pctl, d->hwirq,
1051 eint_offsets->pol_clr);
1052 writel(mask, reg);
1053 } else {
1054 reg = mtk_eint_get_offset(pctl, d->hwirq,
1055 eint_offsets->pol_set);
1056 writel(mask, reg);
1057 }
1058
1059 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1060 reg = mtk_eint_get_offset(pctl, d->hwirq,
1061 eint_offsets->sens_clr);
1062 writel(mask, reg);
1063 } else {
1064 reg = mtk_eint_get_offset(pctl, d->hwirq,
1065 eint_offsets->sens_set);
1066 writel(mask, reg);
1067 }
1068
3221f40b
YC		 1069 if (pctl->eint_dual_edges[d->hwirq])
1070 mtk_eint_flip_edge(pctl, d->hwirq);
1071
d9819eb9
MM		 1072 return 0;
1073}
1074
58a5e1b6
MM		 1075static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1076{
1077 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1078 int shift = d->hwirq & 0x1f;
1079 int reg = d->hwirq >> 5;
1080
1081 if (on)
1082 pctl->wake_mask[reg] |= BIT(shift);
1083 else
1084 pctl->wake_mask[reg] &= ~BIT(shift);
1085
1086 return 0;
1087}
1088
1089static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1090 void __iomem *eint_reg_base, u32 *buf)
1091{
1092 int port;
1093 void __iomem *reg;
1094
1095 for (port = 0; port < chip->ports; port++) {
1096 reg = eint_reg_base + (port << 2);
1097 writel_relaxed(~buf[port], reg + chip->mask_set);
1098 writel_relaxed(buf[port], reg + chip->mask_clr);
1099 }
1100}
1101
1102static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1103 void __iomem *eint_reg_base, u32 *buf)
1104{
1105 int port;
1106 void __iomem *reg;
1107
1108 for (port = 0; port < chip->ports; port++) {
1109 reg = eint_reg_base + chip->mask + (port << 2);
1110 buf[port] = ~readl_relaxed(reg);
1111 /* Mask is 0 when irq is enabled, and 1 when disabled. */
1112 }
1113}
1114
1115static int mtk_eint_suspend(struct device *device)
1116{
1117 void __iomem *reg;
1118 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1119 const struct mtk_eint_offsets *eint_offsets =
1120 &pctl->devdata->eint_offsets;
1121
1122 reg = pctl->eint_reg_base;
1123 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1124 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1125
1126 return 0;
1127}
1128
1129static int mtk_eint_resume(struct device *device)
1130{
1131 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1132 const struct mtk_eint_offsets *eint_offsets =
1133 &pctl->devdata->eint_offsets;
1134
1135 mtk_eint_chip_write_mask(eint_offsets,
1136 pctl->eint_reg_base, pctl->cur_mask);
1137
1138 return 0;
1139}
1140
1141const struct dev_pm_ops mtk_eint_pm_ops = {
1142 .suspend = mtk_eint_suspend,
1143 .resume = mtk_eint_resume,
1144};
1145
d9819eb9
MM		 1146static void mtk_eint_ack(struct irq_data *d)
1147{
1148 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1149 const struct mtk_eint_offsets *eint_offsets =
1150 &pctl->devdata->eint_offsets;
1151 u32 mask = BIT(d->hwirq & 0x1f);
1152 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1153 eint_offsets->ack);
1154
1155 writel(mask, reg);
1156}
1157
1158static struct irq_chip mtk_pinctrl_irq_chip = {
1159 .name = "mt-eint",
58a5e1b6 1160 .irq_disable = mtk_eint_mask,
d9819eb9
MM		 1161 .irq_mask = mtk_eint_mask,
1162 .irq_unmask = mtk_eint_unmask,
1163 .irq_ack = mtk_eint_ack,
1164 .irq_set_type = mtk_eint_set_type,
58a5e1b6 1165 .irq_set_wake = mtk_eint_irq_set_wake,
d9819eb9
MM		 1166 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1167 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1168};
1169
1170static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1171{
1172 const struct mtk_eint_offsets *eint_offsets =
1173 &pctl->devdata->eint_offsets;
1174 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1175 unsigned int i;
1176
1177 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1178 writel(0xffffffff, reg);
1179 reg += 4;
1180 }
1181 return 0;
1182}
1183
1184static inline void
1185mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1186{
1187 unsigned int rst, ctrl_offset;
1188 unsigned int bit, dbnc;
1189 const struct mtk_eint_offsets *eint_offsets =
1190 &pctl->devdata->eint_offsets;
1191
1192 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1193 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1194 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1195 if ((bit & dbnc) > 0) {
1196 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1197 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1198 writel(rst, pctl->eint_reg_base + ctrl_offset);
1199 }
1200}
1201
bd0b9ac4 1202static void mtk_eint_irq_handler(struct irq_desc *desc)
d9819eb9 1203{
5663bb27
JL		 1204 struct irq_chip *chip = irq_desc_get_chip(desc);
1205 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
d9819eb9
MM		 1206 unsigned int status, eint_num;
1207 int offset, index, virq;
1208 const struct mtk_eint_offsets *eint_offsets =
1209 &pctl->devdata->eint_offsets;
1210 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
3221f40b
YC		 1211 int dual_edges, start_level, curr_level;
1212 const struct mtk_desc_pin *pin;
d9819eb9
MM		 1213
1214 chained_irq_enter(chip, desc);
1215 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1216 status = readl(reg);
1217 reg += 4;
1218 while (status) {
1219 offset = __ffs(status);
1220 index = eint_num + offset;
1221 virq = irq_find_mapping(pctl->domain, index);
1222 status &= ~BIT(offset);
1223
3221f40b
YC		 1224 dual_edges = pctl->eint_dual_edges[index];
1225 if (dual_edges) {
1226 /* Clear soft-irq in case we raised it
1227 last time */
1228 writel(BIT(offset), reg - eint_offsets->stat +
1229 eint_offsets->soft_clr);
1230
1231 pin = mtk_find_pin_by_eint_num(pctl, index);
1232 start_level = mtk_gpio_get(pctl->chip,
1233 pin->pin.number);
1234 }
1235
d9819eb9
MM		 1236 generic_handle_irq(virq);
1237
3221f40b
YC		 1238 if (dual_edges) {
1239 curr_level = mtk_eint_flip_edge(pctl, index);
1240
1241 /* If level changed, we might lost one edge
1242 interrupt, raised it through soft-irq */
1243 if (start_level != curr_level)
1244 writel(BIT(offset), reg -
1245 eint_offsets->stat +
1246 eint_offsets->soft_set);
1247 }
1248
d9819eb9
MM		 1249 if (index < pctl->devdata->db_cnt)
1250 mtk_eint_debounce_process(pctl , index);
1251 }
1252 }
1253 chained_irq_exit(chip, desc);
1254}
1255
a6df410d
HY		 1256static int mtk_pctrl_build_state(struct platform_device *pdev)
1257{
1258 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1259 int i;
1260
1261 pctl->ngroups = pctl->devdata->npins;
1262
1263 /* Allocate groups */
0206caa8
AL		 1264 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1265 sizeof(*pctl->groups), GFP_KERNEL);
a6df410d
HY		 1266 if (!pctl->groups)
1267 return -ENOMEM;
1268
1269 /* We assume that one pin is one group, use pin name as group name. */
0206caa8
AL		 1270 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1271 sizeof(*pctl->grp_names), GFP_KERNEL);
a6df410d
HY		 1272 if (!pctl->grp_names)
1273 return -ENOMEM;
1274
1275 for (i = 0; i < pctl->devdata->npins; i++) {
1276 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1277 struct mtk_pinctrl_group *group = pctl->groups + i;
1278
1279 group->name = pin->pin.name;
1280 group->pin = pin->pin.number;
1281
1282 pctl->grp_names[i] = pin->pin.name;
1283 }
1284
1285 return 0;
1286}
1287
a6df410d 1288int mtk_pctrl_init(struct platform_device *pdev,
fc59e66c
HY		 1289 const struct mtk_pinctrl_devdata *data,
1290 struct regmap *regmap)
a6df410d
HY		 1291{
1292 struct pinctrl_pin_desc *pins;
1293 struct mtk_pinctrl *pctl;
1294 struct device_node *np = pdev->dev.of_node, *node;
1295 struct property *prop;
d9819eb9 1296 struct resource *res;
58a5e1b6 1297 int i, ret, irq, ports_buf;
a6df410d
HY		 1298
1299 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1300 if (!pctl)
1301 return -ENOMEM;
1302
1303 platform_set_drvdata(pdev, pctl);
1304
1305 prop = of_find_property(np, "pins-are-numbered", NULL);
1306 if (!prop) {
c445cac3 1307 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
a6df410d
HY		 1308 return -EINVAL;
1309 }
1310
1311 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1312 if (node) {
1313 pctl->regmap1 = syscon_node_to_regmap(node);
1314 if (IS_ERR(pctl->regmap1))
1315 return PTR_ERR(pctl->regmap1);
fc59e66c
HY		 1316 } else if (regmap) {
1317 pctl->regmap1 = regmap;
1318 } else {
1319 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1320 return -EINVAL;
a6df410d
HY		 1321 }
1322
1323 /* Only 8135 has two base addr, other SoCs have only one. */
1324 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1325 if (node) {
1326 pctl->regmap2 = syscon_node_to_regmap(node);
1327 if (IS_ERR(pctl->regmap2))
1328 return PTR_ERR(pctl->regmap2);
1329 }
1330
1331 pctl->devdata = data;
1332 ret = mtk_pctrl_build_state(pdev);
1333 if (ret) {
1334 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1335 return -EINVAL;
1336 }
1337
0206caa8 1338 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
a6df410d
HY		 1339 GFP_KERNEL);
1340 if (!pins)
1341 return -ENOMEM;
1342
1343 for (i = 0; i < pctl->devdata->npins; i++)
1344 pins[i] = pctl->devdata->pins[i].pin;
d48c2c02
HY		 1345
1346 pctl->pctl_desc.name = dev_name(&pdev->dev);
1347 pctl->pctl_desc.owner = THIS_MODULE;
1348 pctl->pctl_desc.pins = pins;
1349 pctl->pctl_desc.npins = pctl->devdata->npins;
1350 pctl->pctl_desc.confops = &mtk_pconf_ops;
1351 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1352 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
a6df410d 1353 pctl->dev = &pdev->dev;
d48c2c02
HY		 1354
1355 pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
323de9ef 1356 if (IS_ERR(pctl->pctl_dev)) {
a6df410d 1357 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
323de9ef 1358 return PTR_ERR(pctl->pctl_dev);
a6df410d
HY		 1359 }
1360
1361 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1362 if (!pctl->chip) {
1363 ret = -ENOMEM;
1364 goto pctrl_error;
1365 }
1366
fc63d854 1367 *pctl->chip = mtk_gpio_chip;
a6df410d
HY		 1368 pctl->chip->ngpio = pctl->devdata->npins;
1369 pctl->chip->label = dev_name(&pdev->dev);
58383c78 1370 pctl->chip->parent = &pdev->dev;
fc59e66c 1371 pctl->chip->base = -1;
a6df410d 1372
11aa679a 1373 ret = gpiochip_add_data(pctl->chip, pctl);
a6df410d
HY		 1374 if (ret) {
1375 ret = -EINVAL;
1376 goto pctrl_error;
1377 }
1378
1379 /* Register the GPIO to pin mappings. */
1380 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1381 0, 0, pctl->devdata->npins);
1382 if (ret) {
1383 ret = -EINVAL;
1384 goto chip_error;
1385 }
1386
fc63d854 1387 if (!of_property_read_bool(np, "interrupt-controller"))
fc59e66c
HY		 1388 return 0;
1389
d9819eb9
MM		 1390 /* Get EINT register base from dts. */
1391 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1392 if (!res) {
1393 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1394 ret = -EINVAL;
1395 goto chip_error;
1396 }
1397
1398 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1399 if (IS_ERR(pctl->eint_reg_base)) {
1400 ret = -EINVAL;
1401 goto chip_error;
1402 }
1403
58a5e1b6
MM		 1404 ports_buf = pctl->devdata->eint_offsets.ports;
1405 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1406 sizeof(*pctl->wake_mask), GFP_KERNEL);
1407 if (!pctl->wake_mask) {
1408 ret = -ENOMEM;
1409 goto chip_error;
1410 }
1411
1412 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1413 sizeof(*pctl->cur_mask), GFP_KERNEL);
1414 if (!pctl->cur_mask) {
1415 ret = -ENOMEM;
1416 goto chip_error;
1417 }
1418
0206caa8
AL		 1419 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1420 sizeof(int), GFP_KERNEL);
3221f40b
YC		 1421 if (!pctl->eint_dual_edges) {
1422 ret = -ENOMEM;
1423 goto chip_error;
1424 }
1425
d9819eb9
MM		 1426 irq = irq_of_parse_and_map(np, 0);
1427 if (!irq) {
1428 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1429 ret = -EINVAL;
61a35576 1430 goto chip_error;
d9819eb9
MM		 1431 }
1432
1433 pctl->domain = irq_domain_add_linear(np,
1434 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1435 if (!pctl->domain) {
1436 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1437 ret = -ENOMEM;
61a35576 1438 goto chip_error;
d9819eb9
MM		 1439 }
1440
1441 mtk_eint_init(pctl);
1442 for (i = 0; i < pctl->devdata->ap_num; i++) {
1443 int virq = irq_create_mapping(pctl->domain, i);
1444
1445 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1446 handle_level_irq);
1447 irq_set_chip_data(virq, pctl);
e4411899 1448 }
d9819eb9 1449
1e105921 1450 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
a6df410d
HY		 1451 return 0;
1452
1453chip_error:
1454 gpiochip_remove(pctl->chip);
1455pctrl_error:
1456 pinctrl_unregister(pctl->pctl_dev);
1457 return ret;
1458}
1459
1460MODULE_LICENSE("GPL");
1461MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1462MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
Linux kernel - Deliverables
This page took 0.135662 seconds and 5 git commands to generate.