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Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / drivers / pinctrl / nomadik / pinctrl-abx500.c
CommitLineData
0493e649
PC		 1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
f30a3839
LJ		 17#include <linux/of.h>
18#include <linux/of_device.h>
0493e649
PC		 19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/irq.h>
ac652d79 22#include <linux/irqdomain.h>
0493e649
PC		 23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/mfd/abx500.h>
26#include <linux/mfd/abx500/ab8500.h>
0493e649
PC		 27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/pinctrl/pinconf.h>
31#include <linux/pinctrl/pinconf-generic.h>
64a45c98 32#include <linux/pinctrl/machine.h>
0493e649
PC		 33
34#include "pinctrl-abx500.h"
3a198059
LW		 35#include "../core.h"
36#include "../pinconf.h"
b07f92a2 37#include "../pinctrl-utils.h"
0493e649
PC		 38
39/*
40 * The AB9540 and AB8540 GPIO support are extended versions
41 * of the AB8500 GPIO support.
42 * The AB9540 supports an additional (7th) register so that
43 * more GPIO may be configured and used.
44 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
45 * internal pull-up and pull-down capabilities.
46 */
47
48/*
49 * GPIO registers offset
50 * Bank: 0x10
51 */
52#define AB8500_GPIO_SEL1_REG 0x00
53#define AB8500_GPIO_SEL2_REG 0x01
54#define AB8500_GPIO_SEL3_REG 0x02
55#define AB8500_GPIO_SEL4_REG 0x03
56#define AB8500_GPIO_SEL5_REG 0x04
57#define AB8500_GPIO_SEL6_REG 0x05
58#define AB9540_GPIO_SEL7_REG 0x06
59
60#define AB8500_GPIO_DIR1_REG 0x10
61#define AB8500_GPIO_DIR2_REG 0x11
62#define AB8500_GPIO_DIR3_REG 0x12
63#define AB8500_GPIO_DIR4_REG 0x13
64#define AB8500_GPIO_DIR5_REG 0x14
65#define AB8500_GPIO_DIR6_REG 0x15
66#define AB9540_GPIO_DIR7_REG 0x16
67
68#define AB8500_GPIO_OUT1_REG 0x20
69#define AB8500_GPIO_OUT2_REG 0x21
70#define AB8500_GPIO_OUT3_REG 0x22
71#define AB8500_GPIO_OUT4_REG 0x23
72#define AB8500_GPIO_OUT5_REG 0x24
73#define AB8500_GPIO_OUT6_REG 0x25
74#define AB9540_GPIO_OUT7_REG 0x26
75
76#define AB8500_GPIO_PUD1_REG 0x30
77#define AB8500_GPIO_PUD2_REG 0x31
78#define AB8500_GPIO_PUD3_REG 0x32
79#define AB8500_GPIO_PUD4_REG 0x33
80#define AB8500_GPIO_PUD5_REG 0x34
81#define AB8500_GPIO_PUD6_REG 0x35
82#define AB9540_GPIO_PUD7_REG 0x36
83
84#define AB8500_GPIO_IN1_REG 0x40
85#define AB8500_GPIO_IN2_REG 0x41
86#define AB8500_GPIO_IN3_REG 0x42
87#define AB8500_GPIO_IN4_REG 0x43
88#define AB8500_GPIO_IN5_REG 0x44
89#define AB8500_GPIO_IN6_REG 0x45
90#define AB9540_GPIO_IN7_REG 0x46
91#define AB8540_GPIO_VINSEL_REG 0x47
92#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
93#define AB8500_GPIO_ALTFUN_REG 0x50
0493e649
PC		 94#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
95#define AB8540_GPIO_VINSEL_MASK 0x03
96#define AB8540_GPIOX_VBAT_START 51
97#define AB8540_GPIOX_VBAT_END 54
98
acd260b0
PC		 99#define ABX500_GPIO_INPUT 0
100#define ABX500_GPIO_OUTPUT 1
101
0493e649
PC		 102struct abx500_pinctrl {
103 struct device *dev;
104 struct pinctrl_dev *pctldev;
105 struct abx500_pinctrl_soc_data *soc;
106 struct gpio_chip chip;
107 struct ab8500 *parent;
0493e649
PC		 108 struct abx500_gpio_irq_cluster *irq_cluster;
109 int irq_cluster_size;
0493e649
PC		 110};
111
0493e649 112static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
83b423c8 113 unsigned offset, bool *bit)
0493e649 114{
2b016d27 115 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 116 u8 pos = offset % 8;
117 u8 val;
118 int ret;
119
120 reg += offset / 8;
121 ret = abx500_get_register_interruptible(pct->dev,
122 AB8500_MISC, reg, &val);
123
124 *bit = !!(val & BIT(pos));
125
126 if (ret < 0)
127 dev_err(pct->dev,
9be580af
PC		 128 "%s read reg =%x, offset=%x failed (%d)\n",
129 __func__, reg, offset, ret);
0493e649
PC		 130
131 return ret;
132}
133
134static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
83b423c8 135 unsigned offset, int val)
0493e649 136{
2b016d27 137 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 138 u8 pos = offset % 8;
139 int ret;
140
141 reg += offset / 8;
142 ret = abx500_mask_and_set_register_interruptible(pct->dev,
49dcf086 143 AB8500_MISC, reg, BIT(pos), val << pos);
0493e649 144 if (ret < 0)
9be580af
PC		 145 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
146 __func__, reg, offset, ret);
83b423c8 147
0493e649
PC		 148 return ret;
149}
83b423c8 150
0493e649
PC		 151/**
152 * abx500_gpio_get() - Get the particular GPIO value
83b423c8
LJ		 153 * @chip: Gpio device
154 * @offset: GPIO number to read
0493e649
PC		 155 */
156static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
157{
2b016d27 158 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649 159 bool bit;
d8d4f7f8
PC		 160 bool is_out;
161 u8 gpio_offset = offset - 1;
0493e649
PC		 162 int ret;
163
d8d4f7f8
PC		 164 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
165 gpio_offset, &is_out);
9be580af
PC		 166 if (ret < 0)
167 goto out;
d8d4f7f8
PC		 168
169 if (is_out)
170 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
171 gpio_offset, &bit);
172 else
173 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
174 gpio_offset, &bit);
9be580af 175out:
0493e649 176 if (ret < 0) {
9be580af 177 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
0493e649
PC		 178 return ret;
179 }
83b423c8 180
0493e649
PC		 181 return bit;
182}
183
184static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
185{
2b016d27 186 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 187 int ret;
188
189 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
190 if (ret < 0)
9be580af 191 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
0493e649
PC		 192}
193
39178bb2 194#ifdef CONFIG_DEBUG_FS
d2752ae5
PC		 195static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
196 enum abx500_gpio_pull_updown *pull_updown)
0493e649
PC		 197{
198 u8 pos;
d2752ae5 199 u8 val;
0493e649
PC		 200 int ret;
201 struct pullud *pullud;
202
203 if (!pct->soc->pullud) {
204 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
205 __func__);
206 ret = -EPERM;
207 goto out;
208 }
209
210 pullud = pct->soc->pullud;
211
212 if ((offset < pullud->first_pin)
213 || (offset > pullud->last_pin)) {
214 ret = -EINVAL;
215 goto out;
216 }
217
d2752ae5
PC		 218 ret = abx500_get_register_interruptible(pct->dev,
219 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
220
221 pos = (offset - pullud->first_pin) << 1;
222 *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
223
224out:
225 if (ret < 0)
226 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
227
228 return ret;
229}
39178bb2 230#endif
d2752ae5
PC		 231
232static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
233 int offset, enum abx500_gpio_pull_updown val)
234{
235 u8 pos;
236 int ret;
237 struct pullud *pullud;
238
239 if (!pct->soc->pullud) {
240 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
241 __func__);
242 ret = -EPERM;
243 goto out;
244 }
245
246 pullud = pct->soc->pullud;
247
248 if ((offset < pullud->first_pin)
249 || (offset > pullud->last_pin)) {
250 ret = -EINVAL;
251 goto out;
252 }
10a8be54 253 pos = (offset - pullud->first_pin) << 1;
0493e649
PC		 254
255 ret = abx500_mask_and_set_register_interruptible(pct->dev,
256 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
257 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
258
259out:
260 if (ret < 0)
261 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 262
0493e649
PC		 263 return ret;
264}
265
8b5abd18
PC		 266static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
267{
2b016d27 268 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
8b5abd18
PC		 269 struct pullud *pullud = pct->soc->pullud;
270
271 return (pullud &&
272 gpio >= pullud->first_pin &&
273 gpio <= pullud->last_pin);
274}
275
0493e649
PC		 276static int abx500_gpio_direction_output(struct gpio_chip *chip,
277 unsigned offset,
278 int val)
279{
2b016d27 280 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 281 unsigned gpio;
282 int ret;
83b423c8 283
0493e649 284 /* set direction as output */
acd260b0
PC		 285 ret = abx500_gpio_set_bits(chip,
286 AB8500_GPIO_DIR1_REG,
287 offset,
288 ABX500_GPIO_OUTPUT);
0493e649 289 if (ret < 0)
9be580af 290 goto out;
0493e649
PC		 291
292 /* disable pull down */
acd260b0
PC		 293 ret = abx500_gpio_set_bits(chip,
294 AB8500_GPIO_PUD1_REG,
295 offset,
296 ABX500_GPIO_PULL_NONE);
0493e649 297 if (ret < 0)
9be580af 298 goto out;
0493e649
PC		 299
300 /* if supported, disable both pull down and pull up */
301 gpio = offset + 1;
8b5abd18 302 if (abx500_pullud_supported(chip, gpio)) {
d2752ae5 303 ret = abx500_set_pull_updown(pct,
0493e649
PC		 304 gpio,
305 ABX500_GPIO_PULL_NONE);
9be580af
PC		 306 }
307out:
308 if (ret < 0) {
309 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
310 return ret;
0493e649 311 }
83b423c8 312
0493e649
PC		 313 /* set the output as 1 or 0 */
314 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
315}
316
317static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
318{
319 /* set the register as input */
acd260b0
PC		 320 return abx500_gpio_set_bits(chip,
321 AB8500_GPIO_DIR1_REG,
322 offset,
323 ABX500_GPIO_INPUT);
0493e649
PC		 324}
325
326static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
327{
2b016d27 328 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
b9fab6e4
LJ		 329 /* The AB8500 GPIO numbers are off by one */
330 int gpio = offset + 1;
a6a16d27 331 int hwirq;
0493e649
PC		 332 int i;
333
334 for (i = 0; i < pct->irq_cluster_size; i++) {
335 struct abx500_gpio_irq_cluster *cluster =
336 &pct->irq_cluster[i];
337
a6a16d27
LJ		 338 if (gpio >= cluster->start && gpio <= cluster->end) {
339 /*
340 * The ABx500 GPIO's associated IRQs are clustered together
341 * throughout the interrupt numbers at irregular intervals.
342 * To solve this quandry, we have placed the read-in values
343 * into the cluster information table.
344 */
43a255db 345 hwirq = gpio - cluster->start + cluster->to_irq;
a6a16d27
LJ		 346 return irq_create_mapping(pct->parent->domain, hwirq);
347 }
0493e649
PC		 348 }
349
350 return -EINVAL;
351}
352
353static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 354 unsigned gpio, int alt_setting)
0493e649
PC		 355{
356 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
357 struct alternate_functions af = pct->soc->alternate_functions[gpio];
358 int ret;
359 int val;
360 unsigned offset;
83b423c8 361
0493e649
PC		 362 const char *modes[] = {
363 [ABX500_DEFAULT] = "default",
364 [ABX500_ALT_A] = "altA",
365 [ABX500_ALT_B] = "altB",
366 [ABX500_ALT_C] = "altC",
367 };
368
369 /* sanity check */
370 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
371 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
372 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
373 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
374 modes[alt_setting]);
375 return -EINVAL;
376 }
377
378 /* on ABx5xx, there is no GPIO0, so adjust the offset */
379 offset = gpio - 1;
83b423c8 380
0493e649
PC		 381 switch (alt_setting) {
382 case ABX500_DEFAULT:
383 /*
384 * for ABx5xx family, default mode is always selected by
385 * writing 0 to GPIOSELx register, except for pins which
386 * support at least ALT_B mode, default mode is selected
387 * by writing 1 to GPIOSELx register
388 */
389 val = 0;
390 if (af.alt_bit1 != UNUSED)
391 val++;
392
393 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
394 offset, val);
395 break;
83b423c8 396
0493e649
PC		 397 case ABX500_ALT_A:
398 /*
399 * for ABx5xx family, alt_a mode is always selected by
400 * writing 1 to GPIOSELx register, except for pins which
401 * support at least ALT_B mode, alt_a mode is selected
402 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
403 * register
404 */
405 if (af.alt_bit1 != UNUSED) {
406 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
407 offset, 0);
9be580af
PC		 408 if (ret < 0)
409 goto out;
410
0493e649
PC		 411 ret = abx500_gpio_set_bits(chip,
412 AB8500_GPIO_ALTFUN_REG,
413 af.alt_bit1,
c590854d 414 !!(af.alta_val & BIT(0)));
9be580af
PC		 415 if (ret < 0)
416 goto out;
417
0493e649
PC		 418 if (af.alt_bit2 != UNUSED)
419 ret = abx500_gpio_set_bits(chip,
420 AB8500_GPIO_ALTFUN_REG,
421 af.alt_bit2,
6da33dbd 422 !!(af.alta_val & BIT(1)));
0493e649
PC		 423 } else
424 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
425 offset, 1);
426 break;
83b423c8 427
0493e649
PC		 428 case ABX500_ALT_B:
429 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
430 offset, 0);
9be580af
PC		 431 if (ret < 0)
432 goto out;
433
0493e649 434 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
c590854d 435 af.alt_bit1, !!(af.altb_val & BIT(0)));
9be580af
PC		 436 if (ret < 0)
437 goto out;
438
0493e649
PC		 439 if (af.alt_bit2 != UNUSED)
440 ret = abx500_gpio_set_bits(chip,
441 AB8500_GPIO_ALTFUN_REG,
442 af.alt_bit2,
6da33dbd 443 !!(af.altb_val & BIT(1)));
0493e649 444 break;
83b423c8 445
0493e649
PC		 446 case ABX500_ALT_C:
447 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
448 offset, 0);
9be580af
PC		 449 if (ret < 0)
450 goto out;
451
0493e649 452 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
6da33dbd 453 af.alt_bit2, !!(af.altc_val & BIT(0)));
9be580af
PC		 454 if (ret < 0)
455 goto out;
456
0493e649 457 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
c590854d 458 af.alt_bit2, !!(af.altc_val & BIT(1)));
0493e649
PC		 459 break;
460
461 default:
f42cf8d6 462 dev_dbg(pct->dev, "unknown alt_setting %d\n", alt_setting);
83b423c8 463
0493e649
PC		 464 return -EINVAL;
465 }
9be580af
PC		 466out:
467 if (ret < 0)
468 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 469
0493e649
PC		 470 return ret;
471}
472
39178bb2 473#ifdef CONFIG_DEBUG_FS
9be580af 474static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 475 unsigned gpio)
0493e649
PC		 476{
477 u8 mode;
478 bool bit_mode;
479 bool alt_bit1;
480 bool alt_bit2;
481 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
482 struct alternate_functions af = pct->soc->alternate_functions[gpio];
a950cb74
LW		 483 /* on ABx5xx, there is no GPIO0, so adjust the offset */
484 unsigned offset = gpio - 1;
9be580af 485 int ret;
0493e649
PC		 486
487 /*
488 * if gpiosel_bit is set to unused,
489 * it means no GPIO or special case
490 */
491 if (af.gpiosel_bit == UNUSED)
492 return ABX500_DEFAULT;
493
494 /* read GpioSelx register */
9be580af 495 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
0493e649 496 af.gpiosel_bit, &bit_mode);
9be580af
PC		 497 if (ret < 0)
498 goto out;
499
0493e649
PC		 500 mode = bit_mode;
501
502 /* sanity check */
503 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
504 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
505 dev_err(pct->dev,
506 "alt_bitX value not in correct range (-1 to 7)\n");
507 return -EINVAL;
508 }
83b423c8 509
0493e649
PC		 510 /* if alt_bit2 is used, alt_bit1 must be used too */
511 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
512 dev_err(pct->dev,
513 "if alt_bit2 is used, alt_bit1 can't be unused\n");
514 return -EINVAL;
515 }
516
517 /* check if pin use AlternateFunction register */
6a40cdd5 518 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
0493e649
PC		 519 return mode;
520 /*
521 * if pin GPIOSEL bit is set and pin supports alternate function,
522 * it means DEFAULT mode
523 */
524 if (mode)
525 return ABX500_DEFAULT;
83b423c8 526
0493e649
PC		 527 /*
528 * pin use the AlternatFunction register
529 * read alt_bit1 value
530 */
9be580af 531 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
0493e649 532 af.alt_bit1, &alt_bit1);
9be580af
PC		 533 if (ret < 0)
534 goto out;
0493e649 535
9be580af 536 if (af.alt_bit2 != UNUSED) {
0493e649 537 /* read alt_bit2 value */
9be580af
PC		 538 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
539 af.alt_bit2,
0493e649 540 &alt_bit2);
9be580af
PC		 541 if (ret < 0)
542 goto out;
543 } else
0493e649
PC		 544 alt_bit2 = 0;
545
546 mode = (alt_bit2 << 1) + alt_bit1;
547 if (mode == af.alta_val)
548 return ABX500_ALT_A;
549 else if (mode == af.altb_val)
550 return ABX500_ALT_B;
551 else
552 return ABX500_ALT_C;
9be580af
PC		 553
554out:
555 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
556 return ret;
0493e649
PC		 557}
558
0493e649
PC		 559#include <linux/seq_file.h>
560
561static void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 562 struct pinctrl_dev *pctldev,
563 struct gpio_chip *chip,
564 unsigned offset, unsigned gpio)
0493e649 565{
d2752ae5 566 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 567 const char *label = gpiochip_is_requested(chip, offset - 1);
568 u8 gpio_offset = offset - 1;
569 int mode = -1;
570 bool is_out;
d2752ae5 571 bool pd;
ce06f407 572 enum abx500_gpio_pull_updown pud = 0;
9be580af 573 int ret;
83b423c8 574
0493e649
PC		 575 const char *modes[] = {
576 [ABX500_DEFAULT] = "default",
577 [ABX500_ALT_A] = "altA",
578 [ABX500_ALT_B] = "altB",
579 [ABX500_ALT_C] = "altC",
580 };
581
d2752ae5
PC		 582 const char *pull_up_down[] = {
583 [ABX500_GPIO_PULL_DOWN] = "pull down",
584 [ABX500_GPIO_PULL_NONE] = "pull none",
585 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
586 [ABX500_GPIO_PULL_UP] = "pull up",
587 };
588
9be580af
PC		 589 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
590 gpio_offset, &is_out);
591 if (ret < 0)
592 goto out;
d2752ae5
PC		 593
594 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
595 gpio, label ?: "(none)",
596 is_out ? "out" : "in ");
597
598 if (!is_out) {
8b5abd18 599 if (abx500_pullud_supported(chip, offset)) {
9be580af
PC		 600 ret = abx500_get_pull_updown(pct, offset, &pud);
601 if (ret < 0)
602 goto out;
603
d2752ae5
PC		 604 seq_printf(s, " %-9s", pull_up_down[pud]);
605 } else {
9be580af
PC		 606 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
607 gpio_offset, &pd);
608 if (ret < 0)
609 goto out;
610
d2752ae5
PC		 611 seq_printf(s, " %-9s", pull_up_down[pd]);
612 }
613 } else
614 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
0493e649 615
1d54f0fd 616 mode = abx500_get_mode(pctldev, chip, offset);
0493e649 617
d2752ae5 618 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
9be580af
PC		 619
620out:
621 if (ret < 0)
622 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
0493e649
PC		 623}
624
625static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
626{
627 unsigned i;
628 unsigned gpio = chip->base;
2b016d27 629 struct abx500_pinctrl *pct = gpiochip_get_data(chip);
0493e649
PC		 630 struct pinctrl_dev *pctldev = pct->pctldev;
631
632 for (i = 0; i < chip->ngpio; i++, gpio++) {
633 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
634 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
635 seq_printf(s, "\n");
636 }
637}
638
639#else
640static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 641 struct pinctrl_dev *pctldev,
642 struct gpio_chip *chip,
643 unsigned offset, unsigned gpio)
0493e649
PC		 644{
645}
646#define abx500_gpio_dbg_show NULL
647#endif
648
0493e649
PC		 649static struct gpio_chip abx500gpio_chip = {
650 .label = "abx500-gpio",
651 .owner = THIS_MODULE,
98c85d58
JG		 652 .request = gpiochip_generic_request,
653 .free = gpiochip_generic_free,
0493e649
PC		 654 .direction_input = abx500_gpio_direction_input,
655 .get = abx500_gpio_get,
656 .direction_output = abx500_gpio_direction_output,
657 .set = abx500_gpio_set,
658 .to_irq = abx500_gpio_to_irq,
659 .dbg_show = abx500_gpio_dbg_show,
660};
661
0493e649
PC		 662static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
663{
664 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
665
666 return pct->soc->nfunctions;
667}
668
669static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
670 unsigned function)
671{
672 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
673
674 return pct->soc->functions[function].name;
675}
676
677static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
83b423c8
LJ		 678 unsigned function,
679 const char * const **groups,
680 unsigned * const num_groups)
0493e649
PC		 681{
682 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
683
684 *groups = pct->soc->functions[function].groups;
685 *num_groups = pct->soc->functions[function].ngroups;
686
687 return 0;
688}
689
03e9f0ca
LW		 690static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
691 unsigned group)
0493e649
PC		 692{
693 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
694 struct gpio_chip *chip = &pct->chip;
695 const struct abx500_pingroup *g;
696 int i;
697 int ret = 0;
698
699 g = &pct->soc->groups[group];
700 if (g->altsetting < 0)
701 return -EINVAL;
702
703 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
704
705 for (i = 0; i < g->npins; i++) {
706 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
707 g->pins[i], g->altsetting);
708
0493e649
PC		 709 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
710 }
83b423c8 711
9be580af
PC		 712 if (ret < 0)
713 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
714
0493e649
PC		 715 return ret;
716}
717
9c4154ef 718static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
83b423c8
LJ		 719 struct pinctrl_gpio_range *range,
720 unsigned offset)
0493e649
PC		 721{
722 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
723 const struct abx500_pinrange *p;
724 int ret;
725 int i;
726
727 /*
728 * Different ranges have different ways to enable GPIO function on a
729 * pin, so refer back to our local range type, where we handily define
730 * what altfunc enables GPIO for a certain pin.
731 */
732 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
733 p = &pct->soc->gpio_ranges[i];
734 if ((offset >= p->offset) &&
735 (offset < (p->offset + p->npins)))
736 break;
737 }
738
739 if (i == pct->soc->gpio_num_ranges) {
740 dev_err(pct->dev, "%s failed to locate range\n", __func__);
741 return -ENODEV;
742 }
743
744 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
745 p->altfunc, offset);
746
747 ret = abx500_set_mode(pct->pctldev, &pct->chip,
748 offset, p->altfunc);
9be580af 749 if (ret < 0)
0493e649 750 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
0493e649
PC		 751
752 return ret;
753}
754
755static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
83b423c8
LJ		 756 struct pinctrl_gpio_range *range,
757 unsigned offset)
0493e649
PC		 758{
759}
760
022ab148 761static const struct pinmux_ops abx500_pinmux_ops = {
0493e649
PC		 762 .get_functions_count = abx500_pmx_get_funcs_cnt,
763 .get_function_name = abx500_pmx_get_func_name,
764 .get_function_groups = abx500_pmx_get_func_groups,
03e9f0ca 765 .set_mux = abx500_pmx_set,
0493e649
PC		 766 .gpio_request_enable = abx500_gpio_request_enable,
767 .gpio_disable_free = abx500_gpio_disable_free,
768};
769
770static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
771{
772 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
773
774 return pct->soc->ngroups;
775}
776
777static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
83b423c8 778 unsigned selector)
0493e649
PC		 779{
780 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
781
782 return pct->soc->groups[selector].name;
783}
784
785static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
83b423c8
LJ		 786 unsigned selector,
787 const unsigned **pins,
788 unsigned *num_pins)
0493e649
PC		 789{
790 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
791
792 *pins = pct->soc->groups[selector].pins;
793 *num_pins = pct->soc->groups[selector].npins;
83b423c8 794
0493e649
PC		 795 return 0;
796}
797
798static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
83b423c8 799 struct seq_file *s, unsigned offset)
0493e649
PC		 800{
801 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
802 struct gpio_chip *chip = &pct->chip;
803
804 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
805 chip->base + offset - 1);
806}
807
64a45c98
PC		 808static int abx500_dt_add_map_mux(struct pinctrl_map **map,
809 unsigned *reserved_maps,
810 unsigned *num_maps, const char *group,
811 const char *function)
812{
813 if (*num_maps == *reserved_maps)
814 return -ENOSPC;
815
816 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
817 (*map)[*num_maps].data.mux.group = group;
818 (*map)[*num_maps].data.mux.function = function;
819 (*num_maps)++;
820
821 return 0;
822}
823
824static int abx500_dt_add_map_configs(struct pinctrl_map **map,
825 unsigned *reserved_maps,
826 unsigned *num_maps, const char *group,
827 unsigned long *configs, unsigned num_configs)
828{
829 unsigned long *dup_configs;
830
831 if (*num_maps == *reserved_maps)
832 return -ENOSPC;
833
834 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
835 GFP_KERNEL);
836 if (!dup_configs)
837 return -ENOMEM;
838
839 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
840
841 (*map)[*num_maps].data.configs.group_or_pin = group;
842 (*map)[*num_maps].data.configs.configs = dup_configs;
843 (*map)[*num_maps].data.configs.num_configs = num_configs;
844 (*num_maps)++;
845
846 return 0;
847}
848
849static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
850 const char *pin_name)
851{
852 int i, pin_number;
853 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
854
855 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
856 for (i = 0; i < npct->soc->npins; i++)
857 if (npct->soc->pins[i].number == pin_number)
858 return npct->soc->pins[i].name;
859 return NULL;
860}
861
862static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
863 struct device_node *np,
864 struct pinctrl_map **map,
865 unsigned *reserved_maps,
866 unsigned *num_maps)
867{
868 int ret;
869 const char *function = NULL;
870 unsigned long *configs;
871 unsigned int nconfigs = 0;
64a45c98 872 struct property *prop;
64a45c98 873
51d39936 874 ret = of_property_read_string(np, "function", &function);
259145fe 875 if (ret >= 0) {
51d39936
LW		 876 const char *group;
877
878 ret = of_property_count_strings(np, "groups");
259145fe
LW		 879 if (ret < 0)
880 goto exit;
881
882 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
883 num_maps, ret);
884 if (ret < 0)
885 goto exit;
886
51d39936 887 of_property_for_each_string(np, "groups", prop, group) {
259145fe
LW		 888 ret = abx500_dt_add_map_mux(map, reserved_maps,
889 num_maps, group, function);
890 if (ret < 0)
891 goto exit;
892 }
893 }
64a45c98 894
dd4d01f7 895 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &nconfigs);
eea11b0b 896 if (nconfigs) {
51d39936
LW		 897 const char *gpio_name;
898 const char *pin;
899
0564f7d9 900 ret = of_property_count_strings(np, "pins");
259145fe
LW		 901 if (ret < 0)
902 goto exit;
64a45c98 903
259145fe
LW		 904 ret = pinctrl_utils_reserve_map(pctldev, map,
905 reserved_maps,
906 num_maps, ret);
907 if (ret < 0)
908 goto exit;
64a45c98 909
0564f7d9 910 of_property_for_each_string(np, "pins", prop, pin) {
51d39936 911 gpio_name = abx500_find_pin_name(pctldev, pin);
64a45c98
PC		 912
913 ret = abx500_dt_add_map_configs(map, reserved_maps,
914 num_maps, gpio_name, configs, 1);
915 if (ret < 0)
916 goto exit;
917 }
64a45c98 918 }
259145fe 919
64a45c98
PC		 920exit:
921 return ret;
922}
923
924static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
925 struct device_node *np_config,
926 struct pinctrl_map **map, unsigned *num_maps)
927{
928 unsigned reserved_maps;
929 struct device_node *np;
930 int ret;
931
932 reserved_maps = 0;
933 *map = NULL;
934 *num_maps = 0;
935
936 for_each_child_of_node(np_config, np) {
937 ret = abx500_dt_subnode_to_map(pctldev, np, map,
938 &reserved_maps, num_maps);
939 if (ret < 0) {
d32f7fd3 940 pinctrl_utils_free_map(pctldev, *map, *num_maps);
64a45c98
PC		 941 return ret;
942 }
943 }
944
945 return 0;
946}
947
022ab148 948static const struct pinctrl_ops abx500_pinctrl_ops = {
0493e649
PC		 949 .get_groups_count = abx500_get_groups_cnt,
950 .get_group_name = abx500_get_group_name,
951 .get_group_pins = abx500_get_group_pins,
952 .pin_dbg_show = abx500_pin_dbg_show,
64a45c98 953 .dt_node_to_map = abx500_dt_node_to_map,
d32f7fd3 954 .dt_free_map = pinctrl_utils_free_map,
0493e649
PC		 955};
956
9c4154ef 957static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
83b423c8
LJ		 958 unsigned pin,
959 unsigned long *config)
0493e649 960{
1abeebea 961 return -ENOSYS;
0493e649
PC		 962}
963
9c4154ef 964static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
83b423c8 965 unsigned pin,
03b054e9
SY		 966 unsigned long *configs,
967 unsigned num_configs)
0493e649
PC		 968{
969 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 970 struct gpio_chip *chip = &pct->chip;
971 unsigned offset;
61ce1356 972 int ret = -EINVAL;
03b054e9
SY		 973 int i;
974 enum pin_config_param param;
975 enum pin_config_param argument;
976
977 for (i = 0; i < num_configs; i++) {
978 param = pinconf_to_config_param(configs[i]);
979 argument = pinconf_to_config_argument(configs[i]);
980
58383c78 981 dev_dbg(chip->parent, "pin %d [%#lx]: %s %s\n",
03b054e9
SY		 982 pin, configs[i],
983 (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
984 (param == PIN_CONFIG_OUTPUT) ?
985 (argument ? "high" : "low") :
986 (argument ? "pull up" : "pull down"));
987
988 /* on ABx500, there is no GPIO0, so adjust the offset */
989 offset = pin - 1;
990
991 switch (param) {
992 case PIN_CONFIG_BIAS_DISABLE:
993 ret = abx500_gpio_direction_input(chip, offset);
994 if (ret < 0)
995 goto out;
996 /*
997 * Some chips only support pull down, while some
998 * actually support both pull up and pull down. Such
999 * chips have a "pullud" range specified for the pins
1000 * that support both features. If the pin is not
1001 * within that range, we fall back to the old bit set
1002 * that only support pull down.
1003 */
1004 if (abx500_pullud_supported(chip, pin))
1005 ret = abx500_set_pull_updown(pct,
1006 pin,
1007 ABX500_GPIO_PULL_NONE);
1008 else
1009 /* Chip only supports pull down */
1010 ret = abx500_gpio_set_bits(chip,
1011 AB8500_GPIO_PUD1_REG, offset,
1012 ABX500_GPIO_PULL_NONE);
1013 break;
9ed3cd33 1014
03b054e9
SY		 1015 case PIN_CONFIG_BIAS_PULL_DOWN:
1016 ret = abx500_gpio_direction_input(chip, offset);
1017 if (ret < 0)
1018 goto out;
1019 /*
1020 * if argument = 1 set the pull down
1021 * else clear the pull down
1022 * Some chips only support pull down, while some
1023 * actually support both pull up and pull down. Such
1024 * chips have a "pullud" range specified for the pins
1025 * that support both features. If the pin is not
1026 * within that range, we fall back to the old bit set
1027 * that only support pull down.
1028 */
1029 if (abx500_pullud_supported(chip, pin))
1030 ret = abx500_set_pull_updown(pct,
1031 pin,
1032 argument ? ABX500_GPIO_PULL_DOWN :
1033 ABX500_GPIO_PULL_NONE);
1034 else
1035 /* Chip only supports pull down */
1036 ret = abx500_gpio_set_bits(chip,
1037 AB8500_GPIO_PUD1_REG,
1038 offset,
1039 argument ? ABX500_GPIO_PULL_DOWN :
1040 ABX500_GPIO_PULL_NONE);
1041 break;
83b423c8 1042
03b054e9
SY		 1043 case PIN_CONFIG_BIAS_PULL_UP:
1044 ret = abx500_gpio_direction_input(chip, offset);
1045 if (ret < 0)
1046 goto out;
1047 /*
1048 * if argument = 1 set the pull up
1049 * else clear the pull up
1050 */
1051 ret = abx500_gpio_direction_input(chip, offset);
1052 /*
1053 * Some chips only support pull down, while some
1054 * actually support both pull up and pull down. Such
1055 * chips have a "pullud" range specified for the pins
1056 * that support both features. If the pin is not
1057 * within that range, do nothing
1058 */
1059 if (abx500_pullud_supported(chip, pin))
1060 ret = abx500_set_pull_updown(pct,
1061 pin,
1062 argument ? ABX500_GPIO_PULL_UP :
1063 ABX500_GPIO_PULL_NONE);
1064 break;
1065
1066 case PIN_CONFIG_OUTPUT:
1067 ret = abx500_gpio_direction_output(chip, offset,
1068 argument);
1069 break;
1070
1071 default:
58383c78
LW		 1072 dev_err(chip->parent,
1073 "illegal configuration requested\n");
03b054e9
SY		 1074 }
1075 } /* for each config */
9be580af
PC		 1076out:
1077 if (ret < 0)
1078 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 1079
0493e649
PC		 1080 return ret;
1081}
1082
022ab148 1083static const struct pinconf_ops abx500_pinconf_ops = {
0493e649
PC		 1084 .pin_config_get = abx500_pin_config_get,
1085 .pin_config_set = abx500_pin_config_set,
71ca917a 1086 .is_generic = true,
0493e649
PC		 1087};
1088
1089static struct pinctrl_desc abx500_pinctrl_desc = {
1090 .name = "pinctrl-abx500",
1091 .pctlops = &abx500_pinctrl_ops,
1092 .pmxops = &abx500_pinmux_ops,
1093 .confops = &abx500_pinconf_ops,
1094 .owner = THIS_MODULE,
1095};
1096
1097static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1098{
1099 unsigned int lowest = 0;
1100 unsigned int highest = 0;
1101 unsigned int npins = 0;
1102 int i;
1103
1104 /*
1105 * Compute number of GPIOs from the last SoC gpio range descriptors
1106 * These ranges may include "holes" but the GPIO number space shall
1107 * still be homogeneous, so we need to detect and account for any
1108 * such holes so that these are included in the number of GPIO pins.
1109 */
1110 for (i = 0; i < soc->gpio_num_ranges; i++) {
1111 unsigned gstart;
1112 unsigned gend;
1113 const struct abx500_pinrange *p;
1114
1115 p = &soc->gpio_ranges[i];
1116 gstart = p->offset;
1117 gend = p->offset + p->npins - 1;
1118
1119 if (i == 0) {
1120 /* First iteration, set start values */
1121 lowest = gstart;
1122 highest = gend;
1123 } else {
1124 if (gstart < lowest)
1125 lowest = gstart;
1126 if (gend > highest)
1127 highest = gend;
1128 }
1129 }
1130 /* this gives the absolute number of pins */
1131 npins = highest - lowest + 1;
1132 return npins;
1133}
1134
f30a3839
LJ		 1135static const struct of_device_id abx500_gpio_match[] = {
1136 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
1137 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
1138 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
1139 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
e3929714 1140 { }
f30a3839
LJ		 1141};
1142
0493e649
PC		 1143static int abx500_gpio_probe(struct platform_device *pdev)
1144{
f30a3839 1145 struct device_node *np = pdev->dev.of_node;
ac99a037 1146 const struct of_device_id *match;
0493e649 1147 struct abx500_pinctrl *pct;
f30a3839 1148 unsigned int id = -1;
3a4b094d 1149 int ret;
0493e649
PC		 1150 int i;
1151
ac99a037
LW		 1152 if (!np) {
1153 dev_err(&pdev->dev, "gpio dt node missing\n");
86c976e4 1154 return -ENODEV;
0493e649
PC		 1155 }
1156
1157 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1158 GFP_KERNEL);
1159 if (pct == NULL) {
1160 dev_err(&pdev->dev,
1161 "failed to allocate memory for pct\n");
1162 return -ENOMEM;
1163 }
1164
1165 pct->dev = &pdev->dev;
1166 pct->parent = dev_get_drvdata(pdev->dev.parent);
1167 pct->chip = abx500gpio_chip;
58383c78 1168 pct->chip.parent = &pdev->dev;
ac99a037 1169 pct->chip.base = -1; /* Dynamic allocation */
86c976e4 1170
ac99a037
LW		 1171 match = of_match_device(abx500_gpio_match, &pdev->dev);
1172 if (!match) {
1173 dev_err(&pdev->dev, "gpio dt not matching\n");
1174 return -ENODEV;
86c976e4 1175 }
ac99a037 1176 id = (unsigned long)match->data;
86c976e4 1177
0493e649 1178 /* Poke in other ASIC variants here */
f30a3839 1179 switch (id) {
3c937993
PC		 1180 case PINCTRL_AB8500:
1181 abx500_pinctrl_ab8500_init(&pct->soc);
1182 break;
a8f96e41
PC		 1183 case PINCTRL_AB8540:
1184 abx500_pinctrl_ab8540_init(&pct->soc);
1185 break;
09dbec3f
PC		 1186 case PINCTRL_AB9540:
1187 abx500_pinctrl_ab9540_init(&pct->soc);
1188 break;
1aa2d8d4
PC		 1189 case PINCTRL_AB8505:
1190 abx500_pinctrl_ab8505_init(&pct->soc);
1191 break;
0493e649 1192 default:
2fcad12e 1193 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
0493e649
PC		 1194 return -EINVAL;
1195 }
1196
1197 if (!pct->soc) {
1198 dev_err(&pdev->dev, "Invalid SOC data\n");
1199 return -EINVAL;
1200 }
1201
1202 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1203 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1204 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
0493e649 1205
2b016d27 1206 ret = gpiochip_add_data(&pct->chip, pct);
0493e649 1207 if (ret) {
83b423c8 1208 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
ac652d79 1209 return ret;
0493e649
PC		 1210 }
1211 dev_info(&pdev->dev, "added gpiochip\n");
1212
1213 abx500_pinctrl_desc.pins = pct->soc->pins;
1214 abx500_pinctrl_desc.npins = pct->soc->npins;
0ee60110
LD		 1215 pct->pctldev = devm_pinctrl_register(&pdev->dev, &abx500_pinctrl_desc,
1216 pct);
323de9ef 1217 if (IS_ERR(pct->pctldev)) {
0493e649
PC		 1218 dev_err(&pdev->dev,
1219 "could not register abx500 pinctrl driver\n");
323de9ef 1220 ret = PTR_ERR(pct->pctldev);
0493e649
PC		 1221 goto out_rem_chip;
1222 }
1223 dev_info(&pdev->dev, "registered pin controller\n");
1224
1225 /* We will handle a range of GPIO pins */
1226 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1227 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1228
1229 ret = gpiochip_add_pin_range(&pct->chip,
1230 dev_name(&pdev->dev),
1231 p->offset - 1, p->offset, p->npins);
1232 if (ret < 0)
fa1ec996 1233 goto out_rem_chip;
0493e649
PC		 1234 }
1235
1236 platform_set_drvdata(pdev, pct);
1237 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1238
1239 return 0;
1240
1241out_rem_chip:
2fcea6ce 1242 gpiochip_remove(&pct->chip);
0493e649
PC		 1243 return ret;
1244}
1245
83b423c8 1246/**
0493e649 1247 * abx500_gpio_remove() - remove Ab8500-gpio driver
83b423c8 1248 * @pdev: Platform device registered
0493e649
PC		 1249 */
1250static int abx500_gpio_remove(struct platform_device *pdev)
1251{
1252 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
0493e649 1253
2fcea6ce 1254 gpiochip_remove(&pct->chip);
0493e649
PC		 1255 return 0;
1256}
1257
0493e649
PC		 1258static struct platform_driver abx500_gpio_driver = {
1259 .driver = {
1260 .name = "abx500-gpio",
f30a3839 1261 .of_match_table = abx500_gpio_match,
0493e649
PC		 1262 },
1263 .probe = abx500_gpio_probe,
1264 .remove = abx500_gpio_remove,
0493e649
PC		 1265};
1266
1267static int __init abx500_gpio_init(void)
1268{
1269 return platform_driver_register(&abx500_gpio_driver);
1270}
1271core_initcall(abx500_gpio_init);
1272
1273MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1274MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1275MODULE_ALIAS("platform:abx500-gpio");
1276MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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