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Merge tag 'pinctrl-v3.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw...
[deliverable/linux.git] / drivers / pinctrl / nomadik / pinctrl-abx500.c
CommitLineData
0493e649
PC		 1/*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/err.h>
f30a3839
LJ		 17#include <linux/of.h>
18#include <linux/of_device.h>
0493e649
PC		 19#include <linux/platform_device.h>
20#include <linux/gpio.h>
21#include <linux/irq.h>
ac652d79 22#include <linux/irqdomain.h>
0493e649
PC		 23#include <linux/interrupt.h>
24#include <linux/bitops.h>
25#include <linux/mfd/abx500.h>
26#include <linux/mfd/abx500/ab8500.h>
0493e649
PC		 27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/pinctrl/pinconf.h>
31#include <linux/pinctrl/pinconf-generic.h>
64a45c98 32#include <linux/pinctrl/machine.h>
0493e649
PC		 33
34#include "pinctrl-abx500.h"
3a198059
LW		 35#include "../core.h"
36#include "../pinconf.h"
0493e649
PC		 37
38/*
39 * The AB9540 and AB8540 GPIO support are extended versions
40 * of the AB8500 GPIO support.
41 * The AB9540 supports an additional (7th) register so that
42 * more GPIO may be configured and used.
43 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
44 * internal pull-up and pull-down capabilities.
45 */
46
47/*
48 * GPIO registers offset
49 * Bank: 0x10
50 */
51#define AB8500_GPIO_SEL1_REG 0x00
52#define AB8500_GPIO_SEL2_REG 0x01
53#define AB8500_GPIO_SEL3_REG 0x02
54#define AB8500_GPIO_SEL4_REG 0x03
55#define AB8500_GPIO_SEL5_REG 0x04
56#define AB8500_GPIO_SEL6_REG 0x05
57#define AB9540_GPIO_SEL7_REG 0x06
58
59#define AB8500_GPIO_DIR1_REG 0x10
60#define AB8500_GPIO_DIR2_REG 0x11
61#define AB8500_GPIO_DIR3_REG 0x12
62#define AB8500_GPIO_DIR4_REG 0x13
63#define AB8500_GPIO_DIR5_REG 0x14
64#define AB8500_GPIO_DIR6_REG 0x15
65#define AB9540_GPIO_DIR7_REG 0x16
66
67#define AB8500_GPIO_OUT1_REG 0x20
68#define AB8500_GPIO_OUT2_REG 0x21
69#define AB8500_GPIO_OUT3_REG 0x22
70#define AB8500_GPIO_OUT4_REG 0x23
71#define AB8500_GPIO_OUT5_REG 0x24
72#define AB8500_GPIO_OUT6_REG 0x25
73#define AB9540_GPIO_OUT7_REG 0x26
74
75#define AB8500_GPIO_PUD1_REG 0x30
76#define AB8500_GPIO_PUD2_REG 0x31
77#define AB8500_GPIO_PUD3_REG 0x32
78#define AB8500_GPIO_PUD4_REG 0x33
79#define AB8500_GPIO_PUD5_REG 0x34
80#define AB8500_GPIO_PUD6_REG 0x35
81#define AB9540_GPIO_PUD7_REG 0x36
82
83#define AB8500_GPIO_IN1_REG 0x40
84#define AB8500_GPIO_IN2_REG 0x41
85#define AB8500_GPIO_IN3_REG 0x42
86#define AB8500_GPIO_IN4_REG 0x43
87#define AB8500_GPIO_IN5_REG 0x44
88#define AB8500_GPIO_IN6_REG 0x45
89#define AB9540_GPIO_IN7_REG 0x46
90#define AB8540_GPIO_VINSEL_REG 0x47
91#define AB8540_GPIO_PULL_UPDOWN_REG 0x48
92#define AB8500_GPIO_ALTFUN_REG 0x50
0493e649
PC		 93#define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
94#define AB8540_GPIO_VINSEL_MASK 0x03
95#define AB8540_GPIOX_VBAT_START 51
96#define AB8540_GPIOX_VBAT_END 54
97
acd260b0
PC		 98#define ABX500_GPIO_INPUT 0
99#define ABX500_GPIO_OUTPUT 1
100
0493e649
PC		 101struct abx500_pinctrl {
102 struct device *dev;
103 struct pinctrl_dev *pctldev;
104 struct abx500_pinctrl_soc_data *soc;
105 struct gpio_chip chip;
106 struct ab8500 *parent;
0493e649
PC		 107 struct abx500_gpio_irq_cluster *irq_cluster;
108 int irq_cluster_size;
0493e649
PC		 109};
110
111/**
112 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
113 * @chip: Member of the structure abx500_pinctrl
114 */
115static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
116{
117 return container_of(chip, struct abx500_pinctrl, chip);
118}
119
120static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
83b423c8 121 unsigned offset, bool *bit)
0493e649
PC		 122{
123 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
124 u8 pos = offset % 8;
125 u8 val;
126 int ret;
127
128 reg += offset / 8;
129 ret = abx500_get_register_interruptible(pct->dev,
130 AB8500_MISC, reg, &val);
131
132 *bit = !!(val & BIT(pos));
133
134 if (ret < 0)
135 dev_err(pct->dev,
9be580af
PC		 136 "%s read reg =%x, offset=%x failed (%d)\n",
137 __func__, reg, offset, ret);
0493e649
PC		 138
139 return ret;
140}
141
142static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
83b423c8 143 unsigned offset, int val)
0493e649
PC		 144{
145 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
146 u8 pos = offset % 8;
147 int ret;
148
149 reg += offset / 8;
150 ret = abx500_mask_and_set_register_interruptible(pct->dev,
49dcf086 151 AB8500_MISC, reg, BIT(pos), val << pos);
0493e649 152 if (ret < 0)
9be580af
PC		 153 dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n",
154 __func__, reg, offset, ret);
83b423c8 155
0493e649
PC		 156 return ret;
157}
83b423c8 158
0493e649
PC		 159/**
160 * abx500_gpio_get() - Get the particular GPIO value
83b423c8
LJ		 161 * @chip: Gpio device
162 * @offset: GPIO number to read
0493e649
PC		 163 */
164static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
165{
166 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
167 bool bit;
d8d4f7f8
PC		 168 bool is_out;
169 u8 gpio_offset = offset - 1;
0493e649
PC		 170 int ret;
171
d8d4f7f8
PC		 172 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
173 gpio_offset, &is_out);
9be580af
PC		 174 if (ret < 0)
175 goto out;
d8d4f7f8
PC		 176
177 if (is_out)
178 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG,
179 gpio_offset, &bit);
180 else
181 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
182 gpio_offset, &bit);
9be580af 183out:
0493e649 184 if (ret < 0) {
9be580af 185 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
0493e649
PC		 186 return ret;
187 }
83b423c8 188
0493e649
PC		 189 return bit;
190}
191
192static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
193{
194 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
195 int ret;
196
197 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
198 if (ret < 0)
9be580af 199 dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
0493e649
PC		 200}
201
d2752ae5
PC		 202static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset,
203 enum abx500_gpio_pull_updown *pull_updown)
0493e649
PC		 204{
205 u8 pos;
d2752ae5 206 u8 val;
0493e649
PC		 207 int ret;
208 struct pullud *pullud;
209
210 if (!pct->soc->pullud) {
211 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
212 __func__);
213 ret = -EPERM;
214 goto out;
215 }
216
217 pullud = pct->soc->pullud;
218
219 if ((offset < pullud->first_pin)
220 || (offset > pullud->last_pin)) {
221 ret = -EINVAL;
222 goto out;
223 }
224
d2752ae5
PC		 225 ret = abx500_get_register_interruptible(pct->dev,
226 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val);
227
228 pos = (offset - pullud->first_pin) << 1;
229 *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK;
230
231out:
232 if (ret < 0)
233 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
234
235 return ret;
236}
237
238static int abx500_set_pull_updown(struct abx500_pinctrl *pct,
239 int offset, enum abx500_gpio_pull_updown val)
240{
241 u8 pos;
242 int ret;
243 struct pullud *pullud;
244
245 if (!pct->soc->pullud) {
246 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
247 __func__);
248 ret = -EPERM;
249 goto out;
250 }
251
252 pullud = pct->soc->pullud;
253
254 if ((offset < pullud->first_pin)
255 || (offset > pullud->last_pin)) {
256 ret = -EINVAL;
257 goto out;
258 }
10a8be54 259 pos = (offset - pullud->first_pin) << 1;
0493e649
PC		 260
261 ret = abx500_mask_and_set_register_interruptible(pct->dev,
262 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
263 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
264
265out:
266 if (ret < 0)
267 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 268
0493e649
PC		 269 return ret;
270}
271
8b5abd18
PC		 272static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio)
273{
274 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
275 struct pullud *pullud = pct->soc->pullud;
276
277 return (pullud &&
278 gpio >= pullud->first_pin &&
279 gpio <= pullud->last_pin);
280}
281
0493e649
PC		 282static int abx500_gpio_direction_output(struct gpio_chip *chip,
283 unsigned offset,
284 int val)
285{
286 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
0493e649
PC		 287 unsigned gpio;
288 int ret;
83b423c8 289
0493e649 290 /* set direction as output */
acd260b0
PC		 291 ret = abx500_gpio_set_bits(chip,
292 AB8500_GPIO_DIR1_REG,
293 offset,
294 ABX500_GPIO_OUTPUT);
0493e649 295 if (ret < 0)
9be580af 296 goto out;
0493e649
PC		 297
298 /* disable pull down */
acd260b0
PC		 299 ret = abx500_gpio_set_bits(chip,
300 AB8500_GPIO_PUD1_REG,
301 offset,
302 ABX500_GPIO_PULL_NONE);
0493e649 303 if (ret < 0)
9be580af 304 goto out;
0493e649
PC		 305
306 /* if supported, disable both pull down and pull up */
307 gpio = offset + 1;
8b5abd18 308 if (abx500_pullud_supported(chip, gpio)) {
d2752ae5 309 ret = abx500_set_pull_updown(pct,
0493e649
PC		 310 gpio,
311 ABX500_GPIO_PULL_NONE);
9be580af
PC		 312 }
313out:
314 if (ret < 0) {
315 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
316 return ret;
0493e649 317 }
83b423c8 318
0493e649
PC		 319 /* set the output as 1 or 0 */
320 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
321}
322
323static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
324{
325 /* set the register as input */
acd260b0
PC		 326 return abx500_gpio_set_bits(chip,
327 AB8500_GPIO_DIR1_REG,
328 offset,
329 ABX500_GPIO_INPUT);
0493e649
PC		 330}
331
332static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
333{
334 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
b9fab6e4
LJ		 335 /* The AB8500 GPIO numbers are off by one */
336 int gpio = offset + 1;
a6a16d27 337 int hwirq;
0493e649
PC		 338 int i;
339
340 for (i = 0; i < pct->irq_cluster_size; i++) {
341 struct abx500_gpio_irq_cluster *cluster =
342 &pct->irq_cluster[i];
343
a6a16d27
LJ		 344 if (gpio >= cluster->start && gpio <= cluster->end) {
345 /*
346 * The ABx500 GPIO's associated IRQs are clustered together
347 * throughout the interrupt numbers at irregular intervals.
348 * To solve this quandry, we have placed the read-in values
349 * into the cluster information table.
350 */
43a255db 351 hwirq = gpio - cluster->start + cluster->to_irq;
a6a16d27
LJ		 352 return irq_create_mapping(pct->parent->domain, hwirq);
353 }
0493e649
PC		 354 }
355
356 return -EINVAL;
357}
358
359static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 360 unsigned gpio, int alt_setting)
0493e649
PC		 361{
362 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
363 struct alternate_functions af = pct->soc->alternate_functions[gpio];
364 int ret;
365 int val;
366 unsigned offset;
83b423c8 367
0493e649
PC		 368 const char *modes[] = {
369 [ABX500_DEFAULT] = "default",
370 [ABX500_ALT_A] = "altA",
371 [ABX500_ALT_B] = "altB",
372 [ABX500_ALT_C] = "altC",
373 };
374
375 /* sanity check */
376 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
377 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
378 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
379 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
380 modes[alt_setting]);
381 return -EINVAL;
382 }
383
384 /* on ABx5xx, there is no GPIO0, so adjust the offset */
385 offset = gpio - 1;
83b423c8 386
0493e649
PC		 387 switch (alt_setting) {
388 case ABX500_DEFAULT:
389 /*
390 * for ABx5xx family, default mode is always selected by
391 * writing 0 to GPIOSELx register, except for pins which
392 * support at least ALT_B mode, default mode is selected
393 * by writing 1 to GPIOSELx register
394 */
395 val = 0;
396 if (af.alt_bit1 != UNUSED)
397 val++;
398
399 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
400 offset, val);
401 break;
83b423c8 402
0493e649
PC		 403 case ABX500_ALT_A:
404 /*
405 * for ABx5xx family, alt_a mode is always selected by
406 * writing 1 to GPIOSELx register, except for pins which
407 * support at least ALT_B mode, alt_a mode is selected
408 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
409 * register
410 */
411 if (af.alt_bit1 != UNUSED) {
412 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
413 offset, 0);
9be580af
PC		 414 if (ret < 0)
415 goto out;
416
0493e649
PC		 417 ret = abx500_gpio_set_bits(chip,
418 AB8500_GPIO_ALTFUN_REG,
419 af.alt_bit1,
c590854d 420 !!(af.alta_val & BIT(0)));
9be580af
PC		 421 if (ret < 0)
422 goto out;
423
0493e649
PC		 424 if (af.alt_bit2 != UNUSED)
425 ret = abx500_gpio_set_bits(chip,
426 AB8500_GPIO_ALTFUN_REG,
427 af.alt_bit2,
6da33dbd 428 !!(af.alta_val & BIT(1)));
0493e649
PC		 429 } else
430 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
431 offset, 1);
432 break;
83b423c8 433
0493e649
PC		 434 case ABX500_ALT_B:
435 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
436 offset, 0);
9be580af
PC		 437 if (ret < 0)
438 goto out;
439
0493e649 440 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
c590854d 441 af.alt_bit1, !!(af.altb_val & BIT(0)));
9be580af
PC		 442 if (ret < 0)
443 goto out;
444
0493e649
PC		 445 if (af.alt_bit2 != UNUSED)
446 ret = abx500_gpio_set_bits(chip,
447 AB8500_GPIO_ALTFUN_REG,
448 af.alt_bit2,
6da33dbd 449 !!(af.altb_val & BIT(1)));
0493e649 450 break;
83b423c8 451
0493e649
PC		 452 case ABX500_ALT_C:
453 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
454 offset, 0);
9be580af
PC		 455 if (ret < 0)
456 goto out;
457
0493e649 458 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
6da33dbd 459 af.alt_bit2, !!(af.altc_val & BIT(0)));
9be580af
PC		 460 if (ret < 0)
461 goto out;
462
0493e649 463 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
c590854d 464 af.alt_bit2, !!(af.altc_val & BIT(1)));
0493e649
PC		 465 break;
466
467 default:
468 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
83b423c8 469
0493e649
PC		 470 return -EINVAL;
471 }
9be580af
PC		 472out:
473 if (ret < 0)
474 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 475
0493e649
PC		 476 return ret;
477}
478
9be580af 479static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
83b423c8 480 unsigned gpio)
0493e649
PC		 481{
482 u8 mode;
483 bool bit_mode;
484 bool alt_bit1;
485 bool alt_bit2;
486 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
487 struct alternate_functions af = pct->soc->alternate_functions[gpio];
a950cb74
LW		 488 /* on ABx5xx, there is no GPIO0, so adjust the offset */
489 unsigned offset = gpio - 1;
9be580af 490 int ret;
0493e649
PC		 491
492 /*
493 * if gpiosel_bit is set to unused,
494 * it means no GPIO or special case
495 */
496 if (af.gpiosel_bit == UNUSED)
497 return ABX500_DEFAULT;
498
499 /* read GpioSelx register */
9be580af 500 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
0493e649 501 af.gpiosel_bit, &bit_mode);
9be580af
PC		 502 if (ret < 0)
503 goto out;
504
0493e649
PC		 505 mode = bit_mode;
506
507 /* sanity check */
508 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
509 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
510 dev_err(pct->dev,
511 "alt_bitX value not in correct range (-1 to 7)\n");
512 return -EINVAL;
513 }
83b423c8 514
0493e649
PC		 515 /* if alt_bit2 is used, alt_bit1 must be used too */
516 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
517 dev_err(pct->dev,
518 "if alt_bit2 is used, alt_bit1 can't be unused\n");
519 return -EINVAL;
520 }
521
522 /* check if pin use AlternateFunction register */
6a40cdd5 523 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
0493e649
PC		 524 return mode;
525 /*
526 * if pin GPIOSEL bit is set and pin supports alternate function,
527 * it means DEFAULT mode
528 */
529 if (mode)
530 return ABX500_DEFAULT;
83b423c8 531
0493e649
PC		 532 /*
533 * pin use the AlternatFunction register
534 * read alt_bit1 value
535 */
9be580af 536 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
0493e649 537 af.alt_bit1, &alt_bit1);
9be580af
PC		 538 if (ret < 0)
539 goto out;
0493e649 540
9be580af 541 if (af.alt_bit2 != UNUSED) {
0493e649 542 /* read alt_bit2 value */
9be580af
PC		 543 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
544 af.alt_bit2,
0493e649 545 &alt_bit2);
9be580af
PC		 546 if (ret < 0)
547 goto out;
548 } else
0493e649
PC		 549 alt_bit2 = 0;
550
551 mode = (alt_bit2 << 1) + alt_bit1;
552 if (mode == af.alta_val)
553 return ABX500_ALT_A;
554 else if (mode == af.altb_val)
555 return ABX500_ALT_B;
556 else
557 return ABX500_ALT_C;
9be580af
PC		 558
559out:
560 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
561 return ret;
0493e649
PC		 562}
563
564#ifdef CONFIG_DEBUG_FS
565
566#include <linux/seq_file.h>
567
568static void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 569 struct pinctrl_dev *pctldev,
570 struct gpio_chip *chip,
571 unsigned offset, unsigned gpio)
0493e649 572{
d2752ae5 573 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 574 const char *label = gpiochip_is_requested(chip, offset - 1);
575 u8 gpio_offset = offset - 1;
576 int mode = -1;
577 bool is_out;
d2752ae5 578 bool pd;
ce06f407 579 enum abx500_gpio_pull_updown pud = 0;
9be580af 580 int ret;
83b423c8 581
0493e649
PC		 582 const char *modes[] = {
583 [ABX500_DEFAULT] = "default",
584 [ABX500_ALT_A] = "altA",
585 [ABX500_ALT_B] = "altB",
586 [ABX500_ALT_C] = "altC",
587 };
588
d2752ae5
PC		 589 const char *pull_up_down[] = {
590 [ABX500_GPIO_PULL_DOWN] = "pull down",
591 [ABX500_GPIO_PULL_NONE] = "pull none",
592 [ABX500_GPIO_PULL_NONE + 1] = "pull none",
593 [ABX500_GPIO_PULL_UP] = "pull up",
594 };
595
9be580af
PC		 596 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG,
597 gpio_offset, &is_out);
598 if (ret < 0)
599 goto out;
d2752ae5
PC		 600
601 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s",
602 gpio, label ?: "(none)",
603 is_out ? "out" : "in ");
604
605 if (!is_out) {
8b5abd18 606 if (abx500_pullud_supported(chip, offset)) {
9be580af
PC		 607 ret = abx500_get_pull_updown(pct, offset, &pud);
608 if (ret < 0)
609 goto out;
610
d2752ae5
PC		 611 seq_printf(s, " %-9s", pull_up_down[pud]);
612 } else {
9be580af
PC		 613 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG,
614 gpio_offset, &pd);
615 if (ret < 0)
616 goto out;
617
d2752ae5
PC		 618 seq_printf(s, " %-9s", pull_up_down[pd]);
619 }
620 } else
621 seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
0493e649
PC		 622
623 if (pctldev)
624 mode = abx500_get_mode(pctldev, chip, offset);
625
d2752ae5 626 seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]);
9be580af
PC		 627
628out:
629 if (ret < 0)
630 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
0493e649
PC		 631}
632
633static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
634{
635 unsigned i;
636 unsigned gpio = chip->base;
637 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
638 struct pinctrl_dev *pctldev = pct->pctldev;
639
640 for (i = 0; i < chip->ngpio; i++, gpio++) {
641 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
642 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
643 seq_printf(s, "\n");
644 }
645}
646
647#else
648static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
83b423c8
LJ		 649 struct pinctrl_dev *pctldev,
650 struct gpio_chip *chip,
651 unsigned offset, unsigned gpio)
0493e649
PC		 652{
653}
654#define abx500_gpio_dbg_show NULL
655#endif
656
9c4154ef 657static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
0493e649
PC		 658{
659 int gpio = chip->base + offset;
660
661 return pinctrl_request_gpio(gpio);
662}
663
9c4154ef 664static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
0493e649
PC		 665{
666 int gpio = chip->base + offset;
667
668 pinctrl_free_gpio(gpio);
669}
670
671static struct gpio_chip abx500gpio_chip = {
672 .label = "abx500-gpio",
673 .owner = THIS_MODULE,
674 .request = abx500_gpio_request,
675 .free = abx500_gpio_free,
676 .direction_input = abx500_gpio_direction_input,
677 .get = abx500_gpio_get,
678 .direction_output = abx500_gpio_direction_output,
679 .set = abx500_gpio_set,
680 .to_irq = abx500_gpio_to_irq,
681 .dbg_show = abx500_gpio_dbg_show,
682};
683
0493e649
PC		 684static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
685{
686 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
687
688 return pct->soc->nfunctions;
689}
690
691static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
692 unsigned function)
693{
694 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
695
696 return pct->soc->functions[function].name;
697}
698
699static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
83b423c8
LJ		 700 unsigned function,
701 const char * const **groups,
702 unsigned * const num_groups)
0493e649
PC		 703{
704 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
705
706 *groups = pct->soc->functions[function].groups;
707 *num_groups = pct->soc->functions[function].ngroups;
708
709 return 0;
710}
711
0493e649 712static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
83b423c8 713 unsigned group)
0493e649
PC		 714{
715 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
716 struct gpio_chip *chip = &pct->chip;
717 const struct abx500_pingroup *g;
718 int i;
719 int ret = 0;
720
721 g = &pct->soc->groups[group];
722 if (g->altsetting < 0)
723 return -EINVAL;
724
725 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
726
727 for (i = 0; i < g->npins; i++) {
728 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
729 g->pins[i], g->altsetting);
730
0493e649
PC		 731 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
732 }
83b423c8 733
9be580af
PC		 734 if (ret < 0)
735 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
736
0493e649
PC		 737 return ret;
738}
739
9c4154ef 740static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
83b423c8
LJ		 741 struct pinctrl_gpio_range *range,
742 unsigned offset)
0493e649
PC		 743{
744 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
745 const struct abx500_pinrange *p;
746 int ret;
747 int i;
748
749 /*
750 * Different ranges have different ways to enable GPIO function on a
751 * pin, so refer back to our local range type, where we handily define
752 * what altfunc enables GPIO for a certain pin.
753 */
754 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
755 p = &pct->soc->gpio_ranges[i];
756 if ((offset >= p->offset) &&
757 (offset < (p->offset + p->npins)))
758 break;
759 }
760
761 if (i == pct->soc->gpio_num_ranges) {
762 dev_err(pct->dev, "%s failed to locate range\n", __func__);
763 return -ENODEV;
764 }
765
766 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
767 p->altfunc, offset);
768
769 ret = abx500_set_mode(pct->pctldev, &pct->chip,
770 offset, p->altfunc);
9be580af 771 if (ret < 0)
0493e649 772 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
0493e649
PC		 773
774 return ret;
775}
776
777static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
83b423c8
LJ		 778 struct pinctrl_gpio_range *range,
779 unsigned offset)
0493e649
PC		 780{
781}
782
022ab148 783static const struct pinmux_ops abx500_pinmux_ops = {
0493e649
PC		 784 .get_functions_count = abx500_pmx_get_funcs_cnt,
785 .get_function_name = abx500_pmx_get_func_name,
786 .get_function_groups = abx500_pmx_get_func_groups,
787 .enable = abx500_pmx_enable,
0493e649
PC		 788 .gpio_request_enable = abx500_gpio_request_enable,
789 .gpio_disable_free = abx500_gpio_disable_free,
790};
791
792static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
793{
794 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
795
796 return pct->soc->ngroups;
797}
798
799static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
83b423c8 800 unsigned selector)
0493e649
PC		 801{
802 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
803
804 return pct->soc->groups[selector].name;
805}
806
807static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
83b423c8
LJ		 808 unsigned selector,
809 const unsigned **pins,
810 unsigned *num_pins)
0493e649
PC		 811{
812 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
813
814 *pins = pct->soc->groups[selector].pins;
815 *num_pins = pct->soc->groups[selector].npins;
83b423c8 816
0493e649
PC		 817 return 0;
818}
819
820static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
83b423c8 821 struct seq_file *s, unsigned offset)
0493e649
PC		 822{
823 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
824 struct gpio_chip *chip = &pct->chip;
825
826 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
827 chip->base + offset - 1);
828}
829
64a45c98
PC		 830static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
831 struct pinctrl_map *map, unsigned num_maps)
832{
833 int i;
834
835 for (i = 0; i < num_maps; i++)
836 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
837 kfree(map[i].data.configs.configs);
838 kfree(map);
839}
840
841static int abx500_dt_reserve_map(struct pinctrl_map **map,
842 unsigned *reserved_maps,
843 unsigned *num_maps,
844 unsigned reserve)
845{
846 unsigned old_num = *reserved_maps;
847 unsigned new_num = *num_maps + reserve;
848 struct pinctrl_map *new_map;
849
850 if (old_num >= new_num)
851 return 0;
852
853 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
854 if (!new_map)
855 return -ENOMEM;
856
857 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
858
859 *map = new_map;
860 *reserved_maps = new_num;
861
862 return 0;
863}
864
865static int abx500_dt_add_map_mux(struct pinctrl_map **map,
866 unsigned *reserved_maps,
867 unsigned *num_maps, const char *group,
868 const char *function)
869{
870 if (*num_maps == *reserved_maps)
871 return -ENOSPC;
872
873 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
874 (*map)[*num_maps].data.mux.group = group;
875 (*map)[*num_maps].data.mux.function = function;
876 (*num_maps)++;
877
878 return 0;
879}
880
881static int abx500_dt_add_map_configs(struct pinctrl_map **map,
882 unsigned *reserved_maps,
883 unsigned *num_maps, const char *group,
884 unsigned long *configs, unsigned num_configs)
885{
886 unsigned long *dup_configs;
887
888 if (*num_maps == *reserved_maps)
889 return -ENOSPC;
890
891 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
892 GFP_KERNEL);
893 if (!dup_configs)
894 return -ENOMEM;
895
896 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
897
898 (*map)[*num_maps].data.configs.group_or_pin = group;
899 (*map)[*num_maps].data.configs.configs = dup_configs;
900 (*map)[*num_maps].data.configs.num_configs = num_configs;
901 (*num_maps)++;
902
903 return 0;
904}
905
906static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev,
907 const char *pin_name)
908{
909 int i, pin_number;
910 struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
911
912 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
913 for (i = 0; i < npct->soc->npins; i++)
914 if (npct->soc->pins[i].number == pin_number)
915 return npct->soc->pins[i].name;
916 return NULL;
917}
918
919static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
920 struct device_node *np,
921 struct pinctrl_map **map,
922 unsigned *reserved_maps,
923 unsigned *num_maps)
924{
925 int ret;
926 const char *function = NULL;
927 unsigned long *configs;
928 unsigned int nconfigs = 0;
929 bool has_config = 0;
930 unsigned reserve = 0;
931 struct property *prop;
932 const char *group, *gpio_name;
933 struct device_node *np_config;
934
935 ret = of_property_read_string(np, "ste,function", &function);
936 if (ret >= 0)
937 reserve = 1;
938
939 ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
940 if (nconfigs)
941 has_config = 1;
942
943 np_config = of_parse_phandle(np, "ste,config", 0);
944 if (np_config) {
945 ret = pinconf_generic_parse_dt_config(np_config, &configs,
946 &nconfigs);
947 if (ret)
948 goto exit;
949 has_config |= nconfigs;
950 }
951
952 ret = of_property_count_strings(np, "ste,pins");
953 if (ret < 0)
954 goto exit;
955
956 if (has_config)
957 reserve++;
958
959 reserve *= ret;
960
961 ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
962 if (ret < 0)
963 goto exit;
964
965 of_property_for_each_string(np, "ste,pins", prop, group) {
966 if (function) {
967 ret = abx500_dt_add_map_mux(map, reserved_maps,
968 num_maps, group, function);
969 if (ret < 0)
970 goto exit;
971 }
972 if (has_config) {
973 gpio_name = abx500_find_pin_name(pctldev, group);
974
975 ret = abx500_dt_add_map_configs(map, reserved_maps,
976 num_maps, gpio_name, configs, 1);
977 if (ret < 0)
978 goto exit;
979 }
980
981 }
982exit:
983 return ret;
984}
985
986static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
987 struct device_node *np_config,
988 struct pinctrl_map **map, unsigned *num_maps)
989{
990 unsigned reserved_maps;
991 struct device_node *np;
992 int ret;
993
994 reserved_maps = 0;
995 *map = NULL;
996 *num_maps = 0;
997
998 for_each_child_of_node(np_config, np) {
999 ret = abx500_dt_subnode_to_map(pctldev, np, map,
1000 &reserved_maps, num_maps);
1001 if (ret < 0) {
1002 abx500_dt_free_map(pctldev, *map, *num_maps);
1003 return ret;
1004 }
1005 }
1006
1007 return 0;
1008}
1009
022ab148 1010static const struct pinctrl_ops abx500_pinctrl_ops = {
0493e649
PC		 1011 .get_groups_count = abx500_get_groups_cnt,
1012 .get_group_name = abx500_get_group_name,
1013 .get_group_pins = abx500_get_group_pins,
1014 .pin_dbg_show = abx500_pin_dbg_show,
64a45c98
PC		 1015 .dt_node_to_map = abx500_dt_node_to_map,
1016 .dt_free_map = abx500_dt_free_map,
0493e649
PC		 1017};
1018
9c4154ef 1019static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
83b423c8
LJ		 1020 unsigned pin,
1021 unsigned long *config)
0493e649 1022{
1abeebea 1023 return -ENOSYS;
0493e649
PC		 1024}
1025
9c4154ef 1026static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
83b423c8 1027 unsigned pin,
03b054e9
SY		 1028 unsigned long *configs,
1029 unsigned num_configs)
0493e649
PC		 1030{
1031 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
0493e649
PC		 1032 struct gpio_chip *chip = &pct->chip;
1033 unsigned offset;
61ce1356 1034 int ret = -EINVAL;
03b054e9
SY		 1035 int i;
1036 enum pin_config_param param;
1037 enum pin_config_param argument;
1038
1039 for (i = 0; i < num_configs; i++) {
1040 param = pinconf_to_config_param(configs[i]);
1041 argument = pinconf_to_config_argument(configs[i]);
1042
1043 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
1044 pin, configs[i],
1045 (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
1046 (param == PIN_CONFIG_OUTPUT) ?
1047 (argument ? "high" : "low") :
1048 (argument ? "pull up" : "pull down"));
1049
1050 /* on ABx500, there is no GPIO0, so adjust the offset */
1051 offset = pin - 1;
1052
1053 switch (param) {
1054 case PIN_CONFIG_BIAS_DISABLE:
1055 ret = abx500_gpio_direction_input(chip, offset);
1056 if (ret < 0)
1057 goto out;
1058 /*
1059 * Some chips only support pull down, while some
1060 * actually support both pull up and pull down. Such
1061 * chips have a "pullud" range specified for the pins
1062 * that support both features. If the pin is not
1063 * within that range, we fall back to the old bit set
1064 * that only support pull down.
1065 */
1066 if (abx500_pullud_supported(chip, pin))
1067 ret = abx500_set_pull_updown(pct,
1068 pin,
1069 ABX500_GPIO_PULL_NONE);
1070 else
1071 /* Chip only supports pull down */
1072 ret = abx500_gpio_set_bits(chip,
1073 AB8500_GPIO_PUD1_REG, offset,
1074 ABX500_GPIO_PULL_NONE);
1075 break;
9ed3cd33 1076
03b054e9
SY		 1077 case PIN_CONFIG_BIAS_PULL_DOWN:
1078 ret = abx500_gpio_direction_input(chip, offset);
1079 if (ret < 0)
1080 goto out;
1081 /*
1082 * if argument = 1 set the pull down
1083 * else clear the pull down
1084 * Some chips only support pull down, while some
1085 * actually support both pull up and pull down. Such
1086 * chips have a "pullud" range specified for the pins
1087 * that support both features. If the pin is not
1088 * within that range, we fall back to the old bit set
1089 * that only support pull down.
1090 */
1091 if (abx500_pullud_supported(chip, pin))
1092 ret = abx500_set_pull_updown(pct,
1093 pin,
1094 argument ? ABX500_GPIO_PULL_DOWN :
1095 ABX500_GPIO_PULL_NONE);
1096 else
1097 /* Chip only supports pull down */
1098 ret = abx500_gpio_set_bits(chip,
1099 AB8500_GPIO_PUD1_REG,
1100 offset,
1101 argument ? ABX500_GPIO_PULL_DOWN :
1102 ABX500_GPIO_PULL_NONE);
1103 break;
83b423c8 1104
03b054e9
SY		 1105 case PIN_CONFIG_BIAS_PULL_UP:
1106 ret = abx500_gpio_direction_input(chip, offset);
1107 if (ret < 0)
1108 goto out;
1109 /*
1110 * if argument = 1 set the pull up
1111 * else clear the pull up
1112 */
1113 ret = abx500_gpio_direction_input(chip, offset);
1114 /*
1115 * Some chips only support pull down, while some
1116 * actually support both pull up and pull down. Such
1117 * chips have a "pullud" range specified for the pins
1118 * that support both features. If the pin is not
1119 * within that range, do nothing
1120 */
1121 if (abx500_pullud_supported(chip, pin))
1122 ret = abx500_set_pull_updown(pct,
1123 pin,
1124 argument ? ABX500_GPIO_PULL_UP :
1125 ABX500_GPIO_PULL_NONE);
1126 break;
1127
1128 case PIN_CONFIG_OUTPUT:
1129 ret = abx500_gpio_direction_output(chip, offset,
1130 argument);
1131 break;
1132
1133 default:
1134 dev_err(chip->dev, "illegal configuration requested\n");
1135 }
1136 } /* for each config */
9be580af
PC		 1137out:
1138 if (ret < 0)
1139 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
83b423c8 1140
0493e649
PC		 1141 return ret;
1142}
1143
022ab148 1144static const struct pinconf_ops abx500_pinconf_ops = {
0493e649
PC		 1145 .pin_config_get = abx500_pin_config_get,
1146 .pin_config_set = abx500_pin_config_set,
1147};
1148
1149static struct pinctrl_desc abx500_pinctrl_desc = {
1150 .name = "pinctrl-abx500",
1151 .pctlops = &abx500_pinctrl_ops,
1152 .pmxops = &abx500_pinmux_ops,
1153 .confops = &abx500_pinconf_ops,
1154 .owner = THIS_MODULE,
1155};
1156
1157static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
1158{
1159 unsigned int lowest = 0;
1160 unsigned int highest = 0;
1161 unsigned int npins = 0;
1162 int i;
1163
1164 /*
1165 * Compute number of GPIOs from the last SoC gpio range descriptors
1166 * These ranges may include "holes" but the GPIO number space shall
1167 * still be homogeneous, so we need to detect and account for any
1168 * such holes so that these are included in the number of GPIO pins.
1169 */
1170 for (i = 0; i < soc->gpio_num_ranges; i++) {
1171 unsigned gstart;
1172 unsigned gend;
1173 const struct abx500_pinrange *p;
1174
1175 p = &soc->gpio_ranges[i];
1176 gstart = p->offset;
1177 gend = p->offset + p->npins - 1;
1178
1179 if (i == 0) {
1180 /* First iteration, set start values */
1181 lowest = gstart;
1182 highest = gend;
1183 } else {
1184 if (gstart < lowest)
1185 lowest = gstart;
1186 if (gend > highest)
1187 highest = gend;
1188 }
1189 }
1190 /* this gives the absolute number of pins */
1191 npins = highest - lowest + 1;
1192 return npins;
1193}
1194
f30a3839
LJ		 1195static const struct of_device_id abx500_gpio_match[] = {
1196 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
1197 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
1198 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
1199 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
e3929714 1200 { }
f30a3839
LJ		 1201};
1202
0493e649
PC		 1203static int abx500_gpio_probe(struct platform_device *pdev)
1204{
f30a3839 1205 struct device_node *np = pdev->dev.of_node;
ac99a037 1206 const struct of_device_id *match;
0493e649 1207 struct abx500_pinctrl *pct;
f30a3839 1208 unsigned int id = -1;
fa1ec996 1209 int ret, err;
0493e649
PC		 1210 int i;
1211
ac99a037
LW		 1212 if (!np) {
1213 dev_err(&pdev->dev, "gpio dt node missing\n");
86c976e4 1214 return -ENODEV;
0493e649
PC		 1215 }
1216
1217 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
1218 GFP_KERNEL);
1219 if (pct == NULL) {
1220 dev_err(&pdev->dev,
1221 "failed to allocate memory for pct\n");
1222 return -ENOMEM;
1223 }
1224
1225 pct->dev = &pdev->dev;
1226 pct->parent = dev_get_drvdata(pdev->dev.parent);
1227 pct->chip = abx500gpio_chip;
1228 pct->chip.dev = &pdev->dev;
ac99a037 1229 pct->chip.base = -1; /* Dynamic allocation */
86c976e4 1230
ac99a037
LW		 1231 match = of_match_device(abx500_gpio_match, &pdev->dev);
1232 if (!match) {
1233 dev_err(&pdev->dev, "gpio dt not matching\n");
1234 return -ENODEV;
86c976e4 1235 }
ac99a037 1236 id = (unsigned long)match->data;
86c976e4 1237
0493e649 1238 /* Poke in other ASIC variants here */
f30a3839 1239 switch (id) {
3c937993
PC		 1240 case PINCTRL_AB8500:
1241 abx500_pinctrl_ab8500_init(&pct->soc);
1242 break;
a8f96e41
PC		 1243 case PINCTRL_AB8540:
1244 abx500_pinctrl_ab8540_init(&pct->soc);
1245 break;
09dbec3f
PC		 1246 case PINCTRL_AB9540:
1247 abx500_pinctrl_ab9540_init(&pct->soc);
1248 break;
1aa2d8d4
PC		 1249 case PINCTRL_AB8505:
1250 abx500_pinctrl_ab8505_init(&pct->soc);
1251 break;
0493e649 1252 default:
2fcad12e 1253 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
0493e649
PC		 1254 return -EINVAL;
1255 }
1256
1257 if (!pct->soc) {
1258 dev_err(&pdev->dev, "Invalid SOC data\n");
1259 return -EINVAL;
1260 }
1261
1262 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
1263 pct->irq_cluster = pct->soc->gpio_irq_cluster;
1264 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
0493e649 1265
0493e649
PC		 1266 ret = gpiochip_add(&pct->chip);
1267 if (ret) {
83b423c8 1268 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
ac652d79 1269 return ret;
0493e649
PC		 1270 }
1271 dev_info(&pdev->dev, "added gpiochip\n");
1272
1273 abx500_pinctrl_desc.pins = pct->soc->pins;
1274 abx500_pinctrl_desc.npins = pct->soc->npins;
1275 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
1276 if (!pct->pctldev) {
1277 dev_err(&pdev->dev,
1278 "could not register abx500 pinctrl driver\n");
fa1ec996 1279 ret = -EINVAL;
0493e649
PC		 1280 goto out_rem_chip;
1281 }
1282 dev_info(&pdev->dev, "registered pin controller\n");
1283
1284 /* We will handle a range of GPIO pins */
1285 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
1286 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
1287
1288 ret = gpiochip_add_pin_range(&pct->chip,
1289 dev_name(&pdev->dev),
1290 p->offset - 1, p->offset, p->npins);
1291 if (ret < 0)
fa1ec996 1292 goto out_rem_chip;
0493e649
PC		 1293 }
1294
1295 platform_set_drvdata(pdev, pct);
1296 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
1297
1298 return 0;
1299
1300out_rem_chip:
fa1ec996
LJ		 1301 err = gpiochip_remove(&pct->chip);
1302 if (err)
0493e649 1303 dev_info(&pdev->dev, "failed to remove gpiochip\n");
ac652d79 1304
0493e649
PC		 1305 return ret;
1306}
1307
83b423c8 1308/**
0493e649 1309 * abx500_gpio_remove() - remove Ab8500-gpio driver
83b423c8 1310 * @pdev: Platform device registered
0493e649
PC		 1311 */
1312static int abx500_gpio_remove(struct platform_device *pdev)
1313{
1314 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
1315 int ret;
1316
1317 ret = gpiochip_remove(&pct->chip);
1318 if (ret < 0) {
1319 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
1320 ret);
1321 return ret;
1322 }
1323
0493e649
PC		 1324 return 0;
1325}
1326
0493e649
PC		 1327static struct platform_driver abx500_gpio_driver = {
1328 .driver = {
1329 .name = "abx500-gpio",
1330 .owner = THIS_MODULE,
f30a3839 1331 .of_match_table = abx500_gpio_match,
0493e649
PC		 1332 },
1333 .probe = abx500_gpio_probe,
1334 .remove = abx500_gpio_remove,
0493e649
PC		 1335};
1336
1337static int __init abx500_gpio_init(void)
1338{
1339 return platform_driver_register(&abx500_gpio_driver);
1340}
1341core_initcall(abx500_gpio_init);
1342
1343MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1344MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1345MODULE_ALIAS("platform:abx500-gpio");
1346MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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