Commit | Line | Data |
---|---|---|
0493e649 PC |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2013 | |
3 | * | |
4 | * Author: Patrice Chotard <patrice.chotard@st.com> | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/err.h> | |
f30a3839 LJ |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
0493e649 PC |
19 | #include <linux/platform_device.h> |
20 | #include <linux/gpio.h> | |
21 | #include <linux/irq.h> | |
ac652d79 | 22 | #include <linux/irqdomain.h> |
0493e649 PC |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/mfd/abx500.h> | |
26 | #include <linux/mfd/abx500/ab8500.h> | |
0493e649 PC |
27 | #include <linux/pinctrl/pinctrl.h> |
28 | #include <linux/pinctrl/consumer.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
30 | #include <linux/pinctrl/pinconf.h> | |
31 | #include <linux/pinctrl/pinconf-generic.h> | |
64a45c98 | 32 | #include <linux/pinctrl/machine.h> |
0493e649 PC |
33 | |
34 | #include "pinctrl-abx500.h" | |
3a198059 LW |
35 | #include "../core.h" |
36 | #include "../pinconf.h" | |
b07f92a2 | 37 | #include "../pinctrl-utils.h" |
0493e649 PC |
38 | |
39 | /* | |
40 | * The AB9540 and AB8540 GPIO support are extended versions | |
41 | * of the AB8500 GPIO support. | |
42 | * The AB9540 supports an additional (7th) register so that | |
43 | * more GPIO may be configured and used. | |
44 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have | |
45 | * internal pull-up and pull-down capabilities. | |
46 | */ | |
47 | ||
48 | /* | |
49 | * GPIO registers offset | |
50 | * Bank: 0x10 | |
51 | */ | |
52 | #define AB8500_GPIO_SEL1_REG 0x00 | |
53 | #define AB8500_GPIO_SEL2_REG 0x01 | |
54 | #define AB8500_GPIO_SEL3_REG 0x02 | |
55 | #define AB8500_GPIO_SEL4_REG 0x03 | |
56 | #define AB8500_GPIO_SEL5_REG 0x04 | |
57 | #define AB8500_GPIO_SEL6_REG 0x05 | |
58 | #define AB9540_GPIO_SEL7_REG 0x06 | |
59 | ||
60 | #define AB8500_GPIO_DIR1_REG 0x10 | |
61 | #define AB8500_GPIO_DIR2_REG 0x11 | |
62 | #define AB8500_GPIO_DIR3_REG 0x12 | |
63 | #define AB8500_GPIO_DIR4_REG 0x13 | |
64 | #define AB8500_GPIO_DIR5_REG 0x14 | |
65 | #define AB8500_GPIO_DIR6_REG 0x15 | |
66 | #define AB9540_GPIO_DIR7_REG 0x16 | |
67 | ||
68 | #define AB8500_GPIO_OUT1_REG 0x20 | |
69 | #define AB8500_GPIO_OUT2_REG 0x21 | |
70 | #define AB8500_GPIO_OUT3_REG 0x22 | |
71 | #define AB8500_GPIO_OUT4_REG 0x23 | |
72 | #define AB8500_GPIO_OUT5_REG 0x24 | |
73 | #define AB8500_GPIO_OUT6_REG 0x25 | |
74 | #define AB9540_GPIO_OUT7_REG 0x26 | |
75 | ||
76 | #define AB8500_GPIO_PUD1_REG 0x30 | |
77 | #define AB8500_GPIO_PUD2_REG 0x31 | |
78 | #define AB8500_GPIO_PUD3_REG 0x32 | |
79 | #define AB8500_GPIO_PUD4_REG 0x33 | |
80 | #define AB8500_GPIO_PUD5_REG 0x34 | |
81 | #define AB8500_GPIO_PUD6_REG 0x35 | |
82 | #define AB9540_GPIO_PUD7_REG 0x36 | |
83 | ||
84 | #define AB8500_GPIO_IN1_REG 0x40 | |
85 | #define AB8500_GPIO_IN2_REG 0x41 | |
86 | #define AB8500_GPIO_IN3_REG 0x42 | |
87 | #define AB8500_GPIO_IN4_REG 0x43 | |
88 | #define AB8500_GPIO_IN5_REG 0x44 | |
89 | #define AB8500_GPIO_IN6_REG 0x45 | |
90 | #define AB9540_GPIO_IN7_REG 0x46 | |
91 | #define AB8540_GPIO_VINSEL_REG 0x47 | |
92 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 | |
93 | #define AB8500_GPIO_ALTFUN_REG 0x50 | |
0493e649 PC |
94 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 |
95 | #define AB8540_GPIO_VINSEL_MASK 0x03 | |
96 | #define AB8540_GPIOX_VBAT_START 51 | |
97 | #define AB8540_GPIOX_VBAT_END 54 | |
98 | ||
acd260b0 PC |
99 | #define ABX500_GPIO_INPUT 0 |
100 | #define ABX500_GPIO_OUTPUT 1 | |
101 | ||
0493e649 PC |
102 | struct abx500_pinctrl { |
103 | struct device *dev; | |
104 | struct pinctrl_dev *pctldev; | |
105 | struct abx500_pinctrl_soc_data *soc; | |
106 | struct gpio_chip chip; | |
107 | struct ab8500 *parent; | |
0493e649 PC |
108 | struct abx500_gpio_irq_cluster *irq_cluster; |
109 | int irq_cluster_size; | |
0493e649 PC |
110 | }; |
111 | ||
112 | /** | |
113 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl | |
114 | * @chip: Member of the structure abx500_pinctrl | |
115 | */ | |
116 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) | |
117 | { | |
118 | return container_of(chip, struct abx500_pinctrl, chip); | |
119 | } | |
120 | ||
121 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 122 | unsigned offset, bool *bit) |
0493e649 PC |
123 | { |
124 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
125 | u8 pos = offset % 8; | |
126 | u8 val; | |
127 | int ret; | |
128 | ||
129 | reg += offset / 8; | |
130 | ret = abx500_get_register_interruptible(pct->dev, | |
131 | AB8500_MISC, reg, &val); | |
132 | ||
133 | *bit = !!(val & BIT(pos)); | |
134 | ||
135 | if (ret < 0) | |
136 | dev_err(pct->dev, | |
9be580af PC |
137 | "%s read reg =%x, offset=%x failed (%d)\n", |
138 | __func__, reg, offset, ret); | |
0493e649 PC |
139 | |
140 | return ret; | |
141 | } | |
142 | ||
143 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 144 | unsigned offset, int val) |
0493e649 PC |
145 | { |
146 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
147 | u8 pos = offset % 8; | |
148 | int ret; | |
149 | ||
150 | reg += offset / 8; | |
151 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
49dcf086 | 152 | AB8500_MISC, reg, BIT(pos), val << pos); |
0493e649 | 153 | if (ret < 0) |
9be580af PC |
154 | dev_err(pct->dev, "%s write reg, %x offset %x failed (%d)\n", |
155 | __func__, reg, offset, ret); | |
83b423c8 | 156 | |
0493e649 PC |
157 | return ret; |
158 | } | |
83b423c8 | 159 | |
0493e649 PC |
160 | /** |
161 | * abx500_gpio_get() - Get the particular GPIO value | |
83b423c8 LJ |
162 | * @chip: Gpio device |
163 | * @offset: GPIO number to read | |
0493e649 PC |
164 | */ |
165 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) | |
166 | { | |
167 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
168 | bool bit; | |
d8d4f7f8 PC |
169 | bool is_out; |
170 | u8 gpio_offset = offset - 1; | |
0493e649 PC |
171 | int ret; |
172 | ||
d8d4f7f8 PC |
173 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, |
174 | gpio_offset, &is_out); | |
9be580af PC |
175 | if (ret < 0) |
176 | goto out; | |
d8d4f7f8 PC |
177 | |
178 | if (is_out) | |
179 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_OUT1_REG, | |
180 | gpio_offset, &bit); | |
181 | else | |
182 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, | |
183 | gpio_offset, &bit); | |
9be580af | 184 | out: |
0493e649 | 185 | if (ret < 0) { |
9be580af | 186 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); |
0493e649 PC |
187 | return ret; |
188 | } | |
83b423c8 | 189 | |
0493e649 PC |
190 | return bit; |
191 | } | |
192 | ||
193 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
194 | { | |
195 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
196 | int ret; | |
197 | ||
198 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
199 | if (ret < 0) | |
9be580af | 200 | dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret); |
0493e649 PC |
201 | } |
202 | ||
d2752ae5 PC |
203 | static int abx500_get_pull_updown(struct abx500_pinctrl *pct, int offset, |
204 | enum abx500_gpio_pull_updown *pull_updown) | |
0493e649 PC |
205 | { |
206 | u8 pos; | |
d2752ae5 | 207 | u8 val; |
0493e649 PC |
208 | int ret; |
209 | struct pullud *pullud; | |
210 | ||
211 | if (!pct->soc->pullud) { | |
212 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
213 | __func__); | |
214 | ret = -EPERM; | |
215 | goto out; | |
216 | } | |
217 | ||
218 | pullud = pct->soc->pullud; | |
219 | ||
220 | if ((offset < pullud->first_pin) | |
221 | || (offset > pullud->last_pin)) { | |
222 | ret = -EINVAL; | |
223 | goto out; | |
224 | } | |
225 | ||
d2752ae5 PC |
226 | ret = abx500_get_register_interruptible(pct->dev, |
227 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, &val); | |
228 | ||
229 | pos = (offset - pullud->first_pin) << 1; | |
230 | *pull_updown = (val >> pos) & AB8540_GPIO_PULL_UPDOWN_MASK; | |
231 | ||
232 | out: | |
233 | if (ret < 0) | |
234 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
239 | static int abx500_set_pull_updown(struct abx500_pinctrl *pct, | |
240 | int offset, enum abx500_gpio_pull_updown val) | |
241 | { | |
242 | u8 pos; | |
243 | int ret; | |
244 | struct pullud *pullud; | |
245 | ||
246 | if (!pct->soc->pullud) { | |
247 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
248 | __func__); | |
249 | ret = -EPERM; | |
250 | goto out; | |
251 | } | |
252 | ||
253 | pullud = pct->soc->pullud; | |
254 | ||
255 | if ((offset < pullud->first_pin) | |
256 | || (offset > pullud->last_pin)) { | |
257 | ret = -EINVAL; | |
258 | goto out; | |
259 | } | |
10a8be54 | 260 | pos = (offset - pullud->first_pin) << 1; |
0493e649 PC |
261 | |
262 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
263 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, | |
264 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); | |
265 | ||
266 | out: | |
267 | if (ret < 0) | |
268 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 269 | |
0493e649 PC |
270 | return ret; |
271 | } | |
272 | ||
8b5abd18 PC |
273 | static bool abx500_pullud_supported(struct gpio_chip *chip, unsigned gpio) |
274 | { | |
275 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
276 | struct pullud *pullud = pct->soc->pullud; | |
277 | ||
278 | return (pullud && | |
279 | gpio >= pullud->first_pin && | |
280 | gpio <= pullud->last_pin); | |
281 | } | |
282 | ||
0493e649 PC |
283 | static int abx500_gpio_direction_output(struct gpio_chip *chip, |
284 | unsigned offset, | |
285 | int val) | |
286 | { | |
287 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
0493e649 PC |
288 | unsigned gpio; |
289 | int ret; | |
83b423c8 | 290 | |
0493e649 | 291 | /* set direction as output */ |
acd260b0 PC |
292 | ret = abx500_gpio_set_bits(chip, |
293 | AB8500_GPIO_DIR1_REG, | |
294 | offset, | |
295 | ABX500_GPIO_OUTPUT); | |
0493e649 | 296 | if (ret < 0) |
9be580af | 297 | goto out; |
0493e649 PC |
298 | |
299 | /* disable pull down */ | |
acd260b0 PC |
300 | ret = abx500_gpio_set_bits(chip, |
301 | AB8500_GPIO_PUD1_REG, | |
302 | offset, | |
303 | ABX500_GPIO_PULL_NONE); | |
0493e649 | 304 | if (ret < 0) |
9be580af | 305 | goto out; |
0493e649 PC |
306 | |
307 | /* if supported, disable both pull down and pull up */ | |
308 | gpio = offset + 1; | |
8b5abd18 | 309 | if (abx500_pullud_supported(chip, gpio)) { |
d2752ae5 | 310 | ret = abx500_set_pull_updown(pct, |
0493e649 PC |
311 | gpio, |
312 | ABX500_GPIO_PULL_NONE); | |
9be580af PC |
313 | } |
314 | out: | |
315 | if (ret < 0) { | |
316 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
317 | return ret; | |
0493e649 | 318 | } |
83b423c8 | 319 | |
0493e649 PC |
320 | /* set the output as 1 or 0 */ |
321 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
322 | } | |
323 | ||
324 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
325 | { | |
326 | /* set the register as input */ | |
acd260b0 PC |
327 | return abx500_gpio_set_bits(chip, |
328 | AB8500_GPIO_DIR1_REG, | |
329 | offset, | |
330 | ABX500_GPIO_INPUT); | |
0493e649 PC |
331 | } |
332 | ||
333 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
334 | { | |
335 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
b9fab6e4 LJ |
336 | /* The AB8500 GPIO numbers are off by one */ |
337 | int gpio = offset + 1; | |
a6a16d27 | 338 | int hwirq; |
0493e649 PC |
339 | int i; |
340 | ||
341 | for (i = 0; i < pct->irq_cluster_size; i++) { | |
342 | struct abx500_gpio_irq_cluster *cluster = | |
343 | &pct->irq_cluster[i]; | |
344 | ||
a6a16d27 LJ |
345 | if (gpio >= cluster->start && gpio <= cluster->end) { |
346 | /* | |
347 | * The ABx500 GPIO's associated IRQs are clustered together | |
348 | * throughout the interrupt numbers at irregular intervals. | |
349 | * To solve this quandry, we have placed the read-in values | |
350 | * into the cluster information table. | |
351 | */ | |
43a255db | 352 | hwirq = gpio - cluster->start + cluster->to_irq; |
a6a16d27 LJ |
353 | return irq_create_mapping(pct->parent->domain, hwirq); |
354 | } | |
0493e649 PC |
355 | } |
356 | ||
357 | return -EINVAL; | |
358 | } | |
359 | ||
360 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 361 | unsigned gpio, int alt_setting) |
0493e649 PC |
362 | { |
363 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
364 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
365 | int ret; | |
366 | int val; | |
367 | unsigned offset; | |
83b423c8 | 368 | |
0493e649 PC |
369 | const char *modes[] = { |
370 | [ABX500_DEFAULT] = "default", | |
371 | [ABX500_ALT_A] = "altA", | |
372 | [ABX500_ALT_B] = "altB", | |
373 | [ABX500_ALT_C] = "altC", | |
374 | }; | |
375 | ||
376 | /* sanity check */ | |
377 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || | |
378 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || | |
379 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { | |
380 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, | |
381 | modes[alt_setting]); | |
382 | return -EINVAL; | |
383 | } | |
384 | ||
385 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ | |
386 | offset = gpio - 1; | |
83b423c8 | 387 | |
0493e649 PC |
388 | switch (alt_setting) { |
389 | case ABX500_DEFAULT: | |
390 | /* | |
391 | * for ABx5xx family, default mode is always selected by | |
392 | * writing 0 to GPIOSELx register, except for pins which | |
393 | * support at least ALT_B mode, default mode is selected | |
394 | * by writing 1 to GPIOSELx register | |
395 | */ | |
396 | val = 0; | |
397 | if (af.alt_bit1 != UNUSED) | |
398 | val++; | |
399 | ||
400 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
401 | offset, val); | |
402 | break; | |
83b423c8 | 403 | |
0493e649 PC |
404 | case ABX500_ALT_A: |
405 | /* | |
406 | * for ABx5xx family, alt_a mode is always selected by | |
407 | * writing 1 to GPIOSELx register, except for pins which | |
408 | * support at least ALT_B mode, alt_a mode is selected | |
409 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC | |
410 | * register | |
411 | */ | |
412 | if (af.alt_bit1 != UNUSED) { | |
413 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
414 | offset, 0); | |
9be580af PC |
415 | if (ret < 0) |
416 | goto out; | |
417 | ||
0493e649 PC |
418 | ret = abx500_gpio_set_bits(chip, |
419 | AB8500_GPIO_ALTFUN_REG, | |
420 | af.alt_bit1, | |
c590854d | 421 | !!(af.alta_val & BIT(0))); |
9be580af PC |
422 | if (ret < 0) |
423 | goto out; | |
424 | ||
0493e649 PC |
425 | if (af.alt_bit2 != UNUSED) |
426 | ret = abx500_gpio_set_bits(chip, | |
427 | AB8500_GPIO_ALTFUN_REG, | |
428 | af.alt_bit2, | |
6da33dbd | 429 | !!(af.alta_val & BIT(1))); |
0493e649 PC |
430 | } else |
431 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
432 | offset, 1); | |
433 | break; | |
83b423c8 | 434 | |
0493e649 PC |
435 | case ABX500_ALT_B: |
436 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
437 | offset, 0); | |
9be580af PC |
438 | if (ret < 0) |
439 | goto out; | |
440 | ||
0493e649 | 441 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
c590854d | 442 | af.alt_bit1, !!(af.altb_val & BIT(0))); |
9be580af PC |
443 | if (ret < 0) |
444 | goto out; | |
445 | ||
0493e649 PC |
446 | if (af.alt_bit2 != UNUSED) |
447 | ret = abx500_gpio_set_bits(chip, | |
448 | AB8500_GPIO_ALTFUN_REG, | |
449 | af.alt_bit2, | |
6da33dbd | 450 | !!(af.altb_val & BIT(1))); |
0493e649 | 451 | break; |
83b423c8 | 452 | |
0493e649 PC |
453 | case ABX500_ALT_C: |
454 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
455 | offset, 0); | |
9be580af PC |
456 | if (ret < 0) |
457 | goto out; | |
458 | ||
0493e649 | 459 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
6da33dbd | 460 | af.alt_bit2, !!(af.altc_val & BIT(0))); |
9be580af PC |
461 | if (ret < 0) |
462 | goto out; | |
463 | ||
0493e649 | 464 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, |
c590854d | 465 | af.alt_bit2, !!(af.altc_val & BIT(1))); |
0493e649 PC |
466 | break; |
467 | ||
468 | default: | |
469 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); | |
83b423c8 | 470 | |
0493e649 PC |
471 | return -EINVAL; |
472 | } | |
9be580af PC |
473 | out: |
474 | if (ret < 0) | |
475 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 476 | |
0493e649 PC |
477 | return ret; |
478 | } | |
479 | ||
9be580af | 480 | static int abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, |
83b423c8 | 481 | unsigned gpio) |
0493e649 PC |
482 | { |
483 | u8 mode; | |
484 | bool bit_mode; | |
485 | bool alt_bit1; | |
486 | bool alt_bit2; | |
487 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
488 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
a950cb74 LW |
489 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
490 | unsigned offset = gpio - 1; | |
9be580af | 491 | int ret; |
0493e649 PC |
492 | |
493 | /* | |
494 | * if gpiosel_bit is set to unused, | |
495 | * it means no GPIO or special case | |
496 | */ | |
497 | if (af.gpiosel_bit == UNUSED) | |
498 | return ABX500_DEFAULT; | |
499 | ||
500 | /* read GpioSelx register */ | |
9be580af | 501 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), |
0493e649 | 502 | af.gpiosel_bit, &bit_mode); |
9be580af PC |
503 | if (ret < 0) |
504 | goto out; | |
505 | ||
0493e649 PC |
506 | mode = bit_mode; |
507 | ||
508 | /* sanity check */ | |
509 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || | |
510 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { | |
511 | dev_err(pct->dev, | |
512 | "alt_bitX value not in correct range (-1 to 7)\n"); | |
513 | return -EINVAL; | |
514 | } | |
83b423c8 | 515 | |
0493e649 PC |
516 | /* if alt_bit2 is used, alt_bit1 must be used too */ |
517 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { | |
518 | dev_err(pct->dev, | |
519 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); | |
520 | return -EINVAL; | |
521 | } | |
522 | ||
523 | /* check if pin use AlternateFunction register */ | |
6a40cdd5 | 524 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) |
0493e649 PC |
525 | return mode; |
526 | /* | |
527 | * if pin GPIOSEL bit is set and pin supports alternate function, | |
528 | * it means DEFAULT mode | |
529 | */ | |
530 | if (mode) | |
531 | return ABX500_DEFAULT; | |
83b423c8 | 532 | |
0493e649 PC |
533 | /* |
534 | * pin use the AlternatFunction register | |
535 | * read alt_bit1 value | |
536 | */ | |
9be580af | 537 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, |
0493e649 | 538 | af.alt_bit1, &alt_bit1); |
9be580af PC |
539 | if (ret < 0) |
540 | goto out; | |
0493e649 | 541 | |
9be580af | 542 | if (af.alt_bit2 != UNUSED) { |
0493e649 | 543 | /* read alt_bit2 value */ |
9be580af PC |
544 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, |
545 | af.alt_bit2, | |
0493e649 | 546 | &alt_bit2); |
9be580af PC |
547 | if (ret < 0) |
548 | goto out; | |
549 | } else | |
0493e649 PC |
550 | alt_bit2 = 0; |
551 | ||
552 | mode = (alt_bit2 << 1) + alt_bit1; | |
553 | if (mode == af.alta_val) | |
554 | return ABX500_ALT_A; | |
555 | else if (mode == af.altb_val) | |
556 | return ABX500_ALT_B; | |
557 | else | |
558 | return ABX500_ALT_C; | |
9be580af PC |
559 | |
560 | out: | |
561 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
562 | return ret; | |
0493e649 PC |
563 | } |
564 | ||
565 | #ifdef CONFIG_DEBUG_FS | |
566 | ||
567 | #include <linux/seq_file.h> | |
568 | ||
569 | static void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
570 | struct pinctrl_dev *pctldev, |
571 | struct gpio_chip *chip, | |
572 | unsigned offset, unsigned gpio) | |
0493e649 | 573 | { |
d2752ae5 | 574 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); |
0493e649 PC |
575 | const char *label = gpiochip_is_requested(chip, offset - 1); |
576 | u8 gpio_offset = offset - 1; | |
577 | int mode = -1; | |
578 | bool is_out; | |
d2752ae5 | 579 | bool pd; |
ce06f407 | 580 | enum abx500_gpio_pull_updown pud = 0; |
9be580af | 581 | int ret; |
83b423c8 | 582 | |
0493e649 PC |
583 | const char *modes[] = { |
584 | [ABX500_DEFAULT] = "default", | |
585 | [ABX500_ALT_A] = "altA", | |
586 | [ABX500_ALT_B] = "altB", | |
587 | [ABX500_ALT_C] = "altC", | |
588 | }; | |
589 | ||
d2752ae5 PC |
590 | const char *pull_up_down[] = { |
591 | [ABX500_GPIO_PULL_DOWN] = "pull down", | |
592 | [ABX500_GPIO_PULL_NONE] = "pull none", | |
593 | [ABX500_GPIO_PULL_NONE + 1] = "pull none", | |
594 | [ABX500_GPIO_PULL_UP] = "pull up", | |
595 | }; | |
596 | ||
9be580af PC |
597 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, |
598 | gpio_offset, &is_out); | |
599 | if (ret < 0) | |
600 | goto out; | |
d2752ae5 PC |
601 | |
602 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s", | |
603 | gpio, label ?: "(none)", | |
604 | is_out ? "out" : "in "); | |
605 | ||
606 | if (!is_out) { | |
8b5abd18 | 607 | if (abx500_pullud_supported(chip, offset)) { |
9be580af PC |
608 | ret = abx500_get_pull_updown(pct, offset, &pud); |
609 | if (ret < 0) | |
610 | goto out; | |
611 | ||
d2752ae5 PC |
612 | seq_printf(s, " %-9s", pull_up_down[pud]); |
613 | } else { | |
9be580af PC |
614 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, |
615 | gpio_offset, &pd); | |
616 | if (ret < 0) | |
617 | goto out; | |
618 | ||
d2752ae5 PC |
619 | seq_printf(s, " %-9s", pull_up_down[pd]); |
620 | } | |
621 | } else | |
622 | seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo"); | |
0493e649 | 623 | |
1d54f0fd | 624 | mode = abx500_get_mode(pctldev, chip, offset); |
0493e649 | 625 | |
d2752ae5 | 626 | seq_printf(s, " %s", (mode < 0) ? "unknown" : modes[mode]); |
9be580af PC |
627 | |
628 | out: | |
629 | if (ret < 0) | |
630 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
0493e649 PC |
631 | } |
632 | ||
633 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
634 | { | |
635 | unsigned i; | |
636 | unsigned gpio = chip->base; | |
637 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
638 | struct pinctrl_dev *pctldev = pct->pctldev; | |
639 | ||
640 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
641 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ | |
642 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); | |
643 | seq_printf(s, "\n"); | |
644 | } | |
645 | } | |
646 | ||
647 | #else | |
648 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
649 | struct pinctrl_dev *pctldev, |
650 | struct gpio_chip *chip, | |
651 | unsigned offset, unsigned gpio) | |
0493e649 PC |
652 | { |
653 | } | |
654 | #define abx500_gpio_dbg_show NULL | |
655 | #endif | |
656 | ||
9c4154ef | 657 | static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
658 | { |
659 | int gpio = chip->base + offset; | |
660 | ||
661 | return pinctrl_request_gpio(gpio); | |
662 | } | |
663 | ||
9c4154ef | 664 | static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
665 | { |
666 | int gpio = chip->base + offset; | |
667 | ||
668 | pinctrl_free_gpio(gpio); | |
669 | } | |
670 | ||
671 | static struct gpio_chip abx500gpio_chip = { | |
672 | .label = "abx500-gpio", | |
673 | .owner = THIS_MODULE, | |
674 | .request = abx500_gpio_request, | |
675 | .free = abx500_gpio_free, | |
676 | .direction_input = abx500_gpio_direction_input, | |
677 | .get = abx500_gpio_get, | |
678 | .direction_output = abx500_gpio_direction_output, | |
679 | .set = abx500_gpio_set, | |
680 | .to_irq = abx500_gpio_to_irq, | |
681 | .dbg_show = abx500_gpio_dbg_show, | |
682 | }; | |
683 | ||
0493e649 PC |
684 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
685 | { | |
686 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
687 | ||
688 | return pct->soc->nfunctions; | |
689 | } | |
690 | ||
691 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
692 | unsigned function) | |
693 | { | |
694 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
695 | ||
696 | return pct->soc->functions[function].name; | |
697 | } | |
698 | ||
699 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
700 | unsigned function, |
701 | const char * const **groups, | |
702 | unsigned * const num_groups) | |
0493e649 PC |
703 | { |
704 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
705 | ||
706 | *groups = pct->soc->functions[function].groups; | |
707 | *num_groups = pct->soc->functions[function].ngroups; | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
03e9f0ca LW |
712 | static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function, |
713 | unsigned group) | |
0493e649 PC |
714 | { |
715 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
716 | struct gpio_chip *chip = &pct->chip; | |
717 | const struct abx500_pingroup *g; | |
718 | int i; | |
719 | int ret = 0; | |
720 | ||
721 | g = &pct->soc->groups[group]; | |
722 | if (g->altsetting < 0) | |
723 | return -EINVAL; | |
724 | ||
725 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
726 | ||
727 | for (i = 0; i < g->npins; i++) { | |
728 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", | |
729 | g->pins[i], g->altsetting); | |
730 | ||
0493e649 PC |
731 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); |
732 | } | |
83b423c8 | 733 | |
9be580af PC |
734 | if (ret < 0) |
735 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
736 | ||
0493e649 PC |
737 | return ret; |
738 | } | |
739 | ||
9c4154ef | 740 | static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
741 | struct pinctrl_gpio_range *range, |
742 | unsigned offset) | |
0493e649 PC |
743 | { |
744 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
745 | const struct abx500_pinrange *p; | |
746 | int ret; | |
747 | int i; | |
748 | ||
749 | /* | |
750 | * Different ranges have different ways to enable GPIO function on a | |
751 | * pin, so refer back to our local range type, where we handily define | |
752 | * what altfunc enables GPIO for a certain pin. | |
753 | */ | |
754 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
755 | p = &pct->soc->gpio_ranges[i]; | |
756 | if ((offset >= p->offset) && | |
757 | (offset < (p->offset + p->npins))) | |
758 | break; | |
759 | } | |
760 | ||
761 | if (i == pct->soc->gpio_num_ranges) { | |
762 | dev_err(pct->dev, "%s failed to locate range\n", __func__); | |
763 | return -ENODEV; | |
764 | } | |
765 | ||
766 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", | |
767 | p->altfunc, offset); | |
768 | ||
769 | ret = abx500_set_mode(pct->pctldev, &pct->chip, | |
770 | offset, p->altfunc); | |
9be580af | 771 | if (ret < 0) |
0493e649 | 772 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); |
0493e649 PC |
773 | |
774 | return ret; | |
775 | } | |
776 | ||
777 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
778 | struct pinctrl_gpio_range *range, |
779 | unsigned offset) | |
0493e649 PC |
780 | { |
781 | } | |
782 | ||
022ab148 | 783 | static const struct pinmux_ops abx500_pinmux_ops = { |
0493e649 PC |
784 | .get_functions_count = abx500_pmx_get_funcs_cnt, |
785 | .get_function_name = abx500_pmx_get_func_name, | |
786 | .get_function_groups = abx500_pmx_get_func_groups, | |
03e9f0ca | 787 | .set_mux = abx500_pmx_set, |
0493e649 PC |
788 | .gpio_request_enable = abx500_gpio_request_enable, |
789 | .gpio_disable_free = abx500_gpio_disable_free, | |
790 | }; | |
791 | ||
792 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) | |
793 | { | |
794 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
795 | ||
796 | return pct->soc->ngroups; | |
797 | } | |
798 | ||
799 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, | |
83b423c8 | 800 | unsigned selector) |
0493e649 PC |
801 | { |
802 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
803 | ||
804 | return pct->soc->groups[selector].name; | |
805 | } | |
806 | ||
807 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
808 | unsigned selector, |
809 | const unsigned **pins, | |
810 | unsigned *num_pins) | |
0493e649 PC |
811 | { |
812 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
813 | ||
814 | *pins = pct->soc->groups[selector].pins; | |
815 | *num_pins = pct->soc->groups[selector].npins; | |
83b423c8 | 816 | |
0493e649 PC |
817 | return 0; |
818 | } | |
819 | ||
820 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, | |
83b423c8 | 821 | struct seq_file *s, unsigned offset) |
0493e649 PC |
822 | { |
823 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
824 | struct gpio_chip *chip = &pct->chip; | |
825 | ||
826 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, | |
827 | chip->base + offset - 1); | |
828 | } | |
829 | ||
64a45c98 PC |
830 | static int abx500_dt_add_map_mux(struct pinctrl_map **map, |
831 | unsigned *reserved_maps, | |
832 | unsigned *num_maps, const char *group, | |
833 | const char *function) | |
834 | { | |
835 | if (*num_maps == *reserved_maps) | |
836 | return -ENOSPC; | |
837 | ||
838 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
839 | (*map)[*num_maps].data.mux.group = group; | |
840 | (*map)[*num_maps].data.mux.function = function; | |
841 | (*num_maps)++; | |
842 | ||
843 | return 0; | |
844 | } | |
845 | ||
846 | static int abx500_dt_add_map_configs(struct pinctrl_map **map, | |
847 | unsigned *reserved_maps, | |
848 | unsigned *num_maps, const char *group, | |
849 | unsigned long *configs, unsigned num_configs) | |
850 | { | |
851 | unsigned long *dup_configs; | |
852 | ||
853 | if (*num_maps == *reserved_maps) | |
854 | return -ENOSPC; | |
855 | ||
856 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | |
857 | GFP_KERNEL); | |
858 | if (!dup_configs) | |
859 | return -ENOMEM; | |
860 | ||
861 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
862 | ||
863 | (*map)[*num_maps].data.configs.group_or_pin = group; | |
864 | (*map)[*num_maps].data.configs.configs = dup_configs; | |
865 | (*map)[*num_maps].data.configs.num_configs = num_configs; | |
866 | (*num_maps)++; | |
867 | ||
868 | return 0; | |
869 | } | |
870 | ||
871 | static const char *abx500_find_pin_name(struct pinctrl_dev *pctldev, | |
872 | const char *pin_name) | |
873 | { | |
874 | int i, pin_number; | |
875 | struct abx500_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | |
876 | ||
877 | if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1) | |
878 | for (i = 0; i < npct->soc->npins; i++) | |
879 | if (npct->soc->pins[i].number == pin_number) | |
880 | return npct->soc->pins[i].name; | |
881 | return NULL; | |
882 | } | |
883 | ||
884 | static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
885 | struct device_node *np, | |
886 | struct pinctrl_map **map, | |
887 | unsigned *reserved_maps, | |
888 | unsigned *num_maps) | |
889 | { | |
890 | int ret; | |
891 | const char *function = NULL; | |
892 | unsigned long *configs; | |
893 | unsigned int nconfigs = 0; | |
64a45c98 | 894 | struct property *prop; |
64a45c98 | 895 | |
51d39936 | 896 | ret = of_property_read_string(np, "function", &function); |
259145fe | 897 | if (ret >= 0) { |
51d39936 LW |
898 | const char *group; |
899 | ||
900 | ret = of_property_count_strings(np, "groups"); | |
259145fe LW |
901 | if (ret < 0) |
902 | goto exit; | |
903 | ||
904 | ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, | |
905 | num_maps, ret); | |
906 | if (ret < 0) | |
907 | goto exit; | |
908 | ||
51d39936 | 909 | of_property_for_each_string(np, "groups", prop, group) { |
259145fe LW |
910 | ret = abx500_dt_add_map_mux(map, reserved_maps, |
911 | num_maps, group, function); | |
912 | if (ret < 0) | |
913 | goto exit; | |
914 | } | |
915 | } | |
64a45c98 PC |
916 | |
917 | ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs); | |
eea11b0b | 918 | if (nconfigs) { |
51d39936 LW |
919 | const char *gpio_name; |
920 | const char *pin; | |
921 | ||
0564f7d9 | 922 | ret = of_property_count_strings(np, "pins"); |
259145fe LW |
923 | if (ret < 0) |
924 | goto exit; | |
64a45c98 | 925 | |
259145fe LW |
926 | ret = pinctrl_utils_reserve_map(pctldev, map, |
927 | reserved_maps, | |
928 | num_maps, ret); | |
929 | if (ret < 0) | |
930 | goto exit; | |
64a45c98 | 931 | |
0564f7d9 | 932 | of_property_for_each_string(np, "pins", prop, pin) { |
51d39936 | 933 | gpio_name = abx500_find_pin_name(pctldev, pin); |
64a45c98 PC |
934 | |
935 | ret = abx500_dt_add_map_configs(map, reserved_maps, | |
936 | num_maps, gpio_name, configs, 1); | |
937 | if (ret < 0) | |
938 | goto exit; | |
939 | } | |
64a45c98 | 940 | } |
259145fe | 941 | |
64a45c98 PC |
942 | exit: |
943 | return ret; | |
944 | } | |
945 | ||
946 | static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, | |
947 | struct device_node *np_config, | |
948 | struct pinctrl_map **map, unsigned *num_maps) | |
949 | { | |
950 | unsigned reserved_maps; | |
951 | struct device_node *np; | |
952 | int ret; | |
953 | ||
954 | reserved_maps = 0; | |
955 | *map = NULL; | |
956 | *num_maps = 0; | |
957 | ||
958 | for_each_child_of_node(np_config, np) { | |
959 | ret = abx500_dt_subnode_to_map(pctldev, np, map, | |
960 | &reserved_maps, num_maps); | |
961 | if (ret < 0) { | |
b07f92a2 | 962 | pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); |
64a45c98 PC |
963 | return ret; |
964 | } | |
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
022ab148 | 970 | static const struct pinctrl_ops abx500_pinctrl_ops = { |
0493e649 PC |
971 | .get_groups_count = abx500_get_groups_cnt, |
972 | .get_group_name = abx500_get_group_name, | |
973 | .get_group_pins = abx500_get_group_pins, | |
974 | .pin_dbg_show = abx500_pin_dbg_show, | |
64a45c98 | 975 | .dt_node_to_map = abx500_dt_node_to_map, |
b07f92a2 | 976 | .dt_free_map = pinctrl_utils_dt_free_map, |
0493e649 PC |
977 | }; |
978 | ||
9c4154ef | 979 | static int abx500_pin_config_get(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
980 | unsigned pin, |
981 | unsigned long *config) | |
0493e649 | 982 | { |
1abeebea | 983 | return -ENOSYS; |
0493e649 PC |
984 | } |
985 | ||
9c4154ef | 986 | static int abx500_pin_config_set(struct pinctrl_dev *pctldev, |
83b423c8 | 987 | unsigned pin, |
03b054e9 SY |
988 | unsigned long *configs, |
989 | unsigned num_configs) | |
0493e649 PC |
990 | { |
991 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
0493e649 PC |
992 | struct gpio_chip *chip = &pct->chip; |
993 | unsigned offset; | |
61ce1356 | 994 | int ret = -EINVAL; |
03b054e9 SY |
995 | int i; |
996 | enum pin_config_param param; | |
997 | enum pin_config_param argument; | |
998 | ||
999 | for (i = 0; i < num_configs; i++) { | |
1000 | param = pinconf_to_config_param(configs[i]); | |
1001 | argument = pinconf_to_config_argument(configs[i]); | |
1002 | ||
1003 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", | |
1004 | pin, configs[i], | |
1005 | (param == PIN_CONFIG_OUTPUT) ? "output " : "input", | |
1006 | (param == PIN_CONFIG_OUTPUT) ? | |
1007 | (argument ? "high" : "low") : | |
1008 | (argument ? "pull up" : "pull down")); | |
1009 | ||
1010 | /* on ABx500, there is no GPIO0, so adjust the offset */ | |
1011 | offset = pin - 1; | |
1012 | ||
1013 | switch (param) { | |
1014 | case PIN_CONFIG_BIAS_DISABLE: | |
1015 | ret = abx500_gpio_direction_input(chip, offset); | |
1016 | if (ret < 0) | |
1017 | goto out; | |
1018 | /* | |
1019 | * Some chips only support pull down, while some | |
1020 | * actually support both pull up and pull down. Such | |
1021 | * chips have a "pullud" range specified for the pins | |
1022 | * that support both features. If the pin is not | |
1023 | * within that range, we fall back to the old bit set | |
1024 | * that only support pull down. | |
1025 | */ | |
1026 | if (abx500_pullud_supported(chip, pin)) | |
1027 | ret = abx500_set_pull_updown(pct, | |
1028 | pin, | |
1029 | ABX500_GPIO_PULL_NONE); | |
1030 | else | |
1031 | /* Chip only supports pull down */ | |
1032 | ret = abx500_gpio_set_bits(chip, | |
1033 | AB8500_GPIO_PUD1_REG, offset, | |
1034 | ABX500_GPIO_PULL_NONE); | |
1035 | break; | |
9ed3cd33 | 1036 | |
03b054e9 SY |
1037 | case PIN_CONFIG_BIAS_PULL_DOWN: |
1038 | ret = abx500_gpio_direction_input(chip, offset); | |
1039 | if (ret < 0) | |
1040 | goto out; | |
1041 | /* | |
1042 | * if argument = 1 set the pull down | |
1043 | * else clear the pull down | |
1044 | * Some chips only support pull down, while some | |
1045 | * actually support both pull up and pull down. Such | |
1046 | * chips have a "pullud" range specified for the pins | |
1047 | * that support both features. If the pin is not | |
1048 | * within that range, we fall back to the old bit set | |
1049 | * that only support pull down. | |
1050 | */ | |
1051 | if (abx500_pullud_supported(chip, pin)) | |
1052 | ret = abx500_set_pull_updown(pct, | |
1053 | pin, | |
1054 | argument ? ABX500_GPIO_PULL_DOWN : | |
1055 | ABX500_GPIO_PULL_NONE); | |
1056 | else | |
1057 | /* Chip only supports pull down */ | |
1058 | ret = abx500_gpio_set_bits(chip, | |
1059 | AB8500_GPIO_PUD1_REG, | |
1060 | offset, | |
1061 | argument ? ABX500_GPIO_PULL_DOWN : | |
1062 | ABX500_GPIO_PULL_NONE); | |
1063 | break; | |
83b423c8 | 1064 | |
03b054e9 SY |
1065 | case PIN_CONFIG_BIAS_PULL_UP: |
1066 | ret = abx500_gpio_direction_input(chip, offset); | |
1067 | if (ret < 0) | |
1068 | goto out; | |
1069 | /* | |
1070 | * if argument = 1 set the pull up | |
1071 | * else clear the pull up | |
1072 | */ | |
1073 | ret = abx500_gpio_direction_input(chip, offset); | |
1074 | /* | |
1075 | * Some chips only support pull down, while some | |
1076 | * actually support both pull up and pull down. Such | |
1077 | * chips have a "pullud" range specified for the pins | |
1078 | * that support both features. If the pin is not | |
1079 | * within that range, do nothing | |
1080 | */ | |
1081 | if (abx500_pullud_supported(chip, pin)) | |
1082 | ret = abx500_set_pull_updown(pct, | |
1083 | pin, | |
1084 | argument ? ABX500_GPIO_PULL_UP : | |
1085 | ABX500_GPIO_PULL_NONE); | |
1086 | break; | |
1087 | ||
1088 | case PIN_CONFIG_OUTPUT: | |
1089 | ret = abx500_gpio_direction_output(chip, offset, | |
1090 | argument); | |
1091 | break; | |
1092 | ||
1093 | default: | |
1094 | dev_err(chip->dev, "illegal configuration requested\n"); | |
1095 | } | |
1096 | } /* for each config */ | |
9be580af PC |
1097 | out: |
1098 | if (ret < 0) | |
1099 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 1100 | |
0493e649 PC |
1101 | return ret; |
1102 | } | |
1103 | ||
022ab148 | 1104 | static const struct pinconf_ops abx500_pinconf_ops = { |
0493e649 PC |
1105 | .pin_config_get = abx500_pin_config_get, |
1106 | .pin_config_set = abx500_pin_config_set, | |
1107 | }; | |
1108 | ||
1109 | static struct pinctrl_desc abx500_pinctrl_desc = { | |
1110 | .name = "pinctrl-abx500", | |
1111 | .pctlops = &abx500_pinctrl_ops, | |
1112 | .pmxops = &abx500_pinmux_ops, | |
1113 | .confops = &abx500_pinconf_ops, | |
1114 | .owner = THIS_MODULE, | |
1115 | }; | |
1116 | ||
1117 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) | |
1118 | { | |
1119 | unsigned int lowest = 0; | |
1120 | unsigned int highest = 0; | |
1121 | unsigned int npins = 0; | |
1122 | int i; | |
1123 | ||
1124 | /* | |
1125 | * Compute number of GPIOs from the last SoC gpio range descriptors | |
1126 | * These ranges may include "holes" but the GPIO number space shall | |
1127 | * still be homogeneous, so we need to detect and account for any | |
1128 | * such holes so that these are included in the number of GPIO pins. | |
1129 | */ | |
1130 | for (i = 0; i < soc->gpio_num_ranges; i++) { | |
1131 | unsigned gstart; | |
1132 | unsigned gend; | |
1133 | const struct abx500_pinrange *p; | |
1134 | ||
1135 | p = &soc->gpio_ranges[i]; | |
1136 | gstart = p->offset; | |
1137 | gend = p->offset + p->npins - 1; | |
1138 | ||
1139 | if (i == 0) { | |
1140 | /* First iteration, set start values */ | |
1141 | lowest = gstart; | |
1142 | highest = gend; | |
1143 | } else { | |
1144 | if (gstart < lowest) | |
1145 | lowest = gstart; | |
1146 | if (gend > highest) | |
1147 | highest = gend; | |
1148 | } | |
1149 | } | |
1150 | /* this gives the absolute number of pins */ | |
1151 | npins = highest - lowest + 1; | |
1152 | return npins; | |
1153 | } | |
1154 | ||
f30a3839 LJ |
1155 | static const struct of_device_id abx500_gpio_match[] = { |
1156 | { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, | |
1157 | { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, | |
1158 | { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, | |
1159 | { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, | |
e3929714 | 1160 | { } |
f30a3839 LJ |
1161 | }; |
1162 | ||
0493e649 PC |
1163 | static int abx500_gpio_probe(struct platform_device *pdev) |
1164 | { | |
f30a3839 | 1165 | struct device_node *np = pdev->dev.of_node; |
ac99a037 | 1166 | const struct of_device_id *match; |
0493e649 | 1167 | struct abx500_pinctrl *pct; |
f30a3839 | 1168 | unsigned int id = -1; |
3a4b094d | 1169 | int ret; |
0493e649 PC |
1170 | int i; |
1171 | ||
ac99a037 LW |
1172 | if (!np) { |
1173 | dev_err(&pdev->dev, "gpio dt node missing\n"); | |
86c976e4 | 1174 | return -ENODEV; |
0493e649 PC |
1175 | } |
1176 | ||
1177 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), | |
1178 | GFP_KERNEL); | |
1179 | if (pct == NULL) { | |
1180 | dev_err(&pdev->dev, | |
1181 | "failed to allocate memory for pct\n"); | |
1182 | return -ENOMEM; | |
1183 | } | |
1184 | ||
1185 | pct->dev = &pdev->dev; | |
1186 | pct->parent = dev_get_drvdata(pdev->dev.parent); | |
1187 | pct->chip = abx500gpio_chip; | |
1188 | pct->chip.dev = &pdev->dev; | |
ac99a037 | 1189 | pct->chip.base = -1; /* Dynamic allocation */ |
86c976e4 | 1190 | |
ac99a037 LW |
1191 | match = of_match_device(abx500_gpio_match, &pdev->dev); |
1192 | if (!match) { | |
1193 | dev_err(&pdev->dev, "gpio dt not matching\n"); | |
1194 | return -ENODEV; | |
86c976e4 | 1195 | } |
ac99a037 | 1196 | id = (unsigned long)match->data; |
86c976e4 | 1197 | |
0493e649 | 1198 | /* Poke in other ASIC variants here */ |
f30a3839 | 1199 | switch (id) { |
3c937993 PC |
1200 | case PINCTRL_AB8500: |
1201 | abx500_pinctrl_ab8500_init(&pct->soc); | |
1202 | break; | |
a8f96e41 PC |
1203 | case PINCTRL_AB8540: |
1204 | abx500_pinctrl_ab8540_init(&pct->soc); | |
1205 | break; | |
09dbec3f PC |
1206 | case PINCTRL_AB9540: |
1207 | abx500_pinctrl_ab9540_init(&pct->soc); | |
1208 | break; | |
1aa2d8d4 PC |
1209 | case PINCTRL_AB8505: |
1210 | abx500_pinctrl_ab8505_init(&pct->soc); | |
1211 | break; | |
0493e649 | 1212 | default: |
2fcad12e | 1213 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); |
0493e649 PC |
1214 | return -EINVAL; |
1215 | } | |
1216 | ||
1217 | if (!pct->soc) { | |
1218 | dev_err(&pdev->dev, "Invalid SOC data\n"); | |
1219 | return -EINVAL; | |
1220 | } | |
1221 | ||
1222 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); | |
1223 | pct->irq_cluster = pct->soc->gpio_irq_cluster; | |
1224 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; | |
0493e649 | 1225 | |
0493e649 PC |
1226 | ret = gpiochip_add(&pct->chip); |
1227 | if (ret) { | |
83b423c8 | 1228 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
ac652d79 | 1229 | return ret; |
0493e649 PC |
1230 | } |
1231 | dev_info(&pdev->dev, "added gpiochip\n"); | |
1232 | ||
1233 | abx500_pinctrl_desc.pins = pct->soc->pins; | |
1234 | abx500_pinctrl_desc.npins = pct->soc->npins; | |
1235 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); | |
1236 | if (!pct->pctldev) { | |
1237 | dev_err(&pdev->dev, | |
1238 | "could not register abx500 pinctrl driver\n"); | |
fa1ec996 | 1239 | ret = -EINVAL; |
0493e649 PC |
1240 | goto out_rem_chip; |
1241 | } | |
1242 | dev_info(&pdev->dev, "registered pin controller\n"); | |
1243 | ||
1244 | /* We will handle a range of GPIO pins */ | |
1245 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
1246 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; | |
1247 | ||
1248 | ret = gpiochip_add_pin_range(&pct->chip, | |
1249 | dev_name(&pdev->dev), | |
1250 | p->offset - 1, p->offset, p->npins); | |
1251 | if (ret < 0) | |
fa1ec996 | 1252 | goto out_rem_chip; |
0493e649 PC |
1253 | } |
1254 | ||
1255 | platform_set_drvdata(pdev, pct); | |
1256 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); | |
1257 | ||
1258 | return 0; | |
1259 | ||
1260 | out_rem_chip: | |
2fcea6ce | 1261 | gpiochip_remove(&pct->chip); |
0493e649 PC |
1262 | return ret; |
1263 | } | |
1264 | ||
83b423c8 | 1265 | /** |
0493e649 | 1266 | * abx500_gpio_remove() - remove Ab8500-gpio driver |
83b423c8 | 1267 | * @pdev: Platform device registered |
0493e649 PC |
1268 | */ |
1269 | static int abx500_gpio_remove(struct platform_device *pdev) | |
1270 | { | |
1271 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); | |
0493e649 | 1272 | |
2fcea6ce | 1273 | gpiochip_remove(&pct->chip); |
0493e649 PC |
1274 | return 0; |
1275 | } | |
1276 | ||
0493e649 PC |
1277 | static struct platform_driver abx500_gpio_driver = { |
1278 | .driver = { | |
1279 | .name = "abx500-gpio", | |
1280 | .owner = THIS_MODULE, | |
f30a3839 | 1281 | .of_match_table = abx500_gpio_match, |
0493e649 PC |
1282 | }, |
1283 | .probe = abx500_gpio_probe, | |
1284 | .remove = abx500_gpio_remove, | |
0493e649 PC |
1285 | }; |
1286 | ||
1287 | static int __init abx500_gpio_init(void) | |
1288 | { | |
1289 | return platform_driver_register(&abx500_gpio_driver); | |
1290 | } | |
1291 | core_initcall(abx500_gpio_init); | |
1292 | ||
1293 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); | |
1294 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); | |
1295 | MODULE_ALIAS("platform:abx500-gpio"); | |
1296 | MODULE_LICENSE("GPL v2"); |