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0493e649 PC |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2013 | |
3 | * | |
4 | * Author: Patrice Chotard <patrice.chotard@st.com> | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/mfd/abx500.h> | |
23 | #include <linux/mfd/abx500/ab8500.h> | |
24 | #include <linux/mfd/abx500/ab8500-gpio.h> | |
25 | #include <linux/pinctrl/pinctrl.h> | |
26 | #include <linux/pinctrl/consumer.h> | |
27 | #include <linux/pinctrl/pinmux.h> | |
28 | #include <linux/pinctrl/pinconf.h> | |
29 | #include <linux/pinctrl/pinconf-generic.h> | |
30 | ||
31 | #include "pinctrl-abx500.h" | |
32 | ||
33 | /* | |
34 | * The AB9540 and AB8540 GPIO support are extended versions | |
35 | * of the AB8500 GPIO support. | |
36 | * The AB9540 supports an additional (7th) register so that | |
37 | * more GPIO may be configured and used. | |
38 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have | |
39 | * internal pull-up and pull-down capabilities. | |
40 | */ | |
41 | ||
42 | /* | |
43 | * GPIO registers offset | |
44 | * Bank: 0x10 | |
45 | */ | |
46 | #define AB8500_GPIO_SEL1_REG 0x00 | |
47 | #define AB8500_GPIO_SEL2_REG 0x01 | |
48 | #define AB8500_GPIO_SEL3_REG 0x02 | |
49 | #define AB8500_GPIO_SEL4_REG 0x03 | |
50 | #define AB8500_GPIO_SEL5_REG 0x04 | |
51 | #define AB8500_GPIO_SEL6_REG 0x05 | |
52 | #define AB9540_GPIO_SEL7_REG 0x06 | |
53 | ||
54 | #define AB8500_GPIO_DIR1_REG 0x10 | |
55 | #define AB8500_GPIO_DIR2_REG 0x11 | |
56 | #define AB8500_GPIO_DIR3_REG 0x12 | |
57 | #define AB8500_GPIO_DIR4_REG 0x13 | |
58 | #define AB8500_GPIO_DIR5_REG 0x14 | |
59 | #define AB8500_GPIO_DIR6_REG 0x15 | |
60 | #define AB9540_GPIO_DIR7_REG 0x16 | |
61 | ||
62 | #define AB8500_GPIO_OUT1_REG 0x20 | |
63 | #define AB8500_GPIO_OUT2_REG 0x21 | |
64 | #define AB8500_GPIO_OUT3_REG 0x22 | |
65 | #define AB8500_GPIO_OUT4_REG 0x23 | |
66 | #define AB8500_GPIO_OUT5_REG 0x24 | |
67 | #define AB8500_GPIO_OUT6_REG 0x25 | |
68 | #define AB9540_GPIO_OUT7_REG 0x26 | |
69 | ||
70 | #define AB8500_GPIO_PUD1_REG 0x30 | |
71 | #define AB8500_GPIO_PUD2_REG 0x31 | |
72 | #define AB8500_GPIO_PUD3_REG 0x32 | |
73 | #define AB8500_GPIO_PUD4_REG 0x33 | |
74 | #define AB8500_GPIO_PUD5_REG 0x34 | |
75 | #define AB8500_GPIO_PUD6_REG 0x35 | |
76 | #define AB9540_GPIO_PUD7_REG 0x36 | |
77 | ||
78 | #define AB8500_GPIO_IN1_REG 0x40 | |
79 | #define AB8500_GPIO_IN2_REG 0x41 | |
80 | #define AB8500_GPIO_IN3_REG 0x42 | |
81 | #define AB8500_GPIO_IN4_REG 0x43 | |
82 | #define AB8500_GPIO_IN5_REG 0x44 | |
83 | #define AB8500_GPIO_IN6_REG 0x45 | |
84 | #define AB9540_GPIO_IN7_REG 0x46 | |
85 | #define AB8540_GPIO_VINSEL_REG 0x47 | |
86 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 | |
87 | #define AB8500_GPIO_ALTFUN_REG 0x50 | |
88 | #define AB8500_NUM_VIR_GPIO_IRQ 16 | |
89 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 | |
90 | #define AB8540_GPIO_VINSEL_MASK 0x03 | |
91 | #define AB8540_GPIOX_VBAT_START 51 | |
92 | #define AB8540_GPIOX_VBAT_END 54 | |
93 | ||
94 | enum abx500_gpio_action { | |
95 | NONE, | |
96 | STARTUP, | |
97 | SHUTDOWN, | |
98 | MASK, | |
99 | UNMASK | |
100 | }; | |
101 | ||
102 | struct abx500_pinctrl { | |
103 | struct device *dev; | |
104 | struct pinctrl_dev *pctldev; | |
105 | struct abx500_pinctrl_soc_data *soc; | |
106 | struct gpio_chip chip; | |
107 | struct ab8500 *parent; | |
108 | struct mutex lock; | |
109 | u32 irq_base; | |
110 | enum abx500_gpio_action irq_action; | |
111 | u16 rising; | |
112 | u16 falling; | |
113 | struct abx500_gpio_irq_cluster *irq_cluster; | |
114 | int irq_cluster_size; | |
115 | int irq_gpio_rising_offset; | |
116 | int irq_gpio_falling_offset; | |
117 | int irq_gpio_factor; | |
118 | }; | |
119 | ||
120 | /** | |
121 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl | |
122 | * @chip: Member of the structure abx500_pinctrl | |
123 | */ | |
124 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) | |
125 | { | |
126 | return container_of(chip, struct abx500_pinctrl, chip); | |
127 | } | |
128 | ||
129 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, | |
130 | unsigned offset, bool *bit) | |
131 | { | |
132 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
133 | u8 pos = offset % 8; | |
134 | u8 val; | |
135 | int ret; | |
136 | ||
137 | reg += offset / 8; | |
138 | ret = abx500_get_register_interruptible(pct->dev, | |
139 | AB8500_MISC, reg, &val); | |
140 | ||
141 | *bit = !!(val & BIT(pos)); | |
142 | ||
143 | if (ret < 0) | |
144 | dev_err(pct->dev, | |
145 | "%s read reg =%x, offset=%x failed\n", | |
146 | __func__, reg, offset); | |
147 | ||
148 | return ret; | |
149 | } | |
150 | ||
151 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, | |
152 | unsigned offset, int val) | |
153 | { | |
154 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
155 | u8 pos = offset % 8; | |
156 | int ret; | |
157 | ||
158 | reg += offset / 8; | |
159 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
49dcf086 | 160 | AB8500_MISC, reg, BIT(pos), val << pos); |
0493e649 PC |
161 | if (ret < 0) |
162 | dev_err(pct->dev, "%s write failed\n", __func__); | |
163 | return ret; | |
164 | } | |
165 | /** | |
166 | * abx500_gpio_get() - Get the particular GPIO value | |
167 | * @chip: Gpio device | |
168 | * @offset: GPIO number to read | |
169 | */ | |
170 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) | |
171 | { | |
172 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
173 | bool bit; | |
174 | int ret; | |
175 | ||
176 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, | |
177 | offset, &bit); | |
178 | if (ret < 0) { | |
179 | dev_err(pct->dev, "%s failed\n", __func__); | |
180 | return ret; | |
181 | } | |
182 | return bit; | |
183 | } | |
184 | ||
185 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
186 | { | |
187 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
188 | int ret; | |
189 | ||
190 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
191 | if (ret < 0) | |
192 | dev_err(pct->dev, "%s write failed\n", __func__); | |
193 | } | |
194 | ||
195 | static int abx500_config_pull_updown(struct abx500_pinctrl *pct, | |
196 | int offset, enum abx500_gpio_pull_updown val) | |
197 | { | |
198 | u8 pos; | |
199 | int ret; | |
200 | struct pullud *pullud; | |
201 | ||
202 | if (!pct->soc->pullud) { | |
203 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
204 | __func__); | |
205 | ret = -EPERM; | |
206 | goto out; | |
207 | } | |
208 | ||
209 | pullud = pct->soc->pullud; | |
210 | ||
211 | if ((offset < pullud->first_pin) | |
212 | || (offset > pullud->last_pin)) { | |
213 | ret = -EINVAL; | |
214 | goto out; | |
215 | } | |
216 | ||
217 | pos = offset << 1; | |
218 | ||
219 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
220 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, | |
221 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); | |
222 | ||
223 | out: | |
224 | if (ret < 0) | |
225 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
226 | return ret; | |
227 | } | |
228 | ||
229 | static int abx500_gpio_direction_output(struct gpio_chip *chip, | |
230 | unsigned offset, | |
231 | int val) | |
232 | { | |
233 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
234 | struct pullud *pullud = pct->soc->pullud; | |
235 | unsigned gpio; | |
236 | int ret; | |
237 | /* set direction as output */ | |
238 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); | |
239 | if (ret < 0) | |
240 | return ret; | |
241 | ||
242 | /* disable pull down */ | |
243 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); | |
244 | if (ret < 0) | |
245 | return ret; | |
246 | ||
247 | /* if supported, disable both pull down and pull up */ | |
248 | gpio = offset + 1; | |
249 | if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { | |
250 | ret = abx500_config_pull_updown(pct, | |
251 | gpio, | |
252 | ABX500_GPIO_PULL_NONE); | |
253 | if (ret < 0) | |
254 | return ret; | |
255 | } | |
256 | /* set the output as 1 or 0 */ | |
257 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
258 | } | |
259 | ||
260 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
261 | { | |
262 | /* set the register as input */ | |
263 | return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); | |
264 | } | |
265 | ||
266 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
267 | { | |
268 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
269 | int base = pct->irq_base; | |
270 | int i; | |
271 | ||
272 | for (i = 0; i < pct->irq_cluster_size; i++) { | |
273 | struct abx500_gpio_irq_cluster *cluster = | |
274 | &pct->irq_cluster[i]; | |
275 | ||
276 | if (offset >= cluster->start && offset <= cluster->end) | |
277 | return base + offset - cluster->start; | |
278 | ||
279 | /* Advance by the number of gpios in this cluster */ | |
280 | base += cluster->end + cluster->offset - cluster->start + 1; | |
281 | } | |
282 | ||
283 | return -EINVAL; | |
284 | } | |
285 | ||
286 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
287 | unsigned gpio, int alt_setting) | |
288 | { | |
289 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
290 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
291 | int ret; | |
292 | int val; | |
293 | unsigned offset; | |
294 | const char *modes[] = { | |
295 | [ABX500_DEFAULT] = "default", | |
296 | [ABX500_ALT_A] = "altA", | |
297 | [ABX500_ALT_B] = "altB", | |
298 | [ABX500_ALT_C] = "altC", | |
299 | }; | |
300 | ||
301 | /* sanity check */ | |
302 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || | |
303 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || | |
304 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { | |
305 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, | |
306 | modes[alt_setting]); | |
307 | return -EINVAL; | |
308 | } | |
309 | ||
310 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ | |
311 | offset = gpio - 1; | |
312 | switch (alt_setting) { | |
313 | case ABX500_DEFAULT: | |
314 | /* | |
315 | * for ABx5xx family, default mode is always selected by | |
316 | * writing 0 to GPIOSELx register, except for pins which | |
317 | * support at least ALT_B mode, default mode is selected | |
318 | * by writing 1 to GPIOSELx register | |
319 | */ | |
320 | val = 0; | |
321 | if (af.alt_bit1 != UNUSED) | |
322 | val++; | |
323 | ||
324 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
325 | offset, val); | |
326 | break; | |
327 | case ABX500_ALT_A: | |
328 | /* | |
329 | * for ABx5xx family, alt_a mode is always selected by | |
330 | * writing 1 to GPIOSELx register, except for pins which | |
331 | * support at least ALT_B mode, alt_a mode is selected | |
332 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC | |
333 | * register | |
334 | */ | |
335 | if (af.alt_bit1 != UNUSED) { | |
336 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
337 | offset, 0); | |
338 | ret = abx500_gpio_set_bits(chip, | |
339 | AB8500_GPIO_ALTFUN_REG, | |
340 | af.alt_bit1, | |
341 | !!(af.alta_val && BIT(0))); | |
342 | if (af.alt_bit2 != UNUSED) | |
343 | ret = abx500_gpio_set_bits(chip, | |
344 | AB8500_GPIO_ALTFUN_REG, | |
345 | af.alt_bit2, | |
346 | !!(af.alta_val && BIT(1))); | |
347 | } else | |
348 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
349 | offset, 1); | |
350 | break; | |
351 | case ABX500_ALT_B: | |
352 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
353 | offset, 0); | |
354 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
355 | af.alt_bit1, !!(af.altb_val && BIT(0))); | |
356 | if (af.alt_bit2 != UNUSED) | |
357 | ret = abx500_gpio_set_bits(chip, | |
358 | AB8500_GPIO_ALTFUN_REG, | |
359 | af.alt_bit2, | |
360 | !!(af.altb_val && BIT(1))); | |
361 | break; | |
362 | case ABX500_ALT_C: | |
363 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
364 | offset, 0); | |
365 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
366 | af.alt_bit2, !!(af.altc_val && BIT(0))); | |
367 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
368 | af.alt_bit2, !!(af.altc_val && BIT(1))); | |
369 | break; | |
370 | ||
371 | default: | |
372 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); | |
373 | return -EINVAL; | |
374 | } | |
375 | return ret; | |
376 | } | |
377 | ||
378 | static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
379 | unsigned gpio) | |
380 | { | |
381 | u8 mode; | |
382 | bool bit_mode; | |
383 | bool alt_bit1; | |
384 | bool alt_bit2; | |
385 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
386 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
387 | ||
388 | /* | |
389 | * if gpiosel_bit is set to unused, | |
390 | * it means no GPIO or special case | |
391 | */ | |
392 | if (af.gpiosel_bit == UNUSED) | |
393 | return ABX500_DEFAULT; | |
394 | ||
395 | /* read GpioSelx register */ | |
396 | abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (gpio / 8), | |
397 | af.gpiosel_bit, &bit_mode); | |
398 | mode = bit_mode; | |
399 | ||
400 | /* sanity check */ | |
401 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || | |
402 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { | |
403 | dev_err(pct->dev, | |
404 | "alt_bitX value not in correct range (-1 to 7)\n"); | |
405 | return -EINVAL; | |
406 | } | |
407 | /* if alt_bit2 is used, alt_bit1 must be used too */ | |
408 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { | |
409 | dev_err(pct->dev, | |
410 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); | |
411 | return -EINVAL; | |
412 | } | |
413 | ||
414 | /* check if pin use AlternateFunction register */ | |
415 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED)) | |
416 | return mode; | |
417 | /* | |
418 | * if pin GPIOSEL bit is set and pin supports alternate function, | |
419 | * it means DEFAULT mode | |
420 | */ | |
421 | if (mode) | |
422 | return ABX500_DEFAULT; | |
423 | /* | |
424 | * pin use the AlternatFunction register | |
425 | * read alt_bit1 value | |
426 | */ | |
427 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, | |
428 | af.alt_bit1, &alt_bit1); | |
429 | ||
430 | if (af.alt_bit2 != UNUSED) | |
431 | /* read alt_bit2 value */ | |
432 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, | |
433 | &alt_bit2); | |
434 | else | |
435 | alt_bit2 = 0; | |
436 | ||
437 | mode = (alt_bit2 << 1) + alt_bit1; | |
438 | if (mode == af.alta_val) | |
439 | return ABX500_ALT_A; | |
440 | else if (mode == af.altb_val) | |
441 | return ABX500_ALT_B; | |
442 | else | |
443 | return ABX500_ALT_C; | |
444 | } | |
445 | ||
446 | #ifdef CONFIG_DEBUG_FS | |
447 | ||
448 | #include <linux/seq_file.h> | |
449 | ||
450 | static void abx500_gpio_dbg_show_one(struct seq_file *s, | |
451 | struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
452 | unsigned offset, unsigned gpio) | |
453 | { | |
454 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
455 | const char *label = gpiochip_is_requested(chip, offset - 1); | |
456 | u8 gpio_offset = offset - 1; | |
457 | int mode = -1; | |
458 | bool is_out; | |
459 | bool pull; | |
460 | const char *modes[] = { | |
461 | [ABX500_DEFAULT] = "default", | |
462 | [ABX500_ALT_A] = "altA", | |
463 | [ABX500_ALT_B] = "altB", | |
464 | [ABX500_ALT_C] = "altC", | |
465 | }; | |
466 | ||
467 | abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); | |
468 | abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull); | |
469 | ||
470 | if (pctldev) | |
471 | mode = abx500_get_mode(pctldev, chip, offset); | |
472 | ||
473 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s", | |
474 | gpio, label ?: "(none)", | |
475 | is_out ? "out" : "in ", | |
476 | is_out ? | |
477 | (chip->get | |
478 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
479 | : "? ") | |
480 | : (pull ? "pull up" : "pull down"), | |
481 | (mode < 0) ? "unknown" : modes[mode]); | |
482 | ||
483 | if (label && !is_out) { | |
484 | int irq = gpio_to_irq(gpio); | |
485 | struct irq_desc *desc = irq_to_desc(irq); | |
486 | ||
487 | if (irq >= 0 && desc->action) { | |
488 | char *trigger; | |
489 | int irq_offset = irq - pct->irq_base; | |
490 | ||
491 | if (pct->rising & BIT(irq_offset)) | |
492 | trigger = "edge-rising"; | |
493 | else if (pct->falling & BIT(irq_offset)) | |
494 | trigger = "edge-falling"; | |
495 | else | |
496 | trigger = "edge-undefined"; | |
497 | ||
498 | seq_printf(s, " irq-%d %s", irq, trigger); | |
499 | } | |
500 | } | |
501 | } | |
502 | ||
503 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
504 | { | |
505 | unsigned i; | |
506 | unsigned gpio = chip->base; | |
507 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
508 | struct pinctrl_dev *pctldev = pct->pctldev; | |
509 | ||
510 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
511 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ | |
512 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); | |
513 | seq_printf(s, "\n"); | |
514 | } | |
515 | } | |
516 | ||
517 | #else | |
518 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, | |
519 | struct pinctrl_dev *pctldev, | |
520 | struct gpio_chip *chip, | |
521 | unsigned offset, unsigned gpio) | |
522 | { | |
523 | } | |
524 | #define abx500_gpio_dbg_show NULL | |
525 | #endif | |
526 | ||
527 | int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) | |
528 | { | |
529 | int gpio = chip->base + offset; | |
530 | ||
531 | return pinctrl_request_gpio(gpio); | |
532 | } | |
533 | ||
534 | void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) | |
535 | { | |
536 | int gpio = chip->base + offset; | |
537 | ||
538 | pinctrl_free_gpio(gpio); | |
539 | } | |
540 | ||
541 | static struct gpio_chip abx500gpio_chip = { | |
542 | .label = "abx500-gpio", | |
543 | .owner = THIS_MODULE, | |
544 | .request = abx500_gpio_request, | |
545 | .free = abx500_gpio_free, | |
546 | .direction_input = abx500_gpio_direction_input, | |
547 | .get = abx500_gpio_get, | |
548 | .direction_output = abx500_gpio_direction_output, | |
549 | .set = abx500_gpio_set, | |
550 | .to_irq = abx500_gpio_to_irq, | |
551 | .dbg_show = abx500_gpio_dbg_show, | |
552 | }; | |
553 | ||
554 | static unsigned int irq_to_rising(unsigned int irq) | |
555 | { | |
556 | struct abx500_pinctrl *pct = irq_get_chip_data(irq); | |
557 | int offset = irq - pct->irq_base; | |
558 | int new_irq; | |
559 | ||
560 | new_irq = offset * pct->irq_gpio_factor | |
561 | + pct->irq_gpio_rising_offset | |
562 | + pct->parent->irq_base; | |
563 | ||
564 | return new_irq; | |
565 | } | |
566 | ||
567 | static unsigned int irq_to_falling(unsigned int irq) | |
568 | { | |
569 | struct abx500_pinctrl *pct = irq_get_chip_data(irq); | |
570 | int offset = irq - pct->irq_base; | |
571 | int new_irq; | |
572 | ||
573 | new_irq = offset * pct->irq_gpio_factor | |
574 | + pct->irq_gpio_falling_offset | |
575 | + pct->parent->irq_base; | |
576 | return new_irq; | |
577 | ||
578 | } | |
579 | ||
580 | static unsigned int rising_to_irq(unsigned int irq, void *dev) | |
581 | { | |
582 | struct abx500_pinctrl *pct = dev; | |
583 | int offset, new_irq; | |
584 | ||
585 | offset = irq - pct->irq_gpio_rising_offset | |
586 | - pct->parent->irq_base; | |
587 | new_irq = (offset / pct->irq_gpio_factor) | |
588 | + pct->irq_base; | |
589 | ||
590 | return new_irq; | |
591 | } | |
592 | ||
593 | static unsigned int falling_to_irq(unsigned int irq, void *dev) | |
594 | { | |
595 | struct abx500_pinctrl *pct = dev; | |
596 | int offset, new_irq; | |
597 | ||
598 | offset = irq - pct->irq_gpio_falling_offset | |
599 | - pct->parent->irq_base; | |
600 | new_irq = (offset / pct->irq_gpio_factor) | |
601 | + pct->irq_base; | |
602 | ||
603 | return new_irq; | |
604 | } | |
605 | ||
606 | /* | |
607 | * IRQ handler | |
608 | */ | |
609 | ||
610 | static irqreturn_t handle_rising(int irq, void *dev) | |
611 | { | |
612 | ||
613 | handle_nested_irq(rising_to_irq(irq , dev)); | |
614 | return IRQ_HANDLED; | |
615 | } | |
616 | ||
617 | static irqreturn_t handle_falling(int irq, void *dev) | |
618 | { | |
619 | ||
620 | handle_nested_irq(falling_to_irq(irq, dev)); | |
621 | return IRQ_HANDLED; | |
622 | } | |
623 | ||
624 | static void abx500_gpio_irq_lock(struct irq_data *data) | |
625 | { | |
626 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
627 | mutex_lock(&pct->lock); | |
628 | } | |
629 | ||
630 | static void abx500_gpio_irq_sync_unlock(struct irq_data *data) | |
631 | { | |
632 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
633 | unsigned int irq = data->irq; | |
634 | int offset = irq - pct->irq_base; | |
635 | bool rising = pct->rising & BIT(offset); | |
636 | bool falling = pct->falling & BIT(offset); | |
637 | int ret; | |
638 | ||
639 | switch (pct->irq_action) { | |
640 | case STARTUP: | |
641 | if (rising) | |
642 | ret = request_threaded_irq(irq_to_rising(irq), | |
643 | NULL, handle_rising, | |
644 | IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, | |
645 | "abx500-gpio-r", pct); | |
646 | if (falling) | |
647 | ret = request_threaded_irq(irq_to_falling(irq), | |
648 | NULL, handle_falling, | |
649 | IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND, | |
650 | "abx500-gpio-f", pct); | |
651 | break; | |
652 | case SHUTDOWN: | |
653 | if (rising) | |
654 | free_irq(irq_to_rising(irq), pct); | |
655 | if (falling) | |
656 | free_irq(irq_to_falling(irq), pct); | |
657 | break; | |
658 | case MASK: | |
659 | if (rising) | |
660 | disable_irq(irq_to_rising(irq)); | |
661 | if (falling) | |
662 | disable_irq(irq_to_falling(irq)); | |
663 | break; | |
664 | case UNMASK: | |
665 | if (rising) | |
666 | enable_irq(irq_to_rising(irq)); | |
667 | if (falling) | |
668 | enable_irq(irq_to_falling(irq)); | |
669 | break; | |
670 | case NONE: | |
671 | break; | |
672 | } | |
673 | pct->irq_action = NONE; | |
674 | pct->rising &= ~(BIT(offset)); | |
675 | pct->falling &= ~(BIT(offset)); | |
676 | mutex_unlock(&pct->lock); | |
677 | } | |
678 | ||
679 | ||
680 | static void abx500_gpio_irq_mask(struct irq_data *data) | |
681 | { | |
682 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
683 | pct->irq_action = MASK; | |
684 | } | |
685 | ||
686 | static void abx500_gpio_irq_unmask(struct irq_data *data) | |
687 | { | |
688 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
689 | pct->irq_action = UNMASK; | |
690 | } | |
691 | ||
692 | static int abx500_gpio_irq_set_type(struct irq_data *data, unsigned int type) | |
693 | { | |
694 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
695 | unsigned int irq = data->irq; | |
696 | int offset = irq - pct->irq_base; | |
697 | ||
698 | if (type == IRQ_TYPE_EDGE_BOTH) { | |
699 | pct->rising = BIT(offset); | |
700 | pct->falling = BIT(offset); | |
701 | } else if (type == IRQ_TYPE_EDGE_RISING) { | |
702 | pct->rising = BIT(offset); | |
703 | } else { | |
704 | pct->falling = BIT(offset); | |
705 | } | |
706 | return 0; | |
707 | } | |
708 | ||
709 | static unsigned int abx500_gpio_irq_startup(struct irq_data *data) | |
710 | { | |
711 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
712 | pct->irq_action = STARTUP; | |
713 | return 0; | |
714 | } | |
715 | ||
716 | static void abx500_gpio_irq_shutdown(struct irq_data *data) | |
717 | { | |
718 | struct abx500_pinctrl *pct = irq_data_get_irq_chip_data(data); | |
719 | pct->irq_action = SHUTDOWN; | |
720 | } | |
721 | ||
722 | static struct irq_chip abx500_gpio_irq_chip = { | |
723 | .name = "abx500-gpio", | |
724 | .irq_startup = abx500_gpio_irq_startup, | |
725 | .irq_shutdown = abx500_gpio_irq_shutdown, | |
726 | .irq_bus_lock = abx500_gpio_irq_lock, | |
727 | .irq_bus_sync_unlock = abx500_gpio_irq_sync_unlock, | |
728 | .irq_mask = abx500_gpio_irq_mask, | |
729 | .irq_unmask = abx500_gpio_irq_unmask, | |
730 | .irq_set_type = abx500_gpio_irq_set_type, | |
731 | }; | |
732 | ||
733 | static int abx500_gpio_irq_init(struct abx500_pinctrl *pct) | |
734 | { | |
735 | u32 base = pct->irq_base; | |
736 | int irq; | |
737 | ||
738 | for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ ; irq++) { | |
739 | irq_set_chip_data(irq, pct); | |
740 | irq_set_chip_and_handler(irq, &abx500_gpio_irq_chip, | |
741 | handle_simple_irq); | |
742 | irq_set_nested_thread(irq, 1); | |
743 | #ifdef CONFIG_ARM | |
744 | set_irq_flags(irq, IRQF_VALID); | |
745 | #else | |
746 | irq_set_noprobe(irq); | |
747 | #endif | |
748 | } | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static void abx500_gpio_irq_remove(struct abx500_pinctrl *pct) | |
754 | { | |
755 | int base = pct->irq_base; | |
756 | int irq; | |
757 | ||
758 | for (irq = base; irq < base + AB8500_NUM_VIR_GPIO_IRQ; irq++) { | |
759 | #ifdef CONFIG_ARM | |
760 | set_irq_flags(irq, 0); | |
761 | #endif | |
762 | irq_set_chip_and_handler(irq, NULL, NULL); | |
763 | irq_set_chip_data(irq, NULL); | |
764 | } | |
765 | } | |
766 | ||
767 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
768 | { | |
769 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
770 | ||
771 | return pct->soc->nfunctions; | |
772 | } | |
773 | ||
774 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
775 | unsigned function) | |
776 | { | |
777 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
778 | ||
779 | return pct->soc->functions[function].name; | |
780 | } | |
781 | ||
782 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
783 | unsigned function, | |
784 | const char * const **groups, | |
785 | unsigned * const num_groups) | |
786 | { | |
787 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
788 | ||
789 | *groups = pct->soc->functions[function].groups; | |
790 | *num_groups = pct->soc->functions[function].ngroups; | |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
795 | static void abx500_disable_lazy_irq(struct gpio_chip *chip, unsigned gpio) | |
796 | { | |
797 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
798 | int irq; | |
799 | int offset; | |
800 | bool rising; | |
801 | bool falling; | |
802 | ||
803 | /* | |
804 | * check if gpio has interrupt capability and convert | |
805 | * gpio number to irq | |
806 | * On ABx5xx, there is no GPIO0, GPIO1 is the | |
807 | * first one, so adjust gpio number | |
808 | */ | |
809 | gpio--; | |
810 | irq = gpio_to_irq(gpio + chip->base); | |
811 | if (irq < 0) | |
812 | return; | |
813 | ||
814 | offset = irq - pct->irq_base; | |
815 | rising = pct->rising & BIT(offset); | |
816 | falling = pct->falling & BIT(offset); | |
817 | ||
818 | /* nothing to do ?*/ | |
819 | if (!rising && !falling) | |
820 | return; | |
821 | ||
822 | if (rising) { | |
823 | disable_irq(irq_to_rising(irq)); | |
824 | free_irq(irq_to_rising(irq), pct); | |
825 | } | |
826 | if (falling) { | |
827 | disable_irq(irq_to_falling(irq)); | |
828 | free_irq(irq_to_falling(irq), pct); | |
829 | } | |
830 | } | |
831 | ||
832 | static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | |
833 | unsigned group) | |
834 | { | |
835 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
836 | struct gpio_chip *chip = &pct->chip; | |
837 | const struct abx500_pingroup *g; | |
838 | int i; | |
839 | int ret = 0; | |
840 | ||
841 | g = &pct->soc->groups[group]; | |
842 | if (g->altsetting < 0) | |
843 | return -EINVAL; | |
844 | ||
845 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
846 | ||
847 | for (i = 0; i < g->npins; i++) { | |
848 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", | |
849 | g->pins[i], g->altsetting); | |
850 | ||
851 | abx500_disable_lazy_irq(chip, g->pins[i]); | |
852 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); | |
853 | } | |
854 | return ret; | |
855 | } | |
856 | ||
857 | static void abx500_pmx_disable(struct pinctrl_dev *pctldev, | |
858 | unsigned function, unsigned group) | |
859 | { | |
860 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
861 | const struct abx500_pingroup *g; | |
862 | ||
863 | g = &pct->soc->groups[group]; | |
864 | if (g->altsetting < 0) | |
865 | return; | |
866 | ||
867 | /* FIXME: poke out the mux, set the pin to some default state? */ | |
868 | dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
869 | } | |
870 | ||
871 | int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, | |
872 | struct pinctrl_gpio_range *range, | |
873 | unsigned offset) | |
874 | { | |
875 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
876 | const struct abx500_pinrange *p; | |
877 | int ret; | |
878 | int i; | |
879 | ||
880 | /* | |
881 | * Different ranges have different ways to enable GPIO function on a | |
882 | * pin, so refer back to our local range type, where we handily define | |
883 | * what altfunc enables GPIO for a certain pin. | |
884 | */ | |
885 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
886 | p = &pct->soc->gpio_ranges[i]; | |
887 | if ((offset >= p->offset) && | |
888 | (offset < (p->offset + p->npins))) | |
889 | break; | |
890 | } | |
891 | ||
892 | if (i == pct->soc->gpio_num_ranges) { | |
893 | dev_err(pct->dev, "%s failed to locate range\n", __func__); | |
894 | return -ENODEV; | |
895 | } | |
896 | ||
897 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", | |
898 | p->altfunc, offset); | |
899 | ||
900 | ret = abx500_set_mode(pct->pctldev, &pct->chip, | |
901 | offset, p->altfunc); | |
902 | if (ret < 0) { | |
903 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); | |
904 | return ret; | |
905 | } | |
906 | ||
907 | return ret; | |
908 | } | |
909 | ||
910 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, | |
911 | struct pinctrl_gpio_range *range, | |
912 | unsigned offset) | |
913 | { | |
914 | } | |
915 | ||
916 | static struct pinmux_ops abx500_pinmux_ops = { | |
917 | .get_functions_count = abx500_pmx_get_funcs_cnt, | |
918 | .get_function_name = abx500_pmx_get_func_name, | |
919 | .get_function_groups = abx500_pmx_get_func_groups, | |
920 | .enable = abx500_pmx_enable, | |
921 | .disable = abx500_pmx_disable, | |
922 | .gpio_request_enable = abx500_gpio_request_enable, | |
923 | .gpio_disable_free = abx500_gpio_disable_free, | |
924 | }; | |
925 | ||
926 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) | |
927 | { | |
928 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
929 | ||
930 | return pct->soc->ngroups; | |
931 | } | |
932 | ||
933 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, | |
934 | unsigned selector) | |
935 | { | |
936 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
937 | ||
938 | return pct->soc->groups[selector].name; | |
939 | } | |
940 | ||
941 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, | |
942 | unsigned selector, | |
943 | const unsigned **pins, | |
944 | unsigned *num_pins) | |
945 | { | |
946 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
947 | ||
948 | *pins = pct->soc->groups[selector].pins; | |
949 | *num_pins = pct->soc->groups[selector].npins; | |
950 | return 0; | |
951 | } | |
952 | ||
953 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, | |
954 | struct seq_file *s, unsigned offset) | |
955 | { | |
956 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
957 | struct gpio_chip *chip = &pct->chip; | |
958 | ||
959 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, | |
960 | chip->base + offset - 1); | |
961 | } | |
962 | ||
963 | static struct pinctrl_ops abx500_pinctrl_ops = { | |
964 | .get_groups_count = abx500_get_groups_cnt, | |
965 | .get_group_name = abx500_get_group_name, | |
966 | .get_group_pins = abx500_get_group_pins, | |
967 | .pin_dbg_show = abx500_pin_dbg_show, | |
968 | }; | |
969 | ||
970 | int abx500_pin_config_get(struct pinctrl_dev *pctldev, | |
971 | unsigned pin, | |
972 | unsigned long *config) | |
973 | { | |
974 | /* Not implemented */ | |
975 | return -EINVAL; | |
976 | } | |
977 | ||
978 | int abx500_pin_config_set(struct pinctrl_dev *pctldev, | |
979 | unsigned pin, | |
980 | unsigned long config) | |
981 | { | |
982 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
983 | struct pullud *pullud = pct->soc->pullud; | |
984 | struct gpio_chip *chip = &pct->chip; | |
985 | unsigned offset; | |
986 | int ret; | |
987 | enum pin_config_param param = pinconf_to_config_param(config); | |
988 | enum pin_config_param argument = pinconf_to_config_argument(config); | |
989 | ||
990 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", | |
991 | pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", | |
992 | (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : | |
993 | (argument ? "pull up" : "pull down")); | |
994 | /* on ABx500, there is no GPIO0, so adjust the offset */ | |
995 | offset = pin - 1; | |
996 | ||
997 | switch (param) { | |
998 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
999 | /* | |
1000 | * if argument = 1 set the pull down | |
1001 | * else clear the pull down | |
1002 | */ | |
1003 | ret = abx500_gpio_direction_input(chip, offset); | |
1004 | /* | |
1005 | * Some chips only support pull down, while some actually | |
1006 | * support both pull up and pull down. Such chips have | |
1007 | * a "pullud" range specified for the pins that support | |
1008 | * both features. If the pin is not within that range, we | |
1009 | * fall back to the old bit set that only support pull down. | |
1010 | */ | |
1011 | if (pullud && | |
1012 | pin >= pullud->first_pin && | |
1013 | pin <= pullud->last_pin) | |
1014 | ret = abx500_config_pull_updown(pct, | |
1015 | pin, | |
1016 | argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); | |
1017 | else | |
1018 | /* Chip only supports pull down */ | |
1019 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, | |
1020 | offset, argument ? 0 : 1); | |
1021 | break; | |
1022 | case PIN_CONFIG_OUTPUT: | |
1023 | ret = abx500_gpio_direction_output(chip, offset, argument); | |
1024 | break; | |
1025 | default: | |
1026 | dev_err(chip->dev, "illegal configuration requested\n"); | |
1027 | return -EINVAL; | |
1028 | } | |
1029 | return ret; | |
1030 | } | |
1031 | ||
1032 | static struct pinconf_ops abx500_pinconf_ops = { | |
1033 | .pin_config_get = abx500_pin_config_get, | |
1034 | .pin_config_set = abx500_pin_config_set, | |
1035 | }; | |
1036 | ||
1037 | static struct pinctrl_desc abx500_pinctrl_desc = { | |
1038 | .name = "pinctrl-abx500", | |
1039 | .pctlops = &abx500_pinctrl_ops, | |
1040 | .pmxops = &abx500_pinmux_ops, | |
1041 | .confops = &abx500_pinconf_ops, | |
1042 | .owner = THIS_MODULE, | |
1043 | }; | |
1044 | ||
1045 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) | |
1046 | { | |
1047 | unsigned int lowest = 0; | |
1048 | unsigned int highest = 0; | |
1049 | unsigned int npins = 0; | |
1050 | int i; | |
1051 | ||
1052 | /* | |
1053 | * Compute number of GPIOs from the last SoC gpio range descriptors | |
1054 | * These ranges may include "holes" but the GPIO number space shall | |
1055 | * still be homogeneous, so we need to detect and account for any | |
1056 | * such holes so that these are included in the number of GPIO pins. | |
1057 | */ | |
1058 | for (i = 0; i < soc->gpio_num_ranges; i++) { | |
1059 | unsigned gstart; | |
1060 | unsigned gend; | |
1061 | const struct abx500_pinrange *p; | |
1062 | ||
1063 | p = &soc->gpio_ranges[i]; | |
1064 | gstart = p->offset; | |
1065 | gend = p->offset + p->npins - 1; | |
1066 | ||
1067 | if (i == 0) { | |
1068 | /* First iteration, set start values */ | |
1069 | lowest = gstart; | |
1070 | highest = gend; | |
1071 | } else { | |
1072 | if (gstart < lowest) | |
1073 | lowest = gstart; | |
1074 | if (gend > highest) | |
1075 | highest = gend; | |
1076 | } | |
1077 | } | |
1078 | /* this gives the absolute number of pins */ | |
1079 | npins = highest - lowest + 1; | |
1080 | return npins; | |
1081 | } | |
1082 | ||
1083 | static int abx500_gpio_probe(struct platform_device *pdev) | |
1084 | { | |
1085 | struct ab8500_platform_data *abx500_pdata = | |
1086 | dev_get_platdata(pdev->dev.parent); | |
1087 | struct abx500_gpio_platform_data *pdata; | |
1088 | struct abx500_pinctrl *pct; | |
1089 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
1090 | int ret; | |
1091 | int i; | |
1092 | ||
1093 | pdata = abx500_pdata->gpio; | |
1094 | if (!pdata) { | |
1095 | dev_err(&pdev->dev, "gpio platform data missing\n"); | |
1096 | return -ENODEV; | |
1097 | } | |
1098 | ||
1099 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), | |
1100 | GFP_KERNEL); | |
1101 | if (pct == NULL) { | |
1102 | dev_err(&pdev->dev, | |
1103 | "failed to allocate memory for pct\n"); | |
1104 | return -ENOMEM; | |
1105 | } | |
1106 | ||
1107 | pct->dev = &pdev->dev; | |
1108 | pct->parent = dev_get_drvdata(pdev->dev.parent); | |
1109 | pct->chip = abx500gpio_chip; | |
1110 | pct->chip.dev = &pdev->dev; | |
1111 | pct->chip.base = pdata->gpio_base; | |
1112 | pct->irq_base = pdata->irq_base; | |
1113 | ||
1114 | /* initialize the lock */ | |
1115 | mutex_init(&pct->lock); | |
1116 | ||
1117 | /* Poke in other ASIC variants here */ | |
1118 | switch (platid->driver_data) { | |
3c937993 PC |
1119 | case PINCTRL_AB8500: |
1120 | abx500_pinctrl_ab8500_init(&pct->soc); | |
1121 | break; | |
a8f96e41 PC |
1122 | case PINCTRL_AB8540: |
1123 | abx500_pinctrl_ab8540_init(&pct->soc); | |
1124 | break; | |
09dbec3f PC |
1125 | case PINCTRL_AB9540: |
1126 | abx500_pinctrl_ab9540_init(&pct->soc); | |
1127 | break; | |
1aa2d8d4 PC |
1128 | case PINCTRL_AB8505: |
1129 | abx500_pinctrl_ab8505_init(&pct->soc); | |
1130 | break; | |
0493e649 PC |
1131 | default: |
1132 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", | |
1133 | (int) platid->driver_data); | |
1134 | return -EINVAL; | |
1135 | } | |
1136 | ||
1137 | if (!pct->soc) { | |
1138 | dev_err(&pdev->dev, "Invalid SOC data\n"); | |
1139 | return -EINVAL; | |
1140 | } | |
1141 | ||
1142 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); | |
1143 | pct->irq_cluster = pct->soc->gpio_irq_cluster; | |
1144 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; | |
1145 | pct->irq_gpio_rising_offset = pct->soc->irq_gpio_rising_offset; | |
1146 | pct->irq_gpio_falling_offset = pct->soc->irq_gpio_falling_offset; | |
1147 | pct->irq_gpio_factor = pct->soc->irq_gpio_factor; | |
1148 | ||
1149 | ret = abx500_gpio_irq_init(pct); | |
1150 | if (ret) | |
1151 | goto out_free; | |
1152 | ret = gpiochip_add(&pct->chip); | |
1153 | if (ret) { | |
1154 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", | |
1155 | ret); | |
1156 | goto out_rem_irq; | |
1157 | } | |
1158 | dev_info(&pdev->dev, "added gpiochip\n"); | |
1159 | ||
1160 | abx500_pinctrl_desc.pins = pct->soc->pins; | |
1161 | abx500_pinctrl_desc.npins = pct->soc->npins; | |
1162 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); | |
1163 | if (!pct->pctldev) { | |
1164 | dev_err(&pdev->dev, | |
1165 | "could not register abx500 pinctrl driver\n"); | |
1166 | goto out_rem_chip; | |
1167 | } | |
1168 | dev_info(&pdev->dev, "registered pin controller\n"); | |
1169 | ||
1170 | /* We will handle a range of GPIO pins */ | |
1171 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
1172 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; | |
1173 | ||
1174 | ret = gpiochip_add_pin_range(&pct->chip, | |
1175 | dev_name(&pdev->dev), | |
1176 | p->offset - 1, p->offset, p->npins); | |
1177 | if (ret < 0) | |
1178 | return ret; | |
1179 | } | |
1180 | ||
1181 | platform_set_drvdata(pdev, pct); | |
1182 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); | |
1183 | ||
1184 | return 0; | |
1185 | ||
1186 | out_rem_chip: | |
1187 | ret = gpiochip_remove(&pct->chip); | |
1188 | if (ret) | |
1189 | dev_info(&pdev->dev, "failed to remove gpiochip\n"); | |
1190 | out_rem_irq: | |
1191 | abx500_gpio_irq_remove(pct); | |
1192 | out_free: | |
1193 | mutex_destroy(&pct->lock); | |
1194 | return ret; | |
1195 | } | |
1196 | ||
1197 | /* | |
1198 | * abx500_gpio_remove() - remove Ab8500-gpio driver | |
1199 | * @pdev : Platform device registered | |
1200 | */ | |
1201 | static int abx500_gpio_remove(struct platform_device *pdev) | |
1202 | { | |
1203 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); | |
1204 | int ret; | |
1205 | ||
1206 | ret = gpiochip_remove(&pct->chip); | |
1207 | if (ret < 0) { | |
1208 | dev_err(pct->dev, "unable to remove gpiochip: %d\n", | |
1209 | ret); | |
1210 | return ret; | |
1211 | } | |
1212 | ||
1213 | mutex_destroy(&pct->lock); | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | static const struct platform_device_id abx500_pinctrl_id[] = { | |
1219 | { "pinctrl-ab8500", PINCTRL_AB8500 }, | |
1220 | { "pinctrl-ab8540", PINCTRL_AB8540 }, | |
1221 | { "pinctrl-ab9540", PINCTRL_AB9540 }, | |
1222 | { "pinctrl-ab8505", PINCTRL_AB8505 }, | |
1223 | { }, | |
1224 | }; | |
1225 | ||
1226 | static struct platform_driver abx500_gpio_driver = { | |
1227 | .driver = { | |
1228 | .name = "abx500-gpio", | |
1229 | .owner = THIS_MODULE, | |
1230 | }, | |
1231 | .probe = abx500_gpio_probe, | |
1232 | .remove = abx500_gpio_remove, | |
1233 | .id_table = abx500_pinctrl_id, | |
1234 | }; | |
1235 | ||
1236 | static int __init abx500_gpio_init(void) | |
1237 | { | |
1238 | return platform_driver_register(&abx500_gpio_driver); | |
1239 | } | |
1240 | core_initcall(abx500_gpio_init); | |
1241 | ||
1242 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); | |
1243 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); | |
1244 | MODULE_ALIAS("platform:abx500-gpio"); | |
1245 | MODULE_LICENSE("GPL v2"); |