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0493e649 PC |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2013 | |
3 | * | |
4 | * Author: Patrice Chotard <patrice.chotard@st.com> | |
5 | * License terms: GNU General Public License (GPL) version 2 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/err.h> | |
f30a3839 LJ |
17 | #include <linux/of.h> |
18 | #include <linux/of_device.h> | |
0493e649 PC |
19 | #include <linux/platform_device.h> |
20 | #include <linux/gpio.h> | |
21 | #include <linux/irq.h> | |
ac652d79 | 22 | #include <linux/irqdomain.h> |
0493e649 PC |
23 | #include <linux/interrupt.h> |
24 | #include <linux/bitops.h> | |
25 | #include <linux/mfd/abx500.h> | |
26 | #include <linux/mfd/abx500/ab8500.h> | |
27 | #include <linux/mfd/abx500/ab8500-gpio.h> | |
28 | #include <linux/pinctrl/pinctrl.h> | |
29 | #include <linux/pinctrl/consumer.h> | |
30 | #include <linux/pinctrl/pinmux.h> | |
31 | #include <linux/pinctrl/pinconf.h> | |
32 | #include <linux/pinctrl/pinconf-generic.h> | |
33 | ||
34 | #include "pinctrl-abx500.h" | |
35 | ||
36 | /* | |
37 | * The AB9540 and AB8540 GPIO support are extended versions | |
38 | * of the AB8500 GPIO support. | |
39 | * The AB9540 supports an additional (7th) register so that | |
40 | * more GPIO may be configured and used. | |
41 | * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have | |
42 | * internal pull-up and pull-down capabilities. | |
43 | */ | |
44 | ||
45 | /* | |
46 | * GPIO registers offset | |
47 | * Bank: 0x10 | |
48 | */ | |
49 | #define AB8500_GPIO_SEL1_REG 0x00 | |
50 | #define AB8500_GPIO_SEL2_REG 0x01 | |
51 | #define AB8500_GPIO_SEL3_REG 0x02 | |
52 | #define AB8500_GPIO_SEL4_REG 0x03 | |
53 | #define AB8500_GPIO_SEL5_REG 0x04 | |
54 | #define AB8500_GPIO_SEL6_REG 0x05 | |
55 | #define AB9540_GPIO_SEL7_REG 0x06 | |
56 | ||
57 | #define AB8500_GPIO_DIR1_REG 0x10 | |
58 | #define AB8500_GPIO_DIR2_REG 0x11 | |
59 | #define AB8500_GPIO_DIR3_REG 0x12 | |
60 | #define AB8500_GPIO_DIR4_REG 0x13 | |
61 | #define AB8500_GPIO_DIR5_REG 0x14 | |
62 | #define AB8500_GPIO_DIR6_REG 0x15 | |
63 | #define AB9540_GPIO_DIR7_REG 0x16 | |
64 | ||
65 | #define AB8500_GPIO_OUT1_REG 0x20 | |
66 | #define AB8500_GPIO_OUT2_REG 0x21 | |
67 | #define AB8500_GPIO_OUT3_REG 0x22 | |
68 | #define AB8500_GPIO_OUT4_REG 0x23 | |
69 | #define AB8500_GPIO_OUT5_REG 0x24 | |
70 | #define AB8500_GPIO_OUT6_REG 0x25 | |
71 | #define AB9540_GPIO_OUT7_REG 0x26 | |
72 | ||
73 | #define AB8500_GPIO_PUD1_REG 0x30 | |
74 | #define AB8500_GPIO_PUD2_REG 0x31 | |
75 | #define AB8500_GPIO_PUD3_REG 0x32 | |
76 | #define AB8500_GPIO_PUD4_REG 0x33 | |
77 | #define AB8500_GPIO_PUD5_REG 0x34 | |
78 | #define AB8500_GPIO_PUD6_REG 0x35 | |
79 | #define AB9540_GPIO_PUD7_REG 0x36 | |
80 | ||
81 | #define AB8500_GPIO_IN1_REG 0x40 | |
82 | #define AB8500_GPIO_IN2_REG 0x41 | |
83 | #define AB8500_GPIO_IN3_REG 0x42 | |
84 | #define AB8500_GPIO_IN4_REG 0x43 | |
85 | #define AB8500_GPIO_IN5_REG 0x44 | |
86 | #define AB8500_GPIO_IN6_REG 0x45 | |
87 | #define AB9540_GPIO_IN7_REG 0x46 | |
88 | #define AB8540_GPIO_VINSEL_REG 0x47 | |
89 | #define AB8540_GPIO_PULL_UPDOWN_REG 0x48 | |
90 | #define AB8500_GPIO_ALTFUN_REG 0x50 | |
0493e649 PC |
91 | #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03 |
92 | #define AB8540_GPIO_VINSEL_MASK 0x03 | |
93 | #define AB8540_GPIOX_VBAT_START 51 | |
94 | #define AB8540_GPIOX_VBAT_END 54 | |
95 | ||
0493e649 PC |
96 | struct abx500_pinctrl { |
97 | struct device *dev; | |
98 | struct pinctrl_dev *pctldev; | |
99 | struct abx500_pinctrl_soc_data *soc; | |
100 | struct gpio_chip chip; | |
101 | struct ab8500 *parent; | |
0493e649 PC |
102 | struct abx500_gpio_irq_cluster *irq_cluster; |
103 | int irq_cluster_size; | |
0493e649 PC |
104 | }; |
105 | ||
106 | /** | |
107 | * to_abx500_pinctrl() - get the pointer to abx500_pinctrl | |
108 | * @chip: Member of the structure abx500_pinctrl | |
109 | */ | |
110 | static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip) | |
111 | { | |
112 | return container_of(chip, struct abx500_pinctrl, chip); | |
113 | } | |
114 | ||
115 | static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 116 | unsigned offset, bool *bit) |
0493e649 PC |
117 | { |
118 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
119 | u8 pos = offset % 8; | |
120 | u8 val; | |
121 | int ret; | |
122 | ||
123 | reg += offset / 8; | |
124 | ret = abx500_get_register_interruptible(pct->dev, | |
125 | AB8500_MISC, reg, &val); | |
126 | ||
127 | *bit = !!(val & BIT(pos)); | |
128 | ||
129 | if (ret < 0) | |
130 | dev_err(pct->dev, | |
131 | "%s read reg =%x, offset=%x failed\n", | |
132 | __func__, reg, offset); | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
137 | static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg, | |
83b423c8 | 138 | unsigned offset, int val) |
0493e649 PC |
139 | { |
140 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
141 | u8 pos = offset % 8; | |
142 | int ret; | |
143 | ||
144 | reg += offset / 8; | |
145 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
49dcf086 | 146 | AB8500_MISC, reg, BIT(pos), val << pos); |
0493e649 PC |
147 | if (ret < 0) |
148 | dev_err(pct->dev, "%s write failed\n", __func__); | |
83b423c8 | 149 | |
0493e649 PC |
150 | return ret; |
151 | } | |
83b423c8 | 152 | |
0493e649 PC |
153 | /** |
154 | * abx500_gpio_get() - Get the particular GPIO value | |
83b423c8 LJ |
155 | * @chip: Gpio device |
156 | * @offset: GPIO number to read | |
0493e649 PC |
157 | */ |
158 | static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset) | |
159 | { | |
160 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
161 | bool bit; | |
162 | int ret; | |
163 | ||
164 | ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG, | |
165 | offset, &bit); | |
166 | if (ret < 0) { | |
167 | dev_err(pct->dev, "%s failed\n", __func__); | |
168 | return ret; | |
169 | } | |
83b423c8 | 170 | |
0493e649 PC |
171 | return bit; |
172 | } | |
173 | ||
174 | static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |
175 | { | |
176 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
177 | int ret; | |
178 | ||
179 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
180 | if (ret < 0) | |
181 | dev_err(pct->dev, "%s write failed\n", __func__); | |
182 | } | |
183 | ||
184 | static int abx500_config_pull_updown(struct abx500_pinctrl *pct, | |
83b423c8 | 185 | int offset, enum abx500_gpio_pull_updown val) |
0493e649 PC |
186 | { |
187 | u8 pos; | |
188 | int ret; | |
189 | struct pullud *pullud; | |
190 | ||
191 | if (!pct->soc->pullud) { | |
192 | dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature", | |
193 | __func__); | |
194 | ret = -EPERM; | |
195 | goto out; | |
196 | } | |
197 | ||
198 | pullud = pct->soc->pullud; | |
199 | ||
200 | if ((offset < pullud->first_pin) | |
201 | || (offset > pullud->last_pin)) { | |
202 | ret = -EINVAL; | |
203 | goto out; | |
204 | } | |
205 | ||
10a8be54 | 206 | pos = (offset - pullud->first_pin) << 1; |
0493e649 PC |
207 | |
208 | ret = abx500_mask_and_set_register_interruptible(pct->dev, | |
209 | AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG, | |
210 | AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos); | |
211 | ||
212 | out: | |
213 | if (ret < 0) | |
214 | dev_err(pct->dev, "%s failed (%d)\n", __func__, ret); | |
83b423c8 | 215 | |
0493e649 PC |
216 | return ret; |
217 | } | |
218 | ||
219 | static int abx500_gpio_direction_output(struct gpio_chip *chip, | |
220 | unsigned offset, | |
221 | int val) | |
222 | { | |
223 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
224 | struct pullud *pullud = pct->soc->pullud; | |
225 | unsigned gpio; | |
226 | int ret; | |
83b423c8 | 227 | |
0493e649 PC |
228 | /* set direction as output */ |
229 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1); | |
230 | if (ret < 0) | |
231 | return ret; | |
232 | ||
233 | /* disable pull down */ | |
234 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1); | |
235 | if (ret < 0) | |
236 | return ret; | |
237 | ||
238 | /* if supported, disable both pull down and pull up */ | |
239 | gpio = offset + 1; | |
240 | if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) { | |
241 | ret = abx500_config_pull_updown(pct, | |
242 | gpio, | |
243 | ABX500_GPIO_PULL_NONE); | |
244 | if (ret < 0) | |
245 | return ret; | |
246 | } | |
83b423c8 | 247 | |
0493e649 PC |
248 | /* set the output as 1 or 0 */ |
249 | return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val); | |
250 | } | |
251 | ||
252 | static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
253 | { | |
254 | /* set the register as input */ | |
255 | return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0); | |
256 | } | |
257 | ||
258 | static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
259 | { | |
260 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
b9fab6e4 LJ |
261 | /* The AB8500 GPIO numbers are off by one */ |
262 | int gpio = offset + 1; | |
a6a16d27 | 263 | int hwirq; |
0493e649 PC |
264 | int i; |
265 | ||
266 | for (i = 0; i < pct->irq_cluster_size; i++) { | |
267 | struct abx500_gpio_irq_cluster *cluster = | |
268 | &pct->irq_cluster[i]; | |
269 | ||
a6a16d27 LJ |
270 | if (gpio >= cluster->start && gpio <= cluster->end) { |
271 | /* | |
272 | * The ABx500 GPIO's associated IRQs are clustered together | |
273 | * throughout the interrupt numbers at irregular intervals. | |
274 | * To solve this quandry, we have placed the read-in values | |
275 | * into the cluster information table. | |
276 | */ | |
43a255db | 277 | hwirq = gpio - cluster->start + cluster->to_irq; |
a6a16d27 LJ |
278 | return irq_create_mapping(pct->parent->domain, hwirq); |
279 | } | |
0493e649 PC |
280 | } |
281 | ||
282 | return -EINVAL; | |
283 | } | |
284 | ||
285 | static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 286 | unsigned gpio, int alt_setting) |
0493e649 PC |
287 | { |
288 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
289 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
290 | int ret; | |
291 | int val; | |
292 | unsigned offset; | |
83b423c8 | 293 | |
0493e649 PC |
294 | const char *modes[] = { |
295 | [ABX500_DEFAULT] = "default", | |
296 | [ABX500_ALT_A] = "altA", | |
297 | [ABX500_ALT_B] = "altB", | |
298 | [ABX500_ALT_C] = "altC", | |
299 | }; | |
300 | ||
301 | /* sanity check */ | |
302 | if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) || | |
303 | ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) || | |
304 | ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) { | |
305 | dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio, | |
306 | modes[alt_setting]); | |
307 | return -EINVAL; | |
308 | } | |
309 | ||
310 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ | |
311 | offset = gpio - 1; | |
83b423c8 | 312 | |
0493e649 PC |
313 | switch (alt_setting) { |
314 | case ABX500_DEFAULT: | |
315 | /* | |
316 | * for ABx5xx family, default mode is always selected by | |
317 | * writing 0 to GPIOSELx register, except for pins which | |
318 | * support at least ALT_B mode, default mode is selected | |
319 | * by writing 1 to GPIOSELx register | |
320 | */ | |
321 | val = 0; | |
322 | if (af.alt_bit1 != UNUSED) | |
323 | val++; | |
324 | ||
325 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
326 | offset, val); | |
327 | break; | |
83b423c8 | 328 | |
0493e649 PC |
329 | case ABX500_ALT_A: |
330 | /* | |
331 | * for ABx5xx family, alt_a mode is always selected by | |
332 | * writing 1 to GPIOSELx register, except for pins which | |
333 | * support at least ALT_B mode, alt_a mode is selected | |
334 | * by writing 0 to GPIOSELx register and 0 in ALTFUNC | |
335 | * register | |
336 | */ | |
337 | if (af.alt_bit1 != UNUSED) { | |
338 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
339 | offset, 0); | |
340 | ret = abx500_gpio_set_bits(chip, | |
341 | AB8500_GPIO_ALTFUN_REG, | |
342 | af.alt_bit1, | |
343 | !!(af.alta_val && BIT(0))); | |
344 | if (af.alt_bit2 != UNUSED) | |
345 | ret = abx500_gpio_set_bits(chip, | |
346 | AB8500_GPIO_ALTFUN_REG, | |
347 | af.alt_bit2, | |
348 | !!(af.alta_val && BIT(1))); | |
349 | } else | |
350 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
351 | offset, 1); | |
352 | break; | |
83b423c8 | 353 | |
0493e649 PC |
354 | case ABX500_ALT_B: |
355 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
356 | offset, 0); | |
357 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
358 | af.alt_bit1, !!(af.altb_val && BIT(0))); | |
359 | if (af.alt_bit2 != UNUSED) | |
360 | ret = abx500_gpio_set_bits(chip, | |
361 | AB8500_GPIO_ALTFUN_REG, | |
362 | af.alt_bit2, | |
363 | !!(af.altb_val && BIT(1))); | |
364 | break; | |
83b423c8 | 365 | |
0493e649 PC |
366 | case ABX500_ALT_C: |
367 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG, | |
368 | offset, 0); | |
369 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
370 | af.alt_bit2, !!(af.altc_val && BIT(0))); | |
371 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG, | |
372 | af.alt_bit2, !!(af.altc_val && BIT(1))); | |
373 | break; | |
374 | ||
375 | default: | |
376 | dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting); | |
83b423c8 | 377 | |
0493e649 PC |
378 | return -EINVAL; |
379 | } | |
83b423c8 | 380 | |
0493e649 PC |
381 | return ret; |
382 | } | |
383 | ||
384 | static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip, | |
83b423c8 | 385 | unsigned gpio) |
0493e649 PC |
386 | { |
387 | u8 mode; | |
388 | bool bit_mode; | |
389 | bool alt_bit1; | |
390 | bool alt_bit2; | |
391 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
392 | struct alternate_functions af = pct->soc->alternate_functions[gpio]; | |
a950cb74 LW |
393 | /* on ABx5xx, there is no GPIO0, so adjust the offset */ |
394 | unsigned offset = gpio - 1; | |
0493e649 PC |
395 | |
396 | /* | |
397 | * if gpiosel_bit is set to unused, | |
398 | * it means no GPIO or special case | |
399 | */ | |
400 | if (af.gpiosel_bit == UNUSED) | |
401 | return ABX500_DEFAULT; | |
402 | ||
403 | /* read GpioSelx register */ | |
a950cb74 | 404 | abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8), |
0493e649 PC |
405 | af.gpiosel_bit, &bit_mode); |
406 | mode = bit_mode; | |
407 | ||
408 | /* sanity check */ | |
409 | if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) || | |
410 | (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) { | |
411 | dev_err(pct->dev, | |
412 | "alt_bitX value not in correct range (-1 to 7)\n"); | |
413 | return -EINVAL; | |
414 | } | |
83b423c8 | 415 | |
0493e649 PC |
416 | /* if alt_bit2 is used, alt_bit1 must be used too */ |
417 | if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) { | |
418 | dev_err(pct->dev, | |
419 | "if alt_bit2 is used, alt_bit1 can't be unused\n"); | |
420 | return -EINVAL; | |
421 | } | |
422 | ||
423 | /* check if pin use AlternateFunction register */ | |
6a40cdd5 | 424 | if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED)) |
0493e649 PC |
425 | return mode; |
426 | /* | |
427 | * if pin GPIOSEL bit is set and pin supports alternate function, | |
428 | * it means DEFAULT mode | |
429 | */ | |
430 | if (mode) | |
431 | return ABX500_DEFAULT; | |
83b423c8 | 432 | |
0493e649 PC |
433 | /* |
434 | * pin use the AlternatFunction register | |
435 | * read alt_bit1 value | |
436 | */ | |
437 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, | |
438 | af.alt_bit1, &alt_bit1); | |
439 | ||
440 | if (af.alt_bit2 != UNUSED) | |
441 | /* read alt_bit2 value */ | |
442 | abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2, | |
443 | &alt_bit2); | |
444 | else | |
445 | alt_bit2 = 0; | |
446 | ||
447 | mode = (alt_bit2 << 1) + alt_bit1; | |
448 | if (mode == af.alta_val) | |
449 | return ABX500_ALT_A; | |
450 | else if (mode == af.altb_val) | |
451 | return ABX500_ALT_B; | |
452 | else | |
453 | return ABX500_ALT_C; | |
454 | } | |
455 | ||
456 | #ifdef CONFIG_DEBUG_FS | |
457 | ||
458 | #include <linux/seq_file.h> | |
459 | ||
460 | static void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
461 | struct pinctrl_dev *pctldev, |
462 | struct gpio_chip *chip, | |
463 | unsigned offset, unsigned gpio) | |
0493e649 | 464 | { |
0493e649 PC |
465 | const char *label = gpiochip_is_requested(chip, offset - 1); |
466 | u8 gpio_offset = offset - 1; | |
467 | int mode = -1; | |
468 | bool is_out; | |
469 | bool pull; | |
83b423c8 | 470 | |
0493e649 PC |
471 | const char *modes[] = { |
472 | [ABX500_DEFAULT] = "default", | |
473 | [ABX500_ALT_A] = "altA", | |
474 | [ABX500_ALT_B] = "altB", | |
475 | [ABX500_ALT_C] = "altC", | |
476 | }; | |
477 | ||
478 | abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out); | |
479 | abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull); | |
480 | ||
481 | if (pctldev) | |
482 | mode = abx500_get_mode(pctldev, chip, offset); | |
483 | ||
484 | seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s", | |
485 | gpio, label ?: "(none)", | |
486 | is_out ? "out" : "in ", | |
487 | is_out ? | |
488 | (chip->get | |
489 | ? (chip->get(chip, offset) ? "hi" : "lo") | |
490 | : "? ") | |
491 | : (pull ? "pull up" : "pull down"), | |
492 | (mode < 0) ? "unknown" : modes[mode]); | |
0493e649 PC |
493 | } |
494 | ||
495 | static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
496 | { | |
497 | unsigned i; | |
498 | unsigned gpio = chip->base; | |
499 | struct abx500_pinctrl *pct = to_abx500_pinctrl(chip); | |
500 | struct pinctrl_dev *pctldev = pct->pctldev; | |
501 | ||
502 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
503 | /* On AB8500, there is no GPIO0, the first is the GPIO 1 */ | |
504 | abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio); | |
505 | seq_printf(s, "\n"); | |
506 | } | |
507 | } | |
508 | ||
509 | #else | |
510 | static inline void abx500_gpio_dbg_show_one(struct seq_file *s, | |
83b423c8 LJ |
511 | struct pinctrl_dev *pctldev, |
512 | struct gpio_chip *chip, | |
513 | unsigned offset, unsigned gpio) | |
0493e649 PC |
514 | { |
515 | } | |
516 | #define abx500_gpio_dbg_show NULL | |
517 | #endif | |
518 | ||
9c4154ef | 519 | static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
520 | { |
521 | int gpio = chip->base + offset; | |
522 | ||
523 | return pinctrl_request_gpio(gpio); | |
524 | } | |
525 | ||
9c4154ef | 526 | static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset) |
0493e649 PC |
527 | { |
528 | int gpio = chip->base + offset; | |
529 | ||
530 | pinctrl_free_gpio(gpio); | |
531 | } | |
532 | ||
533 | static struct gpio_chip abx500gpio_chip = { | |
534 | .label = "abx500-gpio", | |
535 | .owner = THIS_MODULE, | |
536 | .request = abx500_gpio_request, | |
537 | .free = abx500_gpio_free, | |
538 | .direction_input = abx500_gpio_direction_input, | |
539 | .get = abx500_gpio_get, | |
540 | .direction_output = abx500_gpio_direction_output, | |
541 | .set = abx500_gpio_set, | |
542 | .to_irq = abx500_gpio_to_irq, | |
543 | .dbg_show = abx500_gpio_dbg_show, | |
544 | }; | |
545 | ||
0493e649 PC |
546 | static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) |
547 | { | |
548 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
549 | ||
550 | return pct->soc->nfunctions; | |
551 | } | |
552 | ||
553 | static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
554 | unsigned function) | |
555 | { | |
556 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
557 | ||
558 | return pct->soc->functions[function].name; | |
559 | } | |
560 | ||
561 | static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
562 | unsigned function, |
563 | const char * const **groups, | |
564 | unsigned * const num_groups) | |
0493e649 PC |
565 | { |
566 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
567 | ||
568 | *groups = pct->soc->functions[function].groups; | |
569 | *num_groups = pct->soc->functions[function].ngroups; | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
0493e649 | 574 | static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, |
83b423c8 | 575 | unsigned group) |
0493e649 PC |
576 | { |
577 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
578 | struct gpio_chip *chip = &pct->chip; | |
579 | const struct abx500_pingroup *g; | |
580 | int i; | |
581 | int ret = 0; | |
582 | ||
583 | g = &pct->soc->groups[group]; | |
584 | if (g->altsetting < 0) | |
585 | return -EINVAL; | |
586 | ||
587 | dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins); | |
588 | ||
589 | for (i = 0; i < g->npins; i++) { | |
590 | dev_dbg(pct->dev, "setting pin %d to altsetting %d\n", | |
591 | g->pins[i], g->altsetting); | |
592 | ||
0493e649 PC |
593 | ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting); |
594 | } | |
83b423c8 | 595 | |
0493e649 PC |
596 | return ret; |
597 | } | |
598 | ||
599 | static void abx500_pmx_disable(struct pinctrl_dev *pctldev, | |
83b423c8 | 600 | unsigned function, unsigned group) |
0493e649 PC |
601 | { |
602 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
603 | const struct abx500_pingroup *g; | |
604 | ||
605 | g = &pct->soc->groups[group]; | |
606 | if (g->altsetting < 0) | |
607 | return; | |
608 | ||
609 | /* FIXME: poke out the mux, set the pin to some default state? */ | |
610 | dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins); | |
611 | } | |
612 | ||
9c4154ef | 613 | static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
614 | struct pinctrl_gpio_range *range, |
615 | unsigned offset) | |
0493e649 PC |
616 | { |
617 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
618 | const struct abx500_pinrange *p; | |
619 | int ret; | |
620 | int i; | |
621 | ||
622 | /* | |
623 | * Different ranges have different ways to enable GPIO function on a | |
624 | * pin, so refer back to our local range type, where we handily define | |
625 | * what altfunc enables GPIO for a certain pin. | |
626 | */ | |
627 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
628 | p = &pct->soc->gpio_ranges[i]; | |
629 | if ((offset >= p->offset) && | |
630 | (offset < (p->offset + p->npins))) | |
631 | break; | |
632 | } | |
633 | ||
634 | if (i == pct->soc->gpio_num_ranges) { | |
635 | dev_err(pct->dev, "%s failed to locate range\n", __func__); | |
636 | return -ENODEV; | |
637 | } | |
638 | ||
639 | dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n", | |
640 | p->altfunc, offset); | |
641 | ||
642 | ret = abx500_set_mode(pct->pctldev, &pct->chip, | |
643 | offset, p->altfunc); | |
644 | if (ret < 0) { | |
645 | dev_err(pct->dev, "%s setting altfunc failed\n", __func__); | |
646 | return ret; | |
647 | } | |
648 | ||
649 | return ret; | |
650 | } | |
651 | ||
652 | static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
653 | struct pinctrl_gpio_range *range, |
654 | unsigned offset) | |
0493e649 PC |
655 | { |
656 | } | |
657 | ||
022ab148 | 658 | static const struct pinmux_ops abx500_pinmux_ops = { |
0493e649 PC |
659 | .get_functions_count = abx500_pmx_get_funcs_cnt, |
660 | .get_function_name = abx500_pmx_get_func_name, | |
661 | .get_function_groups = abx500_pmx_get_func_groups, | |
662 | .enable = abx500_pmx_enable, | |
663 | .disable = abx500_pmx_disable, | |
664 | .gpio_request_enable = abx500_gpio_request_enable, | |
665 | .gpio_disable_free = abx500_gpio_disable_free, | |
666 | }; | |
667 | ||
668 | static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev) | |
669 | { | |
670 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
671 | ||
672 | return pct->soc->ngroups; | |
673 | } | |
674 | ||
675 | static const char *abx500_get_group_name(struct pinctrl_dev *pctldev, | |
83b423c8 | 676 | unsigned selector) |
0493e649 PC |
677 | { |
678 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
679 | ||
680 | return pct->soc->groups[selector].name; | |
681 | } | |
682 | ||
683 | static int abx500_get_group_pins(struct pinctrl_dev *pctldev, | |
83b423c8 LJ |
684 | unsigned selector, |
685 | const unsigned **pins, | |
686 | unsigned *num_pins) | |
0493e649 PC |
687 | { |
688 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
689 | ||
690 | *pins = pct->soc->groups[selector].pins; | |
691 | *num_pins = pct->soc->groups[selector].npins; | |
83b423c8 | 692 | |
0493e649 PC |
693 | return 0; |
694 | } | |
695 | ||
696 | static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev, | |
83b423c8 | 697 | struct seq_file *s, unsigned offset) |
0493e649 PC |
698 | { |
699 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
700 | struct gpio_chip *chip = &pct->chip; | |
701 | ||
702 | abx500_gpio_dbg_show_one(s, pctldev, chip, offset, | |
703 | chip->base + offset - 1); | |
704 | } | |
705 | ||
022ab148 | 706 | static const struct pinctrl_ops abx500_pinctrl_ops = { |
0493e649 PC |
707 | .get_groups_count = abx500_get_groups_cnt, |
708 | .get_group_name = abx500_get_group_name, | |
709 | .get_group_pins = abx500_get_group_pins, | |
710 | .pin_dbg_show = abx500_pin_dbg_show, | |
711 | }; | |
712 | ||
9c4154ef | 713 | static int abx500_pin_config_get(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
714 | unsigned pin, |
715 | unsigned long *config) | |
0493e649 | 716 | { |
1abeebea | 717 | return -ENOSYS; |
0493e649 PC |
718 | } |
719 | ||
9c4154ef | 720 | static int abx500_pin_config_set(struct pinctrl_dev *pctldev, |
83b423c8 LJ |
721 | unsigned pin, |
722 | unsigned long config) | |
0493e649 PC |
723 | { |
724 | struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev); | |
725 | struct pullud *pullud = pct->soc->pullud; | |
726 | struct gpio_chip *chip = &pct->chip; | |
727 | unsigned offset; | |
9ed3cd33 | 728 | int ret = 0; |
0493e649 PC |
729 | enum pin_config_param param = pinconf_to_config_param(config); |
730 | enum pin_config_param argument = pinconf_to_config_argument(config); | |
731 | ||
732 | dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n", | |
733 | pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input", | |
734 | (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") : | |
735 | (argument ? "pull up" : "pull down")); | |
83b423c8 | 736 | |
0493e649 PC |
737 | /* on ABx500, there is no GPIO0, so adjust the offset */ |
738 | offset = pin - 1; | |
739 | ||
740 | switch (param) { | |
741 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
742 | /* | |
743 | * if argument = 1 set the pull down | |
744 | * else clear the pull down | |
745 | */ | |
746 | ret = abx500_gpio_direction_input(chip, offset); | |
747 | /* | |
748 | * Some chips only support pull down, while some actually | |
749 | * support both pull up and pull down. Such chips have | |
750 | * a "pullud" range specified for the pins that support | |
751 | * both features. If the pin is not within that range, we | |
752 | * fall back to the old bit set that only support pull down. | |
753 | */ | |
754 | if (pullud && | |
755 | pin >= pullud->first_pin && | |
756 | pin <= pullud->last_pin) | |
757 | ret = abx500_config_pull_updown(pct, | |
758 | pin, | |
759 | argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE); | |
760 | else | |
761 | /* Chip only supports pull down */ | |
762 | ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, | |
763 | offset, argument ? 0 : 1); | |
764 | break; | |
83b423c8 | 765 | |
9ed3cd33 PC |
766 | case PIN_CONFIG_BIAS_PULL_UP: |
767 | /* | |
768 | * if argument = 1 set the pull up | |
769 | * else clear the pull up | |
770 | */ | |
771 | ret = abx500_gpio_direction_input(chip, offset); | |
772 | /* | |
773 | * Some chips only support pull down, while some actually | |
774 | * support both pull up and pull down. Such chips have | |
775 | * a "pullud" range specified for the pins that support | |
776 | * both features. If the pin is not within that range, do | |
777 | * nothing | |
778 | */ | |
779 | if (pullud && | |
780 | pin >= pullud->first_pin && | |
781 | pin <= pullud->last_pin) { | |
782 | ret = abx500_config_pull_updown(pct, | |
783 | pin, | |
784 | argument ? ABX500_GPIO_PULL_UP : ABX500_GPIO_PULL_NONE); | |
785 | } | |
786 | break; | |
787 | ||
0493e649 PC |
788 | case PIN_CONFIG_OUTPUT: |
789 | ret = abx500_gpio_direction_output(chip, offset, argument); | |
83b423c8 | 790 | |
0493e649 | 791 | break; |
83b423c8 | 792 | |
0493e649 PC |
793 | default: |
794 | dev_err(chip->dev, "illegal configuration requested\n"); | |
83b423c8 | 795 | |
0493e649 PC |
796 | return -EINVAL; |
797 | } | |
83b423c8 | 798 | |
0493e649 PC |
799 | return ret; |
800 | } | |
801 | ||
022ab148 | 802 | static const struct pinconf_ops abx500_pinconf_ops = { |
0493e649 PC |
803 | .pin_config_get = abx500_pin_config_get, |
804 | .pin_config_set = abx500_pin_config_set, | |
805 | }; | |
806 | ||
807 | static struct pinctrl_desc abx500_pinctrl_desc = { | |
808 | .name = "pinctrl-abx500", | |
809 | .pctlops = &abx500_pinctrl_ops, | |
810 | .pmxops = &abx500_pinmux_ops, | |
811 | .confops = &abx500_pinconf_ops, | |
812 | .owner = THIS_MODULE, | |
813 | }; | |
814 | ||
815 | static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc) | |
816 | { | |
817 | unsigned int lowest = 0; | |
818 | unsigned int highest = 0; | |
819 | unsigned int npins = 0; | |
820 | int i; | |
821 | ||
822 | /* | |
823 | * Compute number of GPIOs from the last SoC gpio range descriptors | |
824 | * These ranges may include "holes" but the GPIO number space shall | |
825 | * still be homogeneous, so we need to detect and account for any | |
826 | * such holes so that these are included in the number of GPIO pins. | |
827 | */ | |
828 | for (i = 0; i < soc->gpio_num_ranges; i++) { | |
829 | unsigned gstart; | |
830 | unsigned gend; | |
831 | const struct abx500_pinrange *p; | |
832 | ||
833 | p = &soc->gpio_ranges[i]; | |
834 | gstart = p->offset; | |
835 | gend = p->offset + p->npins - 1; | |
836 | ||
837 | if (i == 0) { | |
838 | /* First iteration, set start values */ | |
839 | lowest = gstart; | |
840 | highest = gend; | |
841 | } else { | |
842 | if (gstart < lowest) | |
843 | lowest = gstart; | |
844 | if (gend > highest) | |
845 | highest = gend; | |
846 | } | |
847 | } | |
848 | /* this gives the absolute number of pins */ | |
849 | npins = highest - lowest + 1; | |
850 | return npins; | |
851 | } | |
852 | ||
f30a3839 LJ |
853 | static const struct of_device_id abx500_gpio_match[] = { |
854 | { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, }, | |
855 | { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, | |
856 | { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, | |
857 | { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, | |
e3929714 | 858 | { } |
f30a3839 LJ |
859 | }; |
860 | ||
0493e649 PC |
861 | static int abx500_gpio_probe(struct platform_device *pdev) |
862 | { | |
863 | struct ab8500_platform_data *abx500_pdata = | |
864 | dev_get_platdata(pdev->dev.parent); | |
f30a3839 LJ |
865 | struct abx500_gpio_platform_data *pdata = NULL; |
866 | struct device_node *np = pdev->dev.of_node; | |
0493e649 PC |
867 | struct abx500_pinctrl *pct; |
868 | const struct platform_device_id *platid = platform_get_device_id(pdev); | |
f30a3839 | 869 | unsigned int id = -1; |
fa1ec996 | 870 | int ret, err; |
0493e649 PC |
871 | int i; |
872 | ||
f30a3839 LJ |
873 | if (abx500_pdata) |
874 | pdata = abx500_pdata->gpio; | |
f30a3839 | 875 | |
86c976e4 LJ |
876 | if (!(pdata || np)) { |
877 | dev_err(&pdev->dev, "gpio dt and platform data missing\n"); | |
878 | return -ENODEV; | |
0493e649 PC |
879 | } |
880 | ||
881 | pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl), | |
882 | GFP_KERNEL); | |
883 | if (pct == NULL) { | |
884 | dev_err(&pdev->dev, | |
885 | "failed to allocate memory for pct\n"); | |
886 | return -ENOMEM; | |
887 | } | |
888 | ||
889 | pct->dev = &pdev->dev; | |
890 | pct->parent = dev_get_drvdata(pdev->dev.parent); | |
891 | pct->chip = abx500gpio_chip; | |
892 | pct->chip.dev = &pdev->dev; | |
f30a3839 | 893 | pct->chip.base = (np) ? -1 : pdata->gpio_base; |
0493e649 | 894 | |
86c976e4 LJ |
895 | if (platid) |
896 | id = platid->driver_data; | |
897 | else if (np) { | |
898 | const struct of_device_id *match; | |
899 | ||
900 | match = of_match_device(abx500_gpio_match, &pdev->dev); | |
901 | if (match) | |
902 | id = (unsigned long)match->data; | |
903 | } | |
904 | ||
0493e649 | 905 | /* Poke in other ASIC variants here */ |
f30a3839 | 906 | switch (id) { |
3c937993 PC |
907 | case PINCTRL_AB8500: |
908 | abx500_pinctrl_ab8500_init(&pct->soc); | |
909 | break; | |
a8f96e41 PC |
910 | case PINCTRL_AB8540: |
911 | abx500_pinctrl_ab8540_init(&pct->soc); | |
912 | break; | |
09dbec3f PC |
913 | case PINCTRL_AB9540: |
914 | abx500_pinctrl_ab9540_init(&pct->soc); | |
915 | break; | |
1aa2d8d4 PC |
916 | case PINCTRL_AB8505: |
917 | abx500_pinctrl_ab8505_init(&pct->soc); | |
918 | break; | |
0493e649 | 919 | default: |
2fcad12e | 920 | dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id); |
0493e649 PC |
921 | return -EINVAL; |
922 | } | |
923 | ||
924 | if (!pct->soc) { | |
925 | dev_err(&pdev->dev, "Invalid SOC data\n"); | |
926 | return -EINVAL; | |
927 | } | |
928 | ||
929 | pct->chip.ngpio = abx500_get_gpio_num(pct->soc); | |
930 | pct->irq_cluster = pct->soc->gpio_irq_cluster; | |
931 | pct->irq_cluster_size = pct->soc->ngpio_irq_cluster; | |
0493e649 | 932 | |
0493e649 PC |
933 | ret = gpiochip_add(&pct->chip); |
934 | if (ret) { | |
83b423c8 | 935 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); |
ac652d79 | 936 | return ret; |
0493e649 PC |
937 | } |
938 | dev_info(&pdev->dev, "added gpiochip\n"); | |
939 | ||
940 | abx500_pinctrl_desc.pins = pct->soc->pins; | |
941 | abx500_pinctrl_desc.npins = pct->soc->npins; | |
942 | pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct); | |
943 | if (!pct->pctldev) { | |
944 | dev_err(&pdev->dev, | |
945 | "could not register abx500 pinctrl driver\n"); | |
fa1ec996 | 946 | ret = -EINVAL; |
0493e649 PC |
947 | goto out_rem_chip; |
948 | } | |
949 | dev_info(&pdev->dev, "registered pin controller\n"); | |
950 | ||
951 | /* We will handle a range of GPIO pins */ | |
952 | for (i = 0; i < pct->soc->gpio_num_ranges; i++) { | |
953 | const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i]; | |
954 | ||
955 | ret = gpiochip_add_pin_range(&pct->chip, | |
956 | dev_name(&pdev->dev), | |
957 | p->offset - 1, p->offset, p->npins); | |
958 | if (ret < 0) | |
fa1ec996 | 959 | goto out_rem_chip; |
0493e649 PC |
960 | } |
961 | ||
962 | platform_set_drvdata(pdev, pct); | |
963 | dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n"); | |
964 | ||
965 | return 0; | |
966 | ||
967 | out_rem_chip: | |
fa1ec996 LJ |
968 | err = gpiochip_remove(&pct->chip); |
969 | if (err) | |
0493e649 | 970 | dev_info(&pdev->dev, "failed to remove gpiochip\n"); |
ac652d79 | 971 | |
0493e649 PC |
972 | return ret; |
973 | } | |
974 | ||
83b423c8 | 975 | /** |
0493e649 | 976 | * abx500_gpio_remove() - remove Ab8500-gpio driver |
83b423c8 | 977 | * @pdev: Platform device registered |
0493e649 PC |
978 | */ |
979 | static int abx500_gpio_remove(struct platform_device *pdev) | |
980 | { | |
981 | struct abx500_pinctrl *pct = platform_get_drvdata(pdev); | |
982 | int ret; | |
983 | ||
984 | ret = gpiochip_remove(&pct->chip); | |
985 | if (ret < 0) { | |
986 | dev_err(pct->dev, "unable to remove gpiochip: %d\n", | |
987 | ret); | |
988 | return ret; | |
989 | } | |
990 | ||
0493e649 PC |
991 | return 0; |
992 | } | |
993 | ||
994 | static const struct platform_device_id abx500_pinctrl_id[] = { | |
995 | { "pinctrl-ab8500", PINCTRL_AB8500 }, | |
996 | { "pinctrl-ab8540", PINCTRL_AB8540 }, | |
997 | { "pinctrl-ab9540", PINCTRL_AB9540 }, | |
998 | { "pinctrl-ab8505", PINCTRL_AB8505 }, | |
999 | { }, | |
1000 | }; | |
1001 | ||
1002 | static struct platform_driver abx500_gpio_driver = { | |
1003 | .driver = { | |
1004 | .name = "abx500-gpio", | |
1005 | .owner = THIS_MODULE, | |
f30a3839 | 1006 | .of_match_table = abx500_gpio_match, |
0493e649 PC |
1007 | }, |
1008 | .probe = abx500_gpio_probe, | |
1009 | .remove = abx500_gpio_remove, | |
1010 | .id_table = abx500_pinctrl_id, | |
1011 | }; | |
1012 | ||
1013 | static int __init abx500_gpio_init(void) | |
1014 | { | |
1015 | return platform_driver_register(&abx500_gpio_driver); | |
1016 | } | |
1017 | core_initcall(abx500_gpio_init); | |
1018 | ||
1019 | MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>"); | |
1020 | MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO"); | |
1021 | MODULE_ALIAS("platform:abx500-gpio"); | |
1022 | MODULE_LICENSE("GPL v2"); |